2 * Copyright (c) 1997-2000 Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/malloc.h>
40 #include <machine/clock.h>
41 #include <machine/bus.h>
42 #include <machine/resource.h>
43 #include <machine/vmparam.h>
47 #include <pc98/pc98/pc98.h>
49 #include <isa/isareg.h>
51 #include <isa/isavar.h>
53 #include <dev/ppbus/ppbconf.h>
54 #include <dev/ppbus/ppb_msq.h>
57 #include <pc98/pc98/ppcreg.h>
59 #include <isa/ppcreg.h>
64 #define LOG_PPC(function, ppc, string) \
65 if (bootverbose) printf("%s: %s\n", function, string)
68 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
70 devclass_t ppc_devclass;
72 static int ppc_probe(device_t dev);
73 static int ppc_attach(device_t dev);
74 static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val);
76 static void ppc_reset_epp(device_t);
77 static void ppc_ecp_sync(device_t);
78 static void ppcintr(void *arg);
80 static int ppc_exec_microseq(device_t, struct ppb_microseq **);
81 static int ppc_setmode(device_t, int);
83 static int ppc_read(device_t, char *, int, int);
84 static int ppc_write(device_t, char *, int, int);
86 static u_char ppc_io(device_t, int, u_char *, int, u_char);
88 static int ppc_setup_intr(device_t, device_t, struct resource *, int,
89 void (*)(void *), void *, void **);
90 static int ppc_teardown_intr(device_t, device_t, struct resource *, void *);
92 static device_method_t ppc_methods[] = {
93 /* device interface */
94 DEVMETHOD(device_probe, ppc_probe),
95 DEVMETHOD(device_attach, ppc_attach),
98 DEVMETHOD(bus_read_ivar, ppc_read_ivar),
99 DEVMETHOD(bus_setup_intr, ppc_setup_intr),
100 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr),
101 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
103 /* ppbus interface */
104 DEVMETHOD(ppbus_io, ppc_io),
105 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq),
106 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp),
107 DEVMETHOD(ppbus_setmode, ppc_setmode),
108 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync),
109 DEVMETHOD(ppbus_read, ppc_read),
110 DEVMETHOD(ppbus_write, ppc_write),
115 static driver_t ppc_driver = {
118 sizeof(struct ppc_data),
121 static char *ppc_models[] = {
122 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
123 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0
126 /* list of available modes */
127 static char *ppc_avms[] = {
128 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
129 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
130 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
131 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
134 /* list of current executing modes
135 * Note that few modes do not actually exist.
137 static char *ppc_modes[] = {
138 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
139 "EPP", "EPP", "EPP", "ECP",
140 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
141 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
144 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
148 * BIOS printer list - used by BIOS probe.
150 #define BIOS_PPC_PORTS 0x408
151 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
152 #define BIOS_MAX_PPC 4
159 ppc_ecp_sync(device_t dev) {
162 struct ppc_data *ppc = DEVTOSOFTC(dev);
164 if (!(ppc->ppc_avm & PPB_ECP))
168 if ((r & 0xe0) != PPC_ECR_EPP)
171 for (i = 0; i < 100; i++) {
178 printf("ppc%d: ECP sync failed as data still " \
179 "present in FIFO.\n", ppc->ppc_unit);
187 * Detect parallel port FIFO
190 ppc_detect_fifo(struct ppc_data *ppc)
193 char ctr_sav, ctr, cc;
197 ecr_sav = r_ecr(ppc);
198 ctr_sav = r_ctr(ppc);
200 /* enter ECP configuration mode, no interrupt, no DMA */
203 /* read PWord size - transfers in FIFO mode must be PWord aligned */
204 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
206 /* XXX 16 and 32 bits implementations not supported */
207 if (ppc->ppc_pword != PPC_PWORD_8) {
208 LOG_PPC(__FUNCTION__, ppc, "PWord not supported");
212 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
214 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
216 /* enter ECP test mode, no interrupt, no DMA */
220 for (i=0; i<1024; i++) {
221 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
227 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO");
231 /* enable interrupts, no DMA */
234 /* determine readIntrThreshold
235 * fill the FIFO until serviceIntr is set
237 for (i=0; i<1024; i++) {
238 w_fifo(ppc, (char)i);
239 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
240 /* readThreshold reached */
243 if (r_ecr(ppc) & PPC_FIFO_FULL) {
250 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO");
254 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
255 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
256 w_ecr(ppc, 0xd0); /* enable interrupts */
258 /* determine writeIntrThreshold
259 * empty the FIFO until serviceIntr is set
261 for (i=ppc->ppc_fifo; i>0; i--) {
262 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
263 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO");
266 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
267 /* writeIntrThreshold reached */
268 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
270 /* if FIFO empty before the last byte, error */
271 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
272 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO");
277 /* FIFO must be empty after the last byte */
278 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
279 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO");
296 ppc_detect_port(struct ppc_data *ppc)
299 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
301 if (r_dtr(ppc) != 0xaa)
308 * EPP timeout, according to the PC87332 manual
309 * Semantics of clearing EPP timeout bit.
310 * PC87332 - reading SPP_STR does it...
311 * SMC - write 1 to EPP timeout bit XXX
312 * Others - (?) write 0 to EPP timeout bit
315 ppc_reset_epp_timeout(struct ppc_data *ppc)
321 w_str(ppc, r & 0xfe);
327 ppc_check_epp_timeout(struct ppc_data *ppc)
329 ppc_reset_epp_timeout(ppc);
331 return (!(r_str(ppc) & TIMEOUT));
335 * Configure current operating mode
338 ppc_generic_setmode(struct ppc_data *ppc, int mode)
342 /* check if mode is available */
343 if (mode && !(ppc->ppc_avm & mode))
346 /* if ECP mode, configure ecr register */
347 if (ppc->ppc_avm & PPB_ECP) {
348 /* return to byte mode (keeping direction bit),
349 * no interrupt, no DMA to be able to change to
352 w_ecr(ppc, PPC_ECR_RESET);
353 ecr = PPC_DISABLE_INTR;
357 else if (mode & PPB_ECP)
358 /* select ECP mode */
360 else if (mode & PPB_PS2)
361 /* select PS2 mode with ECP */
364 /* select COMPATIBLE/NIBBLE mode */
370 ppc->ppc_mode = mode;
376 * The ppc driver is free to choose options like FIFO or DMA
377 * if ECP mode is available.
379 * The 'RAW' option allows the upper drivers to force the ppc mode
380 * even with FIFO, DMA available.
383 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
387 /* check if mode is available */
388 if (mode && !(ppc->ppc_avm & mode))
391 /* if ECP mode, configure ecr register */
392 if (ppc->ppc_avm & PPB_ECP) {
393 /* return to byte mode (keeping direction bit),
394 * no interrupt, no DMA to be able to change to
397 w_ecr(ppc, PPC_ECR_RESET);
398 ecr = PPC_DISABLE_INTR;
401 /* select EPP mode */
403 else if (mode & PPB_ECP)
404 /* select ECP mode */
406 else if (mode & PPB_PS2)
407 /* select PS2 mode with ECP */
410 /* select COMPATIBLE/NIBBLE mode */
416 ppc->ppc_mode = mode;
421 #ifdef PPC_PROBE_CHIPSET
425 * Probe for a Natsemi PC873xx-family part.
427 * References in this function are to the National Semiconductor
428 * PC87332 datasheet TL/C/11930, May 1995 revision.
430 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
431 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
432 static int pc873xx_irqtab[] = {5, 7, 5, 0};
434 static int pc873xx_regstab[] = {
435 PC873_FER, PC873_FAR, PC873_PTR,
436 PC873_FCR, PC873_PCR, PC873_PMC,
437 PC873_TUP, PC873_SID, PC873_PNP0,
438 PC873_PNP1, PC873_LPTBA, -1
441 static char *pc873xx_rnametab[] = {
442 "FER", "FAR", "PTR", "FCR", "PCR",
443 "PMC", "TUP", "SID", "PNP0", "PNP1",
448 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
450 static int index = 0;
452 int ptr, pcr, val, i;
454 while ((idport = pc873xx_basetab[index++])) {
456 /* XXX should check first to see if this location is already claimed */
459 * Pull the 873xx through the power-on ID cycle (2.2,1.).
460 * We can't use this to locate the chip as it may already have
461 * been used by the BIOS.
463 (void)inb(idport); (void)inb(idport);
464 (void)inb(idport); (void)inb(idport);
467 * Read the SID byte. Possible values are :
473 outb(idport, PC873_SID);
474 val = inb(idport + 1);
475 if ((val & 0xf0) == 0x10) {
476 ppc->ppc_model = NS_PC87332;
477 } else if ((val & 0xf8) == 0x70) {
478 ppc->ppc_model = NS_PC87306;
479 } else if ((val & 0xf8) == 0x50) {
480 ppc->ppc_model = NS_PC87334;
482 if (bootverbose && (val != 0xff))
483 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
484 continue ; /* not recognised */
487 /* print registers */
490 for (i=0; pc873xx_regstab[i] != -1; i++) {
491 outb(idport, pc873xx_regstab[i]);
492 printf(" %s=0x%x", pc873xx_rnametab[i],
493 inb(idport + 1) & 0xff);
499 * We think we have one. Is it enabled and where we want it to be?
501 outb(idport, PC873_FER);
502 val = inb(idport + 1);
503 if (!(val & PC873_PPENABLE)) {
505 printf("PC873xx parallel port disabled\n");
508 outb(idport, PC873_FAR);
509 val = inb(idport + 1) & 0x3;
510 /* XXX we should create a driver instance for every port found */
511 if (pc873xx_porttab[val] != ppc->ppc_base) {
513 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
514 pc873xx_porttab[val], ppc->ppc_base);
518 outb(idport, PC873_PTR);
519 ptr = inb(idport + 1);
521 /* get irq settings */
522 if (ppc->ppc_base == 0x378)
523 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
525 irq = pc873xx_irqtab[val];
528 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
531 * Check if irq settings are correct
533 if (irq != ppc->ppc_irq) {
535 * If the chipset is not locked and base address is 0x378,
536 * we have another chance
538 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
539 if (ppc->ppc_irq == 7) {
540 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
541 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
543 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
544 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
547 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
550 printf("PC873xx sorry, can't change irq setting\n");
554 printf("PC873xx irq settings are correct\n");
557 outb(idport, PC873_PCR);
558 pcr = inb(idport + 1);
560 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
562 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
564 ppc->ppc_avm |= PPB_NIBBLE;
568 if (pcr & PC873_EPPEN) {
569 ppc->ppc_avm |= PPB_EPP;
574 if (pcr & PC873_EPP19)
575 ppc->ppc_epp = EPP_1_9;
577 ppc->ppc_epp = EPP_1_7;
579 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
580 outb(idport, PC873_PTR);
581 ptr = inb(idport + 1);
582 if (ptr & PC873_EPPRDIR)
583 printf(", Regular mode");
585 printf(", Automatic mode");
587 } else if (pcr & PC873_ECPEN) {
588 ppc->ppc_avm |= PPB_ECP;
592 if (pcr & PC873_ECPCLK) { /* XXX */
593 ppc->ppc_avm |= PPB_PS2;
598 outb(idport, PC873_PTR);
599 ptr = inb(idport + 1);
600 if (ptr & PC873_EXTENDED) {
601 ppc->ppc_avm |= PPB_SPP;
608 printf("PC873xx unlocked");
610 if (chipset_mode & PPB_ECP) {
611 if ((chipset_mode & PPB_EPP) && bootverbose)
612 printf(", ECP+EPP not supported");
615 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
616 outb(idport + 1, pcr);
617 outb(idport + 1, pcr);
622 } else if (chipset_mode & PPB_EPP) {
623 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
624 pcr |= (PC873_EPPEN | PC873_EPP19);
625 outb(idport + 1, pcr);
626 outb(idport + 1, pcr);
628 ppc->ppc_epp = EPP_1_9; /* XXX */
633 /* enable automatic direction turnover */
634 if (ppc->ppc_model == NS_PC87332) {
635 outb(idport, PC873_PTR);
636 ptr = inb(idport + 1);
637 ptr &= ~PC873_EPPRDIR;
638 outb(idport + 1, ptr);
639 outb(idport + 1, ptr);
642 printf(", Automatic mode");
645 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
646 outb(idport + 1, pcr);
647 outb(idport + 1, pcr);
649 /* configure extended bit in PTR */
650 outb(idport, PC873_PTR);
651 ptr = inb(idport + 1);
653 if (chipset_mode & PPB_PS2) {
654 ptr |= PC873_EXTENDED;
660 /* default to NIBBLE mode */
661 ptr &= ~PC873_EXTENDED;
666 outb(idport + 1, ptr);
667 outb(idport + 1, ptr);
670 ppc->ppc_avm = chipset_mode;
676 ppc->ppc_type = PPC_TYPE_GENERIC;
677 ppc_generic_setmode(ppc, chipset_mode);
679 return(chipset_mode);
685 * ppc_smc37c66xgt_detect
687 * SMC FDC37C66xGT configuration.
690 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
695 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
697 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
700 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
703 * Detection: enter configuration mode and read CRD register.
707 outb(csr, SMC665_iCODE);
708 outb(csr, SMC665_iCODE);
712 if (inb(cio) == 0x65) {
717 for (i = 0; i < 2; i++) {
719 outb(csr, SMC666_iCODE);
720 outb(csr, SMC666_iCODE);
724 if (inb(cio) == 0x66) {
729 /* Another chance, CSR may be hard-configured to be at 0x370 */
735 * If chipset not found, do not continue.
743 /* read the port's address: bits 0 and 1 of CR1 */
744 r = inb(cio) & SMC_CR1_ADDR;
745 if (port_address[(int)r] != ppc->ppc_base)
748 ppc->ppc_model = type;
751 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
752 * If SPP mode is detected, try to set ECP+EPP mode
757 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
761 printf(" CR4=0x%x", inb(cio) & 0xff);
768 /* autodetect mode */
770 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
771 if (type == SMC_37C666GT) {
772 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
774 printf(" configuration hardwired, supposing " \
778 if ((inb(cio) & SMC_CR1_MODE) == 0) {
779 /* already in extended parallel port mode, read CR4 */
781 r = (inb(cio) & SMC_CR4_EMODE);
785 ppc->ppc_avm |= PPB_SPP;
791 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
797 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
803 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
805 printf(" ECP+EPP SPP");
809 /* not an extended port mode */
810 ppc->ppc_avm |= PPB_SPP;
817 ppc->ppc_avm = chipset_mode;
819 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
820 if (type == SMC_37C666GT)
824 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
825 /* do not use ECP when the mode is not forced to */
826 outb(cio, r | SMC_CR1_MODE);
830 /* an extended mode is selected */
831 outb(cio, r & ~SMC_CR1_MODE);
833 /* read CR4 register and reset mode field */
835 r = inb(cio) & ~SMC_CR4_EMODE;
837 if (chipset_mode & PPB_ECP) {
838 if (chipset_mode & PPB_EPP) {
839 outb(cio, r | SMC_ECPEPP);
843 outb(cio, r | SMC_ECP);
849 outb(cio, r | SMC_EPPSPP);
854 ppc->ppc_avm = chipset_mode;
857 /* set FIFO threshold to 16 */
858 if (ppc->ppc_avm & PPB_ECP) {
869 if (ppc->ppc_avm & PPB_EPP) {
875 * Set the EPP protocol...
876 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
878 if (ppc->ppc_epp == EPP_1_9)
879 outb(cio, (r & ~SMC_CR4_EPPTYPE));
881 outb(cio, (r | SMC_CR4_EPPTYPE));
884 /* end config mode */
887 ppc->ppc_type = PPC_TYPE_SMCLIKE;
888 ppc_smclike_setmode(ppc, chipset_mode);
890 return (chipset_mode);
894 * Winbond W83877F stuff
896 * EFER: extended function enable register
897 * EFIR: extended function index register
898 * EFDR: extended function data register
900 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
901 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
903 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
904 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
905 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
906 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
909 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
912 unsigned char r, hefere, hefras;
914 for (i = 0; i < 4; i ++) {
915 /* first try to enable configuration registers */
916 efer = w83877f_efers[i];
918 /* write the key to the EFER */
919 for (j = 0; j < w83877f_keyiter[i]; j ++)
920 outb (efer, w83877f_keys[i]);
922 /* then check HEFERE and HEFRAS bits */
924 hefere = inb(efdr) & WINB_HEFERE;
927 hefras = inb(efdr) & WINB_HEFRAS;
931 * 0 1 write 89h to 250h (power-on default)
932 * 1 0 write 86h twice to 3f0h
933 * 1 1 write 87h twice to 3f0h
934 * 0 0 write 88h to 250h
936 if ((hefere | hefras) == w83877f_hefs[i])
940 return (-1); /* failed */
943 /* check base port address - read from CR23 */
945 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
948 /* read CHIP ID from CR9/bits0-3 */
951 switch (inb(efdr) & WINB_CHIPID) {
952 case WINB_W83877F_ID:
953 ppc->ppc_model = WINB_W83877F;
956 case WINB_W83877AF_ID:
957 ppc->ppc_model = WINB_W83877AF;
961 ppc->ppc_model = WINB_UNKNOWN;
965 /* dump of registers */
966 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
967 for (i = 0; i <= 0xd; i ++) {
969 printf("0x%x ", inb(efdr));
971 for (i = 0x10; i <= 0x17; i ++) {
973 printf("0x%x ", inb(efdr));
976 printf("0x%x ", inb(efdr));
977 for (i = 0x20; i <= 0x29; i ++) {
979 printf("0x%x ", inb(efdr));
982 printf("ppc%d:", ppc->ppc_unit);
985 ppc->ppc_type = PPC_TYPE_GENERIC;
988 /* autodetect mode */
992 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
996 r |= (inb(efdr) & WINB_PRTMODS2);
1001 printf("ppc%d: W83757 compatible mode\n",
1003 return (-1); /* generic or SMC-like */
1010 printf(" not in parallel port mode\n");
1013 case (WINB_PARALLEL | WINB_EPP_SPP):
1014 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1019 case (WINB_PARALLEL | WINB_ECP):
1020 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1025 case (WINB_PARALLEL | WINB_ECP_EPP):
1026 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1027 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1030 printf(" ECP+EPP SPP");
1033 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r);
1039 /* select CR9 and set PRTMODS2 bit */
1041 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1043 /* select CR0 and reset PRTMODSx bits */
1045 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1047 if (chipset_mode & PPB_ECP) {
1048 if (chipset_mode & PPB_EPP) {
1049 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1053 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1056 outb(efdr, inb(efdr) | WINB_ECP);
1061 /* select EPP_SPP otherwise */
1062 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1066 ppc->ppc_avm = chipset_mode;
1072 /* exit configuration mode */
1075 switch (ppc->ppc_type) {
1076 case PPC_TYPE_SMCLIKE:
1077 ppc_smclike_setmode(ppc, chipset_mode);
1080 ppc_generic_setmode(ppc, chipset_mode);
1084 return (chipset_mode);
1089 * ppc_generic_detect
1092 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1094 /* default to generic */
1095 ppc->ppc_type = PPC_TYPE_GENERIC;
1098 printf("ppc%d:", ppc->ppc_unit);
1100 if (!chipset_mode) {
1101 /* first, check for ECP */
1102 w_ecr(ppc, PPC_ECR_PS2);
1103 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1104 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1108 /* search for SMC style ECP+EPP mode */
1109 w_ecr(ppc, PPC_ECR_EPP);
1112 /* try to reset EPP timeout bit */
1113 if (ppc_check_epp_timeout(ppc)) {
1114 ppc->ppc_avm |= PPB_EPP;
1116 if (ppc->ppc_avm & PPB_ECP) {
1117 /* SMC like chipset found */
1118 ppc->ppc_model = SMC_LIKE;
1119 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1128 /* restore to standard mode */
1129 w_ecr(ppc, PPC_ECR_STD);
1132 /* XXX try to detect NIBBLE and PS2 modes */
1133 ppc->ppc_avm |= PPB_NIBBLE;
1139 ppc->ppc_avm = chipset_mode;
1145 switch (ppc->ppc_type) {
1146 case PPC_TYPE_SMCLIKE:
1147 ppc_smclike_setmode(ppc, chipset_mode);
1150 ppc_generic_setmode(ppc, chipset_mode);
1154 return (chipset_mode);
1160 * mode is the mode suggested at boot
1163 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1165 #ifdef PPC_PROBE_CHIPSET
1168 /* list of supported chipsets */
1169 int (*chipset_detect[])(struct ppc_data *, int) = {
1171 ppc_smc37c66xgt_detect,
1178 /* if can't find the port and mode not forced return error */
1179 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1180 return (EIO); /* failed, port not present */
1182 /* assume centronics compatible mode is supported */
1183 ppc->ppc_avm = PPB_COMPATIBLE;
1185 #ifdef PPC_PROBE_CHIPSET
1186 /* we have to differenciate available chipset modes,
1187 * chipset running modes and IEEE-1284 operating modes
1189 * after detection, the port must support running in compatible mode
1191 if (ppc->ppc_flags & 0x40) {
1193 printf("ppc: chipset forced to generic\n");
1196 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1198 #ifdef PPC_PROBE_CHIPSET
1200 for (i=0; chipset_detect[i] != NULL; i++) {
1201 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1202 ppc->ppc_mode = mode;
1209 /* configure/detect ECP FIFO */
1210 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1211 ppc_detect_fifo(ppc);
1217 * ppc_exec_microseq()
1219 * Execute a microsequence.
1220 * Microsequence mechanism is supposed to handle fast I/O operations.
1223 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1225 struct ppc_data *ppc = DEVTOSOFTC(dev);
1226 struct ppb_microseq *mi;
1233 register int accum = 0;
1234 register char *ptr = 0;
1236 struct ppb_microseq *stack = 0;
1238 /* microsequence registers are equivalent to PC-like port registers */
1239 #define r_reg(register,ppc) (inb((ppc)->ppc_base + register))
1240 #define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte)
1242 #define INCR_PC (mi ++) /* increment program counter */
1246 switch (mi->opcode) {
1248 cc = r_reg(mi->arg[0].i, ppc);
1249 cc &= (char)mi->arg[2].i; /* clear mask */
1250 cc |= (char)mi->arg[1].i; /* assert mask */
1251 w_reg(mi->arg[0].i, ppc, cc);
1255 case MS_OP_RASSERT_P:
1259 if ((len = mi->arg[0].i) == MS_ACCUM) {
1260 accum = ppc->ppc_accum;
1261 for (; accum; accum--)
1262 w_reg(reg, ppc, *ptr++);
1263 ppc->ppc_accum = accum;
1265 for (i=0; i<len; i++)
1266 w_reg(reg, ppc, *ptr++);
1272 case MS_OP_RFETCH_P:
1274 mask = (char)mi->arg[2].i;
1277 if ((len = mi->arg[0].i) == MS_ACCUM) {
1278 accum = ppc->ppc_accum;
1279 for (; accum; accum--)
1280 *ptr++ = r_reg(reg, ppc) & mask;
1281 ppc->ppc_accum = accum;
1283 for (i=0; i<len; i++)
1284 *ptr++ = r_reg(reg, ppc) & mask;
1291 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1299 /* let's suppose the next instr. is the same */
1301 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1302 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1304 if (mi->opcode == MS_OP_DELAY) {
1305 DELAY(mi->arg[0].i);
1313 tsleep(NULL, PPBPRI, "ppbdelay",
1314 mi->arg[0].i * (hz/1000));
1320 iter = mi->arg[1].i;
1321 p = (char *)mi->arg[2].p;
1323 /* XXX delay limited to 255 us */
1324 for (i=0; i<iter; i++) {
1325 w_reg(reg, ppc, *p++);
1326 DELAY((unsigned char)*p++);
1332 ppc->ppc_accum = mi->arg[0].i;
1337 if (--ppc->ppc_accum > 0)
1344 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1351 if ((cc & (char)mi->arg[0].i) == 0)
1358 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1366 * If the C call returns !0 then end the microseq.
1367 * The current state of ptr is passed to the C function
1369 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1376 ppc->ppc_ptr = (char *)mi->arg[0].p;
1382 panic("%s: too much calls", __FUNCTION__);
1385 /* store the state of the actual
1390 /* jump to the new microsequence */
1391 mi = (struct ppb_microseq *)mi->arg[0].p;
1398 /* retrieve microseq and pc state before the call */
1401 /* reset the stack */
1404 /* XXX return code */
1412 /* can't return to ppb level during the execution
1413 * of a submicrosequence */
1415 panic("%s: can't return to ppb level",
1418 /* update pc for ppb level of execution */
1421 /* return to ppb level of execution */
1425 panic("%s: unknown microsequence opcode 0x%x",
1426 __FUNCTION__, mi->opcode);
1436 device_t dev = (device_t)arg;
1437 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1438 u_char ctr, ecr, str;
1445 printf("![%x/%x/%x]", ctr, ecr, str);
1448 /* don't use ecp mode with IRQENABLE set */
1449 if (ctr & IRQENABLE) {
1453 /* interrupts are generated by nFault signal
1454 * only in ECP mode */
1455 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1456 /* check if ppc driver has programmed the
1457 * nFault interrupt */
1458 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1460 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1461 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1463 /* shall be handled by underlying layers XXX */
1468 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1469 /* disable interrupts (should be done by hardware though) */
1470 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1471 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1474 /* check if DMA completed */
1475 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1480 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1483 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1493 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1495 /* wakeup the waiting process */
1496 wakeup((caddr_t)ppc);
1499 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1501 /* classic interrupt I/O */
1502 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1509 ppc_read(device_t dev, char *buf, int len, int mode)
1515 * Call this function if you want to send data in any advanced mode
1516 * of your parallel port: FIFO, DMA
1518 * If what you want is not possible (no ECP, no DMA...),
1519 * EINVAL is returned
1522 ppc_write(device_t dev, char *buf, int len, int how)
1524 struct ppc_data *ppc = DEVTOSOFTC(dev);
1525 char ecr, ecr_sav, ctr, ctr_sav;
1533 ecr_sav = r_ecr(ppc);
1534 ctr_sav = r_ctr(ppc);
1537 * Send buffer with DMA, FIFO and interrupts
1539 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) {
1541 if (ppc->ppc_dmachan >= 0) {
1543 /* byte mode, no intr, no DMA, dir=0, flush fifo
1545 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1548 /* disable nAck interrupts */
1553 ppc->ppc_dmaflags = 0;
1554 ppc->ppc_dmaddr = (caddr_t)buf;
1555 ppc->ppc_dmacnt = (u_int)len;
1557 switch (ppc->ppc_mode) {
1558 case PPB_COMPATIBLE:
1559 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1560 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1563 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1573 /* enter splhigh() not to be preempted
1574 * by the dma interrupt, we may miss
1575 * the wakeup otherwise
1579 ppc->ppc_dmastat = PPC_DMA_INIT;
1581 /* enable interrupts */
1582 ecr &= ~PPC_SERVICE_INTR;
1583 ppc->ppc_irqstat = PPC_IRQ_DMA;
1592 printf("s%d", ppc->ppc_dmacnt);
1594 ppc->ppc_dmastat = PPC_DMA_STARTED;
1596 /* Wait for the DMA completed interrupt. We hope we won't
1597 * miss it, otherwise a signal will be necessary to unlock the
1602 error = tsleep((caddr_t)ppc,
1603 PPBPRI | PCATCH, "ppcdma", 0);
1605 } while (error == EWOULDBLOCK);
1615 ppc->ppc_dmaflags, ppc->ppc_dmaddr,
1616 ppc->ppc_dmacnt, ppc->ppc_dmachan);
1618 /* no dma, no interrupt, flush the fifo */
1619 w_ecr(ppc, PPC_ECR_RESET);
1621 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1625 /* wait for an empty fifo */
1626 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1628 for (spin=100; spin; spin--)
1629 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1634 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100);
1635 if (error != EWOULDBLOCK) {
1639 /* no dma, no interrupt, flush the fifo */
1640 w_ecr(ppc, PPC_ECR_RESET);
1642 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1649 /* no dma, no interrupt, flush the fifo */
1650 w_ecr(ppc, PPC_ECR_RESET);
1653 error = EINVAL; /* XXX we should FIFO and
1660 /* PDRQ must be kept unasserted until nPDACK is
1661 * deasserted for a minimum of 350ns (SMC datasheet)
1663 * Consequence may be a FIFO that never empty
1667 w_ecr(ppc, ecr_sav);
1668 w_ctr(ppc, ctr_sav);
1674 ppc_reset_epp(device_t dev)
1676 struct ppc_data *ppc = DEVTOSOFTC(dev);
1678 ppc_reset_epp_timeout(ppc);
1684 ppc_setmode(device_t dev, int mode)
1686 struct ppc_data *ppc = DEVTOSOFTC(dev);
1688 switch (ppc->ppc_type) {
1689 case PPC_TYPE_SMCLIKE:
1690 return (ppc_smclike_setmode(ppc, mode));
1693 case PPC_TYPE_GENERIC:
1695 return (ppc_generic_setmode(ppc, mode));
1704 ppc_probe(device_t dev)
1707 static short next_bios_ppc = 0;
1709 struct ppc_data *ppc;
1714 #define PC98_IEEE_1284_DISABLE 0x100
1715 #define PC98_IEEE_1284_PORT 0x140
1717 unsigned int pc98_ieee_mode = 0x00;
1721 /* If we are a PNP device, abort. Otherwise we attach to *everthing* */
1722 if (isa_get_logicalid(dev))
1725 parent = device_get_parent(dev);
1727 /* XXX shall be set after detection */
1728 device_set_desc(dev, "Parallel port");
1731 * Allocate the ppc_data structure.
1733 ppc = DEVTOSOFTC(dev);
1734 bzero(ppc, sizeof(struct ppc_data));
1736 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0;
1737 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0;
1739 /* retrieve ISA parameters */
1740 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL);
1744 * If port not specified, use bios list.
1748 if((next_bios_ppc < BIOS_MAX_PPC) &&
1749 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1750 port = *(BIOS_PORTS+next_bios_ppc++);
1752 device_printf(dev, "parallel port found at 0x%x\n",
1755 device_printf(dev, "parallel port not found.\n");
1759 if (next_bios_ppc == 0) {
1760 /* Use default IEEE-1284 port of NEC PC-98x1 */
1761 port = PC98_IEEE_1284_PORT;
1764 device_printf(dev, "parallel port found at 0x%x\n",
1768 bus_set_resource(dev, SYS_RES_IOPORT, 0, port, IO_LPTSIZE);
1773 * There isn't a bios list on alpha. Put it in the usual place.
1776 bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc, IO_LPTSIZE);
1780 /* IO port is mandatory */
1781 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1782 &ppc->rid_ioport, 0, ~0,
1783 IO_LPTSIZE, RF_ACTIVE);
1784 if (ppc->res_ioport == 0) {
1785 device_printf(dev, "cannot reserve I/O port range\n");
1788 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1790 ppc->ppc_flags = device_get_flags(dev);
1792 if (!(ppc->ppc_flags & 0x20)) {
1793 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq,
1794 0ul, ~0ul, 1, RF_SHAREABLE);
1795 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq,
1796 0ul, ~0ul, 1, RF_ACTIVE);
1800 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1802 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1804 ppc->ppc_unit = device_get_unit(dev);
1805 ppc->ppc_model = GENERIC;
1807 ppc->ppc_mode = PPB_COMPATIBLE;
1808 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1810 ppc->ppc_type = PPC_TYPE_GENERIC;
1814 * IEEE STD 1284 Function Check and Enable
1815 * for default IEEE-1284 port of NEC PC-98x1
1817 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) &&
1818 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1819 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1820 pc98_ieee_mode = tmp;
1821 if ((tmp & 0x10) == 0x10) {
1822 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1823 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1824 if ((tmp & 0x10) == 0x10)
1827 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1828 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1829 if ((tmp & 0x10) != 0x10)
1832 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1837 * Try to detect the chipset and its mode.
1839 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1846 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) &&
1847 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1848 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
1851 if (ppc->res_irq != 0) {
1852 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1855 if (ppc->res_ioport != 0) {
1856 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1858 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1861 if (ppc->res_drq != 0) {
1862 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1864 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1871 ppc_attach(device_t dev)
1873 struct ppc_data *ppc = DEVTOSOFTC(dev);
1876 device_t parent = device_get_parent(dev);
1878 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1879 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1880 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1881 ppc_epp_protocol[ppc->ppc_epp] : "");
1884 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1885 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1887 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1888 /* acquire the DMA channel forever */ /* XXX */
1889 isa_dma_acquire(ppc->ppc_dmachan);
1890 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1893 /* add ppbus as a child of this isa to parallel bridge */
1894 ppbus = device_add_child(dev, "ppbus", -1);
1897 * Probe the ppbus and attach devices found.
1899 device_probe_and_attach(ppbus);
1901 /* register the ppc interrupt handler as default */
1903 /* default to the tty mask for registration */ /* XXX */
1904 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY,
1905 ppcintr, dev, &ppc->intr_cookie) == 0) {
1907 /* remember the ppcintr is registered */
1908 ppc->ppc_registered = 1;
1916 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1918 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
1921 outsb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1924 outsw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1927 outsl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1930 insb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1933 insw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1936 insl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt);
1939 return (r_dtr(ppc));
1942 return (r_str(ppc));
1945 return (r_ctr(ppc));
1948 return (r_epp_A(ppc));
1951 return (r_epp_D(ppc));
1954 return (r_ecr(ppc));
1957 return (r_fifo(ppc));
1981 panic("%s: unknown I/O operation", __FUNCTION__);
1985 return (0); /* not significative */
1989 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1991 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1994 case PPC_IVAR_EPP_PROTO:
1995 *val = (u_long)ppc->ppc_epp;
1998 *val = (u_long)ppc->ppc_irq;
2008 * Resource is useless here since ppbus devices' interrupt handlers are
2009 * multiplexed to the same resource initially allocated by ppc
2012 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2013 void (*ihand)(void *), void *arg, void **cookiep)
2016 struct ppc_data *ppc = DEVTOSOFTC(bus);
2018 if (ppc->ppc_registered) {
2019 /* XXX refuse registration if DMA is in progress */
2021 /* first, unregister the default interrupt handler */
2022 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
2023 bus, ppc->res_irq, ppc->intr_cookie)))
2026 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2027 /* ppc->res_irq); */
2029 /* DMA/FIFO operation won't be possible anymore */
2030 ppc->ppc_registered = 0;
2033 /* pass registration to the upper layer, ignore the incoming resource */
2034 return (BUS_SETUP_INTR(device_get_parent(bus), child,
2035 r, flags, ihand, arg, cookiep));
2039 * When no underlying device has a registered interrupt, register the ppc
2043 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
2046 struct ppc_data *ppc = DEVTOSOFTC(bus);
2047 device_t parent = device_get_parent(bus);
2049 /* pass unregistration to the upper layer */
2050 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2053 /* default to the tty mask for registration */ /* XXX */
2055 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2056 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) {
2058 /* remember the ppcintr is registered */
2059 ppc->ppc_registered = 1;
2065 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0);