2 * Copyright (c) 1997, 1998 Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
36 #include <sys/kernel.h>
38 #include <machine/clock.h>
41 #include <vm/vm_param.h>
44 #include <i386/isa/isa_device.h>
45 #include <pc98/pc98/pc98.h>
47 #include <dev/ppbus/ppbconf.h>
48 #include <dev/ppbus/ppb_msq.h>
50 #include <pc98/pc98/ppcreg.h>
54 #define LOG_PPC(function, ppc, string) \
55 if (bootverbose) printf("%s: %s\n", function, string)
57 static int ppcprobe(struct isa_device *);
58 static int ppcattach(struct isa_device *);
60 struct isa_driver ppcdriver = {
61 ppcprobe, ppcattach, "ppc"
64 static struct ppc_data *ppcdata[NPPC];
67 static char *ppc_types[] = {
68 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
69 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0
72 /* list of available modes */
73 static char *ppc_avms[] = {
74 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
75 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
76 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
77 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
80 /* list of current executing modes
81 * Note that few modes do not actually exist.
83 static char *ppc_modes[] = {
84 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
85 "EPP", "EPP", "EPP", "ECP",
86 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
87 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
90 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
93 * BIOS printer list - used by BIOS probe.
95 #define BIOS_PPC_PORTS 0x408
96 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
97 #define BIOS_MAX_PPC 4
100 * All these functions are default actions for IN/OUT operations.
101 * They may be redefined if needed.
103 static void ppc_outsb_epp(int unit, char *addr, int cnt) {
104 outsb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
105 static void ppc_outsw_epp(int unit, char *addr, int cnt) {
106 outsw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
107 static void ppc_outsl_epp(int unit, char *addr, int cnt) {
108 outsl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
109 static void ppc_insb_epp(int unit, char *addr, int cnt) {
110 insb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
111 static void ppc_insw_epp(int unit, char *addr, int cnt) {
112 insw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
113 static void ppc_insl_epp(int unit, char *addr, int cnt) {
114 insl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
116 static u_char ppc_rdtr(int unit) { return r_dtr(ppcdata[unit]); }
117 static u_char ppc_rstr(int unit) { return r_str(ppcdata[unit]); }
118 static u_char ppc_rctr(int unit) { return r_ctr(ppcdata[unit]); }
119 static u_char ppc_repp_A(int unit) { return r_epp_A(ppcdata[unit]); }
120 static u_char ppc_repp_D(int unit) { return r_epp_D(ppcdata[unit]); }
121 static u_char ppc_recr(int unit) { return r_ecr(ppcdata[unit]); }
122 static u_char ppc_rfifo(int unit) { return r_fifo(ppcdata[unit]); }
124 static void ppc_wdtr(int unit, char byte) { w_dtr(ppcdata[unit], byte); }
125 static void ppc_wstr(int unit, char byte) { w_str(ppcdata[unit], byte); }
126 static void ppc_wctr(int unit, char byte) { w_ctr(ppcdata[unit], byte); }
127 static void ppc_wepp_A(int unit, char byte) { w_epp_A(ppcdata[unit], byte); }
128 static void ppc_wepp_D(int unit, char byte) { w_epp_D(ppcdata[unit], byte); }
129 static void ppc_wecr(int unit, char byte) { w_ecr(ppcdata[unit], byte); }
130 static void ppc_wfifo(int unit, char byte) { w_fifo(ppcdata[unit], byte); }
132 static void ppc_reset_epp_timeout(int);
133 static void ppc_ecp_sync(int);
134 static ointhand2_t ppcintr;
136 static int ppc_exec_microseq(int, struct ppb_microseq **);
137 static int ppc_generic_setmode(int, int);
138 static int ppc_smclike_setmode(int, int);
140 static int ppc_read(int, char *, int, int);
141 static int ppc_write(int, char *, int, int);
143 static struct ppb_adapter ppc_smclike_adapter = {
145 0, /* no intr handler, filled by chipset dependent code */
147 ppc_reset_epp_timeout, ppc_ecp_sync,
151 ppc_smclike_setmode, ppc_read, ppc_write,
153 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp,
154 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp,
156 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp_A, ppc_repp_D, ppc_recr, ppc_rfifo,
157 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp_A, ppc_wepp_D, ppc_wecr, ppc_wfifo
160 static struct ppb_adapter ppc_generic_adapter = {
162 0, /* no intr handler, filled by chipset dependent code */
164 ppc_reset_epp_timeout, ppc_ecp_sync,
168 ppc_generic_setmode, ppc_read, ppc_write,
170 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp,
171 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp,
173 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp_A, ppc_repp_D, ppc_recr, ppc_rfifo,
174 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp_A, ppc_wepp_D, ppc_wecr, ppc_wfifo
181 ppc_ecp_sync(int unit) {
183 struct ppc_data *ppc = ppcdata[unit];
186 if (!(ppc->ppc_avm & PPB_ECP))
190 if ((r & 0xe0) != PPC_ECR_EPP)
193 for (i = 0; i < 100; i++) {
200 printf("ppc%d: ECP sync failed as data still " \
201 "present in FIFO.\n", unit);
209 * Detect parallel port FIFO
212 ppc_detect_fifo(struct ppc_data *ppc)
215 char ctr_sav, ctr, cc;
219 ecr_sav = r_ecr(ppc);
220 ctr_sav = r_ctr(ppc);
222 /* enter ECP configuration mode, no interrupt, no DMA */
225 /* read PWord size - transfers in FIFO mode must be PWord aligned */
226 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
228 /* XXX 16 and 32 bits implementations not supported */
229 if (ppc->ppc_pword != PPC_PWORD_8) {
230 LOG_PPC(__FUNCTION__, ppc, "PWord not supported");
234 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
236 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
238 /* enter ECP test mode, no interrupt, no DMA */
242 for (i=0; i<1024; i++) {
243 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
249 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO");
253 /* enable interrupts, no DMA */
256 /* determine readIntrThreshold
257 * fill the FIFO until serviceIntr is set
259 for (i=0; i<1024; i++) {
260 w_fifo(ppc, (char)i);
261 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
262 /* readThreshold reached */
265 if (r_ecr(ppc) & PPC_FIFO_FULL) {
272 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO");
276 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
277 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
278 w_ecr(ppc, 0xd0); /* enable interrupts */
280 /* determine writeIntrThreshold
281 * empty the FIFO until serviceIntr is set
283 for (i=ppc->ppc_fifo; i>0; i--) {
284 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
285 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO");
288 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
289 /* writeIntrThreshold reached */
290 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
292 /* if FIFO empty before the last byte, error */
293 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
294 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO");
299 /* FIFO must be empty after the last byte */
300 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
301 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO");
318 ppc_detect_port(struct ppc_data *ppc)
321 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
323 if (r_dtr(ppc) != 0xaa)
332 * Probe for a Natsemi PC873xx-family part.
334 * References in this function are to the National Semiconductor
335 * PC87332 datasheet TL/C/11930, May 1995 revision.
337 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
338 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
339 static int pc873xx_irqtab[] = {5, 7, 5, 0};
341 static int pc873xx_regstab[] = {
342 PC873_FER, PC873_FAR, PC873_PTR,
343 PC873_FCR, PC873_PCR, PC873_PMC,
344 PC873_TUP, PC873_SID, PC873_PNP0,
345 PC873_PNP1, PC873_LPTBA, -1
348 static char *pc873xx_rnametab[] = {
349 "FER", "FAR", "PTR", "FCR", "PCR",
350 "PMC", "TUP", "SID", "PNP0", "PNP1",
355 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
357 static int index = 0;
359 int ptr, pcr, val, i;
361 while ((idport = pc873xx_basetab[index++])) {
363 /* XXX should check first to see if this location is already claimed */
366 * Pull the 873xx through the power-on ID cycle (2.2,1.).
367 * We can't use this to locate the chip as it may already have
368 * been used by the BIOS.
370 (void)inb(idport); (void)inb(idport);
371 (void)inb(idport); (void)inb(idport);
374 * Read the SID byte. Possible values are :
380 outb(idport, PC873_SID);
381 val = inb(idport + 1);
382 if ((val & 0xf0) == 0x10) {
383 ppc->ppc_type = NS_PC87332;
384 } else if ((val & 0xf8) == 0x70) {
385 ppc->ppc_type = NS_PC87306;
386 } else if ((val & 0xf8) == 0x50) {
387 ppc->ppc_type = NS_PC87334;
389 if (bootverbose && (val != 0xff))
390 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
391 continue ; /* not recognised */
394 /* print registers */
397 for (i=0; pc873xx_regstab[i] != -1; i++) {
398 outb(idport, pc873xx_regstab[i]);
399 printf(" %s=0x%x", pc873xx_rnametab[i],
400 inb(idport + 1) & 0xff);
406 * We think we have one. Is it enabled and where we want it to be?
408 outb(idport, PC873_FER);
409 val = inb(idport + 1);
410 if (!(val & PC873_PPENABLE)) {
412 printf("PC873xx parallel port disabled\n");
415 outb(idport, PC873_FAR);
416 val = inb(idport + 1) & 0x3;
417 /* XXX we should create a driver instance for every port found */
418 if (pc873xx_porttab[val] != ppc->ppc_base) {
420 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
421 pc873xx_porttab[val], ppc->ppc_base);
425 outb(idport, PC873_PTR);
426 ptr = inb(idport + 1);
428 /* get irq settings */
429 if (ppc->ppc_base == 0x378)
430 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
432 irq = pc873xx_irqtab[val];
435 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
438 * Check if irq settings are correct
440 if (irq != ppc->ppc_irq) {
442 * If the chipset is not locked and base address is 0x378,
443 * we have another chance
445 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
446 if (ppc->ppc_irq == 7) {
447 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
448 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
450 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
451 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
454 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
457 printf("PC873xx sorry, can't change irq setting\n");
461 printf("PC873xx irq settings are correct\n");
464 outb(idport, PC873_PCR);
465 pcr = inb(idport + 1);
467 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
469 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
471 ppc->ppc_avm |= PPB_NIBBLE;
475 if (pcr & PC873_EPPEN) {
476 ppc->ppc_avm |= PPB_EPP;
481 if (pcr & PC873_EPP19)
482 ppc->ppc_epp = EPP_1_9;
484 ppc->ppc_epp = EPP_1_7;
486 if ((ppc->ppc_type == NS_PC87332) && bootverbose) {
487 outb(idport, PC873_PTR);
488 ptr = inb(idport + 1);
489 if (ptr & PC873_EPPRDIR)
490 printf(", Regular mode");
492 printf(", Automatic mode");
494 } else if (pcr & PC873_ECPEN) {
495 ppc->ppc_avm |= PPB_ECP;
499 if (pcr & PC873_ECPCLK) { /* XXX */
500 ppc->ppc_avm |= PPB_PS2;
505 outb(idport, PC873_PTR);
506 ptr = inb(idport + 1);
507 if (ptr & PC873_EXTENDED) {
508 ppc->ppc_avm |= PPB_SPP;
515 printf("PC873xx unlocked");
517 if (chipset_mode & PPB_ECP) {
518 if ((chipset_mode & PPB_EPP) && bootverbose)
519 printf(", ECP+EPP not supported");
522 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
523 outb(idport + 1, pcr);
524 outb(idport + 1, pcr);
529 } else if (chipset_mode & PPB_EPP) {
530 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
531 pcr |= (PC873_EPPEN | PC873_EPP19);
532 outb(idport + 1, pcr);
533 outb(idport + 1, pcr);
535 ppc->ppc_epp = EPP_1_9; /* XXX */
540 /* enable automatic direction turnover */
541 if (ppc->ppc_type == NS_PC87332) {
542 outb(idport, PC873_PTR);
543 ptr = inb(idport + 1);
544 ptr &= ~PC873_EPPRDIR;
545 outb(idport + 1, ptr);
546 outb(idport + 1, ptr);
549 printf(", Automatic mode");
552 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
553 outb(idport + 1, pcr);
554 outb(idport + 1, pcr);
556 /* configure extended bit in PTR */
557 outb(idport, PC873_PTR);
558 ptr = inb(idport + 1);
560 if (chipset_mode & PPB_PS2) {
561 ptr |= PC873_EXTENDED;
567 /* default to NIBBLE mode */
568 ptr &= ~PC873_EXTENDED;
573 outb(idport + 1, ptr);
574 outb(idport + 1, ptr);
577 ppc->ppc_avm = chipset_mode;
583 ppc->ppc_link.adapter = &ppc_generic_adapter;
584 ppc_generic_setmode(ppc->ppc_unit, chipset_mode);
586 return(chipset_mode);
592 ppc_check_epp_timeout(struct ppc_data *ppc)
594 ppc_reset_epp_timeout(ppc->ppc_unit);
596 return (!(r_str(ppc) & TIMEOUT));
600 * ppc_smc37c66xgt_detect
602 * SMC FDC37C66xGT configuration.
605 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
610 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
612 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
615 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
618 * Detection: enter configuration mode and read CRD register.
622 outb(csr, SMC665_iCODE);
623 outb(csr, SMC665_iCODE);
627 if (inb(cio) == 0x65) {
632 for (i = 0; i < 2; i++) {
634 outb(csr, SMC666_iCODE);
635 outb(csr, SMC666_iCODE);
639 if (inb(cio) == 0x66) {
644 /* Another chance, CSR may be hard-configured to be at 0x370 */
650 * If chipset not found, do not continue.
658 /* read the port's address: bits 0 and 1 of CR1 */
659 r = inb(cio) & SMC_CR1_ADDR;
660 if (port_address[(int)r] != ppc->ppc_base)
663 ppc->ppc_type = type;
666 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
667 * If SPP mode is detected, try to set ECP+EPP mode
672 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
676 printf(" CR4=0x%x", inb(cio) & 0xff);
683 /* autodetect mode */
685 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
686 if (type == SMC_37C666GT) {
687 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
689 printf(" configuration hardwired, supposing " \
693 if ((inb(cio) & SMC_CR1_MODE) == 0) {
694 /* already in extended parallel port mode, read CR4 */
696 r = (inb(cio) & SMC_CR4_EMODE);
700 ppc->ppc_avm |= PPB_SPP;
706 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
712 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
718 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
720 printf(" ECP+EPP SPP");
724 /* not an extended port mode */
725 ppc->ppc_avm |= PPB_SPP;
732 ppc->ppc_avm = chipset_mode;
734 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
735 if (type == SMC_37C666GT)
739 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
740 /* do not use ECP when the mode is not forced to */
741 outb(cio, r | SMC_CR1_MODE);
745 /* an extended mode is selected */
746 outb(cio, r & ~SMC_CR1_MODE);
748 /* read CR4 register and reset mode field */
750 r = inb(cio) & ~SMC_CR4_EMODE;
752 if (chipset_mode & PPB_ECP) {
753 if (chipset_mode & PPB_EPP) {
754 outb(cio, r | SMC_ECPEPP);
758 outb(cio, r | SMC_ECP);
764 outb(cio, r | SMC_EPPSPP);
769 ppc->ppc_avm = chipset_mode;
772 /* set FIFO threshold to 16 */
773 if (ppc->ppc_avm & PPB_ECP) {
784 if (ppc->ppc_avm & PPB_EPP) {
790 * Set the EPP protocol...
791 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
793 if (ppc->ppc_epp == EPP_1_9)
794 outb(cio, (r & ~SMC_CR4_EPPTYPE));
796 outb(cio, (r | SMC_CR4_EPPTYPE));
799 /* end config mode */
802 ppc->ppc_link.adapter = &ppc_smclike_adapter;
803 ppc_smclike_setmode(ppc->ppc_unit, chipset_mode);
805 return (chipset_mode);
809 * Winbond W83877F stuff
811 * EFER: extended function enable register
812 * EFIR: extended function index register
813 * EFDR: extended function data register
815 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
816 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
818 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
819 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
820 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
821 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
824 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
827 unsigned char r, hefere, hefras;
829 for (i = 0; i < 4; i ++) {
830 /* first try to enable configuration registers */
831 efer = w83877f_efers[i];
833 /* write the key to the EFER */
834 for (j = 0; j < w83877f_keyiter[i]; j ++)
835 outb (efer, w83877f_keys[i]);
837 /* then check HEFERE and HEFRAS bits */
839 hefere = inb(efdr) & WINB_HEFERE;
842 hefras = inb(efdr) & WINB_HEFRAS;
846 * 0 1 write 89h to 250h (power-on default)
847 * 1 0 write 86h twice to 3f0h
848 * 1 1 write 87h twice to 3f0h
849 * 0 0 write 88h to 250h
851 if ((hefere | hefras) == w83877f_hefs[i])
855 return (-1); /* failed */
858 /* check base port address - read from CR23 */
860 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
863 /* read CHIP ID from CR9/bits0-3 */
866 switch (inb(efdr) & WINB_CHIPID) {
867 case WINB_W83877F_ID:
868 ppc->ppc_type = WINB_W83877F;
871 case WINB_W83877AF_ID:
872 ppc->ppc_type = WINB_W83877AF;
876 ppc->ppc_type = WINB_UNKNOWN;
880 /* dump of registers */
881 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
882 for (i = 0; i <= 0xd; i ++) {
884 printf("0x%x ", inb(efdr));
886 for (i = 0x10; i <= 0x17; i ++) {
888 printf("0x%x ", inb(efdr));
891 printf("0x%x ", inb(efdr));
892 for (i = 0x20; i <= 0x29; i ++) {
894 printf("0x%x ", inb(efdr));
897 printf("ppc%d:", ppc->ppc_unit);
900 ppc->ppc_link.adapter = &ppc_generic_adapter;
903 /* autodetect mode */
907 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
911 r |= (inb(efdr) & WINB_PRTMODS2);
916 printf("ppc%d: W83757 compatible mode\n",
918 return (-1); /* generic or SMC-like */
925 printf(" not in parallel port mode\n");
928 case (WINB_PARALLEL | WINB_EPP_SPP):
929 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
934 case (WINB_PARALLEL | WINB_ECP):
935 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
940 case (WINB_PARALLEL | WINB_ECP_EPP):
941 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
942 ppc->ppc_link.adapter = &ppc_smclike_adapter;
945 printf(" ECP+EPP SPP");
948 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r);
954 /* select CR9 and set PRTMODS2 bit */
956 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
958 /* select CR0 and reset PRTMODSx bits */
960 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
962 if (chipset_mode & PPB_ECP) {
963 if (chipset_mode & PPB_EPP) {
964 outb(efdr, inb(efdr) | WINB_ECP_EPP);
968 ppc->ppc_link.adapter = &ppc_smclike_adapter;
971 outb(efdr, inb(efdr) | WINB_ECP);
976 /* select EPP_SPP otherwise */
977 outb(efdr, inb(efdr) | WINB_EPP_SPP);
981 ppc->ppc_avm = chipset_mode;
987 /* exit configuration mode */
990 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode);
992 return (chipset_mode);
999 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1001 /* default to generic */
1002 ppc->ppc_link.adapter = &ppc_generic_adapter;
1005 printf("ppc%d:", ppc->ppc_unit);
1007 if (!chipset_mode) {
1008 /* first, check for ECP */
1009 w_ecr(ppc, PPC_ECR_PS2);
1010 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1011 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1015 /* search for SMC style ECP+EPP mode */
1016 w_ecr(ppc, PPC_ECR_EPP);
1019 /* try to reset EPP timeout bit */
1020 if (ppc_check_epp_timeout(ppc)) {
1021 ppc->ppc_avm |= PPB_EPP;
1023 if (ppc->ppc_avm & PPB_ECP) {
1024 /* SMC like chipset found */
1025 ppc->ppc_type = SMC_LIKE;
1026 ppc->ppc_link.adapter = &ppc_smclike_adapter;
1035 /* restore to standard mode */
1036 w_ecr(ppc, PPC_ECR_STD);
1039 /* XXX try to detect NIBBLE and PS2 modes */
1040 ppc->ppc_avm |= PPB_NIBBLE;
1046 ppc->ppc_avm = chipset_mode;
1052 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode);
1054 return (chipset_mode);
1060 * mode is the mode suggested at boot
1063 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1067 /* list of supported chipsets */
1068 int (*chipset_detect[])(struct ppc_data *, int) = {
1070 ppc_smc37c66xgt_detect,
1076 /* if can't find the port and mode not forced return error */
1077 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1078 return (EIO); /* failed, port not present */
1080 /* assume centronics compatible mode is supported */
1081 ppc->ppc_avm = PPB_COMPATIBLE;
1083 /* we have to differenciate available chipset modes,
1084 * chipset running modes and IEEE-1284 operating modes
1086 * after detection, the port must support running in compatible mode
1088 if (ppc->ppc_flags & 0x40) {
1090 printf("ppc: chipset forced to generic\n");
1092 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1095 for (i=0; chipset_detect[i] != NULL; i++) {
1096 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1097 ppc->ppc_mode = mode;
1103 /* configure/detect ECP FIFO */
1104 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1105 ppc_detect_fifo(ppc);
1111 * ppc_exec_microseq()
1113 * Execute a microsequence.
1114 * Microsequence mechanism is supposed to handle fast I/O operations.
1117 ppc_exec_microseq(int unit, struct ppb_microseq **p_msq)
1119 struct ppc_data *ppc = ppcdata[unit];
1120 struct ppb_microseq *mi;
1127 register int accum = 0;
1128 register char *ptr = 0;
1130 struct ppb_microseq *stack = 0;
1132 /* microsequence registers are equivalent to PC-like port registers */
1133 #define r_reg(register,ppc) (inb((ppc)->ppc_base + register))
1134 #define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte)
1136 #define INCR_PC (mi ++) /* increment program counter */
1140 switch (mi->opcode) {
1142 cc = r_reg(mi->arg[0].i, ppc);
1143 cc &= (char)mi->arg[2].i; /* clear mask */
1144 cc |= (char)mi->arg[1].i; /* assert mask */
1145 w_reg(mi->arg[0].i, ppc, cc);
1149 case MS_OP_RASSERT_P:
1153 if ((len = mi->arg[0].i) == MS_ACCUM) {
1154 accum = ppc->ppc_accum;
1155 for (; accum; accum--)
1156 w_reg(reg, ppc, *ptr++);
1157 ppc->ppc_accum = accum;
1159 for (i=0; i<len; i++)
1160 w_reg(reg, ppc, *ptr++);
1166 case MS_OP_RFETCH_P:
1168 mask = (char)mi->arg[2].i;
1171 if ((len = mi->arg[0].i) == MS_ACCUM) {
1172 accum = ppc->ppc_accum;
1173 for (; accum; accum--)
1174 *ptr++ = r_reg(reg, ppc) & mask;
1175 ppc->ppc_accum = accum;
1177 for (i=0; i<len; i++)
1178 *ptr++ = r_reg(reg, ppc) & mask;
1185 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1193 /* let's suppose the next instr. is the same */
1195 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1196 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1198 if (mi->opcode == MS_OP_DELAY) {
1199 DELAY(mi->arg[0].i);
1207 tsleep(NULL, PPBPRI, "ppbdelay",
1208 mi->arg[0].i * (hz/1000));
1214 iter = mi->arg[1].i;
1215 p = (char *)mi->arg[2].p;
1217 /* XXX delay limited to 255 us */
1218 for (i=0; i<iter; i++) {
1219 w_reg(reg, ppc, *p++);
1220 DELAY((unsigned char)*p++);
1226 ppc->ppc_accum = mi->arg[0].i;
1231 if (--ppc->ppc_accum > 0)
1238 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1245 if ((cc & (char)mi->arg[0].i) == 0)
1252 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1260 * If the C call returns !0 then end the microseq.
1261 * The current state of ptr is passed to the C function
1263 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1270 ppc->ppc_ptr = (char *)mi->arg[0].p;
1276 panic("%s: too much calls", __FUNCTION__);
1279 /* store the state of the actual
1284 /* jump to the new microsequence */
1285 mi = (struct ppb_microseq *)mi->arg[0].p;
1292 /* retrieve microseq and pc state before the call */
1295 /* reset the stack */
1298 /* XXX return code */
1306 /* can't return to ppb level during the execution
1307 * of a submicrosequence */
1309 panic("%s: can't return to ppb level",
1312 /* update pc for ppb level of execution */
1315 /* return to ppb level of execution */
1319 panic("%s: unknown microsequence opcode 0x%x",
1320 __FUNCTION__, mi->opcode);
1330 struct ppc_data *ppc = ppcdata[unit];
1331 u_char ctr, ecr, str;
1338 printf("![%x/%x/%x]", ctr, ecr, str);
1341 /* don't use ecp mode with IRQENABLE set */
1342 if (ctr & IRQENABLE) {
1343 /* call upper code */
1344 ppb_intr(&ppc->ppc_link);
1348 /* interrupts are generated by nFault signal
1349 * only in ECP mode */
1350 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1351 /* check if ppc driver has programmed the
1352 * nFault interrupt */
1353 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1355 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1356 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1358 /* call upper code */
1359 ppb_intr(&ppc->ppc_link);
1364 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1365 /* disable interrupts (should be done by hardware though) */
1366 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1367 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1370 /* check if DMA completed */
1371 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1376 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1379 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1389 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1391 /* wakeup the waiting process */
1392 wakeup((caddr_t)ppc);
1395 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1397 /* classic interrupt I/O */
1398 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1406 ppc_read(int unit, char *buf, int len, int mode)
1412 * Call this function if you want to send data in any advanced mode
1413 * of your parallel port: FIFO, DMA
1415 * If what you want is not possible (no ECP, no DMA...),
1416 * EINVAL is returned
1419 ppc_write(int unit, char *buf, int len, int how)
1421 struct ppc_data *ppc = ppcdata[unit];
1422 char ecr, ecr_sav, ctr, ctr_sav;
1430 ecr_sav = r_ecr(ppc);
1431 ctr_sav = r_ctr(ppc);
1434 * Send buffer with DMA, FIFO and interrupts
1436 if (ppc->ppc_avm & PPB_ECP) {
1438 if (ppc->ppc_dmachan >= 0) {
1440 /* byte mode, no intr, no DMA, dir=0, flush fifo
1442 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1445 /* disable nAck interrupts */
1450 ppc->ppc_dmaflags = 0;
1451 ppc->ppc_dmaddr = (caddr_t)buf;
1452 ppc->ppc_dmacnt = (u_int)len;
1454 switch (ppc->ppc_mode) {
1455 case PPB_COMPATIBLE:
1456 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1457 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1460 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1470 /* enter splhigh() not to be preempted
1471 * by the dma interrupt, we may miss
1472 * the wakeup otherwise
1476 ppc->ppc_dmastat = PPC_DMA_INIT;
1478 /* enable interrupts */
1479 ecr &= ~PPC_SERVICE_INTR;
1480 ppc->ppc_irqstat = PPC_IRQ_DMA;
1489 printf("s%d", ppc->ppc_dmacnt);
1491 ppc->ppc_dmastat = PPC_DMA_STARTED;
1493 /* Wait for the DMA completed interrupt. We hope we won't
1494 * miss it, otherwise a signal will be necessary to unlock the
1499 error = tsleep((caddr_t)ppc,
1500 PPBPRI | PCATCH, "ppcdma", 0);
1502 } while (error == EWOULDBLOCK);
1512 ppc->ppc_dmaflags, ppc->ppc_dmaddr,
1513 ppc->ppc_dmacnt, ppc->ppc_dmachan);
1515 /* no dma, no interrupt, flush the fifo */
1516 w_ecr(ppc, PPC_ECR_RESET);
1518 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1522 /* wait for an empty fifo */
1523 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1525 for (spin=100; spin; spin--)
1526 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1531 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100);
1532 if (error != EWOULDBLOCK) {
1536 /* no dma, no interrupt, flush the fifo */
1537 w_ecr(ppc, PPC_ECR_RESET);
1539 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1546 /* no dma, no interrupt, flush the fifo */
1547 w_ecr(ppc, PPC_ECR_RESET);
1550 error = EINVAL; /* XXX we should FIFO and
1557 /* PDRQ must be kept unasserted until nPDACK is
1558 * deasserted for a minimum of 350ns (SMC datasheet)
1560 * Consequence may be a FIFO that never empty
1564 w_ecr(ppc, ecr_sav);
1565 w_ctr(ppc, ctr_sav);
1571 * Configure current operating mode
1574 ppc_generic_setmode(int unit, int mode)
1576 struct ppc_data *ppc = ppcdata[unit];
1579 /* check if mode is available */
1580 if (mode && !(ppc->ppc_avm & mode))
1583 /* if ECP mode, configure ecr register */
1584 if (ppc->ppc_avm & PPB_ECP) {
1585 /* return to byte mode (keeping direction bit),
1586 * no interrupt, no DMA to be able to change to
1589 w_ecr(ppc, PPC_ECR_RESET);
1590 ecr = PPC_DISABLE_INTR;
1594 else if (mode & PPB_ECP)
1595 /* select ECP mode */
1597 else if (mode & PPB_PS2)
1598 /* select PS2 mode with ECP */
1601 /* select COMPATIBLE/NIBBLE mode */
1607 ppc->ppc_mode = mode;
1613 * The ppc driver is free to choose options like FIFO or DMA
1614 * if ECP mode is available.
1616 * The 'RAW' option allows the upper drivers to force the ppc mode
1617 * even with FIFO, DMA available.
1620 ppc_smclike_setmode(int unit, int mode)
1622 struct ppc_data *ppc = ppcdata[unit];
1625 /* check if mode is available */
1626 if (mode && !(ppc->ppc_avm & mode))
1629 /* if ECP mode, configure ecr register */
1630 if (ppc->ppc_avm & PPB_ECP) {
1631 /* return to byte mode (keeping direction bit),
1632 * no interrupt, no DMA to be able to change to
1635 w_ecr(ppc, PPC_ECR_RESET);
1636 ecr = PPC_DISABLE_INTR;
1639 /* select EPP mode */
1641 else if (mode & PPB_ECP)
1642 /* select ECP mode */
1644 else if (mode & PPB_PS2)
1645 /* select PS2 mode with ECP */
1648 /* select COMPATIBLE/NIBBLE mode */
1654 ppc->ppc_mode = mode;
1660 * EPP timeout, according to the PC87332 manual
1661 * Semantics of clearing EPP timeout bit.
1662 * PC87332 - reading SPP_STR does it...
1663 * SMC - write 1 to EPP timeout bit XXX
1664 * Others - (?) write 0 to EPP timeout bit
1667 ppc_reset_epp_timeout(int unit)
1669 struct ppc_data *ppc = ppcdata[unit];
1673 w_str(ppc, r | 0x1);
1674 w_str(ppc, r & 0xfe);
1680 ppcprobe(struct isa_device *dvp)
1682 static short next_bios_ppc = 0;
1683 struct ppc_data *ppc;
1685 #define PC98_IEEE_1284_DISABLE 0x100
1686 #define PC98_IEEE_1284_PORT 0x140
1688 unsigned int pc98_ieee_mode = 0x00;
1693 * If port not specified, use bios list.
1695 if(dvp->id_iobase < 0) {
1697 if((next_bios_ppc < BIOS_MAX_PPC) &&
1698 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1699 dvp->id_iobase = *(BIOS_PORTS+next_bios_ppc++);
1701 printf("ppc: parallel port found at 0x%x\n",
1705 if(next_bios_ppc == 0) {
1706 /* Use default IEEE-1284 port of NEC PC-98x1 */
1707 dvp->id_iobase = PC98_IEEE_1284_PORT;
1710 printf("ppc: parallel port found at 0x%x\n",
1718 * Port was explicitly specified.
1719 * This allows probing of ports unknown to the BIOS.
1723 * Allocate the ppc_data structure.
1725 ppc = malloc(sizeof(struct ppc_data), M_DEVBUF, M_NOWAIT);
1727 printf("ppc: cannot malloc!\n");
1730 bzero(ppc, sizeof(struct ppc_data));
1732 ppc->ppc_base = dvp->id_iobase;
1733 ppc->ppc_unit = dvp->id_unit;
1734 ppc->ppc_type = GENERIC;
1736 /* store boot flags */
1737 ppc->ppc_flags = dvp->id_flags;
1739 ppc->ppc_mode = PPB_COMPATIBLE;
1740 ppc->ppc_epp = (dvp->id_flags & 0x10) >> 4;
1743 * XXX Try and detect if interrupts are working
1745 if (!(dvp->id_flags & 0x20) && dvp->id_irq)
1746 ppc->ppc_irq = ffs(dvp->id_irq) - 1;
1748 ppc->ppc_dmachan = dvp->id_drq;
1750 ppcdata[ppc->ppc_unit] = ppc;
1754 * Link the Parallel Port Chipset (adapter) to
1755 * the future ppbus. Default to a generic chipset
1757 ppc->ppc_link.adapter_unit = ppc->ppc_unit;
1758 ppc->ppc_link.adapter = &ppc_generic_adapter;
1762 * IEEE STD 1284 Function Check and Enable
1763 * for default IEEE-1284 port of NEC PC-98x1
1765 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) &&
1766 !(dvp->id_flags & PC98_IEEE_1284_DISABLE)) {
1767 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1768 pc98_ieee_mode = tmp;
1769 if ((tmp & 0x10) == 0x10) {
1770 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1771 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1772 if ((tmp & 0x10) == 0x10)
1775 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1776 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1777 if ((tmp & 0x10) != 0x10)
1780 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1785 * Try to detect the chipset and its mode.
1787 if (ppc_detect(ppc, dvp->id_flags & 0xf))
1790 return (IO_LPTSIZE);
1794 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) &&
1795 !(dvp->id_flags & PC98_IEEE_1284_DISABLE)) {
1796 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
1803 ppcattach(struct isa_device *isdp)
1805 struct ppc_data *ppc = ppcdata[isdp->id_unit];
1806 struct ppb_data *ppbus;
1808 printf("ppc%d: %s chipset (%s) in %s mode%s\n", ppc->ppc_unit,
1809 ppc_types[ppc->ppc_type], ppc_avms[ppc->ppc_avm],
1810 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1811 ppc_epp_protocol[ppc->ppc_epp] : "");
1814 printf("ppc%d: FIFO with %d/%d/%d bytes threshold\n",
1815 ppc->ppc_unit, ppc->ppc_fifo, ppc->ppc_wthr,
1818 isdp->id_ointr = ppcintr;
1821 * Prepare ppbus data area for upper level code.
1823 ppbus = ppb_alloc_bus();
1828 ppc->ppc_link.ppbus = ppbus;
1829 ppbus->ppb_link = &ppc->ppc_link;
1831 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1833 /* acquire the DMA channel forever */
1834 isa_dma_acquire(ppc->ppc_dmachan);
1835 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1839 * Probe the ppbus and attach devices found.
1841 ppb_attachdevs(ppbus);