2 * Copyright (c) 1997, 1998 Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/kernel.h>
39 #include <machine/clock.h>
42 #include <vm/vm_param.h>
45 #include <i386/isa/isa_device.h>
46 #include <pc98/pc98/pc98.h>
48 #include <dev/ppbus/ppbconf.h>
49 #include <dev/ppbus/ppb_msq.h>
51 #include <pc98/pc98/ppcreg.h>
55 #define LOG_PPC(function, ppc, string) \
56 if (bootverbose) printf("%s: %s\n", function, string)
58 static int ppcprobe(struct isa_device *);
59 static int ppcattach(struct isa_device *);
61 struct isa_driver ppcdriver = {
62 ppcprobe, ppcattach, "ppc"
65 static struct ppc_data *ppcdata[NPPC];
68 static char *ppc_types[] = {
69 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
70 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0
73 /* list of available modes */
74 static char *ppc_avms[] = {
75 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
76 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
77 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
78 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
81 /* list of current executing modes
82 * Note that few modes do not actually exist.
84 static char *ppc_modes[] = {
85 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
86 "EPP", "EPP", "EPP", "ECP",
87 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
88 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
91 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
94 * BIOS printer list - used by BIOS probe.
96 #define BIOS_PPC_PORTS 0x408
97 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
98 #define BIOS_MAX_PPC 4
101 * All these functions are default actions for IN/OUT operations.
102 * They may be redefined if needed.
104 static void ppc_outsb_epp(int unit, char *addr, int cnt) {
105 outsb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
106 static void ppc_outsw_epp(int unit, char *addr, int cnt) {
107 outsw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
108 static void ppc_outsl_epp(int unit, char *addr, int cnt) {
109 outsl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
110 static void ppc_insb_epp(int unit, char *addr, int cnt) {
111 insb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
112 static void ppc_insw_epp(int unit, char *addr, int cnt) {
113 insw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
114 static void ppc_insl_epp(int unit, char *addr, int cnt) {
115 insl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); }
117 static u_char ppc_rdtr(int unit) { return r_dtr(ppcdata[unit]); }
118 static u_char ppc_rstr(int unit) { return r_str(ppcdata[unit]); }
119 static u_char ppc_rctr(int unit) { return r_ctr(ppcdata[unit]); }
120 static u_char ppc_repp_A(int unit) { return r_epp_A(ppcdata[unit]); }
121 static u_char ppc_repp_D(int unit) { return r_epp_D(ppcdata[unit]); }
122 static u_char ppc_recr(int unit) { return r_ecr(ppcdata[unit]); }
123 static u_char ppc_rfifo(int unit) { return r_fifo(ppcdata[unit]); }
125 static void ppc_wdtr(int unit, char byte) { w_dtr(ppcdata[unit], byte); }
126 static void ppc_wstr(int unit, char byte) { w_str(ppcdata[unit], byte); }
127 static void ppc_wctr(int unit, char byte) { w_ctr(ppcdata[unit], byte); }
128 static void ppc_wepp_A(int unit, char byte) { w_epp_A(ppcdata[unit], byte); }
129 static void ppc_wepp_D(int unit, char byte) { w_epp_D(ppcdata[unit], byte); }
130 static void ppc_wecr(int unit, char byte) { w_ecr(ppcdata[unit], byte); }
131 static void ppc_wfifo(int unit, char byte) { w_fifo(ppcdata[unit], byte); }
133 static void ppc_reset_epp_timeout(int);
134 static void ppc_ecp_sync(int);
135 static ointhand2_t ppcintr;
137 static int ppc_exec_microseq(int, struct ppb_microseq **);
138 static int ppc_generic_setmode(int, int);
139 static int ppc_smclike_setmode(int, int);
141 static int ppc_read(int, char *, int, int);
142 static int ppc_write(int, char *, int, int);
144 static struct ppb_adapter ppc_smclike_adapter = {
146 0, /* no intr handler, filled by chipset dependent code */
148 ppc_reset_epp_timeout, ppc_ecp_sync,
152 ppc_smclike_setmode, ppc_read, ppc_write,
154 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp,
155 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp,
157 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp_A, ppc_repp_D, ppc_recr, ppc_rfifo,
158 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp_A, ppc_wepp_D, ppc_wecr, ppc_wfifo
161 static struct ppb_adapter ppc_generic_adapter = {
163 0, /* no intr handler, filled by chipset dependent code */
165 ppc_reset_epp_timeout, ppc_ecp_sync,
169 ppc_generic_setmode, ppc_read, ppc_write,
171 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp,
172 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp,
174 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp_A, ppc_repp_D, ppc_recr, ppc_rfifo,
175 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp_A, ppc_wepp_D, ppc_wecr, ppc_wfifo
182 ppc_ecp_sync(int unit) {
184 struct ppc_data *ppc = ppcdata[unit];
187 if (!(ppc->ppc_avm & PPB_ECP))
191 if ((r & 0xe0) != PPC_ECR_EPP)
194 for (i = 0; i < 100; i++) {
201 printf("ppc%d: ECP sync failed as data still " \
202 "present in FIFO.\n", unit);
210 * Detect parallel port FIFO
213 ppc_detect_fifo(struct ppc_data *ppc)
216 char ctr_sav, ctr, cc;
220 ecr_sav = r_ecr(ppc);
221 ctr_sav = r_ctr(ppc);
223 /* enter ECP configuration mode, no interrupt, no DMA */
226 /* read PWord size - transfers in FIFO mode must be PWord aligned */
227 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
229 /* XXX 16 and 32 bits implementations not supported */
230 if (ppc->ppc_pword != PPC_PWORD_8) {
231 LOG_PPC(__FUNCTION__, ppc, "PWord not supported");
235 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
237 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
239 /* enter ECP test mode, no interrupt, no DMA */
243 for (i=0; i<1024; i++) {
244 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
250 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO");
254 /* enable interrupts, no DMA */
257 /* determine readIntrThreshold
258 * fill the FIFO until serviceIntr is set
260 for (i=0; i<1024; i++) {
261 w_fifo(ppc, (char)i);
262 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
263 /* readThreshold reached */
266 if (r_ecr(ppc) & PPC_FIFO_FULL) {
273 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO");
277 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
278 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
279 w_ecr(ppc, 0xd0); /* enable interrupts */
281 /* determine writeIntrThreshold
282 * empty the FIFO until serviceIntr is set
284 for (i=ppc->ppc_fifo; i>0; i--) {
285 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
286 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO");
289 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
290 /* writeIntrThreshold reached */
291 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
293 /* if FIFO empty before the last byte, error */
294 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
295 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO");
300 /* FIFO must be empty after the last byte */
301 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
302 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO");
319 ppc_detect_port(struct ppc_data *ppc)
322 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
324 if (r_dtr(ppc) != 0xaa)
333 * Probe for a Natsemi PC873xx-family part.
335 * References in this function are to the National Semiconductor
336 * PC87332 datasheet TL/C/11930, May 1995 revision.
338 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
339 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
340 static int pc873xx_irqtab[] = {5, 7, 5, 0};
342 static int pc873xx_regstab[] = {
343 PC873_FER, PC873_FAR, PC873_PTR,
344 PC873_FCR, PC873_PCR, PC873_PMC,
345 PC873_TUP, PC873_SID, PC873_PNP0,
346 PC873_PNP1, PC873_LPTBA, -1
349 static char *pc873xx_rnametab[] = {
350 "FER", "FAR", "PTR", "FCR", "PCR",
351 "PMC", "TUP", "SID", "PNP0", "PNP1",
356 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
358 static int index = 0;
360 int ptr, pcr, val, i;
362 while ((idport = pc873xx_basetab[index++])) {
364 /* XXX should check first to see if this location is already claimed */
367 * Pull the 873xx through the power-on ID cycle (2.2,1.).
368 * We can't use this to locate the chip as it may already have
369 * been used by the BIOS.
371 (void)inb(idport); (void)inb(idport);
372 (void)inb(idport); (void)inb(idport);
375 * Read the SID byte. Possible values are :
381 outb(idport, PC873_SID);
382 val = inb(idport + 1);
383 if ((val & 0xf0) == 0x10) {
384 ppc->ppc_type = NS_PC87332;
385 } else if ((val & 0xf8) == 0x70) {
386 ppc->ppc_type = NS_PC87306;
387 } else if ((val & 0xf8) == 0x50) {
388 ppc->ppc_type = NS_PC87334;
390 if (bootverbose && (val != 0xff))
391 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
392 continue ; /* not recognised */
395 /* print registers */
398 for (i=0; pc873xx_regstab[i] != -1; i++) {
399 outb(idport, pc873xx_regstab[i]);
400 printf(" %s=0x%x", pc873xx_rnametab[i],
401 inb(idport + 1) & 0xff);
407 * We think we have one. Is it enabled and where we want it to be?
409 outb(idport, PC873_FER);
410 val = inb(idport + 1);
411 if (!(val & PC873_PPENABLE)) {
413 printf("PC873xx parallel port disabled\n");
416 outb(idport, PC873_FAR);
417 val = inb(idport + 1) & 0x3;
418 /* XXX we should create a driver instance for every port found */
419 if (pc873xx_porttab[val] != ppc->ppc_base) {
421 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
422 pc873xx_porttab[val], ppc->ppc_base);
426 outb(idport, PC873_PTR);
427 ptr = inb(idport + 1);
429 /* get irq settings */
430 if (ppc->ppc_base == 0x378)
431 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
433 irq = pc873xx_irqtab[val];
436 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
439 * Check if irq settings are correct
441 if (irq != ppc->ppc_irq) {
443 * If the chipset is not locked and base address is 0x378,
444 * we have another chance
446 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
447 if (ppc->ppc_irq == 7) {
448 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
449 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
451 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
452 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
455 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
458 printf("PC873xx sorry, can't change irq setting\n");
462 printf("PC873xx irq settings are correct\n");
465 outb(idport, PC873_PCR);
466 pcr = inb(idport + 1);
468 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
470 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
472 ppc->ppc_avm |= PPB_NIBBLE;
476 if (pcr & PC873_EPPEN) {
477 ppc->ppc_avm |= PPB_EPP;
482 if (pcr & PC873_EPP19)
483 ppc->ppc_epp = EPP_1_9;
485 ppc->ppc_epp = EPP_1_7;
487 if ((ppc->ppc_type == NS_PC87332) && bootverbose) {
488 outb(idport, PC873_PTR);
489 ptr = inb(idport + 1);
490 if (ptr & PC873_EPPRDIR)
491 printf(", Regular mode");
493 printf(", Automatic mode");
495 } else if (pcr & PC873_ECPEN) {
496 ppc->ppc_avm |= PPB_ECP;
500 if (pcr & PC873_ECPCLK) { /* XXX */
501 ppc->ppc_avm |= PPB_PS2;
506 outb(idport, PC873_PTR);
507 ptr = inb(idport + 1);
508 if (ptr & PC873_EXTENDED) {
509 ppc->ppc_avm |= PPB_SPP;
516 printf("PC873xx unlocked");
518 if (chipset_mode & PPB_ECP) {
519 if ((chipset_mode & PPB_EPP) && bootverbose)
520 printf(", ECP+EPP not supported");
523 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
524 outb(idport + 1, pcr);
525 outb(idport + 1, pcr);
530 } else if (chipset_mode & PPB_EPP) {
531 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
532 pcr |= (PC873_EPPEN | PC873_EPP19);
533 outb(idport + 1, pcr);
534 outb(idport + 1, pcr);
536 ppc->ppc_epp = EPP_1_9; /* XXX */
541 /* enable automatic direction turnover */
542 if (ppc->ppc_type == NS_PC87332) {
543 outb(idport, PC873_PTR);
544 ptr = inb(idport + 1);
545 ptr &= ~PC873_EPPRDIR;
546 outb(idport + 1, ptr);
547 outb(idport + 1, ptr);
550 printf(", Automatic mode");
553 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
554 outb(idport + 1, pcr);
555 outb(idport + 1, pcr);
557 /* configure extended bit in PTR */
558 outb(idport, PC873_PTR);
559 ptr = inb(idport + 1);
561 if (chipset_mode & PPB_PS2) {
562 ptr |= PC873_EXTENDED;
568 /* default to NIBBLE mode */
569 ptr &= ~PC873_EXTENDED;
574 outb(idport + 1, ptr);
575 outb(idport + 1, ptr);
578 ppc->ppc_avm = chipset_mode;
584 ppc->ppc_link.adapter = &ppc_generic_adapter;
585 ppc_generic_setmode(ppc->ppc_unit, chipset_mode);
587 return(chipset_mode);
593 ppc_check_epp_timeout(struct ppc_data *ppc)
595 ppc_reset_epp_timeout(ppc->ppc_unit);
597 return (!(r_str(ppc) & TIMEOUT));
601 * ppc_smc37c66xgt_detect
603 * SMC FDC37C66xGT configuration.
606 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
611 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
613 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
616 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
619 * Detection: enter configuration mode and read CRD register.
623 outb(csr, SMC665_iCODE);
624 outb(csr, SMC665_iCODE);
628 if (inb(cio) == 0x65) {
633 for (i = 0; i < 2; i++) {
635 outb(csr, SMC666_iCODE);
636 outb(csr, SMC666_iCODE);
640 if (inb(cio) == 0x66) {
645 /* Another chance, CSR may be hard-configured to be at 0x370 */
651 * If chipset not found, do not continue.
659 /* read the port's address: bits 0 and 1 of CR1 */
660 r = inb(cio) & SMC_CR1_ADDR;
661 if (port_address[(int)r] != ppc->ppc_base)
664 ppc->ppc_type = type;
667 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
668 * If SPP mode is detected, try to set ECP+EPP mode
673 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
677 printf(" CR4=0x%x", inb(cio) & 0xff);
684 /* autodetect mode */
686 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
687 if (type == SMC_37C666GT) {
688 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
690 printf(" configuration hardwired, supposing " \
694 if ((inb(cio) & SMC_CR1_MODE) == 0) {
695 /* already in extended parallel port mode, read CR4 */
697 r = (inb(cio) & SMC_CR4_EMODE);
701 ppc->ppc_avm |= PPB_SPP;
707 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
713 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
719 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
721 printf(" ECP+EPP SPP");
725 /* not an extended port mode */
726 ppc->ppc_avm |= PPB_SPP;
733 ppc->ppc_avm = chipset_mode;
735 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
736 if (type == SMC_37C666GT)
740 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
741 /* do not use ECP when the mode is not forced to */
742 outb(cio, r | SMC_CR1_MODE);
746 /* an extended mode is selected */
747 outb(cio, r & ~SMC_CR1_MODE);
749 /* read CR4 register and reset mode field */
751 r = inb(cio) & ~SMC_CR4_EMODE;
753 if (chipset_mode & PPB_ECP) {
754 if (chipset_mode & PPB_EPP) {
755 outb(cio, r | SMC_ECPEPP);
759 outb(cio, r | SMC_ECP);
765 outb(cio, r | SMC_EPPSPP);
770 ppc->ppc_avm = chipset_mode;
773 /* set FIFO threshold to 16 */
774 if (ppc->ppc_avm & PPB_ECP) {
785 if (ppc->ppc_avm & PPB_EPP) {
791 * Set the EPP protocol...
792 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
794 if (ppc->ppc_epp == EPP_1_9)
795 outb(cio, (r & ~SMC_CR4_EPPTYPE));
797 outb(cio, (r | SMC_CR4_EPPTYPE));
800 /* end config mode */
803 ppc->ppc_link.adapter = &ppc_smclike_adapter;
804 ppc_smclike_setmode(ppc->ppc_unit, chipset_mode);
806 return (chipset_mode);
810 * Winbond W83877F stuff
812 * EFER: extended function enable register
813 * EFIR: extended function index register
814 * EFDR: extended function data register
816 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
817 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
819 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
820 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
821 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
822 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
825 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
828 unsigned char r, hefere, hefras;
830 for (i = 0; i < 4; i ++) {
831 /* first try to enable configuration registers */
832 efer = w83877f_efers[i];
834 /* write the key to the EFER */
835 for (j = 0; j < w83877f_keyiter[i]; j ++)
836 outb (efer, w83877f_keys[i]);
838 /* then check HEFERE and HEFRAS bits */
840 hefere = inb(efdr) & WINB_HEFERE;
843 hefras = inb(efdr) & WINB_HEFRAS;
847 * 0 1 write 89h to 250h (power-on default)
848 * 1 0 write 86h twice to 3f0h
849 * 1 1 write 87h twice to 3f0h
850 * 0 0 write 88h to 250h
852 if ((hefere | hefras) == w83877f_hefs[i])
856 return (-1); /* failed */
859 /* check base port address - read from CR23 */
861 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
864 /* read CHIP ID from CR9/bits0-3 */
867 switch (inb(efdr) & WINB_CHIPID) {
868 case WINB_W83877F_ID:
869 ppc->ppc_type = WINB_W83877F;
872 case WINB_W83877AF_ID:
873 ppc->ppc_type = WINB_W83877AF;
877 ppc->ppc_type = WINB_UNKNOWN;
881 /* dump of registers */
882 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
883 for (i = 0; i <= 0xd; i ++) {
885 printf("0x%x ", inb(efdr));
887 for (i = 0x10; i <= 0x17; i ++) {
889 printf("0x%x ", inb(efdr));
892 printf("0x%x ", inb(efdr));
893 for (i = 0x20; i <= 0x29; i ++) {
895 printf("0x%x ", inb(efdr));
898 printf("ppc%d:", ppc->ppc_unit);
901 ppc->ppc_link.adapter = &ppc_generic_adapter;
904 /* autodetect mode */
908 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
912 r |= (inb(efdr) & WINB_PRTMODS2);
917 printf("ppc%d: W83757 compatible mode\n",
919 return (-1); /* generic or SMC-like */
926 printf(" not in parallel port mode\n");
929 case (WINB_PARALLEL | WINB_EPP_SPP):
930 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
935 case (WINB_PARALLEL | WINB_ECP):
936 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
941 case (WINB_PARALLEL | WINB_ECP_EPP):
942 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
943 ppc->ppc_link.adapter = &ppc_smclike_adapter;
946 printf(" ECP+EPP SPP");
949 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r);
955 /* select CR9 and set PRTMODS2 bit */
957 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
959 /* select CR0 and reset PRTMODSx bits */
961 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
963 if (chipset_mode & PPB_ECP) {
964 if (chipset_mode & PPB_EPP) {
965 outb(efdr, inb(efdr) | WINB_ECP_EPP);
969 ppc->ppc_link.adapter = &ppc_smclike_adapter;
972 outb(efdr, inb(efdr) | WINB_ECP);
977 /* select EPP_SPP otherwise */
978 outb(efdr, inb(efdr) | WINB_EPP_SPP);
982 ppc->ppc_avm = chipset_mode;
988 /* exit configuration mode */
991 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode);
993 return (chipset_mode);
1000 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1002 /* default to generic */
1003 ppc->ppc_link.adapter = &ppc_generic_adapter;
1006 printf("ppc%d:", ppc->ppc_unit);
1008 if (!chipset_mode) {
1009 /* first, check for ECP */
1010 w_ecr(ppc, PPC_ECR_PS2);
1011 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1012 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1016 /* search for SMC style ECP+EPP mode */
1017 w_ecr(ppc, PPC_ECR_EPP);
1020 /* try to reset EPP timeout bit */
1021 if (ppc_check_epp_timeout(ppc)) {
1022 ppc->ppc_avm |= PPB_EPP;
1024 if (ppc->ppc_avm & PPB_ECP) {
1025 /* SMC like chipset found */
1026 ppc->ppc_type = SMC_LIKE;
1027 ppc->ppc_link.adapter = &ppc_smclike_adapter;
1036 /* restore to standard mode */
1037 w_ecr(ppc, PPC_ECR_STD);
1040 /* XXX try to detect NIBBLE and PS2 modes */
1041 ppc->ppc_avm |= PPB_NIBBLE;
1047 ppc->ppc_avm = chipset_mode;
1053 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode);
1055 return (chipset_mode);
1061 * mode is the mode suggested at boot
1064 ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1068 /* list of supported chipsets */
1069 int (*chipset_detect[])(struct ppc_data *, int) = {
1071 ppc_smc37c66xgt_detect,
1077 /* if can't find the port and mode not forced return error */
1078 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1079 return (EIO); /* failed, port not present */
1081 /* assume centronics compatible mode is supported */
1082 ppc->ppc_avm = PPB_COMPATIBLE;
1084 /* we have to differenciate available chipset modes,
1085 * chipset running modes and IEEE-1284 operating modes
1087 * after detection, the port must support running in compatible mode
1089 if (ppc->ppc_flags & 0x40) {
1091 printf("ppc: chipset forced to generic\n");
1093 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1096 for (i=0; chipset_detect[i] != NULL; i++) {
1097 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1098 ppc->ppc_mode = mode;
1104 /* configure/detect ECP FIFO */
1105 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1106 ppc_detect_fifo(ppc);
1112 * ppc_exec_microseq()
1114 * Execute a microsequence.
1115 * Microsequence mechanism is supposed to handle fast I/O operations.
1118 ppc_exec_microseq(int unit, struct ppb_microseq **p_msq)
1120 struct ppc_data *ppc = ppcdata[unit];
1121 struct ppb_microseq *mi;
1128 register int accum = 0;
1129 register char *ptr = 0;
1131 struct ppb_microseq *stack = 0;
1133 /* microsequence registers are equivalent to PC-like port registers */
1134 #define r_reg(register,ppc) (inb((ppc)->ppc_base + register))
1135 #define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte)
1137 #define INCR_PC (mi ++) /* increment program counter */
1141 switch (mi->opcode) {
1143 cc = r_reg(mi->arg[0].i, ppc);
1144 cc &= (char)mi->arg[2].i; /* clear mask */
1145 cc |= (char)mi->arg[1].i; /* assert mask */
1146 w_reg(mi->arg[0].i, ppc, cc);
1150 case MS_OP_RASSERT_P:
1154 if ((len = mi->arg[0].i) == MS_ACCUM) {
1155 accum = ppc->ppc_accum;
1156 for (; accum; accum--)
1157 w_reg(reg, ppc, *ptr++);
1158 ppc->ppc_accum = accum;
1160 for (i=0; i<len; i++)
1161 w_reg(reg, ppc, *ptr++);
1167 case MS_OP_RFETCH_P:
1169 mask = (char)mi->arg[2].i;
1172 if ((len = mi->arg[0].i) == MS_ACCUM) {
1173 accum = ppc->ppc_accum;
1174 for (; accum; accum--)
1175 *ptr++ = r_reg(reg, ppc) & mask;
1176 ppc->ppc_accum = accum;
1178 for (i=0; i<len; i++)
1179 *ptr++ = r_reg(reg, ppc) & mask;
1186 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1194 /* let's suppose the next instr. is the same */
1196 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1197 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1199 if (mi->opcode == MS_OP_DELAY) {
1200 DELAY(mi->arg[0].i);
1208 tsleep(NULL, PPBPRI, "ppbdelay",
1209 mi->arg[0].i * (hz/1000));
1215 iter = mi->arg[1].i;
1216 p = (char *)mi->arg[2].p;
1218 /* XXX delay limited to 255 us */
1219 for (i=0; i<iter; i++) {
1220 w_reg(reg, ppc, *p++);
1221 DELAY((unsigned char)*p++);
1227 ppc->ppc_accum = mi->arg[0].i;
1232 if (--ppc->ppc_accum > 0)
1239 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1246 if ((cc & (char)mi->arg[0].i) == 0)
1253 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1261 * If the C call returns !0 then end the microseq.
1262 * The current state of ptr is passed to the C function
1264 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1271 ppc->ppc_ptr = (char *)mi->arg[0].p;
1277 panic("%s: too much calls", __FUNCTION__);
1280 /* store the state of the actual
1285 /* jump to the new microsequence */
1286 mi = (struct ppb_microseq *)mi->arg[0].p;
1293 /* retrieve microseq and pc state before the call */
1296 /* reset the stack */
1299 /* XXX return code */
1307 /* can't return to ppb level during the execution
1308 * of a submicrosequence */
1310 panic("%s: can't return to ppb level",
1313 /* update pc for ppb level of execution */
1316 /* return to ppb level of execution */
1320 panic("%s: unknown microsequence opcode 0x%x",
1321 __FUNCTION__, mi->opcode);
1331 struct ppc_data *ppc = ppcdata[unit];
1332 u_char ctr, ecr, str;
1339 printf("![%x/%x/%x]", ctr, ecr, str);
1342 /* don't use ecp mode with IRQENABLE set */
1343 if (ctr & IRQENABLE) {
1344 /* call upper code */
1345 ppb_intr(&ppc->ppc_link);
1349 /* interrupts are generated by nFault signal
1350 * only in ECP mode */
1351 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1352 /* check if ppc driver has programmed the
1353 * nFault interrupt */
1354 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1356 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1357 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1359 /* call upper code */
1360 ppb_intr(&ppc->ppc_link);
1365 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1366 /* disable interrupts (should be done by hardware though) */
1367 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1368 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1371 /* check if DMA completed */
1372 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1377 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1380 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1390 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1392 /* wakeup the waiting process */
1393 wakeup((caddr_t)ppc);
1396 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1398 /* classic interrupt I/O */
1399 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1407 ppc_read(int unit, char *buf, int len, int mode)
1413 * Call this function if you want to send data in any advanced mode
1414 * of your parallel port: FIFO, DMA
1416 * If what you want is not possible (no ECP, no DMA...),
1417 * EINVAL is returned
1420 ppc_write(int unit, char *buf, int len, int how)
1422 struct ppc_data *ppc = ppcdata[unit];
1423 char ecr, ecr_sav, ctr, ctr_sav;
1431 ecr_sav = r_ecr(ppc);
1432 ctr_sav = r_ctr(ppc);
1435 * Send buffer with DMA, FIFO and interrupts
1437 if (ppc->ppc_avm & PPB_ECP) {
1439 if (ppc->ppc_dmachan >= 0) {
1441 /* byte mode, no intr, no DMA, dir=0, flush fifo
1443 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1446 /* disable nAck interrupts */
1451 ppc->ppc_dmaflags = 0;
1452 ppc->ppc_dmaddr = (caddr_t)buf;
1453 ppc->ppc_dmacnt = (u_int)len;
1455 switch (ppc->ppc_mode) {
1456 case PPB_COMPATIBLE:
1457 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1458 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1461 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1471 /* enter splhigh() not to be preempted
1472 * by the dma interrupt, we may miss
1473 * the wakeup otherwise
1477 ppc->ppc_dmastat = PPC_DMA_INIT;
1479 /* enable interrupts */
1480 ecr &= ~PPC_SERVICE_INTR;
1481 ppc->ppc_irqstat = PPC_IRQ_DMA;
1490 printf("s%d", ppc->ppc_dmacnt);
1492 ppc->ppc_dmastat = PPC_DMA_STARTED;
1494 /* Wait for the DMA completed interrupt. We hope we won't
1495 * miss it, otherwise a signal will be necessary to unlock the
1500 error = tsleep((caddr_t)ppc,
1501 PPBPRI | PCATCH, "ppcdma", 0);
1503 } while (error == EWOULDBLOCK);
1513 ppc->ppc_dmaflags, ppc->ppc_dmaddr,
1514 ppc->ppc_dmacnt, ppc->ppc_dmachan);
1516 /* no dma, no interrupt, flush the fifo */
1517 w_ecr(ppc, PPC_ECR_RESET);
1519 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1523 /* wait for an empty fifo */
1524 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1526 for (spin=100; spin; spin--)
1527 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1532 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100);
1533 if (error != EWOULDBLOCK) {
1537 /* no dma, no interrupt, flush the fifo */
1538 w_ecr(ppc, PPC_ECR_RESET);
1540 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1547 /* no dma, no interrupt, flush the fifo */
1548 w_ecr(ppc, PPC_ECR_RESET);
1551 error = EINVAL; /* XXX we should FIFO and
1558 /* PDRQ must be kept unasserted until nPDACK is
1559 * deasserted for a minimum of 350ns (SMC datasheet)
1561 * Consequence may be a FIFO that never empty
1565 w_ecr(ppc, ecr_sav);
1566 w_ctr(ppc, ctr_sav);
1572 * Configure current operating mode
1575 ppc_generic_setmode(int unit, int mode)
1577 struct ppc_data *ppc = ppcdata[unit];
1580 /* check if mode is available */
1581 if (mode && !(ppc->ppc_avm & mode))
1584 /* if ECP mode, configure ecr register */
1585 if (ppc->ppc_avm & PPB_ECP) {
1586 /* return to byte mode (keeping direction bit),
1587 * no interrupt, no DMA to be able to change to
1590 w_ecr(ppc, PPC_ECR_RESET);
1591 ecr = PPC_DISABLE_INTR;
1595 else if (mode & PPB_ECP)
1596 /* select ECP mode */
1598 else if (mode & PPB_PS2)
1599 /* select PS2 mode with ECP */
1602 /* select COMPATIBLE/NIBBLE mode */
1608 ppc->ppc_mode = mode;
1614 * The ppc driver is free to choose options like FIFO or DMA
1615 * if ECP mode is available.
1617 * The 'RAW' option allows the upper drivers to force the ppc mode
1618 * even with FIFO, DMA available.
1621 ppc_smclike_setmode(int unit, int mode)
1623 struct ppc_data *ppc = ppcdata[unit];
1626 /* check if mode is available */
1627 if (mode && !(ppc->ppc_avm & mode))
1630 /* if ECP mode, configure ecr register */
1631 if (ppc->ppc_avm & PPB_ECP) {
1632 /* return to byte mode (keeping direction bit),
1633 * no interrupt, no DMA to be able to change to
1636 w_ecr(ppc, PPC_ECR_RESET);
1637 ecr = PPC_DISABLE_INTR;
1640 /* select EPP mode */
1642 else if (mode & PPB_ECP)
1643 /* select ECP mode */
1645 else if (mode & PPB_PS2)
1646 /* select PS2 mode with ECP */
1649 /* select COMPATIBLE/NIBBLE mode */
1655 ppc->ppc_mode = mode;
1661 * EPP timeout, according to the PC87332 manual
1662 * Semantics of clearing EPP timeout bit.
1663 * PC87332 - reading SPP_STR does it...
1664 * SMC - write 1 to EPP timeout bit XXX
1665 * Others - (?) write 0 to EPP timeout bit
1668 ppc_reset_epp_timeout(int unit)
1670 struct ppc_data *ppc = ppcdata[unit];
1674 w_str(ppc, r | 0x1);
1675 w_str(ppc, r & 0xfe);
1681 ppcprobe(struct isa_device *dvp)
1683 static short next_bios_ppc = 0;
1684 struct ppc_data *ppc;
1686 #define PC98_IEEE_1284_DISABLE 0x100
1687 #define PC98_IEEE_1284_PORT 0x140
1689 unsigned int pc98_ieee_mode = 0x00;
1694 * If port not specified, use bios list.
1696 if(dvp->id_iobase < 0) {
1698 if((next_bios_ppc < BIOS_MAX_PPC) &&
1699 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1700 dvp->id_iobase = *(BIOS_PORTS+next_bios_ppc++);
1702 printf("ppc: parallel port found at 0x%x\n",
1706 if(next_bios_ppc == 0) {
1707 /* Use default IEEE-1284 port of NEC PC-98x1 */
1708 dvp->id_iobase = PC98_IEEE_1284_PORT;
1711 printf("ppc: parallel port found at 0x%x\n",
1719 * Port was explicitly specified.
1720 * This allows probing of ports unknown to the BIOS.
1724 * Allocate the ppc_data structure.
1726 ppc = malloc(sizeof(struct ppc_data), M_DEVBUF, M_NOWAIT);
1728 printf("ppc: cannot malloc!\n");
1731 bzero(ppc, sizeof(struct ppc_data));
1733 ppc->ppc_base = dvp->id_iobase;
1734 ppc->ppc_unit = dvp->id_unit;
1735 ppc->ppc_type = GENERIC;
1737 /* store boot flags */
1738 ppc->ppc_flags = dvp->id_flags;
1740 ppc->ppc_mode = PPB_COMPATIBLE;
1741 ppc->ppc_epp = (dvp->id_flags & 0x10) >> 4;
1744 * XXX Try and detect if interrupts are working
1746 if (!(dvp->id_flags & 0x20) && dvp->id_irq)
1747 ppc->ppc_irq = ffs(dvp->id_irq) - 1;
1749 ppc->ppc_dmachan = dvp->id_drq;
1751 ppcdata[ppc->ppc_unit] = ppc;
1755 * Link the Parallel Port Chipset (adapter) to
1756 * the future ppbus. Default to a generic chipset
1758 ppc->ppc_link.adapter_unit = ppc->ppc_unit;
1759 ppc->ppc_link.adapter = &ppc_generic_adapter;
1763 * IEEE STD 1284 Function Check and Enable
1764 * for default IEEE-1284 port of NEC PC-98x1
1766 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) &&
1767 !(dvp->id_flags & PC98_IEEE_1284_DISABLE)) {
1768 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1769 pc98_ieee_mode = tmp;
1770 if ((tmp & 0x10) == 0x10) {
1771 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1772 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1773 if ((tmp & 0x10) == 0x10)
1776 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1777 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1778 if ((tmp & 0x10) != 0x10)
1781 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1786 * Try to detect the chipset and its mode.
1788 if (ppc_detect(ppc, dvp->id_flags & 0xf))
1791 return (IO_LPTSIZE);
1795 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) &&
1796 !(dvp->id_flags & PC98_IEEE_1284_DISABLE)) {
1797 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
1804 ppcattach(struct isa_device *isdp)
1806 struct ppc_data *ppc = ppcdata[isdp->id_unit];
1807 struct ppb_data *ppbus;
1809 printf("ppc%d: %s chipset (%s) in %s mode%s\n", ppc->ppc_unit,
1810 ppc_types[ppc->ppc_type], ppc_avms[ppc->ppc_avm],
1811 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1812 ppc_epp_protocol[ppc->ppc_epp] : "");
1815 printf("ppc%d: FIFO with %d/%d/%d bytes threshold\n",
1816 ppc->ppc_unit, ppc->ppc_fifo, ppc->ppc_wthr,
1819 isdp->id_ointr = ppcintr;
1822 * Prepare ppbus data area for upper level code.
1824 ppbus = ppb_alloc_bus();
1829 ppc->ppc_link.ppbus = ppbus;
1830 ppbus->ppb_link = &ppc->ppc_link;
1832 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1834 /* acquire the DMA channel forever */
1835 isa_dma_acquire(ppc->ppc_dmachan);
1836 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1840 * Probe the ppbus and attach devices found.
1842 ppb_attachdevs(ppbus);