2 * Copyright (c) 1997 Nicolas Souchu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Parallel Port Chipset type.
36 #define SMC_37C665GT 1
37 #define SMC_37C666GT 2
40 #define INTEL_820191AA 5 /* XXX not implemented */
42 #define WINB_W83877F 7
43 #define WINB_W83877AF 8
44 #define WINB_UNKNOWN 9
48 * Parallel Port Chipset Type. SMC versus GENERIC (others)
50 #define PPC_TYPE_SMCLIKE 0
51 #define PPC_TYPE_GENERIC 1
54 * Generic structure to hold parallel port chipset info.
59 int ppc_model; /* chipset model if detected */
60 int ppc_type; /* generic or smclike chipset type */
62 int ppc_mode; /* chipset current mode */
63 int ppc_avm; /* chipset available modes */
65 #define PPC_IRQ_NONE 0x0
66 #define PPC_IRQ_nACK 0x1
67 #define PPC_IRQ_DMA 0x2
68 #define PPC_IRQ_FIFO 0x4
69 #define PPC_IRQ_nFAULT 0x8
70 int ppc_irqstat; /* remind irq settings */
72 #define PPC_DMA_INIT 0x01
73 #define PPC_DMA_STARTED 0x02
74 #define PPC_DMA_COMPLETE 0x03
75 #define PPC_DMA_INTERRUPTED 0x04
76 #define PPC_DMA_ERROR 0x05
77 int ppc_dmastat; /* dma state */
78 int ppc_dmachan; /* dma channel */
79 int ppc_dmaflags; /* dma transfer flags */
80 caddr_t ppc_dmaddr; /* buffer address */
81 u_int ppc_dmacnt; /* count of bytes sent with dma */
83 #define PPC_PWORD_MASK 0x30
84 #define PPC_PWORD_16 0x00
85 #define PPC_PWORD_8 0x10
86 #define PPC_PWORD_32 0x20
87 char ppc_pword; /* PWord size */
88 short ppc_fifo; /* FIFO threshold */
90 short ppc_wthr; /* writeIntrThresold */
91 short ppc_rthr; /* readIntrThresold */
93 char *ppc_ptr; /* microseq current pointer */
94 int ppc_accum; /* microseq accumulator */
95 int ppc_base; /* parallel port base address */
96 int ppc_epp; /* EPP mode (1.7 or 1.9) */
99 unsigned char ppc_flags;
101 device_t ppbus; /* parallel port chipset corresponding ppbus */
103 int rid_irq, rid_drq, rid_ioport;
104 struct resource *res_irq, *res_drq, *res_ioport;
108 int ppc_registered; /* 1 if ppcintr() is the registered interrupt */
112 * Parallel Port Chipset registers.
114 #define PPC_SPP_DTR 0 /* SPP data register */
115 #define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */
116 #define PPC_SPP_STR 1 /* SPP status register */
117 #define PPC_SPP_CTR 2 /* SPP control register */
118 #define PPC_EPP_ADDR 3 /* EPP address register (8 bit) */
119 #define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */
121 #define PPC_1284_ENABLE 0x09 /* IEEE STD 1284 Enable register */
122 #define PPC_ECP_D_FIFO 0x0c /* ECP Data fifo register */
123 #define PPC_ECP_CNFGA 0x0c /* Configuration register A */
124 #define PPC_ECP_CNFGB 0x0d /* Configuration register B */
125 #define PPC_ECP_ECR 0x0e /* ECP extended control register */
127 #define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */
128 #define PPC_ECP_CNFGA 0x400 /* Configuration register A */
129 #define PPC_ECP_CNFGB 0x401 /* Configuration register B */
130 #define PPC_ECP_ECR 0x402 /* ECP extended control register */
133 #define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */
134 #define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */
135 #define PPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */
136 #define PPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */
137 #define PPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */
138 #define PPC_ECR_STD 0x0
139 #define PPC_ECR_PS2 0x20
140 #define PPC_ECR_FIFO 0x40
141 #define PPC_ECR_ECP 0x60
142 #define PPC_ECR_EPP 0x80
144 #define PPC_DISABLE_INTR (PPC_SERVICE_INTR | PPC_nFAULT_INTR)
145 #define PPC_ECR_RESET (PPC_ECR_PS2 | PPC_DISABLE_INTR)
147 #define r_dtr(ppc) (inb((ppc)->ppc_base + PPC_SPP_DTR))
148 #define r_str(ppc) (inb((ppc)->ppc_base + PPC_SPP_STR))
149 #define r_ctr(ppc) (inb((ppc)->ppc_base + PPC_SPP_CTR))
150 #define r_epp_A(ppc) (inb((ppc)->ppc_base + PPC_EPP_ADDR))
151 #define r_epp_D(ppc) (inb((ppc)->ppc_base + PPC_EPP_DATA))
152 #define r_cnfgA(ppc) (inb((ppc)->ppc_base + PPC_ECP_CNFGA))
153 #define r_cnfgB(ppc) (inb((ppc)->ppc_base + PPC_ECP_CNFGB))
154 #define r_ecr(ppc) (inb((ppc)->ppc_base + PPC_ECP_ECR))
155 #define r_fifo(ppc) (inb((ppc)->ppc_base + PPC_ECP_D_FIFO))
157 #define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte)
158 #define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte)
159 #define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte)
160 #define w_epp_A(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_ADDR, byte)
161 #define w_epp_D(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte)
162 #define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte)
163 #define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_D_FIFO, byte)
166 * Register defines for the PC873xx parts
169 #define PC873_FER 0x00
170 #define PC873_PPENABLE (1<<0)
171 #define PC873_FAR 0x01
172 #define PC873_PTR 0x02
173 #define PC873_CFGLOCK (1<<6)
174 #define PC873_EPPRDIR (1<<7)
175 #define PC873_EXTENDED (1<<7)
176 #define PC873_LPTBIRQ7 (1<<3)
177 #define PC873_FCR 0x03
178 #define PC873_ZWS (1<<5)
179 #define PC873_ZWSPWDN (1<<6)
180 #define PC873_PCR 0x04
181 #define PC873_EPPEN (1<<0)
182 #define PC873_EPP19 (1<<1)
183 #define PC873_ECPEN (1<<2)
184 #define PC873_ECPCLK (1<<3)
185 #define PC873_PMC 0x06
186 #define PC873_TUP 0x07
187 #define PC873_SID 0x08
188 #define PC873_PNP0 0x1b
189 #define PC873_PNP1 0x1c
190 #define PC873_LPTBA 0x19
193 * Register defines for the SMC FDC37C66xGT parts
197 #define SMC665_iCODE 0x55
198 #define SMC666_iCODE 0x44
200 /* Base configuration ports */
201 #define SMC66x_CSR 0x3F0
202 #define SMC666_CSR 0x370 /* hard-configured value for 666 */
205 #define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */
206 #define SMC_CR1_MODE (1<<3) /* bit 3 */
207 #define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */
208 #define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */
211 #define SMC_SPP 0x0 /* SPP */
212 #define SMC_EPPSPP 0x1 /* EPP and SPP */
213 #define SMC_ECP 0x2 /* ECP */
214 #define SMC_ECPEPP 0x3 /* ECP and EPP */
217 * Register defines for the Winbond W83877F parts
220 #define WINB_W83877F_ID 0xa
221 #define WINB_W83877AF_ID 0xb
223 /* Configuration bits */
224 #define WINB_HEFERE (1<<5) /* CROC bit 5 */
225 #define WINB_HEFRAS (1<<0) /* CR16 bit 0 */
227 #define WINB_PNPCVS (1<<2) /* CR16 bit 2 */
228 #define WINB_CHIPID 0xf /* CR9 bits 0-3 */
230 #define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */
231 #define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */
232 #define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */
234 /* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */
235 #define WINB_W83757 0x0
236 #define WINB_EXTFDC 0x4
237 #define WINB_EXTADP 0x8
238 #define WINB_EXT2FDD 0xc
239 #define WINB_JOYSTICK 0x80
241 #define WINB_PARALLEL 0x80
242 #define WINB_EPP_SPP 0x4
244 #define WINB_ECP_EPP 0xc