2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
34 * $Id: sio.c,v 1.74 1999/01/08 16:09:22 kato Exp $
37 #include "opt_comconsole.h"
38 #include "opt_compat.h"
40 #include "opt_devfs.h"
46 * Serial driver, based on 386BSD-0.1 com driver.
47 * Mostly rewritten to use pseudo-DMA.
48 * Works for National Semiconductor NS8250-NS16550AF UARTs.
49 * COM driver, based on HP dca driver.
51 * Changes for PC-Card integration:
52 * - Added PC-Card driver table and handlers
54 /*===============================================================
55 * 386BSD(98),FreeBSD-1.1x(98) com driver.
57 * modified for PC9801 by M.Ishii
58 * Kyoto University Microcomputer Club (KMC)
59 * Chou "TEFUTEFU" Hirotomi
60 * Kyoto Univ. the faculty of medicine
61 *===============================================================
62 * FreeBSD-2.0.1(98) sio driver.
64 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
65 * T.Koike(hfc01340@niftyserve.or.jp)
66 * implement kernel device configuration
67 * aizu@orient.center.nitech.ac.jp
71 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local
73 * This driver is under debugging,has bugs.
76 * options COM_MULTIPORT #if using MC16550II
77 * device sio0 at nec? port 0x30 tty irq 4 #internal
78 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1
79 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2
80 * # ~~~~~iobase ~~multi port flag
81 * # ~ master device is sio1
83 * cd /dev; MAKEDEV ttyd0 ttyd1 ..
85 * 57600bps is too fast for sio0(internal8251)
87 * #set default speed 9600
90 * stty </dev/ttyid$i crtscts 9600
91 * : # ~~~~ default speed(can change after init.)
95 * 5) PC9861K,PIO9032B,B98_01
99 * modified for AIWA B98-01
100 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
102 * How to configure...
103 * # options COM_MULTIPORT # support for MICROCORE MC16550II
104 * ... comment-out this line, which will conflict with B98_01.
105 * options "B98_01" # support for AIWA B98-01
106 * device sio1 at nec? port 0x00d1 tty irq ?
107 * device sio2 at nec? port 0x00d5 tty irq ?
108 * ... you can leave these lines `irq ?', irq will be autodetected.
111 * Modified by Y.Takahashi of Kogakuin University.
115 #define COM_IF_INTERNAL 0x00
116 #define COM_IF_PC9861K_1 0x01
117 #define COM_IF_PC9861K_2 0x02
118 #define COM_IF_IND_SS_1 0x03
119 #define COM_IF_IND_SS_2 0x04
120 #define COM_IF_PIO9032B_1 0x05
121 #define COM_IF_PIO9032B_2 0x06
122 #define COM_IF_B98_01_1 0x07
123 #define COM_IF_B98_01_2 0x08
124 #define COM_IF_END1 COM_IF_B98_01_2
125 #define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */
126 #define COM_IF_NS16550 0x11
127 #define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */
128 #define COM_IF_MC16550II 0x13
129 #define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */
130 #define COM_IF_RSB3000 0x15
131 #define COM_IF_RSB384 0x16
132 #define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */
133 #define COM_IF_RSA98III 0x18
134 #define COM_IF_ESP98 0x19
135 #define COM_IF_END2 COM_IF_ESP98
138 #include <sys/param.h>
139 #include <sys/systm.h>
140 #include <sys/reboot.h>
141 #include <sys/malloc.h>
143 #include <sys/proc.h>
144 #include <sys/conf.h>
145 #include <sys/dkstat.h>
146 #include <sys/fcntl.h>
147 #include <sys/interrupt.h>
148 #include <sys/kernel.h>
149 #include <sys/syslog.h>
150 #include <sys/sysctl.h>
152 #include <sys/devfsext.h>
155 #include <machine/clock.h>
156 #include <machine/ipl.h>
158 #include <machine/lock.h>
162 #include <pc98/pc98/pc98.h>
163 #include <pc98/pc98/pc98_machdep.h>
164 #include <i386/isa/icu.h>
165 #include <i386/isa/ic/i8251.h>
167 #include <i386/isa/isa.h>
169 #include <i386/isa/isa_device.h>
170 #include <i386/isa/sioreg.h>
171 #include <i386/isa/intr_machdep.h>
174 #include <i386/isa/ic/esp.h>
176 #include <i386/isa/ic/ns16550.h>
178 #include <i386/isa/ic/rsa.h>
183 #include <pccard/cardinfo.h>
184 #include <pccard/slot.h>
188 #include <i386/isa/pnp.h>
192 #define disable_intr() COM_DISABLE_INTR()
193 #define enable_intr() COM_ENABLE_INTR()
198 #define EXTRA_SIO MAX_PNP_CARDS
204 #define NSIOTOT (NSIO + EXTRA_SIO)
206 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
207 #define RS_IBUFSIZE 256
209 #define CALLOUT_MASK 0x80
210 #define CONTROL_MASK 0x60
211 #define CONTROL_INIT_STATE 0x20
212 #define CONTROL_LOCK_STATE 0x40
213 #define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
214 #define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
215 #define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
218 /* checks in flags for multiport and which is multiport "master chip"
221 #define COM_ISMULTIPORT(dev) ((dev)->id_flags & 0x01)
222 #define COM_MPMASTER(dev) (((dev)->id_flags >> 8) & 0x0ff)
223 #define COM_NOTAST4(dev) ((dev)->id_flags & 0x04)
224 #endif /* COM_MULTIPORT */
226 #define COM_CONSOLE(dev) ((dev)->id_flags & 0x10)
227 #define COM_FORCECONSOLE(dev) ((dev)->id_flags & 0x20)
228 #define COM_LLCONSOLE(dev) ((dev)->id_flags & 0x40)
229 #define COM_LOSESOUTINTS(dev) ((dev)->id_flags & 0x08)
230 #define COM_NOFIFO(dev) ((dev)->id_flags & 0x02)
231 #define COM_ST16650A(dev) ((dev)->id_flags & 0x20000)
232 #define COM_C_NOPROBE (0x40000)
233 #define COM_NOPROBE(dev) ((dev)->id_flags & COM_C_NOPROBE)
234 #define COM_C_IIR_TXRDYBUG (0x80000)
235 #define COM_IIR_TXRDYBUG(dev) ((dev)->id_flags & COM_C_IIR_TXRDYBUG)
236 #define COM_FIFOSIZE(dev) (((dev)->id_flags & 0xff000000) >> 24)
239 #define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
241 #define com_scr 7 /* scratch register for 16450-16550 (R/W) */
245 * Input buffer watermarks.
246 * The external device is asked to stop sending when the buffer exactly reaches
247 * high water, or when the high level requests it.
248 * The high level is notified immediately (rather than at a later clock tick)
249 * when this watermark is reached.
250 * The buffer size is chosen so the watermark should almost never be reached.
251 * The low watermark is invisibly 0 since the buffer is always emptied all at
254 #define RS_IHIGHWATER (3 * RS_IBUFSIZE / 4)
258 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
259 * than the other bits so that they can be tested as a group without masking
262 * The following com and tty flags correspond closely:
263 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
265 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
266 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
267 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
268 * TS_FLUSH is not used.
269 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
270 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
272 #define CS_BUSY 0x80 /* output in progress */
273 #define CS_TTGO 0x40 /* output not stopped by XOFF */
274 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
275 #define CS_CHECKMSR 1 /* check of MSR scheduled */
276 #define CS_CTS_OFLOW 2 /* use CTS output flow control */
277 #define CS_DTR_OFF 0x10 /* DTR held off */
278 #define CS_ODONE 4 /* output completed */
279 #define CS_RTS_IFLOW 8 /* use RTS input flow control */
280 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
282 static char const * const error_desc[] = {
285 #define CE_INTERRUPT_BUF_OVERFLOW 1
286 "interrupt-level buffer overflow",
287 #define CE_TTY_BUF_OVERFLOW 2
288 "tty-level buffer overflow",
292 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
294 /* types. XXX - should be elsewhere */
295 typedef u_int Port_t; /* hardware port */
296 typedef u_char bool_t; /* boolean */
298 /* queue of linear buffers */
300 u_char *l_head; /* next char to process */
301 u_char *l_tail; /* one past the last char to process */
302 struct lbq *l_next; /* next in queue */
303 bool_t l_queued; /* nonzero if queued */
306 /* com device structure */
308 u_int id_flags; /* Copy isa device falgas */
309 u_char state; /* miscellaneous flag bits */
310 bool_t active_out; /* nonzero if the callout device is open */
311 u_char cfcr_image; /* copy of value written to CFCR */
313 bool_t esp; /* is this unit a hayes esp board? */
315 u_char extra_state; /* more flag bits, separate for order trick */
316 u_char fifo_image; /* copy of value written to FIFO */
317 bool_t hasfifo; /* nonzero for 16550 UARTs */
318 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
319 bool_t loses_outints; /* nonzero if device loses output interrupts */
320 u_char mcr_image; /* copy of value written to MCR */
322 bool_t multiport; /* is this unit part of a multiport device? */
323 #endif /* COM_MULTIPORT */
324 bool_t no_irq; /* nonzero if irq is not attached */
325 bool_t gone; /* hardware disappeared */
326 bool_t poll; /* nonzero if polling is required */
327 bool_t poll_output; /* nonzero if polling for output is required */
328 int unit; /* unit number */
329 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
331 u_int wopeners; /* # processes waiting for DCD in open() */
334 * The high level of the driver never reads status registers directly
335 * because there would be too many side effects to handle conveniently.
336 * Instead, it reads copies of the registers stored here by the
339 u_char last_modem_status; /* last MSR read by intr handler */
340 u_char prev_modem_status; /* last MSR handled by high level */
342 u_char hotchar; /* ldisc-specific char to be handled ASAP */
343 u_char *ibuf; /* start of input buffer */
344 u_char *ibufend; /* end of input buffer */
345 u_char *ihighwater; /* threshold in input buffer */
346 u_char *iptr; /* next free spot in input buffer */
348 struct lbq obufq; /* head of queue of output buffers */
349 struct lbq obufs[2]; /* output buffers */
354 Port_t in_modem_port;
355 Port_t intr_ctrl_port;
357 int pc98_prev_modem_status;
358 int pc98_modem_delta;
359 int modem_car_chg_timer;
360 int pc98_prev_siocmd;
361 int pc98_prev_siomod;
365 Port_t data_port; /* i/o ports */
372 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
374 Port_t modem_ctl_port;
375 Port_t line_status_port;
376 Port_t modem_status_port;
377 Port_t intr_ctl_port; /* Ports of IIR register */
379 struct tty *tp; /* cross reference */
382 struct termios it_in; /* should be in struct tty */
383 struct termios it_out;
386 struct termios lt_in; /* should be in struct tty */
387 struct termios lt_out;
390 bool_t do_dcd_timestamp;
391 struct timeval timestamp;
392 struct timeval dcd_timestamp;
394 u_long bytes_in; /* statistics */
396 u_int delta_error_counts[CE_NTYPES];
397 u_long error_counts[CE_NTYPES];
400 * Ping-pong input buffers. The extra factor of 2 in the sizes is
401 * to allow for an error byte for each input byte.
404 u_long CE_INPUT_OFFSET;
409 * Data area for output buffers. Someday we should build the output
410 * buffer queue without copying data.
415 #define CE_INPUT_OFFSET RS_IBUFSIZE
416 u_char ibuf1[2 * RS_IBUFSIZE];
417 u_char ibuf2[2 * RS_IBUFSIZE];
420 * Data area for output buffers. Someday we should build the output
421 * buffer queue without copying data.
427 void *devfs_token_ttyd;
428 void *devfs_token_ttyl;
429 void *devfs_token_ttyi;
430 void *devfs_token_cuaa;
431 void *devfs_token_cual;
432 void *devfs_token_cuai;
437 static int espattach __P((struct isa_device *isdp, struct com_s *com,
440 static int sioattach __P((struct isa_device *dev));
441 static timeout_t siobusycheck;
442 static timeout_t siodtrwakeup;
443 static void comhardclose __P((struct com_s *com));
444 static ointhand2_t siointr;
445 static void siointr1 __P((struct com_s *com));
446 static int commctl __P((struct com_s *com, int bits, int how));
447 static int comparam __P((struct tty *tp, struct termios *t));
448 static swihand_t siopoll;
449 static int sioprobe __P((struct isa_device *dev));
450 static void siosettimeout __P((void));
451 static void comstart __P((struct tty *tp));
452 static timeout_t comwakeup;
453 static void disc_optim __P((struct tty *tp, struct termios *t,
457 static char driver_name[] = "sio";
459 /* table and macro for fast conversion from a unit number to its com struct */
460 static struct com_s *p_com_addr[NSIOTOT];
461 #define com_addr(unit) (p_com_addr[unit])
463 struct isa_driver siodriver = {
464 sioprobe, sioattach, driver_name
467 static d_open_t sioopen;
468 static d_close_t sioclose;
469 static d_read_t sioread;
470 static d_write_t siowrite;
471 static d_ioctl_t sioioctl;
472 static d_stop_t siostop;
473 static d_devtotty_t siodevtotty;
475 #define CDEV_MAJOR 28
476 static struct cdevsw sio_cdevsw = {
477 sioopen, sioclose, sioread, siowrite,
478 sioioctl, siostop, noreset, siodevtotty,
479 ttpoll, nommap, NULL, driver_name,
480 NULL, -1, nodump, nopsize,
484 static int comconsole = -1;
485 static volatile speed_t comdefaultrate = CONSPEED;
486 static u_int com_events; /* input chars + weighted output completions */
487 static Port_t siocniobase;
488 static bool_t sio_registered;
489 static int sio_timeout;
490 static int sio_timeouts_until_log;
491 static struct callout_handle sio_timeout_handle
492 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
494 static struct tty *sio_tty[NSIOTOT];
496 static struct tty sio_tty[NSIOTOT];
498 static const int nsio_tty = NSIOTOT;
504 Port_t cmd, sts, ctrl, mod;
508 #define COM_INT_DISABLE {int previpri; previpri=spltty();
509 #define COM_INT_ENABLE splx(previpri);}
510 #define IEN_TxFLAG IEN_Tx
512 #define COM_CARRIER_DETECT_EMULATE 0
513 #define PC98_CHECK_MODEM_INTERVAL (hz/10)
514 #define DCD_OFF_TOLERANCE 2
515 #define DCD_ON_RECOGNITION 2
516 #define IS_8251(if_type) (!(if_type & 0x10))
517 #define COM1_EXT_CLOCK 0x40000
519 static void commint __P((dev_t dev));
520 static void com_tiocm_set __P((struct com_s *com, int msr));
521 static void com_tiocm_bis __P((struct com_s *com, int msr));
522 static void com_tiocm_bic __P((struct com_s *com, int msr));
523 static int com_tiocm_get __P((struct com_s *com));
524 static int com_tiocm_get_delta __P((struct com_s *com));
525 static void pc98_msrint_start __P((dev_t dev));
526 static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed));
527 static int pc98_ttspeedtab __P((struct com_s *com, int speed));
528 static int pc98_get_modem_status __P((struct com_s *com));
529 static timeout_t pc98_check_msr;
530 static void pc98_set_baud_rate __P((struct com_s *com, int count));
531 static void pc98_i8251_reset __P((struct com_s *com, int mode, int command));
532 static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod));
533 static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
534 static int pc98_check_i8251_interrupt __P((struct com_s *com));
535 static int pc98_i8251_get_cmd __P((struct com_s *com));
536 static int pc98_i8251_get_mod __P((struct com_s *com));
537 static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
538 static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
539 static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
540 static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
541 static int pc98_check_if_type __P((struct isa_device *dev, struct siodev *iod));
542 static void pc98_check_sysclock __P((void));
543 static int pc98_set_ioport __P((struct com_s *com, int id_flags));
545 #define com_int_Tx_disable(com) \
546 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
547 #define com_int_Tx_enable(com) \
548 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
549 #define com_int_Rx_disable(com) \
550 pc98_disable_i8251_interrupt(com,IEN_Rx)
551 #define com_int_Rx_enable(com) \
552 pc98_enable_i8251_interrupt(com,IEN_Rx)
553 #define com_int_TxRx_disable(com) \
554 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
555 #define com_int_TxRx_enable(com) \
556 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
557 #define com_send_break_on(com) \
558 pc98_i8251_or_cmd(com,CMD8251_SBRK)
559 #define com_send_break_off(com) \
560 pc98_i8251_clear_cmd(com,CMD8251_SBRK)
562 static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
584 static struct speedtab pc98fast_speedtab[] = {
585 9600, 0x80 | COMBRD(9600),
586 19200, 0x80 | COMBRD(19200),
587 38400, 0x80 | COMBRD(38400),
588 57600, 0x80 | COMBRD(57600),
589 115200, 0x80 | COMBRD(115200),
592 static struct speedtab comspeedtab_pio9032b[] = {
603 static struct speedtab comspeedtab_b98_01[] = {
618 static struct speedtab comspeedtab_mc16550[] = {
634 static struct speedtab comspeedtab_rsb384[] = {
655 static struct speedtab comspeedtab_rsa[] = {
657 { 50, COMBRD_RSA(50) },
658 { 75, COMBRD_RSA(75) },
659 { 110, COMBRD_RSA(110) },
660 { 134, COMBRD_RSA(134) },
661 { 150, COMBRD_RSA(150) },
662 { 200, COMBRD_RSA(200) },
663 { 300, COMBRD_RSA(300) },
664 { 600, COMBRD_RSA(600) },
665 { 1200, COMBRD_RSA(1200) },
666 { 1800, COMBRD_RSA(1800) },
667 { 2400, COMBRD_RSA(2400) },
668 { 4800, COMBRD_RSA(4800) },
669 { 9600, COMBRD_RSA(9600) },
670 { 19200, COMBRD_RSA(19200) },
671 { 38400, COMBRD_RSA(38400) },
672 { 57600, COMBRD_RSA(57600) },
673 { 115200, COMBRD_RSA(115200) },
674 { 230400, COMBRD_RSA(230400) },
675 { 460800, COMBRD_RSA(460800) },
676 { 921600, COMBRD_RSA(921600) },
681 static struct speedtab comspeedtab[] = {
685 { 110, COMBRD(110) },
686 { 134, COMBRD(134) },
687 { 150, COMBRD(150) },
688 { 200, COMBRD(200) },
689 { 300, COMBRD(300) },
690 { 600, COMBRD(600) },
691 { 1200, COMBRD(1200) },
692 { 1800, COMBRD(1800) },
693 { 2400, COMBRD(2400) },
694 { 4800, COMBRD(4800) },
695 { 9600, COMBRD(9600) },
696 { 19200, COMBRD(19200) },
697 { 38400, COMBRD(38400) },
698 { 57600, COMBRD(57600) },
699 { 115200, COMBRD(115200) },
708 struct speedtab *speedtab;
711 /* COM_IF_INTERNAL */
712 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
713 -1, pc98speedtab, 1 },
714 /* COM_IF_PC9861K_1 */
715 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
717 /* COM_IF_PC9861K_2 */
718 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
720 /* COM_IF_IND_SS_1 */
721 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
722 3, comspeedtab_mc16550, 1 },
723 /* COM_IF_IND_SS_2 */
724 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
725 3, comspeedtab_mc16550, 1 },
726 /* COM_IF_PIO9032B_1 */
727 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
728 7, comspeedtab_pio9032b, 1 },
729 /* COM_IF_PIO9032B_2 */
730 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
731 7, comspeedtab_pio9032b, 1 },
732 /* COM_IF_B98_01_1 */
733 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
734 7, comspeedtab_b98_01, 0 },
735 /* COM_IF_B98_01_2 */
736 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
737 7, comspeedtab_b98_01, 0 },
739 #define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
740 #define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
741 #define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
742 #define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
743 #define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
744 #define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
745 #define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
753 struct speedtab *speedtab;
754 } if_16550a_type[] = {
756 { " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab },
758 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
759 /* COM_IF_SECOND_CCU */
760 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
761 /* COM_IF_MC16550II */
762 { " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
764 { " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
766 { " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
768 { " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
769 /* COM_IF_MODEM_CARD */
770 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
771 /* COM_IF_RSA98III */
772 { " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa },
774 { " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 },
781 /* XXX configure this properly. */
782 static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
783 static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
785 #define ESP98_CMD1 (ESP_CMD1 * 0x100)
786 #define ESP98_CMD2 (ESP_CMD2 * 0x100)
787 #define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
788 #define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
792 /* XXX configure this properly. */
793 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
794 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
800 * handle sysctl read/write requests for console speed
802 * In addition to setting comdefaultrate for I/O through /dev/console,
803 * also set the initial and lock values for the /dev/ttyXX device
804 * if there is one associated with the console. Finally, if the /dev/tty
805 * device has already been open, change the speed on the open running port
810 sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS
817 newspeed = comdefaultrate;
819 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
820 if (error || !req->newptr)
823 comdefaultrate = newspeed;
825 if (comconsole < 0) /* serial console not selected? */
828 com = com_addr(comconsole);
833 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
834 * (note, the lock rates really are boolean -- if non-zero, disallow
837 com->it_in.c_ispeed = com->it_in.c_ospeed =
838 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
839 com->it_out.c_ispeed = com->it_out.c_ospeed =
840 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
843 * if we're open, change the running rate too
846 if (tp && (tp->t_state & TS_ISOPEN)) {
847 tp->t_termios.c_ispeed =
848 tp->t_termios.c_ospeed = comdefaultrate;
850 error = comparam(tp, &tp->t_termios);
856 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
857 0, 0, sysctl_machdep_comdefaultrate, "I", "");
861 * PC-Card (PCMCIA) specific code.
863 static int sioinit __P((struct pccard_devinfo *));
864 static void siounload __P((struct pccard_devinfo *));
865 static int card_intr __P((struct pccard_devinfo *));
867 static struct pccard_device sio_info = {
872 0, /* Attributes - presently unused */
873 &tty_imask /* Interrupt mask for device */
874 /* XXX - Should this also include net_imask? */
877 DATA_SET(pccarddrv_set, sio_info);
880 * Initialize the device - called from Slot manager.
883 sioinit(struct pccard_devinfo *devi)
886 /* validate unit number. */
887 if (devi->isahd.id_unit >= (NSIOTOT))
889 /* Make sure it isn't already probed. */
890 if (com_addr(devi->isahd.id_unit))
893 /* It's already probed as serial by Upper */
894 devi->isahd.id_flags |= COM_C_NOPROBE;
897 * Probe the device. If a value is returned, the
898 * device was found at the location.
900 if (sioprobe(&devi->isahd) == 0)
902 if (sioattach(&devi->isahd) == 0)
909 * siounload - unload the driver and clear the table.
911 * This is usually called when the card is ejected, but
912 * can be caused by a modunload of a controller driver.
913 * The idea is to reset the driver's view of the device
914 * and ensure that any driver entry points such as
915 * read and write do not hang.
918 siounload(struct pccard_devinfo *devi)
923 printf("NULL devi in siounload\n");
926 com = com_addr(devi->isahd.id_unit);
928 printf("NULL com in siounload\n");
932 printf("sio%d already unloaded!\n",devi->isahd.id_unit);
935 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
937 printf("sio%d: unload\n", devi->isahd.id_unit);
943 com_addr(com->unit) = NULL;
945 bzero(com->ibuf1, com->CE_INPUT_OFFSET * 6);
947 bzero(com, sizeof *com);
949 printf("sio%d: unload,gone\n", devi->isahd.id_unit);
954 * card_intr - Shared interrupt called from
955 * front end of PC-Card handler.
958 card_intr(struct pccard_devinfo *devi)
963 com = com_addr(devi->isahd.id_unit);
964 if (com && !com->gone)
965 siointr1(com_addr(devi->isahd.id_unit));
969 #endif /* NCARD > 0 */
973 struct isa_device *dev;
975 static bool_t already_init;
978 struct isa_device *idev;
980 intrmask_t irqmap[4];
984 struct isa_device *xdev;
991 Port_t rsabase = NULL;
996 * Turn off MCR_IENABLE for all likely serial ports. An unused
997 * port with its MCR_IENABLE gate open will inhibit interrupts
998 * from any used port that shares the interrupt vector.
999 * XXX the gate enable is elsewhere for some multiports.
1001 for (xdev = isa_devtab_tty; xdev->id_driver != NULL; xdev++)
1003 if (xdev->id_driver == &siodriver && xdev->id_enabled) {
1004 tmp = (xdev->id_flags >> 24) & 0xff;
1006 outb((xdev->id_iobase & 0xff00) | PC98SIO_cmd_port(tmp & 0x0f), 0xf2);
1008 if (tmp == COM_IF_RSA98III) {
1009 rsabase = xdev->id_iobase & 0xfff0;
1011 if (rsabase != xdev->id_iobase)
1014 outb(xdev->id_iobase + 8 + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1016 outb(xdev->id_iobase + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1019 if (xdev->id_driver == &siodriver && xdev->id_enabled)
1020 outb(xdev->id_iobase + com_mcr, 0);
1022 already_init = TRUE;
1025 if (COM_LLCONSOLE(dev)) {
1026 printf("sio%d: reserved for low-level i/o\n", dev->id_unit);
1034 * If the port is i8251 UART (internal, B98_01)
1036 if (pc98_check_if_type(dev, &iod) == -1)
1039 dev->id_irq = 1 << iod.irq;
1040 if (IS_8251(iod.if_type)) {
1047 outb(iod.cmd, CMD8251_RESET);
1048 DELAY(1000); /* for a while...*/
1049 outb(iod.cmd, 0xf2); /* MODE (dummy) */
1051 outb(iod.cmd, 0x01); /* CMD (dummy) */
1052 DELAY(1000); /* for a while...*/
1053 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
1056 if (if_8251_type[iod.if_type & 0x0f].check_irq) {
1058 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
1059 outb( iod.ctrl, tmp|IEN_TxEMP );
1061 ret = isa_irq_pending() ? 4 : 0;
1062 outb( iod.ctrl, tmp );
1066 * B98_01 doesn't activate TxEMP interrupt line
1067 * when being reset, so we can't check irq pending.
1071 if (epson_machine_id==0x20) { /* XXX */
1078 * If the device is on a multiport card and has an AST/4
1079 * compatible interrupt control register, initialize this
1080 * register and prepare to leave MCR_IENABLE clear in the mcr.
1081 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1082 * Point idev to the device struct giving the correct id_irq.
1083 * This is the struct for the master device if there is one.
1086 mcr_image = MCR_IENABLE;
1088 if (iod.if_type == COM_IF_RSA98III) {
1090 rsabase = idev->id_iobase & 0xfff0;
1091 if (rsabase != idev->id_iobase)
1093 outb(rsabase + rsa_msr, 0x04);
1094 outb(rsabase + rsa_frr, 0x00);
1095 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36)
1097 outb(rsabase + rsa_ier, 0x00);
1098 outb(rsabase + rsa_frr, 0x00);
1099 outb(rsabase + rsa_tivsr, 0x00);
1100 outb(rsabase + rsa_tcr, 0x00);
1103 #ifdef COM_MULTIPORT
1104 if (COM_ISMULTIPORT(dev)) {
1105 idev = find_isadev(isa_devtab_tty, &siodriver,
1108 printf("sio%d: master device %d not configured\n",
1109 dev->id_unit, COM_MPMASTER(dev));
1114 if (!COM_NOTAST4(dev)) {
1115 outb(idev->id_iobase + com_scr,
1116 idev->id_irq ? 0x80 : 0);
1121 #endif /* COM_MULTIPORT */
1122 if (idev->id_irq == 0)
1126 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1129 switch (idev->id_irq) {
1130 case IRQ3: irqout = 4; break;
1131 case IRQ5: irqout = 5; break;
1132 case IRQ6: irqout = 6; break;
1133 case IRQ12: irqout = 7; break;
1135 printf("sio%d: irq configuration error\n", dev->id_unit);
1138 outb((dev->id_iobase & 0x00ff) | tmp, irqout);
1140 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift;
1142 bzero(failures, sizeof failures);
1144 if (iod.if_type == COM_IF_RSA98III)
1145 iobase = dev->id_iobase + 8;
1148 iobase = dev->id_iobase;
1151 * We don't want to get actual interrupts, just masked ones.
1152 * Interrupts from this line should already be masked in the ICU,
1153 * but mask them in the processor as well in case there are some
1154 * (misconfigured) shared interrupts.
1160 * Initialize the speed and the word size and wait long enough to
1161 * drain the maximum of 16 bytes of junk in device output queues.
1162 * The speed is undefined after a master reset and must be set
1163 * before relying on anything related to output. There may be
1164 * junk after a (very fast) soft reboot and (apparently) after
1166 * XXX what about the UART bug avoided by waiting in comparam()?
1167 * We don't want to to wait long enough to drain at 2 bps.
1169 if (iobase == siocniobase)
1170 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1173 tmp = ttspeedtab(SIO_TEST_SPEED,
1174 if_16550a_type[iod.if_type & 0x0f].speedtab);
1175 outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS);
1176 outb(iobase + (com_dlbl << port_shift), tmp & 0xff);
1177 outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff);
1178 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1180 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
1181 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
1182 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
1183 outb(iobase + com_cfcr, CFCR_8BITS);
1185 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1189 * Enable the interrupt gate and disable device interupts. This
1190 * should leave the device driving the interrupt line low and
1191 * guarantee an edge trigger if an interrupt can be generated.
1195 outb(iobase + (com_mcr << port_shift), mcr_image);
1196 outb(iobase + (com_ier << port_shift), 0);
1198 outb(iobase + com_mcr, mcr_image);
1199 outb(iobase + com_ier, 0);
1201 DELAY(1000); /* XXX */
1202 irqmap[0] = isa_irq_pending();
1205 * Attempt to set loopback mode so that we can send a null byte
1206 * without annoying any external device.
1210 outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK);
1212 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK);
1216 * Attempt to generate an output interrupt. On 8250's, setting
1217 * IER_ETXRDY generates an interrupt independent of the current
1218 * setting and independent of whether the THR is empty. On 16450's,
1219 * setting IER_ETXRDY generates an interrupt independent of the
1220 * current setting. On 16550A's, setting IER_ETXRDY only
1221 * generates an interrupt when IER_ETXRDY is not already set.
1224 outb(iobase + (com_ier << port_shift), IER_ETXRDY);
1225 if (iod.if_type == COM_IF_RSA98III) {
1226 outb(rsabase + rsa_ier, 0x04);
1229 outb(iobase + com_ier, IER_ETXRDY);
1233 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1234 * an interrupt. They'd better generate one for actually doing
1235 * output. Loopback may be broken on the same incompatibles but
1236 * it's unlikely to do more than allow the null byte out.
1239 outb(iobase + (com_data << port_shift), 0);
1241 outb(iobase + com_data, 0);
1243 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1246 * Turn off loopback mode so that the interrupt gate works again
1247 * (MCR_IENABLE was hidden). This should leave the device driving
1248 * an interrupt line high. It doesn't matter if the interrupt
1249 * line oscillates while we are not looking at it, since interrupts
1254 outb(iobase + (com_mcr << port_shift), mcr_image);
1256 outb(iobase + com_mcr, mcr_image);
1260 * It's a definitly Serial PCMCIA(16550A), but still be required
1261 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1263 if ( COM_NOPROBE(dev) ) {
1264 /* Reading IIR register twice */
1265 for ( fn = 0; fn < 2; fn ++ ) {
1268 failures[6] = inb(iobase + (com_iir << port_shift));
1270 failures[6] = inb(iobase + com_iir);
1273 /* Check IIR_TXRDY clear ? */
1275 result = if_16550a_type[iod.if_type & 0x0f].io_size;
1277 result = IO_COMSIZE;
1279 if ( failures[6] & IIR_TXRDY ) {
1280 /* Nop, Double check with clearing IER */
1282 outb(iobase + (com_ier << port_shift), 0);
1284 (com_iir << port_shift)) & IIR_NOPEND) {
1286 outb(iobase + com_ier, 0);
1287 if ( inb(iobase + com_iir) & IIR_NOPEND ) {
1289 /* Ok. we're familia this gang */
1290 dev->id_flags |= COM_C_IIR_TXRDYBUG; /* Set IIR_TXRDYBUG */
1292 /* Unknow, Just omit this chip.. XXX*/
1296 /* OK. this is well-known guys */
1297 dev->id_flags &= ~COM_C_IIR_TXRDYBUG; /*Clear IIR_TXRDYBUG*/
1300 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1302 outb(iobase + com_cfcr, CFCR_8BITS);
1305 return (iobase == siocniobase ? IO_COMSIZE : result);
1310 * o the CFCR, IER and MCR in UART hold the values written to them
1311 * (the values happen to be all distinct - this is good for
1312 * avoiding false positive tests from bus echoes).
1313 * o an output interrupt is generated and its vector is correct.
1314 * o the interrupt goes away when the IIR in the UART is read.
1318 failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS;
1319 failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY;
1320 failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image;
1322 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS;
1323 failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
1324 failures[2] = inb(iobase + com_mcr) - mcr_image;
1326 DELAY(10000); /* Some internal modems need this time */
1327 irqmap[1] = isa_irq_pending();
1329 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1331 if (iod.if_type == COM_IF_RSA98III) {
1332 inb(rsabase + rsa_srr);
1335 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
1337 DELAY(1000); /* XXX */
1338 irqmap[2] = isa_irq_pending();
1340 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1342 if (iod.if_type == COM_IF_RSA98III) {
1343 inb(rsabase + rsa_srr);
1346 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1350 * Turn off all device interrupts and check that they go off properly.
1351 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1352 * the OUT2 output of the UART to
1353 * the ICU input. Closing the gate would give a floating ICU input
1354 * (unless there is another device driving at) and spurious interrupts.
1355 * (On the system that this was first tested on, the input floats high
1356 * and gives a (masked) interrupt as soon as the gate is closed.)
1359 outb(iobase + (com_ier << port_shift), 0);
1360 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1361 failures[7] = inb(iobase + (com_ier << port_shift));
1362 if (iod.if_type == COM_IF_RSA98III) {
1363 outb(rsabase + rsa_ier, 0x00);
1366 outb(iobase + com_ier, 0);
1367 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1368 failures[7] = inb(iobase + com_ier);
1370 DELAY(1000); /* XXX */
1371 irqmap[3] = isa_irq_pending();
1373 failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1375 if (iod.if_type == COM_IF_RSA98III) {
1376 inb(rsabase + rsa_srr);
1377 outb(rsabase + rsa_frr, 0x00);
1380 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1385 irqs = irqmap[1] & ~irqmap[0];
1386 if (idev->id_irq != 0 && (idev->id_irq & irqs) == 0)
1388 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
1389 dev->id_unit, ffs(idev->id_irq) - 1, irqs);
1391 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1392 dev->id_unit, irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1395 result = if_16550a_type[iod.if_type & 0x0f].io_size;
1397 result = IO_COMSIZE;
1399 for (fn = 0; fn < sizeof failures; ++fn)
1402 outb(iobase + (com_mcr << port_shift), 0);
1404 outb(iobase + com_mcr, 0);
1408 printf("sio%d: probe failed test(s):",
1410 for (fn = 0; fn < sizeof failures; ++fn)
1417 return (iobase == siocniobase ? IO_COMSIZE : result);
1422 espattach(isdp, com, esp_port)
1423 struct isa_device *isdp;
1431 * Check the ESP-specific I/O port to see if we're an ESP
1432 * card. If not, return failure immediately.
1434 if ((inb(esp_port) & 0xf3) == 0) {
1435 printf(" port 0x%x is not an ESP board?\n", esp_port);
1440 * We've got something that claims to be a Hayes ESP card.
1444 /* Get the dip-switch configuration */
1446 outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1447 dips = inb(esp_port + ESP98_STATUS1);
1449 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1450 dips = inb(esp_port + ESP_STATUS1);
1454 * Bits 0,1 of dips say which COM port we are.
1457 if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03])
1459 if (com->iobase == likely_com_ports[dips & 0x03])
1463 printf(" esp_port has com %d\n", dips & 0x03);
1468 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1471 outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1472 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
1473 val = inb(esp_port + ESP98_STATUS2);
1475 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1476 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1477 val = inb(esp_port + ESP_STATUS2);
1479 if ((val & 0x70) < 0x20) {
1480 printf("-old (%o)", val & 0x70);
1485 * Check for ability to emulate 16550: bit 7 == 1
1487 if ((dips & 0x80) == 0) {
1493 * Okay, we seem to be a Hayes ESP card. Whee.
1496 com->esp_port = esp_port;
1499 #endif /* COM_ESP */
1503 struct isa_device *isdp;
1518 isdp->id_ointr = siointr;
1519 isdp->id_ri_flags |= RI_FAST;
1521 if (((isdp->id_flags >> 24) & 0xff) == COM_IF_RSA98III)
1522 iobase = isdp->id_iobase + 8;
1525 iobase = isdp->id_iobase;
1526 unit = isdp->id_unit;
1528 com = malloc(sizeof *com, M_TTYS, M_NOWAIT);
1530 ibufsize = RS_IBUFSIZE;
1531 if (((isdp->id_flags >> 24) & 0xff) == COM_IF_RSA98III)
1533 com = malloc((sizeof *com) + ibufsize * 6, M_TTYS, M_NOWAIT);
1539 * sioprobe() has initialized the device registers as follows:
1540 * o cfcr = CFCR_8BITS.
1541 * It is most important that CFCR_DLAB is off, so that the
1542 * data port is not hidden when we enable interrupts.
1544 * Interrupts are only enabled when the line is open.
1545 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1546 * interrupt control register or the config specifies no irq.
1547 * Keeping MCR_DTR and MCR_RTS off might stop the external
1548 * device from sending before we are ready.
1550 bzero(com, sizeof *com);
1552 com->CE_INPUT_OFFSET = ibufsize;
1553 com->ibuf1 = (u_char *)com + (sizeof *com);
1554 com->ibuf2 = com->ibuf1 + (ibufsize * 2);
1555 com->obuf1 = com->ibuf2 + (ibufsize * 2);
1556 com->obuf2 = com->obuf1 + ibufsize;
1557 bzero(com->ibuf1, ibufsize * 6);
1560 com->cfcr_image = CFCR_8BITS;
1561 com->dtr_wait = 3 * hz;
1562 com->loses_outints = COM_LOSESOUTINTS(isdp) != 0;
1563 com->no_irq = isdp->id_irq == 0;
1564 com->tx_fifo_size = 1;
1565 com->iptr = com->ibuf = com->ibuf1;
1567 com->ibufend = com->ibuf1 + RS_IBUFSIZE;
1568 com->ihighwater = com->ibuf1 + RS_IHIGHWATER;
1570 com->ibufend = com->ibuf1 + com->CE_INPUT_OFFSET;
1571 com->ihighwater = com->ibuf1 + (3 * com->CE_INPUT_OFFSET / 4);
1573 com->obufs[0].l_head = com->obuf1;
1574 com->obufs[1].l_head = com->obuf2;
1576 com->iobase = iobase;
1578 if (pc98_set_ioport(com, isdp->id_flags) == -1) {
1579 com->pc98_if_type = (isdp->id_flags >> 24) & 0xff;
1580 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1581 com->data_port = iobase + (com_data << port_shift);
1582 com->int_id_port = iobase + (com_iir << port_shift);
1583 com->modem_ctl_port = iobase + (com_mcr << port_shift);
1584 com->mcr_image = inb(com->modem_ctl_port);
1585 com->line_status_port = iobase + (com_lsr << port_shift);
1586 com->modem_status_port = iobase + (com_msr << port_shift);
1587 com->intr_ctl_port = iobase + (com_ier << port_shift);
1589 #else /* not PC98 */
1590 com->data_port = iobase + com_data;
1591 com->int_id_port = iobase + com_iir;
1592 com->modem_ctl_port = iobase + com_mcr;
1593 com->mcr_image = inb(com->modem_ctl_port);
1594 com->line_status_port = iobase + com_lsr;
1595 com->modem_status_port = iobase + com_msr;
1596 com->intr_ctl_port = iobase + com_ier;
1600 * We don't use all the flags from <sys/ttydefaults.h> since they
1601 * are only relevant for logins. It's important to have echo off
1602 * initially so that the line doesn't start blathering before the
1603 * echo flag can be turned off.
1605 com->it_in.c_iflag = 0;
1606 com->it_in.c_oflag = 0;
1607 com->it_in.c_cflag = TTYDEF_CFLAG;
1608 com->it_in.c_lflag = 0;
1609 if (unit == comconsole) {
1611 if (IS_8251(com->pc98_if_type))
1614 com->it_in.c_iflag = TTYDEF_IFLAG;
1615 com->it_in.c_oflag = TTYDEF_OFLAG;
1616 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1617 com->it_in.c_lflag = TTYDEF_LFLAG;
1618 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1619 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1620 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1621 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1623 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1624 termioschars(&com->it_in);
1625 com->it_out = com->it_in;
1627 /* attempt to determine UART type */
1628 printf("sio%d: type", unit);
1632 #ifdef COM_MULTIPORT
1633 if (!COM_ISMULTIPORT(isdp) && !COM_IIR_TXRDYBUG(isdp))
1635 if (!COM_IIR_TXRDYBUG(isdp))
1642 scr = inb(iobase + com_scr);
1643 outb(iobase + com_scr, 0xa5);
1644 scr1 = inb(iobase + com_scr);
1645 outb(iobase + com_scr, 0x5a);
1646 scr2 = inb(iobase + com_scr);
1647 outb(iobase + com_scr, scr);
1648 if (scr1 != 0xa5 || scr2 != 0x5a) {
1650 goto determined_type;
1655 if (IS_8251(com->pc98_if_type)) {
1656 com_int_TxRx_disable( com );
1657 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate );
1658 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1659 com_send_break_off( com );
1660 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1662 outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH);
1664 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1668 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1679 if (COM_NOFIFO(isdp)) {
1680 printf(" 16550A fifo disabled");
1682 com->hasfifo = TRUE;
1684 com->tx_fifo_size = 0; /* XXX flag conflicts. */
1687 if (COM_ST16650A(isdp)) {
1689 com->tx_fifo_size = 32;
1690 printf(" ST16650A");
1692 com->tx_fifo_size = COM_FIFOSIZE(isdp);
1698 if (com->pc98_if_type == COM_IF_RSA98III) {
1699 com->tx_fifo_size = 2048;
1700 com->rsabase = isdp->id_iobase;
1701 outb(com->rsabase + rsa_ier, 0x00);
1702 outb(com->rsabase + rsa_frr, 0x00);
1708 if (com->pc98_if_type == COM_IF_ESP98)
1710 for (espp = likely_esp_ports; *espp != 0; espp++)
1711 if (espattach(isdp, com, *espp)) {
1712 com->tx_fifo_size = 1024;
1716 if (!com->st16650a) {
1717 if (!com->tx_fifo_size)
1718 com->tx_fifo_size = 16;
1720 printf(" lookalike with %d bytes FIFO",
1728 if (com->pc98_if_type == COM_IF_RSB3000) {
1729 /* Set RSB-2000/3000 Extended Buffer mode. */
1731 lcr = inb(iobase + (com_cfcr << port_shift));
1732 outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB);
1733 outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE);
1734 outb(iobase + (com_cfcr << port_shift), lcr);
1741 * Set 16550 compatibility mode.
1742 * We don't use the ESP_MODE_SCALE bit to increase the
1743 * fifo trigger levels because we can't handle large
1745 * XXX flow control should be set in comparam(), not here.
1748 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
1749 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1751 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1752 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1755 /* Set RTS/CTS flow control. */
1757 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
1758 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
1759 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
1761 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1762 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1763 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1766 /* Set flow-control levels. */
1768 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
1769 outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
1770 outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
1771 outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
1772 outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
1774 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1775 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1776 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1777 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1778 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1782 /* Set UART clock prescaler. */
1783 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
1784 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
1787 #endif /* COM_ESP */
1789 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1790 outb(iobase + (com_fifo << port_shift), 0);
1792 outb(iobase + com_fifo, 0);
1796 #ifdef COM_MULTIPORT
1797 if (COM_ISMULTIPORT(isdp)) {
1798 com->multiport = TRUE;
1799 printf(" (multiport");
1800 if (unit == COM_MPMASTER(isdp))
1803 com->no_irq = find_isadev(isa_devtab_tty, &siodriver,
1804 COM_MPMASTER(isdp))->id_irq == 0;
1806 #endif /* COM_MULTIPORT */
1810 if (unit == comconsole)
1811 printf(", console");
1812 if ( COM_IIR_TXRDYBUG(isdp) )
1813 printf(" with a bogus IIR_TXRDY register");
1817 com_addr(unit) = com;
1820 if (!sio_registered) {
1821 dev = makedev(CDEV_MAJOR, 0);
1822 cdevsw_add(&dev, &sio_cdevsw, NULL);
1823 register_swi(SWI_TTY, siopoll);
1824 sio_registered = TRUE;
1827 com->devfs_token_ttyd = devfs_add_devswf(&sio_cdevsw,
1829 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1830 com->devfs_token_ttyi = devfs_add_devswf(&sio_cdevsw,
1831 unit | CONTROL_INIT_STATE, DV_CHR,
1832 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1833 com->devfs_token_ttyl = devfs_add_devswf(&sio_cdevsw,
1834 unit | CONTROL_LOCK_STATE, DV_CHR,
1835 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1836 com->devfs_token_cuaa = devfs_add_devswf(&sio_cdevsw,
1837 unit | CALLOUT_MASK, DV_CHR,
1838 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1839 com->devfs_token_cuai = devfs_add_devswf(&sio_cdevsw,
1840 unit | CALLOUT_MASK | CONTROL_INIT_STATE, DV_CHR,
1841 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1842 com->devfs_token_cual = devfs_add_devswf(&sio_cdevsw,
1843 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, DV_CHR,
1844 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1846 com->id_flags = isdp->id_flags; /* Heritate id_flags for later */
1851 sioopen(dev, flag, mode, p)
1869 unit = MINOR_TO_UNIT(mynor);
1870 if ((u_int) unit >= NSIOTOT || (com = com_addr(unit)) == NULL)
1874 if (mynor & CONTROL_MASK)
1877 tp = com->tp = sio_tty[unit] = ttymalloc(sio_tty[unit]);
1879 tp = com->tp = &sio_tty[unit];
1884 if (!IS_8251(com->pc98_if_type))
1885 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1888 * We jump to this label after all non-interrupted sleeps to pick
1889 * up any changes of the device state.
1892 while (com->state & CS_DTR_OFF) {
1893 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1894 if (com_addr(unit) == NULL)
1896 if (error != 0 || com->gone)
1899 if (tp->t_state & TS_ISOPEN) {
1901 * The device is open, so everything has been initialized.
1904 if (mynor & CALLOUT_MASK) {
1905 if (!com->active_out) {
1910 if (com->active_out) {
1911 if (flag & O_NONBLOCK) {
1915 error = tsleep(&com->active_out,
1916 TTIPRI | PCATCH, "siobi", 0);
1917 if (com_addr(unit) == NULL)
1919 if (error != 0 || com->gone)
1924 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) {
1930 * The device isn't open, so there are no conflicts.
1931 * Initialize it. Initialization is done twice in many
1932 * cases: to preempt sleeping callin opens if we are
1933 * callout, and to complete a callin open after DCD rises.
1935 tp->t_oproc = comstart;
1936 tp->t_param = comparam;
1938 tp->t_termios = mynor & CALLOUT_MASK
1939 ? com->it_out : com->it_in;
1941 tp->t_ififosize = 2 * RS_IBUFSIZE;
1943 tp->t_ififosize = 2 * com->CE_INPUT_OFFSET;
1945 tp->t_ispeedwat = (speed_t)-1;
1946 tp->t_ospeedwat = (speed_t)-1;
1948 if (!IS_8251(com->pc98_if_type))
1950 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1951 com->poll = com->no_irq;
1952 com->poll_output = com->loses_outints;
1954 error = comparam(tp, &tp->t_termios);
1959 if (IS_8251(com->pc98_if_type)) {
1960 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
1961 pc98_msrint_start(dev);
1965 * XXX we should goto open_top if comparam() slept.
1967 iobase = com->iobase;
1970 * (Re)enable and drain fifos.
1972 * Certain SMC chips cause problems if the fifos
1973 * are enabled while input is ready. Turn off the
1974 * fifo if necessary to clear the input. We test
1975 * the input ready bit after enabling the fifos
1976 * since we've already enabled them in comparam()
1977 * and to handle races between enabling and fresh
1982 outb(iobase + (com_fifo << port_shift),
1983 FIFO_RCV_RST | FIFO_XMT_RST
1985 if (com->pc98_if_type == COM_IF_RSA98III)
1986 outb(com->rsabase + rsa_frr , 0x00);
1988 outb(iobase + com_fifo,
1989 FIFO_RCV_RST | FIFO_XMT_RST
1993 * XXX the delays are for superstitious
1994 * historical reasons. It must be less than
1995 * the character time at the maximum
1996 * supported speed (87 usec at 115200 bps
1997 * 8N1). Otherwise we might loop endlessly
1998 * if data is streaming in. We used to use
1999 * delays of 100. That usually worked
2000 * because DELAY(100) used to usually delay
2001 * for about 85 usec instead of 100.
2005 if (!(inb(com->line_status_port) & LSR_RXRDY))
2007 if (com->pc98_if_type == COM_IF_RSA98III
2008 ? !(inb(com->rsabase + rsa_srr) & 0x08)
2009 : !(inb(com->line_status_port) & LSR_RXRDY))
2013 outb(iobase + (com_fifo << port_shift), 0);
2015 outb(iobase + com_fifo, 0);
2018 (void) inb(com->data_port);
2024 if (IS_8251(com->pc98_if_type)) {
2025 com_tiocm_bis(com, TIOCM_LE);
2026 com->pc98_prev_modem_status = pc98_get_modem_status(com);
2027 com_int_Rx_enable(com);
2030 (void) inb(com->line_status_port);
2031 (void) inb(com->data_port);
2032 com->prev_modem_status = com->last_modem_status
2033 = inb(com->modem_status_port);
2034 if (COM_IIR_TXRDYBUG(com)) {
2035 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
2038 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
2039 | IER_ERLS | IER_EMSC);
2042 if (com->pc98_if_type == COM_IF_RSA98III) {
2043 outb(com->rsabase + rsa_ier, 0x1d);
2044 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC);
2052 * Handle initial DCD. Callout devices get a fake initial
2053 * DCD (trapdoor DCD). If we are callout, then any sleeping
2054 * callin opens get woken up and resume sleeping on "siobi"
2055 * instead of "siodcd".
2058 * XXX `mynor & CALLOUT_MASK' should be
2059 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
2060 * TRAPDOOR_CARRIER is the default initial state for callout
2061 * devices and SOFT_CARRIER is like CLOCAL except it hides
2065 if ((IS_8251(com->pc98_if_type) &&
2066 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
2067 (!IS_8251(com->pc98_if_type) &&
2068 (com->prev_modem_status & MSR_DCD)) ||
2069 mynor & CALLOUT_MASK)
2071 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2073 (*linesw[tp->t_line].l_modem)(tp, 1);
2076 * Wait for DCD if necessary.
2078 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2079 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2081 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
2082 if (com_addr(unit) == NULL)
2085 if (error != 0 || com->gone)
2089 error = (*linesw[tp->t_line].l_open)(dev, tp);
2090 disc_optim(tp, &tp->t_termios, com);
2091 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
2092 com->active_out = TRUE;
2096 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
2102 sioclose(dev, flag, mode, p)
2114 if (mynor & CONTROL_MASK)
2116 com = com_addr(MINOR_TO_UNIT(mynor));
2119 (*linesw[tp->t_line].l_close)(tp, flag);
2121 com->modem_checking = 0;
2123 disc_optim(tp, &tp->t_termios, com);
2124 siostop(tp, FREAD | FWRITE);
2130 printf("sio%d: gone\n", com->unit);
2132 com_addr(com->unit) = 0;
2133 bzero(tp,sizeof *tp);
2134 bzero(com,sizeof *com);
2154 iobase = com->iobase;
2157 com->poll_output = FALSE;
2158 com->do_timestamp = FALSE;
2159 com->do_dcd_timestamp = FALSE;
2161 if (IS_8251(com->pc98_if_type))
2162 com_send_break_off(com);
2164 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2165 outb(iobase + (com_cfcr << port_shift),
2166 com->cfcr_image &= ~CFCR_SBREAK);
2169 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2174 if (IS_8251(com->pc98_if_type))
2175 com_int_TxRx_disable(com);
2177 outb(iobase + (com_ier << port_shift), 0);
2178 if (com->pc98_if_type == COM_IF_RSA98III) {
2179 outb(com->rsabase + rsa_ier, 0x00);
2182 outb(iobase + com_ier, 0);
2186 if (IS_8251(com->pc98_if_type))
2187 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2189 tmp = com->prev_modem_status & MSR_DCD;
2191 if (tp->t_cflag & HUPCL
2193 * XXX we will miss any carrier drop between here and the
2194 * next open. Perhaps we should watch DCD even when the
2195 * port is closed; it is not sufficient to check it at
2196 * the next open because it might go up and down while
2197 * we're not watching.
2203 && !(com->prev_modem_status & MSR_DCD)
2205 && !(com->it_in.c_cflag & CLOCAL)
2206 || !(tp->t_state & TS_ISOPEN)) {
2208 if (IS_8251(com->pc98_if_type))
2209 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2212 (void)commctl(com, TIOCM_DTR, DMBIC);
2213 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
2214 timeout(siodtrwakeup, com, com->dtr_wait);
2215 com->state |= CS_DTR_OFF;
2220 if (IS_8251(com->pc98_if_type))
2221 com_tiocm_bic(com, TIOCM_LE );
2227 * Disable fifos so that they are off after controlled
2228 * reboots. Some BIOSes fail to detect 16550s when the
2229 * fifos are enabled.
2232 outb(iobase + (com_fifo << port_shift), 0);
2234 outb(iobase + com_fifo, 0);
2237 com->active_out = FALSE;
2238 wakeup(&com->active_out);
2239 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
2244 sioread(dev, uio, flag)
2254 if (mynor & CONTROL_MASK)
2256 unit = MINOR_TO_UNIT(mynor);
2257 if (com_addr(unit)->gone)
2259 tp = com_addr(unit)->tp;
2260 return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
2264 siowrite(dev, uio, flag)
2274 if (mynor & CONTROL_MASK)
2277 unit = MINOR_TO_UNIT(mynor);
2278 if (com_addr(unit)->gone)
2280 tp = com_addr(unit)->tp;
2282 * (XXX) We disallow virtual consoles if the physical console is
2283 * a serial port. This is in case there is a display attached that
2284 * is not the console. In that situation we don't need/want the X
2285 * server taking over the console.
2287 if (constty != NULL && unit == comconsole)
2289 return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
2299 com = (struct com_s *)chan;
2302 * Clear TS_BUSY if low-level output is complete.
2303 * spl locking is sufficient because siointr1() does not set CS_BUSY.
2304 * If siointr1() clears CS_BUSY after we look at it, then we'll get
2305 * called again. Reading the line status port outside of siointr1()
2306 * is safe because CS_BUSY is clear so there are no output interrupts
2310 if (com->state & CS_BUSY)
2311 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
2313 else if (IS_8251(com->pc98_if_type) &&
2314 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2315 == (STS8251_TxRDY | STS8251_TxEMP) ||
2316 (inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2317 == (LSR_TSRE | LSR_TXRDY)) {
2319 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2320 == (LSR_TSRE | LSR_TXRDY)) {
2322 com->tp->t_state &= ~TS_BUSY;
2324 com->extra_state &= ~CSE_BUSYCHECK;
2326 timeout(siobusycheck, com, hz / 100);
2336 com = (struct com_s *)chan;
2337 com->state &= ~CS_DTR_OFF;
2338 wakeup(&com->dtr_wait);
2345 #ifndef COM_MULTIPORT
2347 siointr1(com_addr(unit));
2349 #else /* COM_MULTIPORT */
2351 bool_t possibly_more_intrs;
2353 u_char rsa_buf_status;
2357 * Loop until there is no activity on any port. This is necessary
2358 * to get an interrupt edge more than to avoid another interrupt.
2359 * If the IRQ signal is just an OR of the IRQ signals from several
2360 * devices, then the edge from one may be lost because another is
2365 possibly_more_intrs = FALSE;
2366 for (unit = 0; unit < NSIOTOT; ++unit) {
2367 com = com_addr(unit);
2370 * would it work here, or be counter-productive?
2375 && IS_8251(com->pc98_if_type)){
2382 && com->pc98_if_type == COM_IF_RSA98III) {
2383 rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9;
2384 if ((rsa_buf_status & 0xc8)
2385 || !(rsa_buf_status & 0x01)) {
2388 != (inb(com->rsabase + rsa_srr) & 0xc9))
2389 possibly_more_intrs = TRUE;
2395 && (inb(com->int_id_port) & IIR_IMASK)
2398 possibly_more_intrs = TRUE;
2400 /* XXX COM_UNLOCK(); */
2402 } while (possibly_more_intrs);
2404 #endif /* COM_MULTIPORT */
2412 u_char modem_status;
2420 u_char rsa_buf_status = 0;
2421 int rsa_tx_fifo_size=0;
2425 int_ctl = inb(com->intr_ctl_port);
2426 int_ctl_new = int_ctl;
2428 while (!com->gone) {
2431 if (IS_8251(com->pc98_if_type)) {
2432 tmp = inb(com->sts_port);
2435 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
2436 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
2437 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
2438 if (tmp & STS8251_PE) line_status |= LSR_PE;
2439 if (tmp & STS8251_OE) line_status |= LSR_OE;
2440 if (tmp & STS8251_FE) line_status |= LSR_FE;
2441 if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
2444 line_status = inb(com->line_status_port);
2446 if (com->pc98_if_type == COM_IF_RSA98III)
2447 rsa_buf_status = inb(com->rsabase + rsa_srr);
2450 /* input event? (check first to help avoid overruns) */
2452 while (line_status & LSR_RCV_MASK) {
2454 while ((line_status & LSR_RCV_MASK)
2455 || (com->pc98_if_type == COM_IF_RSA98III
2456 && (rsa_buf_status & 0x08))) {
2458 /* break/unnattached error bits or real input? */
2460 if (IS_8251(com->pc98_if_type)) {
2461 recv_data = inb(com->data_port);
2463 pc98_i8251_or_cmd(com,CMD8251_ER);
2469 if (com->pc98_if_type == COM_IF_RSA98III) {
2470 if (!(rsa_buf_status & 0x08))
2473 recv_data = inb(com->data_port);
2477 if (!(line_status & LSR_RXRDY))
2480 recv_data = inb(com->data_port);
2484 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2486 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2487 * Otherwise, push the work to a higher level
2488 * (to handle PARMRK) if we're bypassing.
2489 * Otherwise, convert BI/FE and PE+INPCK to 0.
2491 * This makes bypassing work right in the
2492 * usual "raw" case (IGNBRK set, and IGNPAR
2495 * Note: BI together with FE/PE means just BI.
2497 if (line_status & LSR_BI) {
2498 #if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2499 if (com->unit == comconsole) {
2505 || com->tp->t_iflag & IGNBRK)
2509 || com->tp->t_iflag & IGNPAR)
2512 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2513 && (line_status & (LSR_BI | LSR_FE)
2514 || com->tp->t_iflag & INPCK))
2518 if (com->hotchar != 0 && recv_data == com->hotchar)
2521 if (ioptr >= com->ibufend)
2522 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2524 if (com->do_timestamp)
2525 microtime(&com->timestamp);
2528 #if 0 /* for testing input latency vs efficiency */
2529 if (com->iptr - com->ibuf == 8)
2532 ioptr[0] = recv_data;
2534 ioptr[com->CE_INPUT_OFFSET] = line_status;
2536 ioptr[CE_INPUT_OFFSET] = line_status;
2538 com->iptr = ++ioptr;
2539 if (ioptr == com->ihighwater
2540 && com->state & CS_RTS_IFLOW)
2542 if (IS_8251(com->pc98_if_type))
2543 com_tiocm_bic(com, TIOCM_RTS);
2546 outb(com->modem_ctl_port,
2547 com->mcr_image &= ~MCR_RTS);
2548 if (line_status & LSR_OE)
2549 CE_RECORD(com, CE_OVERRUN);
2553 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2554 * jump from the top of the loop to here
2557 if (IS_8251(com->pc98_if_type))
2561 line_status = inb(com->line_status_port) & 0x7F;
2563 if (com->pc98_if_type == COM_IF_RSA98III)
2564 rsa_buf_status = inb(com->rsabase + rsa_srr);
2568 /* modem status change? (always check before doing output) */
2570 if (!IS_8251(com->pc98_if_type)) {
2572 modem_status = inb(com->modem_status_port);
2573 if (modem_status != com->last_modem_status) {
2574 if (com->do_dcd_timestamp
2575 && !(com->last_modem_status & MSR_DCD)
2576 && modem_status & MSR_DCD)
2577 microtime(&com->dcd_timestamp);
2580 * Schedule high level to handle DCD changes. Note
2581 * that we don't use the delta bits anywhere. Some
2582 * UARTs mess them up, and it's easy to remember the
2583 * previous bits and calculate the delta.
2585 com->last_modem_status = modem_status;
2586 if (!(com->state & CS_CHECKMSR)) {
2587 com_events += LOTS_OF_EVENTS;
2588 com->state |= CS_CHECKMSR;
2592 /* handle CTS change immediately for crisp flow ctl */
2593 if (com->state & CS_CTS_OFLOW) {
2594 if (modem_status & MSR_CTS)
2595 com->state |= CS_ODEVREADY;
2597 com->state &= ~CS_ODEVREADY;
2604 /* output queued and everything ready? */
2606 if (line_status & LSR_TXRDY
2607 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2609 if (((com->pc98_if_type == COM_IF_RSA98III)
2610 ? (rsa_buf_status & 0x02)
2611 : (line_status & LSR_TXRDY))
2612 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2614 ioptr = com->obufq.l_head;
2615 if (com->tx_fifo_size > 1) {
2618 ocount = com->obufq.l_tail - ioptr;
2620 if (com->pc98_if_type == COM_IF_RSA98III) {
2621 rsa_buf_status = inb(com->rsabase + rsa_srr);
2622 rsa_tx_fifo_size = 1024;
2623 if (!(rsa_buf_status & 0x01))
2624 rsa_tx_fifo_size = 2048;
2625 if (ocount > rsa_tx_fifo_size)
2626 ocount = rsa_tx_fifo_size;
2629 if (ocount > com->tx_fifo_size)
2630 ocount = com->tx_fifo_size;
2631 com->bytes_out += ocount;
2633 outb(com->data_port, *ioptr++);
2634 while (--ocount != 0);
2636 outb(com->data_port, *ioptr++);
2640 if (IS_8251(com->pc98_if_type))
2641 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2642 com_int_Tx_enable(com);
2644 com->obufq.l_head = ioptr;
2645 if (COM_IIR_TXRDYBUG(com)) {
2646 int_ctl_new = int_ctl | IER_ETXRDY;
2648 if (ioptr >= com->obufq.l_tail) {
2651 qp = com->obufq.l_next;
2652 qp->l_queued = FALSE;
2655 com->obufq.l_head = qp->l_head;
2656 com->obufq.l_tail = qp->l_tail;
2657 com->obufq.l_next = qp;
2659 /* output just completed */
2660 if ( COM_IIR_TXRDYBUG(com) ) {
2661 int_ctl_new = int_ctl & ~IER_ETXRDY;
2663 com->state &= ~CS_BUSY;
2665 if (IS_8251(com->pc98_if_type))
2666 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2667 com_int_Tx_disable(com);
2670 if (!(com->state & CS_ODONE)) {
2671 com_events += LOTS_OF_EVENTS;
2672 com->state |= CS_ODONE;
2673 setsofttty(); /* handle at high level ASAP */
2676 if ( COM_IIR_TXRDYBUG(com) && (int_ctl != int_ctl_new)) {
2677 if (com->pc98_if_type == COM_IF_RSA98III) {
2678 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2679 outb(com->intr_ctl_port, int_ctl_new);
2680 outb(com->rsabase + rsa_ier, 0x1d);
2682 outb(com->intr_ctl_port, int_ctl_new);
2686 else if (line_status & LSR_TXRDY) {
2687 if (IS_8251(com->pc98_if_type))
2688 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2689 com_int_Tx_disable(com);
2691 if (IS_8251(com->pc98_if_type))
2692 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
2697 #ifndef COM_MULTIPORT
2699 if (IS_8251(com->pc98_if_type))
2702 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2703 #endif /* COM_MULTIPORT */
2709 sioioctl(dev, cmd, data, flag, p)
2722 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2724 struct termios term;
2728 com = com_addr(MINOR_TO_UNIT(mynor));
2731 iobase = com->iobase;
2732 if (mynor & CONTROL_MASK) {
2735 switch (mynor & CONTROL_MASK) {
2736 case CONTROL_INIT_STATE:
2737 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
2739 case CONTROL_LOCK_STATE:
2740 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
2743 return (ENODEV); /* /dev/nodev */
2747 error = suser(p->p_ucred, &p->p_acflag);
2750 *ct = *(struct termios *)data;
2753 *(struct termios *)data = *ct;
2756 *(int *)data = TTYDISC;
2759 bzero(data, sizeof(struct winsize));
2766 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2767 term = tp->t_termios;
2769 error = ttsetcompat(tp, &cmd, data, &term);
2773 data = (caddr_t)&term;
2775 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
2777 struct termios *dt = (struct termios *)data;
2778 struct termios *lt = mynor & CALLOUT_MASK
2779 ? &com->lt_out : &com->lt_in;
2781 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2782 | (dt->c_iflag & ~lt->c_iflag);
2783 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2784 | (dt->c_oflag & ~lt->c_oflag);
2785 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2786 | (dt->c_cflag & ~lt->c_cflag);
2787 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2788 | (dt->c_lflag & ~lt->c_lflag);
2789 for (cc = 0; cc < NCCS; ++cc)
2790 if (lt->c_cc[cc] != 0)
2791 dt->c_cc[cc] = tp->t_cc[cc];
2792 if (lt->c_ispeed != 0)
2793 dt->c_ispeed = tp->t_ispeed;
2794 if (lt->c_ospeed != 0)
2795 dt->c_ospeed = tp->t_ospeed;
2797 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
2798 if (error != ENOIOCTL)
2801 error = ttioctl(tp, cmd, data, flag);
2802 disc_optim(tp, &tp->t_termios, com);
2803 if (error != ENOIOCTL) {
2808 if (IS_8251(com->pc98_if_type)) {
2811 com_send_break_on( com );
2814 com_send_break_off( com );
2817 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS );
2820 com_tiocm_bic(com, TIOCM_DTR);
2823 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2824 * changes get undone on the next call to comparam().
2827 com_tiocm_set( com, *(int *)data );
2830 com_tiocm_bis( com, *(int *)data );
2833 com_tiocm_bic( com, *(int *)data );
2836 *(int *)data = com_tiocm_get(com);
2839 /* must be root since the wait applies to following logins */
2840 error = suser(p->p_ucred, &p->p_acflag);
2845 com->dtr_wait = *(int *)data * hz / 100;
2848 *(int *)data = com->dtr_wait * 100 / hz;
2851 com->do_timestamp = TRUE;
2852 *(struct timeval *)data = com->timestamp;
2854 case TIOCDCDTIMESTAMP:
2855 com->do_dcd_timestamp = TRUE;
2856 *(struct timeval *)data = com->dcd_timestamp;
2864 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2869 outb(iobase + (com_cfcr << port_shift),
2870 com->cfcr_image |= CFCR_SBREAK);
2872 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2877 outb(iobase + (com_cfcr << port_shift),
2878 com->cfcr_image &= ~CFCR_SBREAK);
2880 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2884 (void)commctl(com, TIOCM_DTR, DMBIS);
2887 (void)commctl(com, TIOCM_DTR, DMBIC);
2890 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2891 * changes get undone on the next call to comparam().
2894 (void)commctl(com, *(int *)data, DMSET);
2897 (void)commctl(com, *(int *)data, DMBIS);
2900 (void)commctl(com, *(int *)data, DMBIC);
2903 *(int *)data = commctl(com, 0, DMGET);
2906 /* must be root since the wait applies to following logins */
2907 error = suser(p->p_ucred, &p->p_acflag);
2912 com->dtr_wait = *(int *)data * hz / 100;
2915 *(int *)data = com->dtr_wait * 100 / hz;
2918 com->do_timestamp = TRUE;
2919 *(struct timeval *)data = com->timestamp;
2921 case TIOCDCDTIMESTAMP:
2922 com->do_dcd_timestamp = TRUE;
2923 *(struct timeval *)data = com->dcd_timestamp;
2941 if (com_events == 0)
2944 for (unit = 0; unit < NSIOTOT; ++unit) {
2954 com = com_addr(unit);
2958 if (tp == NULL || com->gone) {
2960 * Discard any events related to never-opened or
2961 * going-away devices.
2964 incc = com->iptr - com->ibuf;
2965 com->iptr = com->ibuf;
2966 if (com->state & CS_CHECKMSR) {
2967 incc += LOTS_OF_EVENTS;
2968 com->state &= ~CS_CHECKMSR;
2975 /* switch the role of the low-level input buffers */
2976 if (com->iptr == (ibuf = com->ibuf)) {
2977 buf = NULL; /* not used, but compiler can't tell */
2982 incc = com->iptr - buf;
2984 if (ibuf == com->ibuf1)
2989 com->ibufend = ibuf + RS_IBUFSIZE;
2990 com->ihighwater = ibuf + RS_IHIGHWATER;
2992 com->ibufend = ibuf + com->CE_INPUT_OFFSET;
2993 com->ihighwater = ibuf + (3 * com->CE_INPUT_OFFSET / 4);
2998 * There is now room for another low-level buffer full
2999 * of input, so enable RTS if it is now disabled and
3000 * there is room in the high-level buffer.
3003 if (IS_8251(com->pc98_if_type))
3004 tmp = com_tiocm_get(com) & TIOCM_RTS;
3006 tmp = com->mcr_image & MCR_RTS;
3008 if ((com->state & CS_RTS_IFLOW)
3012 && !(com->mcr_image & MCR_RTS)
3014 && !(tp->t_state & TS_TBLOCK))
3016 if (IS_8251(com->pc98_if_type))
3017 com_tiocm_bis(com, TIOCM_RTS);
3020 outb(com->modem_ctl_port,
3021 com->mcr_image |= MCR_RTS);
3026 if (com->state & CS_CHECKMSR) {
3027 u_char delta_modem_status;
3030 if (!IS_8251(com->pc98_if_type)) {
3033 delta_modem_status = com->last_modem_status
3034 ^ com->prev_modem_status;
3035 com->prev_modem_status = com->last_modem_status;
3036 com_events -= LOTS_OF_EVENTS;
3037 com->state &= ~CS_CHECKMSR;
3039 if (delta_modem_status & MSR_DCD)
3040 (*linesw[tp->t_line].l_modem)
3041 (tp, com->prev_modem_status & MSR_DCD);
3046 if (com->state & CS_ODONE) {
3048 com_events -= LOTS_OF_EVENTS;
3049 com->state &= ~CS_ODONE;
3051 if (!(com->state & CS_BUSY)
3052 && !(com->extra_state & CSE_BUSYCHECK)) {
3053 timeout(siobusycheck, com, hz / 100);
3054 com->extra_state |= CSE_BUSYCHECK;
3056 (*linesw[tp->t_line].l_start)(tp);
3058 if (incc <= 0 || !(tp->t_state & TS_ISOPEN) ||
3059 !(tp->t_cflag & CREAD))
3062 * Avoid the grotesquely inefficient lineswitch routine
3063 * (ttyinput) in "raw" mode. It usually takes about 450
3064 * instructions (that's without canonical processing or echo!).
3065 * slinput is reasonably fast (usually 40 instructions plus
3068 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
3069 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
3070 && (com->state & CS_RTS_IFLOW
3071 || tp->t_iflag & IXOFF)
3072 && !(tp->t_state & TS_TBLOCK))
3076 tp->t_rawcc += incc;
3077 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
3078 += b_to_q((char *)buf, incc, &tp->t_rawq);
3080 if (tp->t_state & TS_TTSTOP
3081 && (tp->t_iflag & IXANY
3082 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
3083 tp->t_state &= ~TS_TTSTOP;
3084 tp->t_lflag &= ~FLUSHO;
3093 line_status = (u_char) buf[CE_INPUT_OFFSET];
3095 line_status = (u_char) buf[com->CE_INPUT_OFFSET];
3097 recv_data = (u_char) *buf++;
3099 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
3100 if (line_status & LSR_BI)
3101 recv_data |= TTY_BI;
3102 if (line_status & LSR_FE)
3103 recv_data |= TTY_FE;
3104 if (line_status & LSR_OE)
3105 recv_data |= TTY_OE;
3106 if (line_status & LSR_PE)
3107 recv_data |= TTY_PE;
3109 (*linesw[tp->t_line].l_rint)(recv_data, tp);
3110 } while (--incc > 0);
3112 if (com_events == 0)
3115 if (com_events >= LOTS_OF_EVENTS)
3142 unit = DEV_TO_UNIT(tp->t_dev);
3143 com = com_addr(unit);
3144 iobase = com->iobase;
3145 if (IS_8251(com->pc98_if_type)) {
3146 divisor = pc98_ttspeedtab(com, t->c_ospeed);
3148 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3150 /* do historical conversions */
3151 if (t->c_ispeed == 0)
3152 t->c_ispeed = t->c_ospeed;
3154 /* check requested parameters */
3155 divisor = ttspeedtab(t->c_ospeed,
3156 if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
3159 /* do historical conversions */
3160 if (t->c_ispeed == 0)
3161 t->c_ispeed = t->c_ospeed;
3163 /* check requested parameters */
3164 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
3166 if (divisor < 0 || divisor > 0 && t->c_ispeed != t->c_ospeed)
3169 /* parameters are OK, convert them to the com struct and the device */
3171 unit = DEV_TO_UNIT(tp->t_dev);
3172 com = com_addr(unit);
3173 iobase = com->iobase;
3177 if (IS_8251(com->pc98_if_type)) {
3179 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3181 com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3185 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
3187 (void)commctl(com, TIOCM_DTR, DMBIS);
3193 if (!IS_8251(com->pc98_if_type)) {
3195 switch (cflag & CSIZE) {
3209 if (cflag & PARENB) {
3211 if (!(cflag & PARODD))
3217 if (com->hasfifo && divisor != 0) {
3219 * Use a fifo trigger level low enough so that the input
3220 * latency from the fifo is less than about 16 msec and
3221 * the total latency is less than about 30 msec. These
3222 * latencies are reasonable for humans. Serial comms
3223 * protocols shouldn't expect anything better since modem
3224 * latencies are larger.
3226 com->fifo_image = t->c_ospeed <= 4800
3227 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
3230 * The Hayes ESP card needs the fifo DMA mode bit set
3231 * in compatibility mode. If not, it will interrupt
3232 * for each character received.
3235 com->fifo_image |= FIFO_DMA_MODE;
3238 outb(iobase + (com_fifo << port_shift), com->fifo_image);
3240 outb(iobase + com_fifo, com->fifo_image);
3247 disable_intr(); /* very important while com_data is hidden */
3250 if (IS_8251(com->pc98_if_type))
3251 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3256 outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB);
3258 outb(iobase + com_cfcr, cfcr | CFCR_DLAB);
3261 * Only set the divisor registers if they would change,
3262 * since on some 16550 incompatibles (UMC8669F), setting
3263 * them while input is arriving them loses sync until
3264 * data stops arriving.
3266 dlbl = divisor & 0xFF;
3268 if (inb(iobase + (com_dlbl << port_shift)) != dlbl)
3269 outb(iobase + (com_dlbl << port_shift), dlbl);
3270 dlbh = (u_int) divisor >> 8;
3271 if (inb(iobase + (com_dlbh << port_shift)) != dlbh)
3272 outb(iobase + (com_dlbh << port_shift), dlbh);
3274 if (inb(iobase + com_dlbl) != dlbl)
3275 outb(iobase + com_dlbl, dlbl);
3276 dlbh = (u_int) divisor >> 8;
3277 if (inb(iobase + com_dlbh) != dlbh)
3278 outb(iobase + com_dlbh, dlbh);
3285 outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr);
3287 outb(iobase + com_cfcr, com->cfcr_image = cfcr);
3290 if (!(tp->t_state & TS_TTSTOP))
3291 com->state |= CS_TTGO;
3293 if (cflag & CRTS_IFLOW) {
3294 if (com->st16650a) {
3295 outb(iobase + com_cfcr, 0xbf);
3296 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40);
3298 com->state |= CS_RTS_IFLOW;
3300 * If CS_RTS_IFLOW just changed from off to on, the change
3301 * needs to be propagated to MCR_RTS. This isn't urgent,
3302 * so do it later by calling comstart() instead of repeating
3303 * a lot of code from comstart() here.
3305 } else if (com->state & CS_RTS_IFLOW) {
3306 com->state &= ~CS_RTS_IFLOW;
3308 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
3309 * on here, since comstart() won't do it later.
3312 if (IS_8251(com->pc98_if_type))
3313 com_tiocm_bis(com, TIOCM_RTS);
3316 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3317 if (com->st16650a) {
3318 outb(iobase + com_cfcr, 0xbf);
3319 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40);
3325 * Set up state to handle output flow control.
3326 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3327 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3329 com->state |= CS_ODEVREADY;
3330 com->state &= ~CS_CTS_OFLOW;
3332 if (com->pc98_if_type == COM_IF_RSA98III) {
3333 param = inb(com->rsabase + rsa_msr);
3334 outb(com->rsabase + rsa_msr, param & 0x14);
3337 if (cflag & CCTS_OFLOW) {
3338 com->state |= CS_CTS_OFLOW;
3340 if (IS_8251(com->pc98_if_type)) {
3341 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3342 com->state &= ~CS_ODEVREADY;
3346 if (com->pc98_if_type == COM_IF_RSA98III) {
3347 /* Set automatic flow control mode */
3348 outb(com->rsabase + rsa_msr, param | 0x08);
3351 if (!(com->last_modem_status & MSR_CTS))
3352 com->state &= ~CS_ODEVREADY;
3353 if (com->st16650a) {
3354 outb(iobase + com_cfcr, 0xbf);
3355 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80);
3361 if (com->st16650a) {
3362 outb(iobase + com_cfcr, 0xbf);
3363 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80);
3369 outb(iobase + (com_cfcr << port_shift), com->cfcr_image);
3371 outb(iobase + com_cfcr, com->cfcr_image);
3375 /* XXX shouldn't call functions while intrs are disabled. */
3376 disc_optim(tp, t, com);
3378 * Recover from fiddling with CS_TTGO. We used to call siointr1()
3379 * unconditionally, but that defeated the careful discarding of
3380 * stale input in sioopen().
3382 if (com->state >= (CS_BUSY | CS_TTGO))
3402 unit = DEV_TO_UNIT(tp->t_dev);
3403 com = com_addr(unit);
3406 if (tp->t_state & TS_TTSTOP)
3407 com->state &= ~CS_TTGO;
3409 com->state |= CS_TTGO;
3410 if (tp->t_state & TS_TBLOCK) {
3412 if (IS_8251(com->pc98_if_type))
3413 tmp = com_tiocm_get(com) & TIOCM_RTS;
3415 tmp = com->mcr_image & MCR_RTS;
3416 if (tmp && (com->state & CS_RTS_IFLOW))
3418 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3421 if (IS_8251(com->pc98_if_type))
3422 com_tiocm_bic(com, TIOCM_RTS);
3425 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3428 if (IS_8251(com->pc98_if_type))
3429 tmp = com_tiocm_get(com) & TIOCM_RTS;
3431 tmp = com->mcr_image & MCR_RTS;
3432 if (!(tmp) && com->iptr < com->ihighwater
3433 && com->state & CS_RTS_IFLOW)
3435 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3436 && com->state & CS_RTS_IFLOW)
3439 if (IS_8251(com->pc98_if_type))
3440 com_tiocm_bis(com, TIOCM_RTS);
3443 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3446 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3449 /* if(IS_8251(com->pc98_if_type))
3450 com_int_Tx_enable(com); */
3455 if (tp->t_outq.c_cc != 0) {
3459 if (!com->obufs[0].l_queued) {
3460 com->obufs[0].l_tail
3461 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3465 com->CE_INPUT_OFFSET);
3467 com->obufs[0].l_next = NULL;
3468 com->obufs[0].l_queued = TRUE;
3470 if (com->state & CS_BUSY) {
3471 qp = com->obufq.l_next;
3472 while ((next = qp->l_next) != NULL)
3474 qp->l_next = &com->obufs[0];
3476 com->obufq.l_head = com->obufs[0].l_head;
3477 com->obufq.l_tail = com->obufs[0].l_tail;
3478 com->obufq.l_next = &com->obufs[0];
3479 com->state |= CS_BUSY;
3483 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3484 com->obufs[1].l_tail
3485 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3489 com->CE_INPUT_OFFSET);
3491 com->obufs[1].l_next = NULL;
3492 com->obufs[1].l_queued = TRUE;
3494 if (com->state & CS_BUSY) {
3495 qp = com->obufq.l_next;
3496 while ((next = qp->l_next) != NULL)
3498 qp->l_next = &com->obufs[1];
3500 com->obufq.l_head = com->obufs[1].l_head;
3501 com->obufq.l_tail = com->obufs[1].l_tail;
3502 com->obufq.l_next = &com->obufs[1];
3503 com->state |= CS_BUSY;
3507 tp->t_state |= TS_BUSY;
3510 if (com->state >= (CS_BUSY | CS_TTGO))
3511 siointr1(com); /* fake interrupt to start output */
3514 /* if(IS_8251(com->pc98_if_type))
3515 com_int_Tx_enable(com); */
3532 com = com_addr(DEV_TO_UNIT(tp->t_dev));
3536 if (IS_8251(com->pc98_if_type))
3537 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3543 /* XXX avoid h/w bug. */
3547 outb(com->iobase + (com_fifo << port_shift),
3548 FIFO_XMT_RST | com->fifo_image);
3549 if (com->pc98_if_type == COM_IF_RSA98III)
3550 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3551 outb(com->iobase + (com_fifo << port_shift),
3552 FIFO_XMT_RST | com->fifo_image);
3554 outb(com->iobase + com_fifo,
3555 FIFO_XMT_RST | com->fifo_image);
3557 com->obufs[0].l_queued = FALSE;
3558 com->obufs[1].l_queued = FALSE;
3559 if (com->state & CS_ODONE)
3560 com_events -= LOTS_OF_EVENTS;
3561 com->state &= ~(CS_ODONE | CS_BUSY);
3562 com->tp->t_state &= ~TS_BUSY;
3567 /* XXX avoid h/w bug. */
3571 if (com->pc98_if_type == COM_IF_RSA98III) {
3572 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3573 inb(com->data_port);
3575 outb(com->iobase + (com_fifo << port_shift),
3576 FIFO_RCV_RST | com->fifo_image);
3578 outb(com->iobase + com_fifo,
3579 FIFO_RCV_RST | com->fifo_image);
3581 com_events -= (com->iptr - com->ibuf);
3582 com->iptr = com->ibuf;
3596 if (mynor & CONTROL_MASK)
3598 unit = MINOR_TO_UNIT(mynor);
3599 if ((u_int) unit >= NSIOTOT)
3601 return (&sio_tty[unit]);
3605 commctl(com, bits, how)
3614 bits = TIOCM_LE; /* XXX - always enabled while open */
3615 mcr = com->mcr_image;
3620 msr = com->prev_modem_status;
3628 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
3629 * more volatile by reading the modem status a lot. Perhaps
3630 * we should latch both bits until the status is read here.
3632 if (msr & (MSR_RI | MSR_TERI))
3637 if (bits & TIOCM_DTR)
3639 if (bits & TIOCM_RTS)
3646 outb(com->modem_ctl_port,
3647 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
3650 outb(com->modem_ctl_port, com->mcr_image |= mcr);
3653 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
3668 * Set our timeout period to 1 second if no polled devices are open.
3669 * Otherwise set it to max(1/200, 1/hz).
3670 * Enable timeouts iff some device is open.
3672 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3675 for (unit = 0; unit < NSIOTOT; ++unit) {
3676 com = com_addr(unit);
3677 if (com != NULL && com->tp != NULL
3678 && com->tp->t_state & TS_ISOPEN && !com->gone) {
3680 if (com->poll || com->poll_output) {
3681 sio_timeout = hz > 200 ? hz / 200 : 1;
3687 sio_timeouts_until_log = hz / sio_timeout;
3688 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3691 /* Flush error messages, if any. */
3692 sio_timeouts_until_log = 1;
3693 comwakeup((void *)NULL);
3694 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3705 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
3708 * Recover from lost output interrupts.
3709 * Poll any lines that don't use interrupts.
3711 for (unit = 0; unit < NSIOTOT; ++unit) {
3712 com = com_addr(unit);
3713 if (com != NULL && !com->gone
3714 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
3722 * Check for and log errors, but not too often.
3724 if (--sio_timeouts_until_log > 0)
3726 sio_timeouts_until_log = hz / sio_timeout;
3727 for (unit = 0; unit < NSIOTOT; ++unit) {
3730 com = com_addr(unit);
3735 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
3740 delta = com->delta_error_counts[errnum];
3741 com->delta_error_counts[errnum] = 0;
3745 total = com->error_counts[errnum] += delta;
3746 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
3747 unit, delta, error_desc[errnum],
3748 delta == 1 ? "" : "s", total);
3754 /* commint is called when modem control line changes */
3758 register struct tty *tp;
3764 unit = MINOR_TO_UNIT(mynor);
3765 com = com_addr(unit);
3768 stat = com_tiocm_get(com);
3769 delta = com_tiocm_get_delta(com);
3771 if (com->state & CS_CTS_OFLOW) {
3772 if (stat & TIOCM_CTS)
3773 com->state |= CS_ODEVREADY;
3775 com->state &= ~CS_ODEVREADY;
3777 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) {
3778 if (stat & TIOCM_CAR )
3779 (void)(*linesw[tp->t_line].l_modem)(tp, 1);
3780 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
3781 /* negate DTR, RTS */
3782 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
3783 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
3784 /* disable IENABLE */
3785 com_int_TxRx_disable( com );
3792 disc_optim(tp, t, com)
3797 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
3798 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
3799 && (!(t->c_iflag & PARMRK)
3800 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
3801 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
3802 && linesw[tp->t_line].l_rint == ttyinput)
3803 tp->t_state |= TS_CAN_BYPASS_L_RINT;
3805 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
3806 com->hotchar = linesw[tp->t_line].l_hotchar;
3810 * Following are all routines needed for SIO to act as console
3812 #include <machine/cons.h>
3822 static speed_t siocngetspeed __P((Port_t, struct speedtab *));
3823 static void siocnclose __P((struct siocnstate *sp));
3824 static void siocnopen __P((struct siocnstate *sp));
3825 static void siocntxwait __P((void));
3828 * XXX: sciocnget() and sciocnputc() are not declared static, as they are
3829 * referred to from i386/i386/i386-gdbstub.c.
3831 static cn_probe_t siocnprobe;
3832 static cn_init_t siocninit;
3833 static cn_checkc_t siocncheckc;
3834 cn_getc_t siocngetc;
3835 cn_putc_t siocnputc;
3837 CONS_DRIVER(sio, siocnprobe, siocninit, siocngetc, siocncheckc, siocnputc);
3845 * Wait for any pending transmission to finish. Required to avoid
3846 * the UART lockup bug when the speed is changed, and for normal
3850 while ((inb(siocniobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3851 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3856 * Read the serial port specified and try to figure out what speed
3857 * it's currently running at. We're assuming the serial port has
3858 * been initialized and is basicly idle. This routine is only intended
3859 * to be run at system startup.
3861 * If the value read from the serial port doesn't make sense, return 0.
3865 siocngetspeed(iobase, table)
3867 struct speedtab *table;
3874 cfcr = inb(iobase + com_cfcr);
3875 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3877 dlbl = inb(iobase + com_dlbl);
3878 dlbh = inb(iobase + com_dlbh);
3880 outb(iobase + com_cfcr, cfcr);
3882 code = dlbh << 8 | dlbl;
3884 for ( ; table->sp_speed != -1; table++)
3885 if (table->sp_code == code)
3886 return (table->sp_speed);
3888 return 0; /* didn't match anything sane */
3893 struct siocnstate *sp;
3901 * Save all the device control registers except the fifo register
3902 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3903 * We can't save the fifo register since it is read-only.
3905 iobase = siocniobase;
3906 sp->ier = inb(iobase + com_ier);
3907 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3909 sp->cfcr = inb(iobase + com_cfcr);
3910 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3911 sp->dlbl = inb(iobase + com_dlbl);
3912 sp->dlbh = inb(iobase + com_dlbh);
3914 * Only set the divisor registers if they would change, since on
3915 * some 16550 incompatibles (Startech), setting them clears the
3916 * data input register. This also reduces the effects of the
3919 divisor = ttspeedtab(comdefaultrate, comspeedtab);
3920 dlbl = divisor & 0xFF;
3921 if (sp->dlbl != dlbl)
3922 outb(iobase + com_dlbl, dlbl);
3923 dlbh = (u_int) divisor >> 8;
3924 if (sp->dlbh != dlbh)
3925 outb(iobase + com_dlbh, dlbh);
3926 outb(iobase + com_cfcr, CFCR_8BITS);
3927 sp->mcr = inb(iobase + com_mcr);
3929 * We don't want interrupts, but must be careful not to "disable"
3930 * them by clearing the MCR_IENABLE bit, since that might cause
3931 * an interrupt by floating the IRQ line.
3933 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
3938 struct siocnstate *sp;
3943 * Restore the device control registers.
3946 iobase = siocniobase;
3947 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3948 if (sp->dlbl != inb(iobase + com_dlbl))
3949 outb(iobase + com_dlbl, sp->dlbl);
3950 if (sp->dlbh != inb(iobase + com_dlbh))
3951 outb(iobase + com_dlbh, sp->dlbh);
3952 outb(iobase + com_cfcr, sp->cfcr);
3954 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
3956 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
3957 outb(iobase + com_ier, sp->ier);
3966 struct isa_device *dvp;
3968 struct siocnstate sp;
3971 * Find our first enabled console, if any. If it is a high-level
3972 * console device, then initialize it and return successfully.
3973 * If it is a low-level console device, then initialize it and
3974 * return unsuccessfully. It must be initialized in both cases
3975 * for early use by console drivers and debuggers. Initializing
3976 * the hardware is not necessary in all cases, since the i/o
3977 * routines initialize it on the fly, but it is necessary if
3978 * input might arrive while the hardware is switched back to an
3979 * uninitialized state. We can't handle multiple console devices
3980 * yet because our low-level routines don't take a device arg.
3981 * We trust the user to set the console flags properly so that we
3982 * don't need to probe.
3984 cp->cn_pri = CN_DEAD;
3985 for (dvp = isa_devtab_tty; dvp->id_driver != NULL; dvp++)
3986 if (dvp->id_driver == &siodriver && dvp->id_enabled
3987 && COM_CONSOLE(dvp)) {
3988 siocniobase = dvp->id_iobase;
3990 if (boothowto & RB_SERIAL) {
3991 boot_speed = siocngetspeed(siocniobase,
3994 comdefaultrate = boot_speed;
3998 * Initialize the divisor latch. We can't rely on
3999 * siocnopen() to do this the first time, since it
4000 * avoids writing to the latch if the latch appears
4001 * to have the correct value. Also, if we didn't
4002 * just read the speed from the hardware, then we
4003 * need to set the speed in hardware so that
4004 * switching it later is null.
4006 cfcr = inb(siocniobase + com_cfcr);
4007 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
4008 outb(siocniobase + com_dlbl,
4009 COMBRD(comdefaultrate) & 0xff);
4010 outb(siocniobase + com_dlbh,
4011 (u_int) COMBRD(comdefaultrate) >> 8);
4012 outb(siocniobase + com_cfcr, cfcr);
4016 if (!COM_LLCONSOLE(dvp)) {
4017 cp->cn_dev = makedev(CDEV_MAJOR, dvp->id_unit);
4018 cp->cn_pri = COM_FORCECONSOLE(dvp)
4019 || boothowto & RB_SERIAL
4020 ? CN_REMOTE : CN_NORMAL;
4030 comconsole = DEV_TO_UNIT(cp->cn_dev);
4040 struct siocnstate sp;
4042 iobase = siocniobase;
4045 if (inb(iobase + com_lsr) & LSR_RXRDY)
4046 c = inb(iobase + com_data);
4062 struct siocnstate sp;
4064 iobase = siocniobase;
4067 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4069 c = inb(iobase + com_data);
4081 struct siocnstate sp;
4086 outb(siocniobase + com_data, c);
4093 * support PnP cards if we are using 'em
4098 static pnpid_t siopnp_ids[] = {
4099 { 0x5015f435, "MOT1550"},
4100 { 0x8113b04e, "Supra1381"},
4101 { 0x9012b04e, "Supra1290"},
4102 { 0x7121b04e, "SupraExpress 56i Sp"},
4103 { 0x11007256, "USR0011"},
4104 { 0x30207256, "USR2030"},
4108 static char *siopnp_probe(u_long csn, u_long vend_id);
4109 static void siopnp_attach(u_long csn, u_long vend_id, char *name,
4110 struct isa_device *dev);
4111 static u_long nsiopnp = NSIO;
4113 static struct pnp_device siopnp = {
4120 DATA_SET (pnpdevice_set, siopnp);
4123 siopnp_probe(u_long csn, u_long vend_id)
4128 for(id = siopnp_ids; id->vend_id != 0; id++) {
4129 if (vend_id == id->vend_id) {
4137 read_pnp_parms(&d, 0);
4138 if (d.enable == 0 || d.flags & 1) {
4139 printf("CSN %lu is disabled.\n", csn);
4149 siopnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev)
4152 struct isa_device *dvp;
4154 if (dev->id_unit >= NSIOTOT)
4157 if (read_pnp_parms(&d, 0) == 0) {
4158 printf("failed to read pnp parms\n");
4162 write_pnp_parms(&d, 0);
4166 dev->id_iobase = d.port[0];
4167 dev->id_irq = (1 << d.irq[0]);
4168 dev->id_ointr = siointr;
4169 dev->id_ri_flags = RI_FAST;
4172 if (dev->id_driver == NULL) {
4173 dev->id_driver = &siodriver;
4174 dvp = find_isadev(isa_devtab_tty, &siodriver, 0);
4176 dev->id_id = dvp->id_id;
4179 if ((dev->id_alive = sioprobe(dev)) != 0)
4182 printf("sio%d: probe failed\n", dev->id_unit);
4188 * pc98 local function
4192 com_tiocm_set(struct com_s *com, int msr)
4196 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS;
4199 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) )
4200 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4201 tmp |= (CMD8251_TxEN|CMD8251_RxEN);
4202 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4203 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4204 pc98_i8251_clear_or_cmd( com, mask, tmp );
4209 com_tiocm_bis(struct com_s *com, int msr)
4215 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4216 tmp |= CMD8251_TxEN|CMD8251_RxEN;
4217 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4218 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4220 pc98_i8251_or_cmd( com, tmp );
4225 com_tiocm_bic(struct com_s *com, int msr)
4231 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4232 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4233 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4235 pc98_i8251_clear_cmd( com, tmp );
4240 com_tiocm_get(struct com_s *com)
4242 return( com->pc98_prev_modem_status );
4246 com_tiocm_get_delta(struct com_s *com)
4250 tmp = com->pc98_modem_delta;
4251 com->pc98_modem_delta = 0;
4255 /* convert to TIOCM_?? ( ioctl.h ) */
4257 pc98_get_modem_status(struct com_s *com)
4262 stat = inb(com->sts_port);
4263 stat2 = inb(com->in_modem_port);
4264 msr = com->pc98_prev_modem_status
4265 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4266 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
4267 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
4268 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
4269 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
4270 #if COM_CARRIER_DETECT_EMULATE
4271 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4279 pc98_check_msr(void* chan)
4283 register struct tty *tp;
4291 unit = MINOR_TO_UNIT(mynor);
4292 com = com_addr(unit);
4296 msr = pc98_get_modem_status(com);
4297 /* make change flag */
4298 delta = msr ^ com->pc98_prev_modem_status;
4299 if ( delta & TIOCM_CAR ) {
4300 if ( com->modem_car_chg_timer ) {
4301 if ( -- com->modem_car_chg_timer )
4304 if ( com->modem_car_chg_timer = ( msr & TIOCM_CAR ) ?
4305 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE )
4309 com->modem_car_chg_timer = 0;
4310 delta = ( msr ^ com->pc98_prev_modem_status ) &
4311 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4312 com->pc98_prev_modem_status = msr;
4313 delta = ( com->pc98_modem_delta |= delta );
4315 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
4319 timeout(pc98_check_msr, (caddr_t)dev,
4320 PC98_CHECK_MODEM_INTERVAL);
4322 com->modem_checking = 0;
4327 pc98_msrint_start(dev_t dev)
4335 unit = MINOR_TO_UNIT(mynor);
4336 com = com_addr(unit);
4337 /* modem control line check routine envoke interval is 1/10 sec */
4338 if ( com->modem_checking == 0 ) {
4339 com->pc98_prev_modem_status = pc98_get_modem_status(com);
4340 com->pc98_modem_delta = 0;
4341 timeout(pc98_check_msr, (caddr_t)dev,
4342 PC98_CHECK_MODEM_INTERVAL);
4343 com->modem_checking = 1;
4349 pc98_disable_i8251_interrupt(struct com_s *com, int mod)
4351 /* disable interrupt */
4354 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4356 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4357 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
4362 pc98_enable_i8251_interrupt(struct com_s *com, int mod)
4367 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4368 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
4373 pc98_check_i8251_interrupt(struct com_s *com)
4375 return ( com->intr_enable & 0x07 );
4379 pc98_i8251_clear_cmd(struct com_s *com, int x)
4384 tmp = com->pc98_prev_siocmd & ~(x);
4385 outb(com->cmd_port, tmp);
4386 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4391 pc98_i8251_or_cmd(struct com_s *com, int x)
4396 tmp = com->pc98_prev_siocmd | (x);
4397 outb(com->cmd_port, tmp);
4398 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4403 pc98_i8251_set_cmd(struct com_s *com, int x)
4409 outb(com->cmd_port, tmp);
4410 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4415 pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4419 tmp = com->pc98_prev_siocmd & ~(clr);
4421 outb(com->cmd_port, tmp);
4422 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4427 pc98_i8251_get_cmd(struct com_s *com)
4429 return com->pc98_prev_siocmd;
4433 pc98_i8251_get_mod(struct com_s *com)
4435 return com->pc98_prev_siomod;
4439 pc98_i8251_reset(struct com_s *com, int mode, int command)
4441 outb(com->cmd_port, 0); /* dummy */
4443 outb(com->cmd_port, 0); /* dummy */
4445 outb(com->cmd_port, 0); /* dummy */
4447 outb(com->cmd_port, CMD8251_RESET); /* internal reset */
4449 outb(com->cmd_port, mode ); /* mode register */
4450 com->pc98_prev_siomod = mode;
4452 pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4456 pc98_check_sysclock(void)
4458 /* get system clock from port */
4459 if ( pc98_machine_type & M_8M ) {
4460 /* 8 MHz system & H98 */
4469 com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4474 count = pc98_ttspeedtab( com, speed );
4475 if ( count < 0 ) return;
4477 previnterrupt = pc98_check_i8251_interrupt(com);
4478 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4480 switch ( cflag&CSIZE ) {
4482 cfcr = MOD8251_5BITS; break;
4484 cfcr = MOD8251_6BITS; break;
4486 cfcr = MOD8251_7BITS; break;
4488 cfcr = MOD8251_8BITS; break;
4490 if ( cflag&PARENB ) {
4492 cfcr |= MOD8251_PODD;
4494 cfcr |= MOD8251_PEVEN;
4496 cfcr |= MOD8251_PDISAB;
4499 cfcr |= MOD8251_STOP2;
4501 cfcr |= MOD8251_STOP1;
4503 if ( count & 0x10000 )
4504 cfcr |= MOD8251_CLKX1;
4506 cfcr |= MOD8251_CLKX16;
4508 if (epson_machine_id != 0x20) { /* XXX */
4510 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4513 /* set baud rate from ospeed */
4514 pc98_set_baud_rate( com, count );
4516 if ( cfcr != pc98_i8251_get_mod(com) )
4517 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4519 pc98_enable_i8251_interrupt( com, previnterrupt );
4523 pc98_ttspeedtab(struct com_s *com, int speed)
4525 int if_type, effect_sp, count = -1, mod;
4527 if_type = com->pc98_if_type & 0x0f;
4529 switch (com->pc98_if_type) {
4530 case COM_IF_INTERNAL:
4531 if (PC98SIO_baud_rate_port(if_type) != -1) {
4532 count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4534 count |= COM1_EXT_CLOCK;
4539 /* for *1CLK asynchronous! mode, TEFUTEFU */
4540 mod = (sysclock == 5) ? 2457600 : 1996800;
4541 effect_sp = ttspeedtab( speed, pc98speedtab );
4542 if ( effect_sp < 0 ) /* XXX */
4543 effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4544 if ( effect_sp <= 0 )
4546 if ( effect_sp == speed )
4548 if ( mod % effect_sp )
4550 count = mod / effect_sp;
4551 if ( count > 65535 )
4553 if ( effect_sp != speed )
4556 case COM_IF_PC9861K_1:
4557 case COM_IF_PC9861K_2:
4560 case COM_IF_IND_SS_1:
4561 case COM_IF_IND_SS_2:
4562 case COM_IF_PIO9032B_1:
4563 case COM_IF_PIO9032B_2:
4564 if ( speed == 0 ) return 0;
4565 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4567 case COM_IF_B98_01_1:
4568 case COM_IF_B98_01_2:
4569 if ( speed == 0 ) return 0;
4570 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4572 if (count == 0 || count == 1) {
4574 count |= 0x20000; /* x1 mode for 76800 and 153600 */
4584 pc98_set_baud_rate( struct com_s *com, int count )
4588 if_type = com->pc98_if_type & 0x0f;
4589 io = com->iobase & 0xff00;
4591 switch (com->pc98_if_type) {
4592 case COM_IF_INTERNAL:
4593 if (PC98SIO_baud_rate_port(if_type) != -1) {
4594 if (count & COM1_EXT_CLOCK) {
4595 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
4598 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
4603 printf( "[ Illegal count : %d ]", count );
4605 } else if ( count == 0 )
4614 outb( 0x75, count & 0xff );
4616 outb( 0x75, (count >> 8) & 0xff );
4619 case COM_IF_IND_SS_1:
4620 case COM_IF_IND_SS_2:
4621 outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
4622 outb(io | PC98SIO_baud_rate_port(if_type), 0);
4623 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
4624 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
4625 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
4627 case COM_IF_PIO9032B_1:
4628 case COM_IF_PIO9032B_2:
4629 outb(io | PC98SIO_baud_rate_port(if_type), count);
4631 case COM_IF_B98_01_1:
4632 case COM_IF_B98_01_2:
4633 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
4636 * Some old B98_01 board should be controlled
4637 * in different way, but this hasn't been tested yet.
4639 outb(io | PC98SIO_func_port(if_type),
4640 (count & 0x20000) ? 0xf0 : 0xf2);
4646 pc98_check_if_type(struct isa_device *dev, struct siodev *iod)
4648 int irr, io, if_type, tmp;
4649 static short irq_tab[2][8] = {
4650 { 3, 5, 6, 9, 10, 12, 13, -1},
4651 { 3, 10, 12, 13, 5, 6, 9, -1}
4654 iod->if_type = if_type = (dev->id_flags >> 24) & 0xff;
4655 if ((if_type < 0 || if_type > COM_IF_END1) &&
4656 (if_type < 0x10 || if_type > COM_IF_END2))
4660 io = dev->id_iobase & 0xff00;
4662 if (IS_8251(iod->if_type)) {
4663 if (PC98SIO_func_port(if_type) != -1) {
4664 outb(io | PC98SIO_func_port(if_type), 0xf2);
4665 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4666 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4667 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4670 iod->cmd = io | PC98SIO_cmd_port(if_type);
4671 iod->sts = io | PC98SIO_sts_port(if_type);
4672 iod->mod = io | PC98SIO_in_modem_port(if_type);
4673 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
4675 if (iod->if_type == COM_IF_INTERNAL) {
4678 /* XXX check new internal port. */
4681 for (tmp = 0; tmp < 100; tmp++) {
4682 if ((inb(0x138) & 1) == 0) {
4683 PC98SIO_baud_rate_port(if_type) = 0x13a;
4684 if_8251_type[if_type].name = " (internal fast)";
4685 if_8251_type[if_type].speedtab = pc98fast_speedtab;
4691 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4692 if ((dev->id_iobase & 0xff) == IO_COM2)
4693 iod->irq = irq_tab[0][tmp];
4695 iod->irq = irq_tab[1][tmp];
4698 irr = if_16550a_type[if_type].irr_read;
4699 #ifdef COM_MULTIPORT
4700 if (!COM_ISMULTIPORT(dev) || dev->id_unit == COM_MPMASTER(dev))
4703 tmp = inb(io | irr);
4704 if (dev->id_iobase & 0x01) /* XXX depend on RSB-384 */
4705 iod->irq = irq_tab[1][tmp >> 3];
4707 iod->irq = irq_tab[0][tmp & 0x07];
4710 if ( iod->irq == -1 ) return -1;
4715 pc98_set_ioport( struct com_s *com, int id_flags )
4719 if_type = (id_flags >> 24) & 0xff;
4720 if (IS_8251(if_type)) {
4721 pc98_check_sysclock();
4722 io = com->iobase & 0xff00;
4723 com->pc98_if_type = if_type;
4725 com->data_port = io | PC98SIO_data_port(if_type);
4726 com->cmd_port = io | PC98SIO_cmd_port(if_type);
4727 com->sts_port = io | PC98SIO_sts_port(if_type);
4728 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
4729 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
4735 #endif /* PC98 defined */