2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $Id: sio.c,v 1.95 1999/05/10 09:37:37 kato Exp $
34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
38 #include "opt_comconsole.h"
39 #include "opt_compat.h"
41 #include "opt_devfs.h"
44 /* #include "pnp.h" */
48 * Serial driver, based on 386BSD-0.1 com driver.
49 * Mostly rewritten to use pseudo-DMA.
50 * Works for National Semiconductor NS8250-NS16550AF UARTs.
51 * COM driver, based on HP dca driver.
53 * Changes for PC-Card integration:
54 * - Added PC-Card driver table and handlers
56 /*===============================================================
57 * 386BSD(98),FreeBSD-1.1x(98) com driver.
59 * modified for PC9801 by M.Ishii
60 * Kyoto University Microcomputer Club (KMC)
61 * Chou "TEFUTEFU" Hirotomi
62 * Kyoto Univ. the faculty of medicine
63 *===============================================================
64 * FreeBSD-2.0.1(98) sio driver.
66 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
67 * T.Koike(hfc01340@niftyserve.or.jp)
68 * implement kernel device configuration
69 * aizu@orient.center.nitech.ac.jp
73 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local
75 * This driver is under debugging,has bugs.
78 * options COM_MULTIPORT #if using MC16550II
79 * device sio0 at nec? port 0x30 tty irq 4 #internal
80 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1
81 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2
82 * # ~~~~~iobase ~~multi port flag
83 * # ~ master device is sio1
85 * cd /dev; MAKEDEV ttyd0 ttyd1 ..
87 * 57600bps is too fast for sio0(internal8251)
89 * #set default speed 9600
92 * stty </dev/ttyid$i crtscts 9600
93 * : # ~~~~ default speed(can change after init.)
97 * 5) PC9861K,PIO9032B,B98_01
101 * modified for AIWA B98-01
102 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
104 * How to configure...
105 * # options COM_MULTIPORT # support for MICROCORE MC16550II
106 * ... comment-out this line, which will conflict with B98_01.
107 * options "B98_01" # support for AIWA B98-01
108 * device sio1 at nec? port 0x00d1 tty irq ?
109 * device sio2 at nec? port 0x00d5 tty irq ?
110 * ... you can leave these lines `irq ?', irq will be autodetected.
113 * Modified by Y.Takahashi of Kogakuin University.
117 #define COM_IF_INTERNAL 0x00
118 #define COM_IF_PC9861K_1 0x01
119 #define COM_IF_PC9861K_2 0x02
120 #define COM_IF_IND_SS_1 0x03
121 #define COM_IF_IND_SS_2 0x04
122 #define COM_IF_PIO9032B_1 0x05
123 #define COM_IF_PIO9032B_2 0x06
124 #define COM_IF_B98_01_1 0x07
125 #define COM_IF_B98_01_2 0x08
126 #define COM_IF_END1 COM_IF_B98_01_2
127 #define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */
128 #define COM_IF_NS16550 0x11
129 #define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */
130 #define COM_IF_MC16550II 0x13
131 #define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */
132 #define COM_IF_RSB3000 0x15
133 #define COM_IF_RSB384 0x16
134 #define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */
135 #define COM_IF_RSA98III 0x18
136 #define COM_IF_ESP98 0x19
137 #define COM_IF_END2 COM_IF_ESP98
140 #include <sys/param.h>
141 #include <sys/systm.h>
142 #include <sys/reboot.h>
143 #include <sys/malloc.h>
145 #include <sys/proc.h>
146 #include <sys/module.h>
147 #include <sys/conf.h>
148 #include <sys/dkstat.h>
149 #include <sys/fcntl.h>
150 #include <sys/interrupt.h>
151 #include <sys/kernel.h>
152 #include <sys/syslog.h>
153 #include <sys/sysctl.h>
155 #include <machine/bus.h>
156 #include <sys/rman.h>
158 #include <sys/devfsext.h>
160 #include <sys/timepps.h>
163 #include <pc98/pc98/pc98.h>
164 #include <pc98/pc98/pc98_machdep.h>
165 #include <i386/isa/ic/i8251.h>
167 #include <isa/isareg.h>
169 #include <isa/isavar.h>
170 #include <machine/lock.h>
172 #include <machine/clock.h>
173 #include <machine/ipl.h>
175 #include <machine/lock.h>
177 #include <machine/resource.h>
179 #include <isa/sioreg.h>
182 #include <i386/isa/ic/esp.h>
184 #include <i386/isa/ic/ns16550.h>
186 #include <i386/isa/ic/rsa.h>
193 #include <sys/module.h>
194 #include <pccard/cardinfo.h>
195 #include <pccard/slot.h>
199 #include <i386/isa/pnp.h>
205 #define disable_intr() 0
206 #define enable_intr() 0
210 #define disable_intr() COM_DISABLE_INTR()
211 #define enable_intr() COM_ENABLE_INTR()
216 #define EXTRA_SIO MAX_PNP_CARDS
222 #define NSIOTOT (NSIO + EXTRA_SIO)
224 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
226 #define CALLOUT_MASK 0x80
227 #define CONTROL_MASK 0x60
228 #define CONTROL_INIT_STATE 0x20
229 #define CONTROL_LOCK_STATE 0x40
230 #define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
231 #define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
232 #define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
235 /* checks in flags for multiport and which is multiport "master chip"
238 #define COM_ISMULTIPORT(flags) ((flags) & 0x01)
239 #define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
240 #define COM_NOTAST4(flags) ((flags) & 0x04)
241 #endif /* COM_MULTIPORT */
243 #define COM_CONSOLE(flags) ((flags) & 0x10)
244 #define COM_FORCECONSOLE(flags) ((flags) & 0x20)
245 #define COM_LLCONSOLE(flags) ((flags) & 0x40)
246 #define COM_DEBUGGER(flags) ((flags) & 0x80)
247 #define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
248 #define COM_NOFIFO(flags) ((flags) & 0x02)
249 #define COM_ST16650A(flags) ((flags) & 0x20000)
250 #define COM_C_NOPROBE (0x40000)
251 #define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
252 #define COM_C_IIR_TXRDYBUG (0x80000)
253 #define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
254 #define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
257 #define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
259 #define com_scr 7 /* scratch register for 16450-16550 (R/W) */
264 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
265 * than the other bits so that they can be tested as a group without masking
268 * The following com and tty flags correspond closely:
269 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
271 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
272 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
273 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
274 * TS_FLUSH is not used.
275 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
276 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
278 #define CS_BUSY 0x80 /* output in progress */
279 #define CS_TTGO 0x40 /* output not stopped by XOFF */
280 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
281 #define CS_CHECKMSR 1 /* check of MSR scheduled */
282 #define CS_CTS_OFLOW 2 /* use CTS output flow control */
283 #define CS_DTR_OFF 0x10 /* DTR held off */
284 #define CS_ODONE 4 /* output completed */
285 #define CS_RTS_IFLOW 8 /* use RTS input flow control */
286 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
288 static char const * const error_desc[] = {
291 #define CE_INTERRUPT_BUF_OVERFLOW 1
292 "interrupt-level buffer overflow",
293 #define CE_TTY_BUF_OVERFLOW 2
294 "tty-level buffer overflow",
298 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
300 /* types. XXX - should be elsewhere */
301 typedef u_int Port_t; /* hardware port */
302 typedef u_char bool_t; /* boolean */
304 /* queue of linear buffers */
306 u_char *l_head; /* next char to process */
307 u_char *l_tail; /* one past the last char to process */
308 struct lbq *l_next; /* next in queue */
309 bool_t l_queued; /* nonzero if queued */
312 /* com device structure */
314 u_int flags; /* Copy isa device flags */
315 u_char state; /* miscellaneous flag bits */
316 bool_t active_out; /* nonzero if the callout device is open */
317 u_char cfcr_image; /* copy of value written to CFCR */
319 bool_t esp; /* is this unit a hayes esp board? */
321 u_char extra_state; /* more flag bits, separate for order trick */
322 u_char fifo_image; /* copy of value written to FIFO */
323 bool_t hasfifo; /* nonzero for 16550 UARTs */
324 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
325 bool_t loses_outints; /* nonzero if device loses output interrupts */
326 u_char mcr_image; /* copy of value written to MCR */
328 bool_t multiport; /* is this unit part of a multiport device? */
329 #endif /* COM_MULTIPORT */
330 bool_t no_irq; /* nonzero if irq is not attached */
331 bool_t gone; /* hardware disappeared */
332 bool_t poll; /* nonzero if polling is required */
333 bool_t poll_output; /* nonzero if polling for output is required */
334 int unit; /* unit number */
335 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
337 u_int wopeners; /* # processes waiting for DCD in open() */
340 * The high level of the driver never reads status registers directly
341 * because there would be too many side effects to handle conveniently.
342 * Instead, it reads copies of the registers stored here by the
345 u_char last_modem_status; /* last MSR read by intr handler */
346 u_char prev_modem_status; /* last MSR handled by high level */
348 u_char hotchar; /* ldisc-specific char to be handled ASAP */
349 u_char *ibuf; /* start of input buffer */
350 u_char *ibufend; /* end of input buffer */
351 u_char *ibufold; /* old input buffer, to be freed */
352 u_char *ihighwater; /* threshold in input buffer */
353 u_char *iptr; /* next free spot in input buffer */
354 int ibufsize; /* size of ibuf (not include error bytes) */
355 int ierroff; /* offset of error bytes in ibuf */
357 struct lbq obufq; /* head of queue of output buffers */
358 struct lbq obufs[2]; /* output buffers */
363 Port_t in_modem_port;
364 Port_t intr_ctrl_port;
366 int pc98_prev_modem_status;
367 int pc98_modem_delta;
368 int modem_car_chg_timer;
369 int pc98_prev_siocmd;
370 int pc98_prev_siomod;
374 Port_t data_port; /* i/o ports */
381 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
383 Port_t modem_ctl_port;
384 Port_t line_status_port;
385 Port_t modem_status_port;
386 Port_t intr_ctl_port; /* Ports of IIR register */
388 struct tty *tp; /* cross reference */
391 struct termios it_in; /* should be in struct tty */
392 struct termios it_out;
395 struct termios lt_in; /* should be in struct tty */
396 struct termios lt_out;
399 bool_t do_dcd_timestamp;
400 struct timeval timestamp;
401 struct timeval dcd_timestamp;
402 struct pps_state pps;
404 u_long bytes_in; /* statistics */
406 u_int delta_error_counts[CE_NTYPES];
407 u_long error_counts[CE_NTYPES];
410 * Data area for output buffers. Someday we should build the output
411 * buffer queue without copying data.
422 void *devfs_token_ttyd;
423 void *devfs_token_ttyl;
424 void *devfs_token_ttyi;
425 void *devfs_token_cuaa;
426 void *devfs_token_cual;
427 void *devfs_token_cuai;
432 static int espattach __P((struct com_s *com, Port_t esp_port));
434 static int sioattach __P((device_t dev));
436 static timeout_t siobusycheck;
437 static timeout_t siodtrwakeup;
438 static void comhardclose __P((struct com_s *com));
439 static void sioinput __P((struct com_s *com));
440 static void siointr1 __P((struct com_s *com));
441 static void siointr __P((void *arg));
442 static int commctl __P((struct com_s *com, int bits, int how));
443 static int comparam __P((struct tty *tp, struct termios *t));
444 static swihand_t siopoll;
445 static int sioprobe __P((device_t dev));
446 static void siosettimeout __P((void));
447 static int siosetwater __P((struct com_s *com, speed_t speed));
448 static void comstart __P((struct tty *tp));
449 static timeout_t comwakeup;
450 static void disc_optim __P((struct tty *tp, struct termios *t,
454 static char driver_name[] = "sio";
456 /* table and macro for fast conversion from a unit number to its com struct */
457 static devclass_t sio_devclass;
458 #define com_addr(unit) ((struct com_s *) \
459 devclass_get_softc(sio_devclass, unit))
461 static device_method_t sio_methods[] = {
462 /* Device interface */
463 DEVMETHOD(device_probe, sioprobe),
464 DEVMETHOD(device_attach, sioattach),
469 static driver_t sio_driver = {
472 sizeof(struct com_s),
475 static d_open_t sioopen;
476 static d_close_t sioclose;
477 static d_read_t sioread;
478 static d_write_t siowrite;
479 static d_ioctl_t sioioctl;
480 static d_stop_t siostop;
481 static d_devtotty_t siodevtotty;
483 #define CDEV_MAJOR 28
484 static struct cdevsw sio_cdevsw = {
485 sioopen, sioclose, sioread, siowrite,
486 sioioctl, siostop, noreset, siodevtotty,
487 ttpoll, nommap, NULL, driver_name,
488 NULL, -1, nodump, nopsize,
493 static volatile speed_t comdefaultrate = CONSPEED;
495 static volatile speed_t gdbdefaultrate = CONSPEED;
497 static u_int com_events; /* input chars + weighted output completions */
498 static Port_t siocniobase;
499 static int siocnunit;
500 static Port_t siogdbiobase;
501 static int siogdbunit = -1;
502 static bool_t sio_registered;
503 static int sio_timeout;
504 static int sio_timeouts_until_log;
505 static struct callout_handle sio_timeout_handle
506 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
508 static struct tty *sio_tty[NSIOTOT];
510 static struct tty sio_tty[NSIOTOT];
512 static const int nsio_tty = NSIOTOT;
518 Port_t cmd, sts, ctrl, mod;
522 #define COM_INT_DISABLE {int previpri; previpri=spltty();
523 #define COM_INT_ENABLE splx(previpri);}
524 #define IEN_TxFLAG IEN_Tx
526 #define COM_CARRIER_DETECT_EMULATE 0
527 #define PC98_CHECK_MODEM_INTERVAL (hz/10)
528 #define DCD_OFF_TOLERANCE 2
529 #define DCD_ON_RECOGNITION 2
530 #define IS_8251(if_type) (!(if_type & 0x10))
531 #define COM1_EXT_CLOCK 0x40000
533 static void commint __P((dev_t dev));
534 static void com_tiocm_set __P((struct com_s *com, int msr));
535 static void com_tiocm_bis __P((struct com_s *com, int msr));
536 static void com_tiocm_bic __P((struct com_s *com, int msr));
537 static int com_tiocm_get __P((struct com_s *com));
538 static int com_tiocm_get_delta __P((struct com_s *com));
539 static void pc98_msrint_start __P((dev_t dev));
540 static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed));
541 static int pc98_ttspeedtab __P((struct com_s *com, int speed));
542 static int pc98_get_modem_status __P((struct com_s *com));
543 static timeout_t pc98_check_msr;
544 static void pc98_set_baud_rate __P((struct com_s *com, int count));
545 static void pc98_i8251_reset __P((struct com_s *com, int mode, int command));
546 static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod));
547 static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
548 static int pc98_check_i8251_interrupt __P((struct com_s *com));
549 static int pc98_i8251_get_cmd __P((struct com_s *com));
550 static int pc98_i8251_get_mod __P((struct com_s *com));
551 static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
552 static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
553 static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
554 static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
555 static int pc98_check_if_type __P((device_t dev, struct siodev *iod));
556 static void pc98_check_sysclock __P((void));
557 static int pc98_set_ioport __P((struct com_s *com, int id_flags));
559 #define com_int_Tx_disable(com) \
560 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
561 #define com_int_Tx_enable(com) \
562 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
563 #define com_int_Rx_disable(com) \
564 pc98_disable_i8251_interrupt(com,IEN_Rx)
565 #define com_int_Rx_enable(com) \
566 pc98_enable_i8251_interrupt(com,IEN_Rx)
567 #define com_int_TxRx_disable(com) \
568 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
569 #define com_int_TxRx_enable(com) \
570 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
571 #define com_send_break_on(com) \
572 pc98_i8251_or_cmd(com,CMD8251_SBRK)
573 #define com_send_break_off(com) \
574 pc98_i8251_clear_cmd(com,CMD8251_SBRK)
576 static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
598 static struct speedtab pc98fast_speedtab[] = {
599 { 9600, 0x80 | COMBRD(9600), },
600 { 19200, 0x80 | COMBRD(19200), },
601 { 38400, 0x80 | COMBRD(38400), },
602 { 57600, 0x80 | COMBRD(57600), },
603 { 115200, 0x80 | COMBRD(115200), },
606 static struct speedtab comspeedtab_pio9032b[] = {
617 static struct speedtab comspeedtab_b98_01[] = {
632 static struct speedtab comspeedtab_mc16550[] = {
648 static struct speedtab comspeedtab_rsb384[] = {
669 static struct speedtab comspeedtab_rsa[] = {
671 { 50, COMBRD_RSA(50) },
672 { 75, COMBRD_RSA(75) },
673 { 110, COMBRD_RSA(110) },
674 { 134, COMBRD_RSA(134) },
675 { 150, COMBRD_RSA(150) },
676 { 200, COMBRD_RSA(200) },
677 { 300, COMBRD_RSA(300) },
678 { 600, COMBRD_RSA(600) },
679 { 1200, COMBRD_RSA(1200) },
680 { 1800, COMBRD_RSA(1800) },
681 { 2400, COMBRD_RSA(2400) },
682 { 4800, COMBRD_RSA(4800) },
683 { 9600, COMBRD_RSA(9600) },
684 { 19200, COMBRD_RSA(19200) },
685 { 38400, COMBRD_RSA(38400) },
686 { 57600, COMBRD_RSA(57600) },
687 { 115200, COMBRD_RSA(115200) },
688 { 230400, COMBRD_RSA(230400) },
689 { 460800, COMBRD_RSA(460800) },
690 { 921600, COMBRD_RSA(921600) },
695 static struct speedtab comspeedtab[] = {
699 { 110, COMBRD(110) },
700 { 134, COMBRD(134) },
701 { 150, COMBRD(150) },
702 { 200, COMBRD(200) },
703 { 300, COMBRD(300) },
704 { 600, COMBRD(600) },
705 { 1200, COMBRD(1200) },
706 { 1800, COMBRD(1800) },
707 { 2400, COMBRD(2400) },
708 { 4800, COMBRD(4800) },
709 { 9600, COMBRD(9600) },
710 { 19200, COMBRD(19200) },
711 { 38400, COMBRD(38400) },
712 { 57600, COMBRD(57600) },
713 { 115200, COMBRD(115200) },
722 struct speedtab *speedtab;
725 /* COM_IF_INTERNAL */
726 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
727 -1, pc98speedtab, 1 },
728 /* COM_IF_PC9861K_1 */
729 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
731 /* COM_IF_PC9861K_2 */
732 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
734 /* COM_IF_IND_SS_1 */
735 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
736 3, comspeedtab_mc16550, 1 },
737 /* COM_IF_IND_SS_2 */
738 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
739 3, comspeedtab_mc16550, 1 },
740 /* COM_IF_PIO9032B_1 */
741 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
742 7, comspeedtab_pio9032b, 1 },
743 /* COM_IF_PIO9032B_2 */
744 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
745 7, comspeedtab_pio9032b, 1 },
746 /* COM_IF_B98_01_1 */
747 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
748 7, comspeedtab_b98_01, 0 },
749 /* COM_IF_B98_01_2 */
750 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
751 7, comspeedtab_b98_01, 0 },
753 #define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
754 #define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
755 #define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
756 #define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
757 #define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
758 #define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
759 #define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
767 struct speedtab *speedtab;
768 } if_16550a_type[] = {
770 { " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab },
772 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
773 /* COM_IF_SECOND_CCU */
774 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
775 /* COM_IF_MC16550II */
776 { " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
778 { " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
780 { " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
782 { " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
783 /* COM_IF_MODEM_CARD */
784 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
785 /* COM_IF_RSA98III */
786 { " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa },
788 { " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 },
795 /* XXX configure this properly. */
796 static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
797 static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
799 #define ESP98_CMD1 (ESP_CMD1 * 0x100)
800 #define ESP98_CMD2 (ESP_CMD2 * 0x100)
801 #define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
802 #define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
806 /* XXX configure this properly. */
807 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
808 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
814 * handle sysctl read/write requests for console speed
816 * In addition to setting comdefaultrate for I/O through /dev/console,
817 * also set the initial and lock values for the /dev/ttyXX device
818 * if there is one associated with the console. Finally, if the /dev/tty
819 * device has already been open, change the speed on the open running port
824 sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS
831 newspeed = comdefaultrate;
833 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
834 if (error || !req->newptr)
837 comdefaultrate = newspeed;
839 if (comconsole < 0) /* serial console not selected? */
842 com = com_addr(comconsole);
847 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
848 * (note, the lock rates really are boolean -- if non-zero, disallow
851 com->it_in.c_ispeed = com->it_in.c_ospeed =
852 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
853 com->it_out.c_ispeed = com->it_out.c_ospeed =
854 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
857 * if we're open, change the running rate too
860 if (tp && (tp->t_state & TS_ISOPEN)) {
861 tp->t_termios.c_ispeed =
862 tp->t_termios.c_ospeed = comdefaultrate;
864 error = comparam(tp, &tp->t_termios);
870 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
871 0, 0, sysctl_machdep_comdefaultrate, "I", "");
875 * PC-Card (PCMCIA) specific code.
877 static int sioinit __P((struct pccard_devinfo *));
878 static void siounload __P((struct pccard_devinfo *));
879 static int card_intr __P((struct pccard_devinfo *));
881 PCCARD_MODULE(sio, sioinit, siounload, card_intr, 0, tty_imask);
884 * Initialize the device - called from Slot manager.
887 sioinit(struct pccard_devinfo *devi)
890 /* validate unit number. */
891 if (devi->isahd.id_unit >= (NSIOTOT))
893 /* Make sure it isn't already probed. */
894 if (com_addr(devi->isahd.id_unit))
897 /* It's already probed as serial by Upper */
898 devi->isahd.id_flags |= COM_C_NOPROBE;
901 * Probe the device. If a value is returned, the
902 * device was found at the location.
904 if (sioprobe(&devi->isahd) == 0)
906 if (sioattach(&devi->isahd) == 0)
913 * siounload - unload the driver and clear the table.
915 * This is usually called when the card is ejected, but
916 * can be caused by a modunload of a controller driver.
917 * The idea is to reset the driver's view of the device
918 * and ensure that any driver entry points such as
919 * read and write do not hang.
922 siounload(struct pccard_devinfo *devi)
927 printf("NULL devi in siounload\n");
930 com = com_addr(devi->isahd.id_unit);
932 printf("NULL com in siounload\n");
936 printf("sio%d already unloaded!\n",devi->isahd.id_unit);
939 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
941 printf("sio%d: unload\n", devi->isahd.id_unit);
947 if (com->ibuf != NULL)
948 free(com->ibuf, M_DEVBUF);
950 printf("sio%d: unload,gone\n", devi->isahd.id_unit);
955 * card_intr - Shared interrupt called from
956 * front end of PC-Card handler.
959 card_intr(struct pccard_devinfo *devi)
964 com = com_addr(devi->isahd.id_unit);
965 if (com && !com->gone)
966 siointr1(com_addr(devi->isahd.id_unit));
970 #endif /* NCARD > 0 */
972 #define SET_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) | (bit))
973 #define CLR_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) & ~(bit))
979 static bool_t already_init;
984 intrmask_t irqmap[4];
989 u_int flags = isa_get_flags(dev);
995 Port_t rsabase = NULL;
1000 * Turn off MCR_IENABLE for all likely serial ports. An unused
1001 * port with its MCR_IENABLE gate open will inhibit interrupts
1002 * from any used port that shares the interrupt vector.
1003 * XXX the gate enable is elsewhere for some multiports.
1008 devclass_get_devices(sio_devclass, &devs, &count);
1010 for (i = 0; i < count; i++) {
1012 tmp = (flags >> 24) & 0xff;
1014 outb((isa_get_port(xdev) & 0xff00) | PC98SIO_cmd_port(tmp & 0x0f), 0xf2);
1016 if (tmp == COM_IF_RSA98III) {
1017 rsabase = isa_get_port(xdev) & 0xfff0;
1018 outb(isa_get_port(xdev) + 8 + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1020 outb(isa_get_port(xdev) + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1023 for (i = 0; i < count; i++) {
1025 outb(isa_get_port(xdev) + com_mcr, 0);
1029 already_init = TRUE;
1032 if (COM_LLCONSOLE(flags)) {
1033 printf("sio%d: reserved for low-level i/o\n",
1034 device_get_unit(dev));
1042 * If the port is i8251 UART (internal, B98_01)
1044 if (pc98_check_if_type(dev, &iod) == -1)
1047 isa_set_irq(dev, iod.irq);
1048 if (IS_8251(iod.if_type)) {
1055 outb(iod.cmd, CMD8251_RESET);
1056 DELAY(1000); /* for a while...*/
1057 outb(iod.cmd, 0xf2); /* MODE (dummy) */
1059 outb(iod.cmd, 0x01); /* CMD (dummy) */
1060 DELAY(1000); /* for a while...*/
1061 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
1064 if (if_8251_type[iod.if_type & 0x0f].check_irq) {
1066 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
1067 outb( iod.ctrl, tmp|IEN_TxEMP );
1069 result = isa_irq_pending() ? 0 : ENXIO;
1070 outb( iod.ctrl, tmp );
1074 * B98_01 doesn't activate TxEMP interrupt line
1075 * when being reset, so we can't check irq pending.
1079 if (epson_machine_id==0x20) { /* XXX */
1082 isa_set_portsize(dev, 4);
1087 * If the device is on a multiport card and has an AST/4
1088 * compatible interrupt control register, initialize this
1089 * register and prepare to leave MCR_IENABLE clear in the mcr.
1090 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1091 * Point idev to the device struct giving the correct id_irq.
1092 * This is the struct for the master device if there is one.
1095 mcr_image = MCR_IENABLE;
1097 if (iod.if_type == COM_IF_RSA98III) {
1099 rsabase = isa_get_port(idev) & 0xfff0;
1100 if (rsabase != isa_get_port(idev))
1102 outb(rsabase + rsa_msr, 0x04);
1103 outb(rsabase + rsa_frr, 0x00);
1104 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36)
1106 outb(rsabase + rsa_ier, 0x00);
1107 outb(rsabase + rsa_frr, 0x00);
1108 outb(rsabase + rsa_tivsr, 0x00);
1109 outb(rsabase + rsa_tcr, 0x00);
1112 #ifdef COM_MULTIPORT
1113 if (COM_ISMULTIPORT(flags)) {
1114 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
1116 printf("sio%d: master device %d not configured\n",
1117 device_get_unit(dev), COM_MPMASTER(flags));
1118 isa_set_irq(dev, 0);
1122 if (!COM_NOTAST4(flags)) {
1123 outb(isa_get_port(idev) + com_scr,
1124 isa_get_irq(idev) >= 0 ? 0x80 : 0);
1129 #endif /* COM_MULTIPORT */
1130 if (isa_get_irq(idev) < 0)
1134 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1137 switch (isa_get_irq(idev)) {
1138 case 3: irqout = 4; break;
1139 case 5: irqout = 5; break;
1140 case 6: irqout = 6; break;
1141 case 12: irqout = 7; break;
1143 printf("sio%d: irq configuration error\n",
1144 device_get_unit(dev));
1147 outb((isa_get_port(dev) & 0x00ff) | tmp, irqout);
1149 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift;
1151 bzero(failures, sizeof failures);
1152 iobase = isa_get_port(dev);
1154 if (iod.if_type == COM_IF_RSA98III)
1159 * We don't want to get actual interrupts, just masked ones.
1160 * Interrupts from this line should already be masked in the ICU,
1161 * but mask them in the processor as well in case there are some
1162 * (misconfigured) shared interrupts.
1168 * Initialize the speed and the word size and wait long enough to
1169 * drain the maximum of 16 bytes of junk in device output queues.
1170 * The speed is undefined after a master reset and must be set
1171 * before relying on anything related to output. There may be
1172 * junk after a (very fast) soft reboot and (apparently) after
1174 * XXX what about the UART bug avoided by waiting in comparam()?
1175 * We don't want to to wait long enough to drain at 2 bps.
1177 if (iobase == siocniobase)
1178 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1181 tmp = ttspeedtab(SIO_TEST_SPEED,
1182 if_16550a_type[iod.if_type & 0x0f].speedtab);
1183 outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS);
1184 outb(iobase + (com_dlbl << port_shift), tmp & 0xff);
1185 outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff);
1186 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1188 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
1189 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
1190 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
1191 outb(iobase + com_cfcr, CFCR_8BITS);
1193 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1197 * Enable the interrupt gate and disable device interupts. This
1198 * should leave the device driving the interrupt line low and
1199 * guarantee an edge trigger if an interrupt can be generated.
1203 outb(iobase + (com_mcr << port_shift), mcr_image);
1204 outb(iobase + (com_ier << port_shift), 0);
1206 outb(iobase + com_mcr, mcr_image);
1207 outb(iobase + com_ier, 0);
1209 DELAY(1000); /* XXX */
1210 irqmap[0] = isa_irq_pending();
1213 * Attempt to set loopback mode so that we can send a null byte
1214 * without annoying any external device.
1218 outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK);
1220 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK);
1224 * Attempt to generate an output interrupt. On 8250's, setting
1225 * IER_ETXRDY generates an interrupt independent of the current
1226 * setting and independent of whether the THR is empty. On 16450's,
1227 * setting IER_ETXRDY generates an interrupt independent of the
1228 * current setting. On 16550A's, setting IER_ETXRDY only
1229 * generates an interrupt when IER_ETXRDY is not already set.
1232 outb(iobase + (com_ier << port_shift), IER_ETXRDY);
1233 if (iod.if_type == COM_IF_RSA98III)
1234 outb(rsabase + rsa_ier, 0x04);
1236 outb(iobase + com_ier, IER_ETXRDY);
1240 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1241 * an interrupt. They'd better generate one for actually doing
1242 * output. Loopback may be broken on the same incompatibles but
1243 * it's unlikely to do more than allow the null byte out.
1246 outb(iobase + (com_data << port_shift), 0);
1248 outb(iobase + com_data, 0);
1250 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1253 * Turn off loopback mode so that the interrupt gate works again
1254 * (MCR_IENABLE was hidden). This should leave the device driving
1255 * an interrupt line high. It doesn't matter if the interrupt
1256 * line oscillates while we are not looking at it, since interrupts
1261 outb(iobase + (com_mcr << port_shift), mcr_image);
1263 outb(iobase + com_mcr, mcr_image);
1267 * It's a definitly Serial PCMCIA(16550A), but still be required
1268 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1270 if ( COM_NOPROBE(flags) ) {
1271 /* Reading IIR register twice */
1272 for ( fn = 0; fn < 2; fn ++ ) {
1275 failures[6] = inb(iobase + (com_iir << port_shift));
1277 failures[6] = inb(iobase + com_iir);
1280 /* Check IIR_TXRDY clear ? */
1282 isa_set_portsize(dev,
1283 if_16550a_type[iod.if_type & 0x0f].io_size);
1285 isa_set_portsize(dev, IO_COMSIZE);
1288 if ( failures[6] & IIR_TXRDY ) {
1289 /* Nop, Double check with clearing IER */
1291 outb(iobase + (com_ier << port_shift), 0);
1293 (com_iir << port_shift)) & IIR_NOPEND) {
1295 outb(iobase + com_ier, 0);
1296 if ( inb(iobase + com_iir) & IIR_NOPEND ) {
1298 /* Ok. we're familia this gang */
1299 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); /* Set IIR_TXRDYBUG */
1301 /* Unknow, Just omit this chip.. XXX*/
1305 /* OK. this is well-known guys */
1306 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); /*Clear IIR_TXRDYBUG*/
1309 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1311 outb(iobase + com_cfcr, CFCR_8BITS);
1314 return (iobase == siocniobase ? 0 : result);
1319 * o the CFCR, IER and MCR in UART hold the values written to them
1320 * (the values happen to be all distinct - this is good for
1321 * avoiding false positive tests from bus echoes).
1322 * o an output interrupt is generated and its vector is correct.
1323 * o the interrupt goes away when the IIR in the UART is read.
1327 failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS;
1328 failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY;
1329 failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image;
1331 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS;
1332 failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
1333 failures[2] = inb(iobase + com_mcr) - mcr_image;
1335 DELAY(10000); /* Some internal modems need this time */
1336 irqmap[1] = isa_irq_pending();
1338 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1340 if (iod.if_type == COM_IF_RSA98III)
1341 inb(rsabase + rsa_srr);
1343 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
1345 DELAY(1000); /* XXX */
1346 irqmap[2] = isa_irq_pending();
1348 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1350 if (iod.if_type == COM_IF_RSA98III)
1351 inb(rsabase + rsa_srr);
1353 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1357 * Turn off all device interrupts and check that they go off properly.
1358 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1359 * the OUT2 output of the UART to
1360 * the ICU input. Closing the gate would give a floating ICU input
1361 * (unless there is another device driving it) and spurious interrupts.
1362 * (On the system that this was first tested on, the input floats high
1363 * and gives a (masked) interrupt as soon as the gate is closed.)
1366 outb(iobase + (com_ier << port_shift), 0);
1367 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1368 failures[7] = inb(iobase + (com_ier << port_shift));
1369 if (iod.if_type == COM_IF_RSA98III)
1370 outb(rsabase + rsa_ier, 0x00);
1372 outb(iobase + com_ier, 0);
1373 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1374 failures[7] = inb(iobase + com_ier);
1376 DELAY(1000); /* XXX */
1377 irqmap[3] = isa_irq_pending();
1379 failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1381 if (iod.if_type == COM_IF_RSA98III) {
1382 inb(rsabase + rsa_srr);
1383 outb(rsabase + rsa_frr, 0x00);
1386 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1391 irqs = irqmap[1] & ~irqmap[0];
1392 if (isa_get_irq(idev) >= 0 && ((1 << isa_get_irq(idev)) & irqs) == 0)
1394 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
1395 device_get_unit(dev), isa_get_irq(idev), irqs);
1397 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1398 device_get_unit(dev),
1399 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1402 isa_set_portsize(dev, if_16550a_type[iod.if_type & 0x0f].io_size);
1404 isa_set_portsize(dev, IO_COMSIZE);
1407 for (fn = 0; fn < sizeof failures; ++fn)
1410 outb(iobase + (com_mcr << port_shift), 0);
1412 outb(iobase + com_mcr, 0);
1416 printf("sio%d: probe failed test(s):",
1417 device_get_unit(dev));
1418 for (fn = 0; fn < sizeof failures; ++fn)
1425 return (iobase == siocniobase ? 0 : result);
1430 espattach(com, esp_port)
1438 * Check the ESP-specific I/O port to see if we're an ESP
1439 * card. If not, return failure immediately.
1441 if ((inb(esp_port) & 0xf3) == 0) {
1442 printf(" port 0x%x is not an ESP board?\n", esp_port);
1447 * We've got something that claims to be a Hayes ESP card.
1451 /* Get the dip-switch configuration */
1453 outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1454 dips = inb(esp_port + ESP98_STATUS1);
1456 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1457 dips = inb(esp_port + ESP_STATUS1);
1461 * Bits 0,1 of dips say which COM port we are.
1464 if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03])
1466 if (com->iobase == likely_com_ports[dips & 0x03])
1470 printf(" esp_port has com %d\n", dips & 0x03);
1475 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1478 outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1479 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
1480 val = inb(esp_port + ESP98_STATUS2);
1482 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1483 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1484 val = inb(esp_port + ESP_STATUS2);
1486 if ((val & 0x70) < 0x20) {
1487 printf("-old (%o)", val & 0x70);
1492 * Check for ability to emulate 16550: bit 7 == 1
1494 if ((dips & 0x80) == 0) {
1500 * Okay, we seem to be a Hayes ESP card. Whee.
1503 com->esp_port = esp_port;
1506 #endif /* COM_ESP */
1519 struct resource *res;
1521 u_int flags = isa_get_flags(dev);
1528 iobase = isa_get_port(dev);
1530 if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
1533 unit = device_get_unit(dev);
1534 com = device_get_softc(dev);
1537 if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
1539 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL)
1541 bzero(obuf, obufsize * 2);
1545 * sioprobe() has initialized the device registers as follows:
1546 * o cfcr = CFCR_8BITS.
1547 * It is most important that CFCR_DLAB is off, so that the
1548 * data port is not hidden when we enable interrupts.
1550 * Interrupts are only enabled when the line is open.
1551 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1552 * interrupt control register or the config specifies no irq.
1553 * Keeping MCR_DTR and MCR_RTS off might stop the external
1554 * device from sending before we are ready.
1556 bzero(com, sizeof *com);
1558 com->obufsize = obufsize;
1560 com->obuf2 = obuf + obufsize;
1563 com->cfcr_image = CFCR_8BITS;
1564 com->dtr_wait = 3 * hz;
1565 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1566 com->no_irq = isa_get_irq(dev) < 0;
1567 com->tx_fifo_size = 1;
1568 com->obufs[0].l_head = com->obuf1;
1569 com->obufs[1].l_head = com->obuf2;
1571 com->iobase = iobase;
1573 if (pc98_set_ioport(com, isa_get_flags(dev)) == -1) {
1574 com->pc98_if_type = (isa_get_flags(dev) >> 24) & 0xff;
1575 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1576 com->data_port = iobase + (com_data << port_shift);
1577 com->int_id_port = iobase + (com_iir << port_shift);
1578 com->modem_ctl_port = iobase + (com_mcr << port_shift);
1579 com->mcr_image = inb(com->modem_ctl_port);
1580 com->line_status_port = iobase + (com_lsr << port_shift);
1581 com->modem_status_port = iobase + (com_msr << port_shift);
1582 com->intr_ctl_port = iobase + (com_ier << port_shift);
1584 #else /* not PC98 */
1585 com->data_port = iobase + com_data;
1586 com->int_id_port = iobase + com_iir;
1587 com->modem_ctl_port = iobase + com_mcr;
1588 com->mcr_image = inb(com->modem_ctl_port);
1589 com->line_status_port = iobase + com_lsr;
1590 com->modem_status_port = iobase + com_msr;
1591 com->intr_ctl_port = iobase + com_ier;
1595 * We don't use all the flags from <sys/ttydefaults.h> since they
1596 * are only relevant for logins. It's important to have echo off
1597 * initially so that the line doesn't start blathering before the
1598 * echo flag can be turned off.
1600 com->it_in.c_iflag = 0;
1601 com->it_in.c_oflag = 0;
1602 com->it_in.c_cflag = TTYDEF_CFLAG;
1603 com->it_in.c_lflag = 0;
1604 if (unit == comconsole) {
1606 if (IS_8251(com->pc98_if_type))
1609 com->it_in.c_iflag = TTYDEF_IFLAG;
1610 com->it_in.c_oflag = TTYDEF_OFLAG;
1611 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1612 com->it_in.c_lflag = TTYDEF_LFLAG;
1613 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1614 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1615 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1616 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1618 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1619 if (siosetwater(com, com->it_in.c_ispeed) != 0) {
1621 free(com, M_DEVBUF);
1625 termioschars(&com->it_in);
1626 com->it_out = com->it_in;
1628 /* attempt to determine UART type */
1629 printf("sio%d: type", unit);
1633 #ifdef COM_MULTIPORT
1634 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1636 if (!COM_IIR_TXRDYBUG(flags))
1643 scr = inb(iobase + com_scr);
1644 outb(iobase + com_scr, 0xa5);
1645 scr1 = inb(iobase + com_scr);
1646 outb(iobase + com_scr, 0x5a);
1647 scr2 = inb(iobase + com_scr);
1648 outb(iobase + com_scr, scr);
1649 if (scr1 != 0xa5 || scr2 != 0x5a) {
1651 goto determined_type;
1656 if (IS_8251(com->pc98_if_type)) {
1657 com_int_TxRx_disable( com );
1658 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate );
1659 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1660 com_send_break_off( com );
1661 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1663 outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH);
1665 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1669 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1680 if (COM_NOFIFO(flags)) {
1681 printf(" 16550A fifo disabled");
1683 com->hasfifo = TRUE;
1685 com->tx_fifo_size = 0; /* XXX flag conflicts. */
1688 if (COM_ST16650A(flags)) {
1690 com->tx_fifo_size = 32;
1691 printf(" ST16650A");
1693 com->tx_fifo_size = COM_FIFOSIZE(flags);
1699 if (com->pc98_if_type == COM_IF_RSA98III) {
1700 com->tx_fifo_size = 2048;
1701 com->rsabase = isa_get_port(dev);
1702 outb(com->rsabase + rsa_ier, 0x00);
1703 outb(com->rsabase + rsa_frr, 0x00);
1709 if (com->pc98_if_type == COM_IF_ESP98)
1711 for (espp = likely_esp_ports; *espp != 0; espp++)
1712 if (espattach(com, *espp)) {
1713 com->tx_fifo_size = 1024;
1717 if (!com->st16650a) {
1718 if (!com->tx_fifo_size)
1719 com->tx_fifo_size = 16;
1721 printf(" lookalike with %d bytes FIFO",
1729 if (com->pc98_if_type == COM_IF_RSB3000) {
1730 /* Set RSB-2000/3000 Extended Buffer mode. */
1732 lcr = inb(iobase + (com_cfcr << port_shift));
1733 outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB);
1734 outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE);
1735 outb(iobase + (com_cfcr << port_shift), lcr);
1742 * Set 16550 compatibility mode.
1743 * We don't use the ESP_MODE_SCALE bit to increase the
1744 * fifo trigger levels because we can't handle large
1746 * XXX flow control should be set in comparam(), not here.
1749 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
1750 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1752 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1753 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1756 /* Set RTS/CTS flow control. */
1758 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
1759 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
1760 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
1762 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1763 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1764 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1767 /* Set flow-control levels. */
1769 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
1770 outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
1771 outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
1772 outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
1773 outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
1775 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1776 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1777 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1778 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1779 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1783 /* Set UART clock prescaler. */
1784 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
1785 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
1788 #endif /* COM_ESP */
1790 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1791 outb(iobase + (com_fifo << port_shift), 0);
1793 outb(iobase + com_fifo, 0);
1797 #ifdef COM_MULTIPORT
1798 if (COM_ISMULTIPORT(flags)) {
1799 com->multiport = TRUE;
1800 printf(" (multiport");
1801 if (unit == COM_MPMASTER(flags))
1805 isa_get_irq(devclass_get_device
1806 (sio_devclass, COM_MPMASTER(flags))) < 0;
1808 #endif /* COM_MULTIPORT */
1812 if (unit == comconsole)
1813 printf(", console");
1814 if ( COM_IIR_TXRDYBUG(flags) )
1815 printf(" with a bogus IIR_TXRDY register");
1818 if (!sio_registered) {
1819 register_swi(SWI_TTY, siopoll);
1820 sio_registered = TRUE;
1823 com->devfs_token_ttyd = devfs_add_devswf(&sio_cdevsw,
1825 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1826 com->devfs_token_ttyi = devfs_add_devswf(&sio_cdevsw,
1827 unit | CONTROL_INIT_STATE, DV_CHR,
1828 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1829 com->devfs_token_ttyl = devfs_add_devswf(&sio_cdevsw,
1830 unit | CONTROL_LOCK_STATE, DV_CHR,
1831 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1832 com->devfs_token_cuaa = devfs_add_devswf(&sio_cdevsw,
1833 unit | CALLOUT_MASK, DV_CHR,
1834 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1835 com->devfs_token_cuai = devfs_add_devswf(&sio_cdevsw,
1836 unit | CALLOUT_MASK | CONTROL_INIT_STATE, DV_CHR,
1837 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1838 com->devfs_token_cual = devfs_add_devswf(&sio_cdevsw,
1839 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, DV_CHR,
1840 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1842 com->flags = isa_get_flags(dev); /* Heritate id_flags for later */
1843 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1844 pps_init(&com->pps);
1846 res = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 0ul, ~0ul, 1,
1847 RF_SHAREABLE | RF_ACTIVE);
1848 BUS_SETUP_INTR(device_get_parent(dev), dev, res,
1849 INTR_TYPE_TTY | INTR_TYPE_FAST,
1856 sioopen(dev, flag, mode, p)
1874 unit = MINOR_TO_UNIT(mynor);
1875 if ((u_int) unit >= NSIOTOT || (com = com_addr(unit)) == NULL)
1879 if (mynor & CONTROL_MASK)
1882 tp = com->tp = sio_tty[unit] = ttymalloc(sio_tty[unit]);
1884 tp = com->tp = &sio_tty[unit];
1889 if (!IS_8251(com->pc98_if_type))
1890 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1893 * We jump to this label after all non-interrupted sleeps to pick
1894 * up any changes of the device state.
1897 while (com->state & CS_DTR_OFF) {
1898 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1899 if (com_addr(unit) == NULL)
1901 if (error != 0 || com->gone)
1904 if (tp->t_state & TS_ISOPEN) {
1906 * The device is open, so everything has been initialized.
1909 if (mynor & CALLOUT_MASK) {
1910 if (!com->active_out) {
1915 if (com->active_out) {
1916 if (flag & O_NONBLOCK) {
1920 error = tsleep(&com->active_out,
1921 TTIPRI | PCATCH, "siobi", 0);
1922 if (com_addr(unit) == NULL)
1924 if (error != 0 || com->gone)
1929 if (tp->t_state & TS_XCLUDE &&
1936 * The device isn't open, so there are no conflicts.
1937 * Initialize it. Initialization is done twice in many
1938 * cases: to preempt sleeping callin opens if we are
1939 * callout, and to complete a callin open after DCD rises.
1941 tp->t_oproc = comstart;
1942 tp->t_param = comparam;
1944 tp->t_termios = mynor & CALLOUT_MASK
1945 ? com->it_out : com->it_in;
1947 if (!IS_8251(com->pc98_if_type))
1949 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1950 com->poll = com->no_irq;
1951 com->poll_output = com->loses_outints;
1953 error = comparam(tp, &tp->t_termios);
1958 if (IS_8251(com->pc98_if_type)) {
1959 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
1960 pc98_msrint_start(dev);
1964 * XXX we should goto open_top if comparam() slept.
1966 iobase = com->iobase;
1969 * (Re)enable and drain fifos.
1971 * Certain SMC chips cause problems if the fifos
1972 * are enabled while input is ready. Turn off the
1973 * fifo if necessary to clear the input. We test
1974 * the input ready bit after enabling the fifos
1975 * since we've already enabled them in comparam()
1976 * and to handle races between enabling and fresh
1981 outb(iobase + (com_fifo << port_shift),
1982 FIFO_RCV_RST | FIFO_XMT_RST
1984 if (com->pc98_if_type == COM_IF_RSA98III)
1985 outb(com->rsabase + rsa_frr , 0x00);
1987 outb(iobase + com_fifo,
1988 FIFO_RCV_RST | FIFO_XMT_RST
1992 * XXX the delays are for superstitious
1993 * historical reasons. It must be less than
1994 * the character time at the maximum
1995 * supported speed (87 usec at 115200 bps
1996 * 8N1). Otherwise we might loop endlessly
1997 * if data is streaming in. We used to use
1998 * delays of 100. That usually worked
1999 * because DELAY(100) used to usually delay
2000 * for about 85 usec instead of 100.
2004 if (!(inb(com->line_status_port) & LSR_RXRDY))
2006 if (com->pc98_if_type == COM_IF_RSA98III
2007 ? !(inb(com->rsabase + rsa_srr) & 0x08)
2008 : !(inb(com->line_status_port) & LSR_RXRDY))
2012 outb(iobase + (com_fifo << port_shift), 0);
2014 outb(iobase + com_fifo, 0);
2017 (void) inb(com->data_port);
2023 if (IS_8251(com->pc98_if_type)) {
2024 com_tiocm_bis(com, TIOCM_LE);
2025 com->pc98_prev_modem_status = pc98_get_modem_status(com);
2026 com_int_Rx_enable(com);
2029 (void) inb(com->line_status_port);
2030 (void) inb(com->data_port);
2031 com->prev_modem_status = com->last_modem_status
2032 = inb(com->modem_status_port);
2033 if (COM_IIR_TXRDYBUG(com->flags)) {
2034 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
2037 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
2038 | IER_ERLS | IER_EMSC);
2041 if (com->pc98_if_type == COM_IF_RSA98III) {
2042 outb(com->rsabase + rsa_ier, 0x1d);
2043 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC);
2051 * Handle initial DCD. Callout devices get a fake initial
2052 * DCD (trapdoor DCD). If we are callout, then any sleeping
2053 * callin opens get woken up and resume sleeping on "siobi"
2054 * instead of "siodcd".
2057 * XXX `mynor & CALLOUT_MASK' should be
2058 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
2059 * TRAPDOOR_CARRIER is the default initial state for callout
2060 * devices and SOFT_CARRIER is like CLOCAL except it hides
2064 if ((IS_8251(com->pc98_if_type) &&
2065 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
2066 (!IS_8251(com->pc98_if_type) &&
2067 (com->prev_modem_status & MSR_DCD)) ||
2068 mynor & CALLOUT_MASK)
2070 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2072 (*linesw[tp->t_line].l_modem)(tp, 1);
2075 * Wait for DCD if necessary.
2077 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2078 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2080 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
2081 if (com_addr(unit) == NULL)
2084 if (error != 0 || com->gone)
2088 error = (*linesw[tp->t_line].l_open)(dev, tp);
2089 disc_optim(tp, &tp->t_termios, com);
2090 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
2091 com->active_out = TRUE;
2095 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
2101 sioclose(dev, flag, mode, p)
2113 if (mynor & CONTROL_MASK)
2115 com = com_addr(MINOR_TO_UNIT(mynor));
2118 (*linesw[tp->t_line].l_close)(tp, flag);
2120 com->modem_checking = 0;
2122 disc_optim(tp, &tp->t_termios, com);
2123 siostop(tp, FREAD | FWRITE);
2129 printf("sio%d: gone\n", com->unit);
2131 if (com->ibuf != NULL)
2132 free(com->ibuf, M_DEVBUF);
2133 bzero(tp, sizeof *tp);
2134 free(com, M_DEVBUF);
2153 iobase = com->iobase;
2156 com->poll_output = FALSE;
2157 com->do_timestamp = FALSE;
2158 com->do_dcd_timestamp = FALSE;
2159 com->pps.ppsparam.mode = 0;
2161 if (IS_8251(com->pc98_if_type))
2162 com_send_break_off(com);
2164 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2165 outb(iobase + (com_cfcr << port_shift),
2166 com->cfcr_image &= ~CFCR_SBREAK);
2169 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2174 if (IS_8251(com->pc98_if_type))
2175 com_int_TxRx_disable(com);
2177 outb(iobase + (com_ier << port_shift), 0);
2178 if (com->pc98_if_type == COM_IF_RSA98III) {
2179 outb(com->rsabase + rsa_ier, 0x00);
2182 outb(iobase + com_ier, 0);
2186 if (IS_8251(com->pc98_if_type))
2187 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2189 tmp = com->prev_modem_status & MSR_DCD;
2191 if (tp->t_cflag & HUPCL
2193 * XXX we will miss any carrier drop between here and the
2194 * next open. Perhaps we should watch DCD even when the
2195 * port is closed; it is not sufficient to check it at
2196 * the next open because it might go up and down while
2197 * we're not watching.
2199 || (!com->active_out
2203 && !(com->prev_modem_status & MSR_DCD)
2205 && !(com->it_in.c_cflag & CLOCAL))
2206 || !(tp->t_state & TS_ISOPEN)) {
2208 if (IS_8251(com->pc98_if_type))
2209 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2212 (void)commctl(com, TIOCM_DTR, DMBIC);
2213 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
2214 timeout(siodtrwakeup, com, com->dtr_wait);
2215 com->state |= CS_DTR_OFF;
2220 if (IS_8251(com->pc98_if_type))
2221 com_tiocm_bic(com, TIOCM_LE );
2227 * Disable fifos so that they are off after controlled
2228 * reboots. Some BIOSes fail to detect 16550s when the
2229 * fifos are enabled.
2232 outb(iobase + (com_fifo << port_shift), 0);
2234 outb(iobase + com_fifo, 0);
2237 com->active_out = FALSE;
2238 wakeup(&com->active_out);
2239 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
2244 sioread(dev, uio, flag)
2253 if (mynor & CONTROL_MASK)
2255 com = com_addr(MINOR_TO_UNIT(mynor));
2258 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag));
2262 siowrite(dev, uio, flag)
2272 if (mynor & CONTROL_MASK)
2275 unit = MINOR_TO_UNIT(mynor);
2276 com = com_addr(unit);
2280 * (XXX) We disallow virtual consoles if the physical console is
2281 * a serial port. This is in case there is a display attached that
2282 * is not the console. In that situation we don't need/want the X
2283 * server taking over the console.
2285 if (constty != NULL && unit == comconsole)
2287 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag));
2297 com = (struct com_s *)chan;
2300 * Clear TS_BUSY if low-level output is complete.
2301 * spl locking is sufficient because siointr1() does not set CS_BUSY.
2302 * If siointr1() clears CS_BUSY after we look at it, then we'll get
2303 * called again. Reading the line status port outside of siointr1()
2304 * is safe because CS_BUSY is clear so there are no output interrupts
2308 if (com->state & CS_BUSY)
2309 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
2311 else if ((IS_8251(com->pc98_if_type) &&
2312 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2313 == (STS8251_TxRDY | STS8251_TxEMP)) ||
2314 (inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2315 == (LSR_TSRE | LSR_TXRDY)) {
2317 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2318 == (LSR_TSRE | LSR_TXRDY)) {
2320 com->tp->t_state &= ~TS_BUSY;
2322 com->extra_state &= ~CSE_BUSYCHECK;
2324 timeout(siobusycheck, com, hz / 100);
2334 com = (struct com_s *)chan;
2335 com->state &= ~CS_DTR_OFF;
2336 wakeup(&com->dtr_wait);
2354 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
2355 com_events -= (com->iptr - com->ibuf);
2356 com->iptr = com->ibuf;
2359 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
2361 * Avoid the grotesquely inefficient lineswitch routine
2362 * (ttyinput) in "raw" mode. It usually takes about 450
2363 * instructions (that's without canonical processing or echo!).
2364 * slinput is reasonably fast (usually 40 instructions plus
2369 incc = com->iptr - buf;
2370 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
2371 && (com->state & CS_RTS_IFLOW
2372 || tp->t_iflag & IXOFF)
2373 && !(tp->t_state & TS_TBLOCK))
2375 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
2376 += b_to_q((char *)buf, incc, &tp->t_rawq);
2380 tp->t_rawcc += incc;
2382 if (tp->t_state & TS_TTSTOP
2383 && (tp->t_iflag & IXANY
2384 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
2385 tp->t_state &= ~TS_TTSTOP;
2386 tp->t_lflag &= ~FLUSHO;
2390 } while (buf < com->iptr);
2394 line_status = buf[com->ierroff];
2397 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
2398 if (line_status & LSR_BI)
2399 recv_data |= TTY_BI;
2400 if (line_status & LSR_FE)
2401 recv_data |= TTY_FE;
2402 if (line_status & LSR_OE)
2403 recv_data |= TTY_OE;
2404 if (line_status & LSR_PE)
2405 recv_data |= TTY_PE;
2407 (*linesw[tp->t_line].l_rint)(recv_data, tp);
2409 } while (buf < com->iptr);
2411 com_events -= (com->iptr - com->ibuf);
2412 com->iptr = com->ibuf;
2415 * There is now room for another low-level buffer full of input,
2416 * so enable RTS if it is now disabled and there is room in the
2417 * high-level buffer.
2420 if (IS_8251(com->pc98_if_type))
2421 tmp = com_tiocm_get(com) & TIOCM_RTS;
2423 tmp = com->mcr_image & MCR_RTS;
2424 if ((com->state & CS_RTS_IFLOW) && !(tmp) &&
2425 !(tp->t_state & TS_TBLOCK))
2426 if (IS_8251(com->pc98_if_type))
2427 com_tiocm_bis(com, TIOCM_RTS);
2429 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2431 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2432 !(tp->t_state & TS_TBLOCK))
2433 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2441 #ifndef COM_MULTIPORT
2443 siointr1((struct com_s *) arg);
2445 #else /* COM_MULTIPORT */
2446 bool_t possibly_more_intrs;
2450 u_char rsa_buf_status;
2454 * Loop until there is no activity on any port. This is necessary
2455 * to get an interrupt edge more than to avoid another interrupt.
2456 * If the IRQ signal is just an OR of the IRQ signals from several
2457 * devices, then the edge from one may be lost because another is
2462 possibly_more_intrs = FALSE;
2463 for (unit = 0; unit < NSIOTOT; ++unit) {
2464 com = com_addr(unit);
2467 * would it work here, or be counter-productive?
2472 && IS_8251(com->pc98_if_type)){
2479 && com->pc98_if_type == COM_IF_RSA98III) {
2480 rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9;
2481 if ((rsa_buf_status & 0xc8)
2482 || !(rsa_buf_status & 0x01)) {
2485 != (inb(com->rsabase + rsa_srr) & 0xc9))
2486 possibly_more_intrs = TRUE;
2492 && (inb(com->int_id_port) & IIR_IMASK)
2495 possibly_more_intrs = TRUE;
2497 /* XXX COM_UNLOCK(); */
2499 } while (possibly_more_intrs);
2501 #endif /* COM_MULTIPORT */
2509 u_char modem_status;
2514 struct timecounter *tc;
2519 u_char rsa_buf_status = 0;
2520 int rsa_tx_fifo_size=0;
2524 int_ctl = inb(com->intr_ctl_port);
2525 int_ctl_new = int_ctl;
2527 while (!com->gone) {
2530 if (IS_8251(com->pc98_if_type)) {
2531 tmp = inb(com->sts_port);
2534 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
2535 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
2536 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
2537 if (tmp & STS8251_PE) line_status |= LSR_PE;
2538 if (tmp & STS8251_OE) line_status |= LSR_OE;
2539 if (tmp & STS8251_FE) line_status |= LSR_FE;
2540 if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
2543 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
2544 modem_status = inb(com->modem_status_port);
2545 if ((modem_status ^ com->last_modem_status) & MSR_DCD) {
2547 count = tc->tc_get_timecount(tc);
2548 pps_event(&com->pps, tc, count,
2549 (modem_status & MSR_DCD) ?
2550 PPS_CAPTURECLEAR : PPS_CAPTUREASSERT);
2553 line_status = inb(com->line_status_port);
2556 if (com->pc98_if_type == COM_IF_RSA98III)
2557 rsa_buf_status = inb(com->rsabase + rsa_srr);
2560 /* input event? (check first to help avoid overruns) */
2562 while (line_status & LSR_RCV_MASK) {
2564 while ((line_status & LSR_RCV_MASK)
2565 || (com->pc98_if_type == COM_IF_RSA98III
2566 && (rsa_buf_status & 0x08))) {
2568 /* break/unnattached error bits or real input? */
2570 if (IS_8251(com->pc98_if_type)) {
2571 recv_data = inb(com->data_port);
2573 pc98_i8251_or_cmd(com,CMD8251_ER);
2579 if (com->pc98_if_type == COM_IF_RSA98III) {
2580 if (!(rsa_buf_status & 0x08))
2583 recv_data = inb(com->data_port);
2587 if (!(line_status & LSR_RXRDY))
2590 recv_data = inb(com->data_port);
2594 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2596 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2597 * Otherwise, push the work to a higher level
2598 * (to handle PARMRK) if we're bypassing.
2599 * Otherwise, convert BI/FE and PE+INPCK to 0.
2601 * This makes bypassing work right in the
2602 * usual "raw" case (IGNBRK set, and IGNPAR
2605 * Note: BI together with FE/PE means just BI.
2607 if (line_status & LSR_BI) {
2608 #if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2609 if (com->unit == comconsole) {
2615 || com->tp->t_iflag & IGNBRK)
2619 || com->tp->t_iflag & IGNPAR)
2622 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2623 && (line_status & (LSR_BI | LSR_FE)
2624 || com->tp->t_iflag & INPCK))
2628 if (com->hotchar != 0 && recv_data == com->hotchar)
2631 if (ioptr >= com->ibufend)
2632 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2634 if (com->do_timestamp)
2635 microtime(&com->timestamp);
2638 #if 0 /* for testing input latency vs efficiency */
2639 if (com->iptr - com->ibuf == 8)
2642 ioptr[0] = recv_data;
2643 ioptr[com->ierroff] = line_status;
2644 com->iptr = ++ioptr;
2645 if (ioptr == com->ihighwater
2646 && com->state & CS_RTS_IFLOW)
2648 if (IS_8251(com->pc98_if_type))
2649 com_tiocm_bic(com, TIOCM_RTS);
2652 outb(com->modem_ctl_port,
2653 com->mcr_image &= ~MCR_RTS);
2654 if (line_status & LSR_OE)
2655 CE_RECORD(com, CE_OVERRUN);
2659 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2660 * jump from the top of the loop to here
2663 if (IS_8251(com->pc98_if_type))
2667 line_status = inb(com->line_status_port) & 0x7F;
2669 if (com->pc98_if_type == COM_IF_RSA98III)
2670 rsa_buf_status = inb(com->rsabase + rsa_srr);
2674 /* modem status change? (always check before doing output) */
2676 if (!IS_8251(com->pc98_if_type)) {
2678 modem_status = inb(com->modem_status_port);
2679 if (modem_status != com->last_modem_status) {
2680 if (com->do_dcd_timestamp
2681 && !(com->last_modem_status & MSR_DCD)
2682 && modem_status & MSR_DCD)
2683 microtime(&com->dcd_timestamp);
2686 * Schedule high level to handle DCD changes. Note
2687 * that we don't use the delta bits anywhere. Some
2688 * UARTs mess them up, and it's easy to remember the
2689 * previous bits and calculate the delta.
2691 com->last_modem_status = modem_status;
2692 if (!(com->state & CS_CHECKMSR)) {
2693 com_events += LOTS_OF_EVENTS;
2694 com->state |= CS_CHECKMSR;
2698 /* handle CTS change immediately for crisp flow ctl */
2699 if (com->state & CS_CTS_OFLOW) {
2700 if (modem_status & MSR_CTS)
2701 com->state |= CS_ODEVREADY;
2703 com->state &= ~CS_ODEVREADY;
2710 /* output queued and everything ready? */
2712 if (line_status & LSR_TXRDY
2713 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2715 if (((com->pc98_if_type == COM_IF_RSA98III)
2716 ? (rsa_buf_status & 0x02)
2717 : (line_status & LSR_TXRDY))
2718 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2720 ioptr = com->obufq.l_head;
2721 if (com->tx_fifo_size > 1) {
2724 ocount = com->obufq.l_tail - ioptr;
2726 if (com->pc98_if_type == COM_IF_RSA98III) {
2727 rsa_buf_status = inb(com->rsabase + rsa_srr);
2728 rsa_tx_fifo_size = 1024;
2729 if (!(rsa_buf_status & 0x01))
2730 rsa_tx_fifo_size = 2048;
2731 if (ocount > rsa_tx_fifo_size)
2732 ocount = rsa_tx_fifo_size;
2735 if (ocount > com->tx_fifo_size)
2736 ocount = com->tx_fifo_size;
2737 com->bytes_out += ocount;
2739 outb(com->data_port, *ioptr++);
2740 while (--ocount != 0);
2742 outb(com->data_port, *ioptr++);
2746 if (IS_8251(com->pc98_if_type))
2747 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2748 com_int_Tx_enable(com);
2750 com->obufq.l_head = ioptr;
2751 if (COM_IIR_TXRDYBUG(com->flags)) {
2752 int_ctl_new = int_ctl | IER_ETXRDY;
2754 if (ioptr >= com->obufq.l_tail) {
2757 qp = com->obufq.l_next;
2758 qp->l_queued = FALSE;
2761 com->obufq.l_head = qp->l_head;
2762 com->obufq.l_tail = qp->l_tail;
2763 com->obufq.l_next = qp;
2765 /* output just completed */
2766 if ( COM_IIR_TXRDYBUG(com->flags) ) {
2767 int_ctl_new = int_ctl & ~IER_ETXRDY;
2769 com->state &= ~CS_BUSY;
2771 if (IS_8251(com->pc98_if_type))
2772 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2773 com_int_Tx_disable(com);
2776 if (!(com->state & CS_ODONE)) {
2777 com_events += LOTS_OF_EVENTS;
2778 com->state |= CS_ODONE;
2779 setsofttty(); /* handle at high level ASAP */
2782 if ( COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
2784 if (com->pc98_if_type == COM_IF_RSA98III) {
2785 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2786 outb(com->intr_ctl_port, int_ctl_new);
2787 outb(com->rsabase + rsa_ier, 0x1d);
2790 outb(com->intr_ctl_port, int_ctl_new);
2794 else if (line_status & LSR_TXRDY) {
2795 if (IS_8251(com->pc98_if_type))
2796 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2797 com_int_Tx_disable(com);
2799 if (IS_8251(com->pc98_if_type))
2800 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
2805 #ifndef COM_MULTIPORT
2807 if (IS_8251(com->pc98_if_type))
2810 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2811 #endif /* COM_MULTIPORT */
2817 sioioctl(dev, cmd, data, flag, p)
2830 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2832 struct termios term;
2836 com = com_addr(MINOR_TO_UNIT(mynor));
2839 iobase = com->iobase;
2840 if (mynor & CONTROL_MASK) {
2843 switch (mynor & CONTROL_MASK) {
2844 case CONTROL_INIT_STATE:
2845 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
2847 case CONTROL_LOCK_STATE:
2848 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
2851 return (ENODEV); /* /dev/nodev */
2858 *ct = *(struct termios *)data;
2861 *(struct termios *)data = *ct;
2864 *(int *)data = TTYDISC;
2867 bzero(data, sizeof(struct winsize));
2874 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2875 term = tp->t_termios;
2877 error = ttsetcompat(tp, &cmd, data, &term);
2881 data = (caddr_t)&term;
2883 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
2885 struct termios *dt = (struct termios *)data;
2886 struct termios *lt = mynor & CALLOUT_MASK
2887 ? &com->lt_out : &com->lt_in;
2889 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2890 | (dt->c_iflag & ~lt->c_iflag);
2891 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2892 | (dt->c_oflag & ~lt->c_oflag);
2893 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2894 | (dt->c_cflag & ~lt->c_cflag);
2895 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2896 | (dt->c_lflag & ~lt->c_lflag);
2897 for (cc = 0; cc < NCCS; ++cc)
2898 if (lt->c_cc[cc] != 0)
2899 dt->c_cc[cc] = tp->t_cc[cc];
2900 if (lt->c_ispeed != 0)
2901 dt->c_ispeed = tp->t_ispeed;
2902 if (lt->c_ospeed != 0)
2903 dt->c_ospeed = tp->t_ospeed;
2905 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
2906 if (error != ENOIOCTL)
2909 error = ttioctl(tp, cmd, data, flag);
2910 disc_optim(tp, &tp->t_termios, com);
2911 if (error != ENOIOCTL) {
2916 if (IS_8251(com->pc98_if_type)) {
2919 com_send_break_on( com );
2922 com_send_break_off( com );
2925 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS );
2928 com_tiocm_bic(com, TIOCM_DTR);
2931 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2932 * changes get undone on the next call to comparam().
2935 com_tiocm_set( com, *(int *)data );
2938 com_tiocm_bis( com, *(int *)data );
2941 com_tiocm_bic( com, *(int *)data );
2944 *(int *)data = com_tiocm_get(com);
2947 /* must be root since the wait applies to following logins */
2953 com->dtr_wait = *(int *)data * hz / 100;
2956 *(int *)data = com->dtr_wait * 100 / hz;
2959 com->do_timestamp = TRUE;
2960 *(struct timeval *)data = com->timestamp;
2962 case TIOCDCDTIMESTAMP:
2963 com->do_dcd_timestamp = TRUE;
2964 *(struct timeval *)data = com->dcd_timestamp;
2972 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2977 outb(iobase + (com_cfcr << port_shift),
2978 com->cfcr_image |= CFCR_SBREAK);
2980 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2985 outb(iobase + (com_cfcr << port_shift),
2986 com->cfcr_image &= ~CFCR_SBREAK);
2988 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2992 (void)commctl(com, TIOCM_DTR, DMBIS);
2995 (void)commctl(com, TIOCM_DTR, DMBIC);
2998 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2999 * changes get undone on the next call to comparam().
3002 (void)commctl(com, *(int *)data, DMSET);
3005 (void)commctl(com, *(int *)data, DMBIS);
3008 (void)commctl(com, *(int *)data, DMBIC);
3011 *(int *)data = commctl(com, 0, DMGET);
3014 /* must be root since the wait applies to following logins */
3020 com->dtr_wait = *(int *)data * hz / 100;
3023 *(int *)data = com->dtr_wait * 100 / hz;
3026 com->do_timestamp = TRUE;
3027 *(struct timeval *)data = com->timestamp;
3029 case TIOCDCDTIMESTAMP:
3030 com->do_dcd_timestamp = TRUE;
3031 *(struct timeval *)data = com->dcd_timestamp;
3035 error = pps_ioctl(cmd, data, &com->pps);
3036 if (error == ENODEV)
3052 if (com_events == 0)
3055 for (unit = 0; unit < NSIOTOT; ++unit) {
3060 com = com_addr(unit);
3064 if (tp == NULL || com->gone) {
3066 * Discard any events related to never-opened or
3067 * going-away devices.
3070 incc = com->iptr - com->ibuf;
3071 com->iptr = com->ibuf;
3072 if (com->state & CS_CHECKMSR) {
3073 incc += LOTS_OF_EVENTS;
3074 com->state &= ~CS_CHECKMSR;
3080 if (com->iptr != com->ibuf) {
3085 if (com->state & CS_CHECKMSR) {
3086 u_char delta_modem_status;
3089 if (!IS_8251(com->pc98_if_type)) {
3092 delta_modem_status = com->last_modem_status
3093 ^ com->prev_modem_status;
3094 com->prev_modem_status = com->last_modem_status;
3095 com_events -= LOTS_OF_EVENTS;
3096 com->state &= ~CS_CHECKMSR;
3098 if (delta_modem_status & MSR_DCD)
3099 (*linesw[tp->t_line].l_modem)
3100 (tp, com->prev_modem_status & MSR_DCD);
3105 if (com->state & CS_ODONE) {
3107 com_events -= LOTS_OF_EVENTS;
3108 com->state &= ~CS_ODONE;
3110 if (!(com->state & CS_BUSY)
3111 && !(com->extra_state & CSE_BUSYCHECK)) {
3112 timeout(siobusycheck, com, hz / 100);
3113 com->extra_state |= CSE_BUSYCHECK;
3115 (*linesw[tp->t_line].l_start)(tp);
3117 if (com_events == 0)
3120 if (com_events >= LOTS_OF_EVENTS)
3145 unit = DEV_TO_UNIT(tp->t_dev);
3146 com = com_addr(unit);
3147 iobase = com->iobase;
3148 if (IS_8251(com->pc98_if_type)) {
3149 divisor = pc98_ttspeedtab(com, t->c_ospeed);
3151 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3153 /* do historical conversions */
3154 if (t->c_ispeed == 0)
3155 t->c_ispeed = t->c_ospeed;
3157 /* check requested parameters */
3158 divisor = ttspeedtab(t->c_ospeed,
3159 if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
3162 /* do historical conversions */
3163 if (t->c_ispeed == 0)
3164 t->c_ispeed = t->c_ospeed;
3166 /* check requested parameters */
3167 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
3169 if (divisor < 0 || divisor > 0 && t->c_ispeed != t->c_ospeed)
3172 /* parameters are OK, convert them to the com struct and the device */
3174 unit = DEV_TO_UNIT(tp->t_dev);
3175 com = com_addr(unit);
3176 iobase = com->iobase;
3180 if (IS_8251(com->pc98_if_type)) {
3182 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3184 com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3188 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
3190 (void)commctl(com, TIOCM_DTR, DMBIS);
3196 if (!IS_8251(com->pc98_if_type)) {
3198 switch (cflag & CSIZE) {
3212 if (cflag & PARENB) {
3214 if (!(cflag & PARODD))
3220 if (com->hasfifo && divisor != 0) {
3222 * Use a fifo trigger level low enough so that the input
3223 * latency from the fifo is less than about 16 msec and
3224 * the total latency is less than about 30 msec. These
3225 * latencies are reasonable for humans. Serial comms
3226 * protocols shouldn't expect anything better since modem
3227 * latencies are larger.
3229 com->fifo_image = t->c_ospeed <= 4800
3230 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
3233 * The Hayes ESP card needs the fifo DMA mode bit set
3234 * in compatibility mode. If not, it will interrupt
3235 * for each character received.
3238 com->fifo_image |= FIFO_DMA_MODE;
3241 outb(iobase + (com_fifo << port_shift), com->fifo_image);
3243 outb(iobase + com_fifo, com->fifo_image);
3251 * This returns with interrupts disabled so that we can complete
3252 * the speed change atomically. Keeping interrupts disabled is
3253 * especially important while com_data is hidden.
3255 (void) siosetwater(com, t->c_ispeed);
3258 if (IS_8251(com->pc98_if_type))
3259 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3264 outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB);
3266 outb(iobase + com_cfcr, cfcr | CFCR_DLAB);
3269 * Only set the divisor registers if they would change,
3270 * since on some 16550 incompatibles (UMC8669F), setting
3271 * them while input is arriving them loses sync until
3272 * data stops arriving.
3274 dlbl = divisor & 0xFF;
3276 if (inb(iobase + (com_dlbl << port_shift)) != dlbl)
3277 outb(iobase + (com_dlbl << port_shift), dlbl);
3278 dlbh = (u_int) divisor >> 8;
3279 if (inb(iobase + (com_dlbh << port_shift)) != dlbh)
3280 outb(iobase + (com_dlbh << port_shift), dlbh);
3282 if (inb(iobase + com_dlbl) != dlbl)
3283 outb(iobase + com_dlbl, dlbl);
3284 dlbh = (u_int) divisor >> 8;
3285 if (inb(iobase + com_dlbh) != dlbh)
3286 outb(iobase + com_dlbh, dlbh);
3293 outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr);
3295 outb(iobase + com_cfcr, com->cfcr_image = cfcr);
3298 if (!(tp->t_state & TS_TTSTOP))
3299 com->state |= CS_TTGO;
3301 if (cflag & CRTS_IFLOW) {
3302 if (com->st16650a) {
3303 outb(iobase + com_cfcr, 0xbf);
3304 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40);
3306 com->state |= CS_RTS_IFLOW;
3308 * If CS_RTS_IFLOW just changed from off to on, the change
3309 * needs to be propagated to MCR_RTS. This isn't urgent,
3310 * so do it later by calling comstart() instead of repeating
3311 * a lot of code from comstart() here.
3313 } else if (com->state & CS_RTS_IFLOW) {
3314 com->state &= ~CS_RTS_IFLOW;
3316 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
3317 * on here, since comstart() won't do it later.
3320 if (IS_8251(com->pc98_if_type))
3321 com_tiocm_bis(com, TIOCM_RTS);
3324 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3325 if (com->st16650a) {
3326 outb(iobase + com_cfcr, 0xbf);
3327 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40);
3333 * Set up state to handle output flow control.
3334 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3335 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3337 com->state |= CS_ODEVREADY;
3338 com->state &= ~CS_CTS_OFLOW;
3340 if (com->pc98_if_type == COM_IF_RSA98III) {
3341 param = inb(com->rsabase + rsa_msr);
3342 outb(com->rsabase + rsa_msr, param & 0x14);
3345 if (cflag & CCTS_OFLOW) {
3346 com->state |= CS_CTS_OFLOW;
3348 if (IS_8251(com->pc98_if_type)) {
3349 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3350 com->state &= ~CS_ODEVREADY;
3354 if (com->pc98_if_type == COM_IF_RSA98III) {
3355 /* Set automatic flow control mode */
3356 outb(com->rsabase + rsa_msr, param | 0x08);
3359 if (!(com->last_modem_status & MSR_CTS))
3360 com->state &= ~CS_ODEVREADY;
3361 if (com->st16650a) {
3362 outb(iobase + com_cfcr, 0xbf);
3363 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80);
3369 if (com->st16650a) {
3370 outb(iobase + com_cfcr, 0xbf);
3371 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80);
3377 outb(iobase + (com_cfcr << port_shift), com->cfcr_image);
3379 outb(iobase + com_cfcr, com->cfcr_image);
3383 /* XXX shouldn't call functions while intrs are disabled. */
3384 disc_optim(tp, t, com);
3386 * Recover from fiddling with CS_TTGO. We used to call siointr1()
3387 * unconditionally, but that defeated the careful discarding of
3388 * stale input in sioopen().
3390 if (com->state >= (CS_BUSY | CS_TTGO))
3396 if (com->ibufold != NULL) {
3397 free(com->ibufold, M_DEVBUF);
3398 com->ibufold = NULL;
3404 siosetwater(com, speed)
3414 * Make the buffer size large enough to handle a softtty interrupt
3415 * latency of about 2 ticks without loss of throughput or data
3416 * (about 3 ticks if input flow control is not used or not honoured,
3417 * but a bit less for CS5-CS7 modes).
3419 cp4ticks = speed / 10 / hz * 4;
3420 for (ibufsize = 128; ibufsize < cp4ticks;)
3423 if (com->pc98_if_type == COM_IF_RSA98III)
3426 if (ibufsize == com->ibufsize) {
3432 * Allocate input buffer. The extra factor of 2 in the size is
3433 * to allow for an error byte for each input byte.
3435 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
3441 /* Initialize non-critical variables. */
3442 com->ibufold = com->ibuf;
3443 com->ibufsize = ibufsize;
3446 tp->t_ififosize = 2 * ibufsize;
3447 tp->t_ispeedwat = (speed_t)-1;
3448 tp->t_ospeedwat = (speed_t)-1;
3452 * Read current input buffer, if any. Continue with interrupts
3456 if (com->iptr != com->ibuf)
3460 * Initialize critical variables, including input buffer watermarks.
3461 * The external device is asked to stop sending when the buffer
3462 * exactly reaches high water, or when the high level requests it.
3463 * The high level is notified immediately (rather than at a later
3464 * clock tick) when this watermark is reached.
3465 * The buffer size is chosen so the watermark should almost never
3467 * The low watermark is invisibly 0 since the buffer is always
3468 * emptied all at once.
3470 com->iptr = com->ibuf = ibuf;
3471 com->ibufend = ibuf + ibufsize;
3472 com->ierroff = ibufsize;
3473 com->ihighwater = ibuf + 3 * ibufsize / 4;
3488 unit = DEV_TO_UNIT(tp->t_dev);
3489 com = com_addr(unit);
3492 if (tp->t_state & TS_TTSTOP)
3493 com->state &= ~CS_TTGO;
3495 com->state |= CS_TTGO;
3496 if (tp->t_state & TS_TBLOCK) {
3498 if (IS_8251(com->pc98_if_type))
3499 tmp = com_tiocm_get(com) & TIOCM_RTS;
3501 tmp = com->mcr_image & MCR_RTS;
3502 if (tmp && (com->state & CS_RTS_IFLOW))
3504 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3507 if (IS_8251(com->pc98_if_type))
3508 com_tiocm_bic(com, TIOCM_RTS);
3511 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3514 if (IS_8251(com->pc98_if_type))
3515 tmp = com_tiocm_get(com) & TIOCM_RTS;
3517 tmp = com->mcr_image & MCR_RTS;
3518 if (!(tmp) && com->iptr < com->ihighwater
3519 && com->state & CS_RTS_IFLOW)
3521 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3522 && com->state & CS_RTS_IFLOW)
3525 if (IS_8251(com->pc98_if_type))
3526 com_tiocm_bis(com, TIOCM_RTS);
3529 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3532 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3535 /* if(IS_8251(com->pc98_if_type))
3536 com_int_Tx_enable(com); */
3541 if (tp->t_outq.c_cc != 0) {
3545 if (!com->obufs[0].l_queued) {
3546 com->obufs[0].l_tail
3547 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3553 com->obufs[0].l_next = NULL;
3554 com->obufs[0].l_queued = TRUE;
3556 if (com->state & CS_BUSY) {
3557 qp = com->obufq.l_next;
3558 while ((next = qp->l_next) != NULL)
3560 qp->l_next = &com->obufs[0];
3562 com->obufq.l_head = com->obufs[0].l_head;
3563 com->obufq.l_tail = com->obufs[0].l_tail;
3564 com->obufq.l_next = &com->obufs[0];
3565 com->state |= CS_BUSY;
3569 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3570 com->obufs[1].l_tail
3571 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3577 com->obufs[1].l_next = NULL;
3578 com->obufs[1].l_queued = TRUE;
3580 if (com->state & CS_BUSY) {
3581 qp = com->obufq.l_next;
3582 while ((next = qp->l_next) != NULL)
3584 qp->l_next = &com->obufs[1];
3586 com->obufq.l_head = com->obufs[1].l_head;
3587 com->obufq.l_tail = com->obufs[1].l_tail;
3588 com->obufq.l_next = &com->obufs[1];
3589 com->state |= CS_BUSY;
3593 tp->t_state |= TS_BUSY;
3596 if (com->state >= (CS_BUSY | CS_TTGO))
3597 siointr1(com); /* fake interrupt to start output */
3600 /* if(IS_8251(com->pc98_if_type))
3601 com_int_Tx_enable(com); */
3618 com = com_addr(DEV_TO_UNIT(tp->t_dev));
3622 if (IS_8251(com->pc98_if_type))
3623 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3629 /* XXX avoid h/w bug. */
3633 outb(com->iobase + (com_fifo << port_shift),
3634 FIFO_XMT_RST | com->fifo_image);
3635 if (com->pc98_if_type == COM_IF_RSA98III)
3636 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3637 outb(com->iobase + (com_fifo << port_shift),
3638 FIFO_XMT_RST | com->fifo_image);
3640 outb(com->iobase + com_fifo,
3641 FIFO_XMT_RST | com->fifo_image);
3643 com->obufs[0].l_queued = FALSE;
3644 com->obufs[1].l_queued = FALSE;
3645 if (com->state & CS_ODONE)
3646 com_events -= LOTS_OF_EVENTS;
3647 com->state &= ~(CS_ODONE | CS_BUSY);
3648 com->tp->t_state &= ~TS_BUSY;
3653 /* XXX avoid h/w bug. */
3657 if (com->pc98_if_type == COM_IF_RSA98III) {
3658 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3659 inb(com->data_port);
3661 outb(com->iobase + (com_fifo << port_shift),
3662 FIFO_RCV_RST | com->fifo_image);
3664 outb(com->iobase + com_fifo,
3665 FIFO_RCV_RST | com->fifo_image);
3667 com_events -= (com->iptr - com->ibuf);
3668 com->iptr = com->ibuf;
3682 if (mynor & CONTROL_MASK)
3684 unit = MINOR_TO_UNIT(mynor);
3685 if ((u_int) unit >= NSIOTOT)
3687 return (&sio_tty[unit]);
3691 commctl(com, bits, how)
3700 bits = TIOCM_LE; /* XXX - always enabled while open */
3701 mcr = com->mcr_image;
3706 msr = com->prev_modem_status;
3714 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
3715 * more volatile by reading the modem status a lot. Perhaps
3716 * we should latch both bits until the status is read here.
3718 if (msr & (MSR_RI | MSR_TERI))
3723 if (bits & TIOCM_DTR)
3725 if (bits & TIOCM_RTS)
3732 outb(com->modem_ctl_port,
3733 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
3736 outb(com->modem_ctl_port, com->mcr_image |= mcr);
3739 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
3754 * Set our timeout period to 1 second if no polled devices are open.
3755 * Otherwise set it to max(1/200, 1/hz).
3756 * Enable timeouts iff some device is open.
3758 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3761 for (unit = 0; unit < NSIOTOT; ++unit) {
3762 com = com_addr(unit);
3763 if (com != NULL && com->tp != NULL
3764 && com->tp->t_state & TS_ISOPEN && !com->gone) {
3766 if (com->poll || com->poll_output) {
3767 sio_timeout = hz > 200 ? hz / 200 : 1;
3773 sio_timeouts_until_log = hz / sio_timeout;
3774 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3777 /* Flush error messages, if any. */
3778 sio_timeouts_until_log = 1;
3779 comwakeup((void *)NULL);
3780 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3791 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
3794 * Recover from lost output interrupts.
3795 * Poll any lines that don't use interrupts.
3797 for (unit = 0; unit < NSIOTOT; ++unit) {
3798 com = com_addr(unit);
3799 if (com != NULL && !com->gone
3800 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
3808 * Check for and log errors, but not too often.
3810 if (--sio_timeouts_until_log > 0)
3812 sio_timeouts_until_log = hz / sio_timeout;
3813 for (unit = 0; unit < NSIOTOT; ++unit) {
3816 com = com_addr(unit);
3821 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
3826 delta = com->delta_error_counts[errnum];
3827 com->delta_error_counts[errnum] = 0;
3831 total = com->error_counts[errnum] += delta;
3832 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
3833 unit, delta, error_desc[errnum],
3834 delta == 1 ? "" : "s", total);
3840 /* commint is called when modem control line changes */
3844 register struct tty *tp;
3850 unit = MINOR_TO_UNIT(mynor);
3851 com = com_addr(unit);
3854 stat = com_tiocm_get(com);
3855 delta = com_tiocm_get_delta(com);
3857 if (com->state & CS_CTS_OFLOW) {
3858 if (stat & TIOCM_CTS)
3859 com->state |= CS_ODEVREADY;
3861 com->state &= ~CS_ODEVREADY;
3863 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) {
3864 if (stat & TIOCM_CAR )
3865 (void)(*linesw[tp->t_line].l_modem)(tp, 1);
3866 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
3867 /* negate DTR, RTS */
3868 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
3869 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
3870 /* disable IENABLE */
3871 com_int_TxRx_disable( com );
3878 disc_optim(tp, t, com)
3883 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
3884 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
3885 && (!(t->c_iflag & PARMRK)
3886 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
3887 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
3888 && linesw[tp->t_line].l_rint == ttyinput)
3889 tp->t_state |= TS_CAN_BYPASS_L_RINT;
3891 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
3892 com->hotchar = linesw[tp->t_line].l_hotchar;
3896 * Following are all routines needed for SIO to act as console
3898 #include <machine/cons.h>
3908 static speed_t siocngetspeed __P((Port_t, struct speedtab *));
3909 static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
3910 static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
3911 static void siocntxwait __P((Port_t iobase));
3914 static cn_probe_t siocnprobe;
3915 static cn_init_t siocninit;
3916 static cn_checkc_t siocncheckc;
3917 static cn_getc_t siocngetc;
3918 static cn_putc_t siocnputc;
3920 CONS_DRIVER(sio, siocnprobe, siocninit, siocngetc, siocncheckc, siocnputc);
3922 /* To get the GDB related variables */
3924 #include <ddb/ddb.h>
3935 * Wait for any pending transmission to finish. Required to avoid
3936 * the UART lockup bug when the speed is changed, and for normal
3940 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3941 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3946 * Read the serial port specified and try to figure out what speed
3947 * it's currently running at. We're assuming the serial port has
3948 * been initialized and is basicly idle. This routine is only intended
3949 * to be run at system startup.
3951 * If the value read from the serial port doesn't make sense, return 0.
3955 siocngetspeed(iobase, table)
3957 struct speedtab *table;
3964 cfcr = inb(iobase + com_cfcr);
3965 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3967 dlbl = inb(iobase + com_dlbl);
3968 dlbh = inb(iobase + com_dlbh);
3970 outb(iobase + com_cfcr, cfcr);
3972 code = dlbh << 8 | dlbl;
3974 for ( ; table->sp_speed != -1; table++)
3975 if (table->sp_code == code)
3976 return (table->sp_speed);
3978 return 0; /* didn't match anything sane */
3982 siocnopen(sp, iobase, speed)
3983 struct siocnstate *sp;
3992 * Save all the device control registers except the fifo register
3993 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3994 * We can't save the fifo register since it is read-only.
3996 sp->ier = inb(iobase + com_ier);
3997 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3998 siocntxwait(iobase);
3999 sp->cfcr = inb(iobase + com_cfcr);
4000 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4001 sp->dlbl = inb(iobase + com_dlbl);
4002 sp->dlbh = inb(iobase + com_dlbh);
4004 * Only set the divisor registers if they would change, since on
4005 * some 16550 incompatibles (Startech), setting them clears the
4006 * data input register. This also reduces the effects of the
4009 divisor = ttspeedtab(speed, comspeedtab);
4010 dlbl = divisor & 0xFF;
4011 if (sp->dlbl != dlbl)
4012 outb(iobase + com_dlbl, dlbl);
4013 dlbh = (u_int) divisor >> 8;
4014 if (sp->dlbh != dlbh)
4015 outb(iobase + com_dlbh, dlbh);
4016 outb(iobase + com_cfcr, CFCR_8BITS);
4017 sp->mcr = inb(iobase + com_mcr);
4019 * We don't want interrupts, but must be careful not to "disable"
4020 * them by clearing the MCR_IENABLE bit, since that might cause
4021 * an interrupt by floating the IRQ line.
4023 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
4027 siocnclose(sp, iobase)
4028 struct siocnstate *sp;
4032 * Restore the device control registers.
4034 siocntxwait(iobase);
4035 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4036 if (sp->dlbl != inb(iobase + com_dlbl))
4037 outb(iobase + com_dlbl, sp->dlbl);
4038 if (sp->dlbh != inb(iobase + com_dlbh))
4039 outb(iobase + com_dlbh, sp->dlbh);
4040 outb(iobase + com_cfcr, sp->cfcr);
4042 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
4044 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
4045 outb(iobase + com_ier, sp->ier);
4058 struct siocnstate sp;
4061 * Find our first enabled console, if any. If it is a high-level
4062 * console device, then initialize it and return successfully.
4063 * If it is a low-level console device, then initialize it and
4064 * return unsuccessfully. It must be initialized in both cases
4065 * for early use by console drivers and debuggers. Initializing
4066 * the hardware is not necessary in all cases, since the i/o
4067 * routines initialize it on the fly, but it is necessary if
4068 * input might arrive while the hardware is switched back to an
4069 * uninitialized state. We can't handle multiple console devices
4070 * yet because our low-level routines don't take a device arg.
4071 * We trust the user to set the console flags properly so that we
4072 * don't need to probe.
4074 cp->cn_pri = CN_DEAD;
4076 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
4078 if (resource_int_value("sio", unit, "flags", &flags))
4080 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
4084 if (resource_int_value("sio", unit, "port", &port))
4088 if (boothowto & RB_SERIAL) {
4089 boot_speed = siocngetspeed(iobase, comspeedtab);
4091 comdefaultrate = boot_speed;
4095 * Initialize the divisor latch. We can't rely on
4096 * siocnopen() to do this the first time, since it
4097 * avoids writing to the latch if the latch appears
4098 * to have the correct value. Also, if we didn't
4099 * just read the speed from the hardware, then we
4100 * need to set the speed in hardware so that
4101 * switching it later is null.
4103 cfcr = inb(iobase + com_cfcr);
4104 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
4105 outb(iobase + com_dlbl,
4106 COMBRD(comdefaultrate) & 0xff);
4107 outb(iobase + com_dlbh,
4108 (u_int) COMBRD(comdefaultrate) >> 8);
4109 outb(iobase + com_cfcr, cfcr);
4111 siocnopen(&sp, iobase, comdefaultrate);
4114 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
4115 cp->cn_dev = makedev(CDEV_MAJOR, unit);
4116 cp->cn_pri = COM_FORCECONSOLE(flags)
4117 || boothowto & RB_SERIAL
4118 ? CN_REMOTE : CN_NORMAL;
4119 printf("sio%d: system console\n", unit);
4120 siocniobase = iobase;
4123 if (COM_DEBUGGER(flags) && !COM_LLCONSOLE(flags)) {
4124 printf("sio%d: gdb debugging port\n", unit);
4125 siogdbiobase = iobase;
4129 gdbdev = makedev(CDEV_MAJOR, unit);
4130 gdb_getc = siocngetc;
4131 gdb_putc = siocnputc;
4140 * XXX Ugly Compatability.
4141 * If no gdb port has been specified, set it to be the console
4142 * as some configuration files don't specify the gdb port.
4144 if (gdbdev == NODEV && (boothowto & RB_GDB)) {
4145 printf("Warning: no GDB port specified. Defaulting to sio%d.\n",
4147 printf("Set flag 0x80 on desired GDB port in your\n");
4148 printf("configuration file (currently sio only).\n");
4149 siogdbiobase = siocniobase;
4150 siogdbunit = siocnunit;
4151 gdbdev = makedev(CDEV_MAJOR, siocnunit);
4152 gdb_getc = siocngetc;
4153 gdb_putc = siocnputc;
4161 struct consdev siocons = {
4162 NULL, NULL, siocngetc, siocncheckc, siocnputc,
4166 extern struct consdev *cn_tab;
4169 siocnattach(port, speed)
4175 struct siocnstate sp;
4178 comdefaultrate = speed;
4183 * Initialize the divisor latch. We can't rely on
4184 * siocnopen() to do this the first time, since it
4185 * avoids writing to the latch if the latch appears
4186 * to have the correct value. Also, if we didn't
4187 * just read the speed from the hardware, then we
4188 * need to set the speed in hardware so that
4189 * switching it later is null.
4191 cfcr = inb(siocniobase + com_cfcr);
4192 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
4193 outb(siocniobase + com_dlbl,
4194 COMBRD(comdefaultrate) & 0xff);
4195 outb(siocniobase + com_dlbh,
4196 (u_int) COMBRD(comdefaultrate) >> 8);
4197 outb(siocniobase + com_cfcr, cfcr);
4199 siocnopen(&sp, siocniobase, comdefaultrate);
4202 siocons.cn_dev = makedev(CDEV_MAJOR, 0);
4208 siogdbattach(port, speed)
4214 struct siocnstate sp;
4216 siogdbiobase = port;
4217 gdbdefaultrate = speed;
4222 * Initialize the divisor latch. We can't rely on
4223 * siocnopen() to do this the first time, since it
4224 * avoids writing to the latch if the latch appears
4225 * to have the correct value. Also, if we didn't
4226 * just read the speed from the hardware, then we
4227 * need to set the speed in hardware so that
4228 * switching it later is null.
4230 cfcr = inb(siogdbiobase + com_cfcr);
4231 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
4232 outb(siogdbiobase + com_dlbl,
4233 COMBRD(gdbdefaultrate) & 0xff);
4234 outb(siogdbiobase + com_dlbh,
4235 (u_int) COMBRD(gdbdefaultrate) >> 8);
4236 outb(siogdbiobase + com_cfcr, cfcr);
4238 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4253 comconsole = DEV_TO_UNIT(cp->cn_dev);
4266 struct siocnstate sp;
4268 if (minor(dev) == siogdbunit)
4269 iobase = siogdbiobase;
4271 iobase = siocniobase;
4273 siocnopen(&sp, iobase, comdefaultrate);
4274 if (inb(iobase + com_lsr) & LSR_RXRDY)
4275 c = inb(iobase + com_data);
4278 siocnclose(&sp, iobase);
4291 struct siocnstate sp;
4293 if (minor(dev) == siogdbunit)
4294 iobase = siogdbiobase;
4296 iobase = siocniobase;
4298 siocnopen(&sp, iobase, comdefaultrate);
4299 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4301 c = inb(iobase + com_data);
4302 siocnclose(&sp, iobase);
4313 struct siocnstate sp;
4316 if (minor(dev) == siogdbunit)
4317 iobase = siogdbiobase;
4319 iobase = siocniobase;
4321 siocnopen(&sp, iobase, comdefaultrate);
4322 siocntxwait(iobase);
4323 outb(iobase + com_data, c);
4324 siocnclose(&sp, iobase);
4335 struct siocnstate sp;
4337 iobase = siogdbiobase;
4339 siocnopen(&sp, iobase, gdbdefaultrate);
4340 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4342 c = inb(iobase + com_data);
4343 siocnclose(&sp, iobase);
4353 struct siocnstate sp;
4356 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4357 siocntxwait(siogdbiobase);
4358 outb(siogdbiobase + com_data, c);
4359 siocnclose(&sp, siogdbiobase);
4366 * support PnP cards if we are using 'em
4371 static pnpid_t siopnp_ids[] = {
4372 { 0x5015f435, "MOT1550"},
4373 { 0x8113b04e, "Supra1381"},
4374 { 0x9012b04e, "Supra1290"},
4375 { 0x7121b04e, "SupraExpress 56i Sp"},
4376 { 0x11007256, "USR0011"},
4377 { 0x30207256, "USR2030"},
4378 { 0x31307256, "USR3031"},
4379 { 0x90307256, "USR3090"},
4380 { 0x0100440e, "Cardinal MVP288IV"},
4384 static char *siopnp_probe(u_long csn, u_long vend_id);
4385 static void siopnp_attach(u_long csn, u_long vend_id, char *name,
4386 struct isa_device *dev);
4387 static u_long nsiopnp = NSIO;
4389 static struct pnp_device siopnp = {
4396 DATA_SET (pnpdevice_set, siopnp);
4399 siopnp_probe(u_long csn, u_long vend_id)
4404 for(id = siopnp_ids; id->vend_id != 0; id++) {
4405 if (vend_id == id->vend_id) {
4413 read_pnp_parms(&d, 0);
4414 if (d.enable == 0 || d.flags & 1) {
4415 printf("CSN %lu is disabled.\n", csn);
4425 siopnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev)
4429 if (dev->id_unit >= NSIOTOT)
4432 if (read_pnp_parms(&d, 0) == 0) {
4433 printf("failed to read pnp parms\n");
4437 write_pnp_parms(&d, 0);
4441 dev->id_iobase = d.port[0];
4442 dev->id_irq = (1 << d.irq[0]);
4443 dev->id_ointr = siointr;
4444 dev->id_ri_flags = RI_FAST;
4447 if (dev->id_driver == NULL) {
4448 dev->id_driver = &siodriver;
4449 dev->id_id = isa_compat_nextid();
4452 if ((dev->id_alive = sioprobe(dev)) != 0)
4455 printf("sio%d: probe failed\n", dev->id_unit);
4459 DEV_DRIVER_MODULE(sio, isa, sio_driver, sio_devclass,
4460 CDEV_MAJOR, NOMAJ, sio_cdevsw, 0, 0);
4464 * pc98 local function
4468 com_tiocm_set(struct com_s *com, int msr)
4472 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS;
4475 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) )
4476 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4477 tmp |= (CMD8251_TxEN|CMD8251_RxEN);
4478 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4479 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4480 pc98_i8251_clear_or_cmd( com, mask, tmp );
4485 com_tiocm_bis(struct com_s *com, int msr)
4491 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4492 tmp |= CMD8251_TxEN|CMD8251_RxEN;
4493 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4494 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4496 pc98_i8251_or_cmd( com, tmp );
4501 com_tiocm_bic(struct com_s *com, int msr)
4507 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4508 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4509 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4511 pc98_i8251_clear_cmd( com, tmp );
4516 com_tiocm_get(struct com_s *com)
4518 return( com->pc98_prev_modem_status );
4522 com_tiocm_get_delta(struct com_s *com)
4526 tmp = com->pc98_modem_delta;
4527 com->pc98_modem_delta = 0;
4531 /* convert to TIOCM_?? ( ioctl.h ) */
4533 pc98_get_modem_status(struct com_s *com)
4538 stat = inb(com->sts_port);
4539 stat2 = inb(com->in_modem_port);
4540 msr = com->pc98_prev_modem_status
4541 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4542 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
4543 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
4544 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
4545 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
4546 #if COM_CARRIER_DETECT_EMULATE
4547 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4555 pc98_check_msr(void* chan)
4559 register struct tty *tp;
4567 unit = MINOR_TO_UNIT(mynor);
4568 com = com_addr(unit);
4572 msr = pc98_get_modem_status(com);
4573 /* make change flag */
4574 delta = msr ^ com->pc98_prev_modem_status;
4575 if ( delta & TIOCM_CAR ) {
4576 if ( com->modem_car_chg_timer ) {
4577 if ( -- com->modem_car_chg_timer )
4580 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ?
4581 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0)
4585 com->modem_car_chg_timer = 0;
4586 delta = ( msr ^ com->pc98_prev_modem_status ) &
4587 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4588 com->pc98_prev_modem_status = msr;
4589 delta = ( com->pc98_modem_delta |= delta );
4591 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
4595 timeout(pc98_check_msr, (caddr_t)dev,
4596 PC98_CHECK_MODEM_INTERVAL);
4598 com->modem_checking = 0;
4603 pc98_msrint_start(dev_t dev)
4611 unit = MINOR_TO_UNIT(mynor);
4612 com = com_addr(unit);
4613 /* modem control line check routine envoke interval is 1/10 sec */
4614 if ( com->modem_checking == 0 ) {
4615 com->pc98_prev_modem_status = pc98_get_modem_status(com);
4616 com->pc98_modem_delta = 0;
4617 timeout(pc98_check_msr, (caddr_t)dev,
4618 PC98_CHECK_MODEM_INTERVAL);
4619 com->modem_checking = 1;
4625 pc98_disable_i8251_interrupt(struct com_s *com, int mod)
4627 /* disable interrupt */
4630 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4632 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4633 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
4638 pc98_enable_i8251_interrupt(struct com_s *com, int mod)
4643 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4644 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
4649 pc98_check_i8251_interrupt(struct com_s *com)
4651 return ( com->intr_enable & 0x07 );
4655 pc98_i8251_clear_cmd(struct com_s *com, int x)
4660 tmp = com->pc98_prev_siocmd & ~(x);
4661 outb(com->cmd_port, tmp);
4662 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4667 pc98_i8251_or_cmd(struct com_s *com, int x)
4672 tmp = com->pc98_prev_siocmd | (x);
4673 outb(com->cmd_port, tmp);
4674 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4679 pc98_i8251_set_cmd(struct com_s *com, int x)
4685 outb(com->cmd_port, tmp);
4686 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4691 pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4695 tmp = com->pc98_prev_siocmd & ~(clr);
4697 outb(com->cmd_port, tmp);
4698 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4703 pc98_i8251_get_cmd(struct com_s *com)
4705 return com->pc98_prev_siocmd;
4709 pc98_i8251_get_mod(struct com_s *com)
4711 return com->pc98_prev_siomod;
4715 pc98_i8251_reset(struct com_s *com, int mode, int command)
4717 outb(com->cmd_port, 0); /* dummy */
4719 outb(com->cmd_port, 0); /* dummy */
4721 outb(com->cmd_port, 0); /* dummy */
4723 outb(com->cmd_port, CMD8251_RESET); /* internal reset */
4725 outb(com->cmd_port, mode ); /* mode register */
4726 com->pc98_prev_siomod = mode;
4728 pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4732 pc98_check_sysclock(void)
4734 /* get system clock from port */
4735 if ( pc98_machine_type & M_8M ) {
4736 /* 8 MHz system & H98 */
4745 com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4750 count = pc98_ttspeedtab( com, speed );
4751 if ( count < 0 ) return;
4753 previnterrupt = pc98_check_i8251_interrupt(com);
4754 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4756 switch ( cflag&CSIZE ) {
4758 cfcr = MOD8251_5BITS; break;
4760 cfcr = MOD8251_6BITS; break;
4762 cfcr = MOD8251_7BITS; break;
4764 cfcr = MOD8251_8BITS; break;
4766 if ( cflag&PARENB ) {
4768 cfcr |= MOD8251_PODD;
4770 cfcr |= MOD8251_PEVEN;
4772 cfcr |= MOD8251_PDISAB;
4775 cfcr |= MOD8251_STOP2;
4777 cfcr |= MOD8251_STOP1;
4779 if ( count & 0x10000 )
4780 cfcr |= MOD8251_CLKX1;
4782 cfcr |= MOD8251_CLKX16;
4784 if (epson_machine_id != 0x20) { /* XXX */
4786 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4789 /* set baud rate from ospeed */
4790 pc98_set_baud_rate( com, count );
4792 if ( cfcr != pc98_i8251_get_mod(com) )
4793 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4795 pc98_enable_i8251_interrupt( com, previnterrupt );
4799 pc98_ttspeedtab(struct com_s *com, int speed)
4801 int if_type, effect_sp, count = -1, mod;
4803 if_type = com->pc98_if_type & 0x0f;
4805 switch (com->pc98_if_type) {
4806 case COM_IF_INTERNAL:
4807 if (PC98SIO_baud_rate_port(if_type) != -1) {
4808 count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4810 count |= COM1_EXT_CLOCK;
4815 /* for *1CLK asynchronous! mode, TEFUTEFU */
4816 mod = (sysclock == 5) ? 2457600 : 1996800;
4817 effect_sp = ttspeedtab( speed, pc98speedtab );
4818 if ( effect_sp < 0 ) /* XXX */
4819 effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4820 if ( effect_sp <= 0 )
4822 if ( effect_sp == speed )
4824 if ( mod % effect_sp )
4826 count = mod / effect_sp;
4827 if ( count > 65535 )
4829 if ( effect_sp != speed )
4832 case COM_IF_PC9861K_1:
4833 case COM_IF_PC9861K_2:
4836 case COM_IF_IND_SS_1:
4837 case COM_IF_IND_SS_2:
4838 case COM_IF_PIO9032B_1:
4839 case COM_IF_PIO9032B_2:
4840 if ( speed == 0 ) return 0;
4841 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4843 case COM_IF_B98_01_1:
4844 case COM_IF_B98_01_2:
4845 if ( speed == 0 ) return 0;
4846 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4848 if (count == 0 || count == 1) {
4850 count |= 0x20000; /* x1 mode for 76800 and 153600 */
4860 pc98_set_baud_rate( struct com_s *com, int count )
4864 if_type = com->pc98_if_type & 0x0f;
4865 io = com->iobase & 0xff00;
4867 switch (com->pc98_if_type) {
4868 case COM_IF_INTERNAL:
4869 if (PC98SIO_baud_rate_port(if_type) != -1) {
4870 if (count & COM1_EXT_CLOCK) {
4871 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
4874 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
4879 printf( "[ Illegal count : %d ]", count );
4881 } else if ( count == 0 )
4890 outb( 0x75, count & 0xff );
4892 outb( 0x75, (count >> 8) & 0xff );
4895 case COM_IF_IND_SS_1:
4896 case COM_IF_IND_SS_2:
4897 outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
4898 outb(io | PC98SIO_baud_rate_port(if_type), 0);
4899 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
4900 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
4901 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
4903 case COM_IF_PIO9032B_1:
4904 case COM_IF_PIO9032B_2:
4905 outb(io | PC98SIO_baud_rate_port(if_type), count);
4907 case COM_IF_B98_01_1:
4908 case COM_IF_B98_01_2:
4909 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
4912 * Some old B98_01 board should be controlled
4913 * in different way, but this hasn't been tested yet.
4915 outb(io | PC98SIO_func_port(if_type),
4916 (count & 0x20000) ? 0xf0 : 0xf2);
4922 pc98_check_if_type(device_t dev, struct siodev *iod)
4924 int irr, io, if_type, tmp;
4925 static short irq_tab[2][8] = {
4926 { 3, 5, 6, 9, 10, 12, 13, -1},
4927 { 3, 10, 12, 13, 5, 6, 9, -1}
4930 iod->if_type = if_type = (isa_get_flags(dev) >> 24) & 0xff;
4931 if ((if_type < 0 || if_type > COM_IF_END1) &&
4932 (if_type < 0x10 || if_type > COM_IF_END2))
4936 io = isa_get_port(dev) & 0xff00;
4938 if (IS_8251(iod->if_type)) {
4939 if (PC98SIO_func_port(if_type) != -1) {
4940 outb(io | PC98SIO_func_port(if_type), 0xf2);
4941 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4942 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4943 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4946 iod->cmd = io | PC98SIO_cmd_port(if_type);
4947 iod->sts = io | PC98SIO_sts_port(if_type);
4948 iod->mod = io | PC98SIO_in_modem_port(if_type);
4949 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
4951 if (iod->if_type == COM_IF_INTERNAL) {
4954 /* XXX check new internal port. */
4957 for (tmp = 0; tmp < 100; tmp++) {
4958 if ((inb(0x138) & 1) == 0) {
4959 PC98SIO_baud_rate_port(if_type) = 0x13a;
4960 if_8251_type[if_type].name = " (internal fast)";
4961 if_8251_type[if_type].speedtab = pc98fast_speedtab;
4967 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4968 if ((isa_get_port(dev) & 0xff) == IO_COM2)
4969 iod->irq = irq_tab[0][tmp];
4971 iod->irq = irq_tab[1][tmp];
4974 irr = if_16550a_type[if_type].irr_read;
4975 #ifdef COM_MULTIPORT
4976 if (!COM_ISMULTIPORT(isa_get_flags(dev)) ||
4977 device_get_unit(dev) == COM_MPMASTER(isa_get_flags(dev)))
4980 tmp = inb(io | irr);
4981 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */
4982 iod->irq = irq_tab[1][tmp >> 3];
4984 iod->irq = irq_tab[0][tmp & 0x07];
4987 if ( iod->irq == -1 ) return -1;
4992 pc98_set_ioport( struct com_s *com, int id_flags )
4996 if_type = (id_flags >> 24) & 0xff;
4997 if (IS_8251(if_type)) {
4998 pc98_check_sysclock();
4999 io = com->iobase & 0xff00;
5000 com->pc98_if_type = if_type;
5002 com->data_port = io | PC98SIO_data_port(if_type);
5003 com->cmd_port = io | PC98SIO_cmd_port(if_type);
5004 com->sts_port = io | PC98SIO_sts_port(if_type);
5005 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
5006 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
5012 #endif /* PC98 defined */