2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
34 * $Id: sio.c,v 1.76 1999/01/19 00:21:53 peter Exp $
37 #include "opt_comconsole.h"
38 #include "opt_compat.h"
40 #include "opt_devfs.h"
46 * Serial driver, based on 386BSD-0.1 com driver.
47 * Mostly rewritten to use pseudo-DMA.
48 * Works for National Semiconductor NS8250-NS16550AF UARTs.
49 * COM driver, based on HP dca driver.
51 * Changes for PC-Card integration:
52 * - Added PC-Card driver table and handlers
54 /*===============================================================
55 * 386BSD(98),FreeBSD-1.1x(98) com driver.
57 * modified for PC9801 by M.Ishii
58 * Kyoto University Microcomputer Club (KMC)
59 * Chou "TEFUTEFU" Hirotomi
60 * Kyoto Univ. the faculty of medicine
61 *===============================================================
62 * FreeBSD-2.0.1(98) sio driver.
64 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
65 * T.Koike(hfc01340@niftyserve.or.jp)
66 * implement kernel device configuration
67 * aizu@orient.center.nitech.ac.jp
71 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local
73 * This driver is under debugging,has bugs.
76 * options COM_MULTIPORT #if using MC16550II
77 * device sio0 at nec? port 0x30 tty irq 4 #internal
78 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1
79 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2
80 * # ~~~~~iobase ~~multi port flag
81 * # ~ master device is sio1
83 * cd /dev; MAKEDEV ttyd0 ttyd1 ..
85 * 57600bps is too fast for sio0(internal8251)
87 * #set default speed 9600
90 * stty </dev/ttyid$i crtscts 9600
91 * : # ~~~~ default speed(can change after init.)
95 * 5) PC9861K,PIO9032B,B98_01
99 * modified for AIWA B98-01
100 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
102 * How to configure...
103 * # options COM_MULTIPORT # support for MICROCORE MC16550II
104 * ... comment-out this line, which will conflict with B98_01.
105 * options "B98_01" # support for AIWA B98-01
106 * device sio1 at nec? port 0x00d1 tty irq ?
107 * device sio2 at nec? port 0x00d5 tty irq ?
108 * ... you can leave these lines `irq ?', irq will be autodetected.
111 * Modified by Y.Takahashi of Kogakuin University.
115 #define COM_IF_INTERNAL 0x00
116 #define COM_IF_PC9861K_1 0x01
117 #define COM_IF_PC9861K_2 0x02
118 #define COM_IF_IND_SS_1 0x03
119 #define COM_IF_IND_SS_2 0x04
120 #define COM_IF_PIO9032B_1 0x05
121 #define COM_IF_PIO9032B_2 0x06
122 #define COM_IF_B98_01_1 0x07
123 #define COM_IF_B98_01_2 0x08
124 #define COM_IF_END1 COM_IF_B98_01_2
125 #define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */
126 #define COM_IF_NS16550 0x11
127 #define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */
128 #define COM_IF_MC16550II 0x13
129 #define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */
130 #define COM_IF_RSB3000 0x15
131 #define COM_IF_RSB384 0x16
132 #define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */
133 #define COM_IF_RSA98III 0x18
134 #define COM_IF_ESP98 0x19
135 #define COM_IF_END2 COM_IF_ESP98
138 #include <sys/param.h>
139 #include <sys/systm.h>
140 #include <sys/reboot.h>
141 #include <sys/malloc.h>
143 #include <sys/proc.h>
144 #include <sys/conf.h>
145 #include <sys/dkstat.h>
146 #include <sys/fcntl.h>
147 #include <sys/interrupt.h>
148 #include <sys/kernel.h>
149 #include <sys/syslog.h>
150 #include <sys/sysctl.h>
152 #include <sys/devfsext.h>
155 #include <machine/clock.h>
156 #include <machine/ipl.h>
158 #include <machine/lock.h>
162 #include <pc98/pc98/pc98.h>
163 #include <pc98/pc98/pc98_machdep.h>
164 #include <i386/isa/icu.h>
165 #include <i386/isa/ic/i8251.h>
167 #include <i386/isa/isa.h>
169 #include <i386/isa/isa_device.h>
170 #include <i386/isa/sioreg.h>
171 #include <i386/isa/intr_machdep.h>
174 #include <i386/isa/ic/esp.h>
176 #include <i386/isa/ic/ns16550.h>
178 #include <i386/isa/ic/rsa.h>
183 #include <sys/module.h>
184 #include <pccard/cardinfo.h>
185 #include <pccard/slot.h>
189 #include <i386/isa/pnp.h>
193 #define disable_intr() COM_DISABLE_INTR()
194 #define enable_intr() COM_ENABLE_INTR()
199 #define EXTRA_SIO MAX_PNP_CARDS
205 #define NSIOTOT (NSIO + EXTRA_SIO)
207 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
208 #define RS_IBUFSIZE 256
210 #define CALLOUT_MASK 0x80
211 #define CONTROL_MASK 0x60
212 #define CONTROL_INIT_STATE 0x20
213 #define CONTROL_LOCK_STATE 0x40
214 #define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
215 #define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
216 #define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
219 /* checks in flags for multiport and which is multiport "master chip"
222 #define COM_ISMULTIPORT(dev) ((dev)->id_flags & 0x01)
223 #define COM_MPMASTER(dev) (((dev)->id_flags >> 8) & 0x0ff)
224 #define COM_NOTAST4(dev) ((dev)->id_flags & 0x04)
225 #endif /* COM_MULTIPORT */
227 #define COM_CONSOLE(dev) ((dev)->id_flags & 0x10)
228 #define COM_FORCECONSOLE(dev) ((dev)->id_flags & 0x20)
229 #define COM_LLCONSOLE(dev) ((dev)->id_flags & 0x40)
230 #define COM_LOSESOUTINTS(dev) ((dev)->id_flags & 0x08)
231 #define COM_NOFIFO(dev) ((dev)->id_flags & 0x02)
232 #define COM_ST16650A(dev) ((dev)->id_flags & 0x20000)
233 #define COM_C_NOPROBE (0x40000)
234 #define COM_NOPROBE(dev) ((dev)->id_flags & COM_C_NOPROBE)
235 #define COM_C_IIR_TXRDYBUG (0x80000)
236 #define COM_IIR_TXRDYBUG(dev) ((dev)->id_flags & COM_C_IIR_TXRDYBUG)
237 #define COM_FIFOSIZE(dev) (((dev)->id_flags & 0xff000000) >> 24)
240 #define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
242 #define com_scr 7 /* scratch register for 16450-16550 (R/W) */
246 * Input buffer watermarks.
247 * The external device is asked to stop sending when the buffer exactly reaches
248 * high water, or when the high level requests it.
249 * The high level is notified immediately (rather than at a later clock tick)
250 * when this watermark is reached.
251 * The buffer size is chosen so the watermark should almost never be reached.
252 * The low watermark is invisibly 0 since the buffer is always emptied all at
255 #define RS_IHIGHWATER (3 * RS_IBUFSIZE / 4)
259 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
260 * than the other bits so that they can be tested as a group without masking
263 * The following com and tty flags correspond closely:
264 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
266 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
267 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
268 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
269 * TS_FLUSH is not used.
270 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
271 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
273 #define CS_BUSY 0x80 /* output in progress */
274 #define CS_TTGO 0x40 /* output not stopped by XOFF */
275 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
276 #define CS_CHECKMSR 1 /* check of MSR scheduled */
277 #define CS_CTS_OFLOW 2 /* use CTS output flow control */
278 #define CS_DTR_OFF 0x10 /* DTR held off */
279 #define CS_ODONE 4 /* output completed */
280 #define CS_RTS_IFLOW 8 /* use RTS input flow control */
281 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
283 static char const * const error_desc[] = {
286 #define CE_INTERRUPT_BUF_OVERFLOW 1
287 "interrupt-level buffer overflow",
288 #define CE_TTY_BUF_OVERFLOW 2
289 "tty-level buffer overflow",
293 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
295 /* types. XXX - should be elsewhere */
296 typedef u_int Port_t; /* hardware port */
297 typedef u_char bool_t; /* boolean */
299 /* queue of linear buffers */
301 u_char *l_head; /* next char to process */
302 u_char *l_tail; /* one past the last char to process */
303 struct lbq *l_next; /* next in queue */
304 bool_t l_queued; /* nonzero if queued */
307 /* com device structure */
309 u_int id_flags; /* Copy isa device falgas */
310 u_char state; /* miscellaneous flag bits */
311 bool_t active_out; /* nonzero if the callout device is open */
312 u_char cfcr_image; /* copy of value written to CFCR */
314 bool_t esp; /* is this unit a hayes esp board? */
316 u_char extra_state; /* more flag bits, separate for order trick */
317 u_char fifo_image; /* copy of value written to FIFO */
318 bool_t hasfifo; /* nonzero for 16550 UARTs */
319 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */
320 bool_t loses_outints; /* nonzero if device loses output interrupts */
321 u_char mcr_image; /* copy of value written to MCR */
323 bool_t multiport; /* is this unit part of a multiport device? */
324 #endif /* COM_MULTIPORT */
325 bool_t no_irq; /* nonzero if irq is not attached */
326 bool_t gone; /* hardware disappeared */
327 bool_t poll; /* nonzero if polling is required */
328 bool_t poll_output; /* nonzero if polling for output is required */
329 int unit; /* unit number */
330 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */
332 u_int wopeners; /* # processes waiting for DCD in open() */
335 * The high level of the driver never reads status registers directly
336 * because there would be too many side effects to handle conveniently.
337 * Instead, it reads copies of the registers stored here by the
340 u_char last_modem_status; /* last MSR read by intr handler */
341 u_char prev_modem_status; /* last MSR handled by high level */
343 u_char hotchar; /* ldisc-specific char to be handled ASAP */
344 u_char *ibuf; /* start of input buffer */
345 u_char *ibufend; /* end of input buffer */
346 u_char *ihighwater; /* threshold in input buffer */
347 u_char *iptr; /* next free spot in input buffer */
349 struct lbq obufq; /* head of queue of output buffers */
350 struct lbq obufs[2]; /* output buffers */
355 Port_t in_modem_port;
356 Port_t intr_ctrl_port;
358 int pc98_prev_modem_status;
359 int pc98_modem_delta;
360 int modem_car_chg_timer;
361 int pc98_prev_siocmd;
362 int pc98_prev_siomod;
366 Port_t data_port; /* i/o ports */
373 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
375 Port_t modem_ctl_port;
376 Port_t line_status_port;
377 Port_t modem_status_port;
378 Port_t intr_ctl_port; /* Ports of IIR register */
380 struct tty *tp; /* cross reference */
383 struct termios it_in; /* should be in struct tty */
384 struct termios it_out;
387 struct termios lt_in; /* should be in struct tty */
388 struct termios lt_out;
391 bool_t do_dcd_timestamp;
392 struct timeval timestamp;
393 struct timeval dcd_timestamp;
395 u_long bytes_in; /* statistics */
397 u_int delta_error_counts[CE_NTYPES];
398 u_long error_counts[CE_NTYPES];
401 * Ping-pong input buffers. The extra factor of 2 in the sizes is
402 * to allow for an error byte for each input byte.
405 u_long CE_INPUT_OFFSET;
410 * Data area for output buffers. Someday we should build the output
411 * buffer queue without copying data.
416 #define CE_INPUT_OFFSET RS_IBUFSIZE
417 u_char ibuf1[2 * RS_IBUFSIZE];
418 u_char ibuf2[2 * RS_IBUFSIZE];
421 * Data area for output buffers. Someday we should build the output
422 * buffer queue without copying data.
428 void *devfs_token_ttyd;
429 void *devfs_token_ttyl;
430 void *devfs_token_ttyi;
431 void *devfs_token_cuaa;
432 void *devfs_token_cual;
433 void *devfs_token_cuai;
438 static int espattach __P((struct isa_device *isdp, struct com_s *com,
441 static int sioattach __P((struct isa_device *dev));
442 static timeout_t siobusycheck;
443 static timeout_t siodtrwakeup;
444 static void comhardclose __P((struct com_s *com));
445 static ointhand2_t siointr;
446 static void siointr1 __P((struct com_s *com));
447 static int commctl __P((struct com_s *com, int bits, int how));
448 static int comparam __P((struct tty *tp, struct termios *t));
449 static swihand_t siopoll;
450 static int sioprobe __P((struct isa_device *dev));
451 static void siosettimeout __P((void));
452 static void comstart __P((struct tty *tp));
453 static timeout_t comwakeup;
454 static void disc_optim __P((struct tty *tp, struct termios *t,
458 static char driver_name[] = "sio";
460 /* table and macro for fast conversion from a unit number to its com struct */
461 static struct com_s *p_com_addr[NSIOTOT];
462 #define com_addr(unit) (p_com_addr[unit])
464 struct isa_driver siodriver = {
465 sioprobe, sioattach, driver_name
468 static d_open_t sioopen;
469 static d_close_t sioclose;
470 static d_read_t sioread;
471 static d_write_t siowrite;
472 static d_ioctl_t sioioctl;
473 static d_stop_t siostop;
474 static d_devtotty_t siodevtotty;
476 #define CDEV_MAJOR 28
477 static struct cdevsw sio_cdevsw = {
478 sioopen, sioclose, sioread, siowrite,
479 sioioctl, siostop, noreset, siodevtotty,
480 ttpoll, nommap, NULL, driver_name,
481 NULL, -1, nodump, nopsize,
485 static int comconsole = -1;
486 static volatile speed_t comdefaultrate = CONSPEED;
487 static u_int com_events; /* input chars + weighted output completions */
488 static Port_t siocniobase;
489 static bool_t sio_registered;
490 static int sio_timeout;
491 static int sio_timeouts_until_log;
492 static struct callout_handle sio_timeout_handle
493 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
495 static struct tty *sio_tty[NSIOTOT];
497 static struct tty sio_tty[NSIOTOT];
499 static const int nsio_tty = NSIOTOT;
505 Port_t cmd, sts, ctrl, mod;
509 #define COM_INT_DISABLE {int previpri; previpri=spltty();
510 #define COM_INT_ENABLE splx(previpri);}
511 #define IEN_TxFLAG IEN_Tx
513 #define COM_CARRIER_DETECT_EMULATE 0
514 #define PC98_CHECK_MODEM_INTERVAL (hz/10)
515 #define DCD_OFF_TOLERANCE 2
516 #define DCD_ON_RECOGNITION 2
517 #define IS_8251(if_type) (!(if_type & 0x10))
518 #define COM1_EXT_CLOCK 0x40000
520 static void commint __P((dev_t dev));
521 static void com_tiocm_set __P((struct com_s *com, int msr));
522 static void com_tiocm_bis __P((struct com_s *com, int msr));
523 static void com_tiocm_bic __P((struct com_s *com, int msr));
524 static int com_tiocm_get __P((struct com_s *com));
525 static int com_tiocm_get_delta __P((struct com_s *com));
526 static void pc98_msrint_start __P((dev_t dev));
527 static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed));
528 static int pc98_ttspeedtab __P((struct com_s *com, int speed));
529 static int pc98_get_modem_status __P((struct com_s *com));
530 static timeout_t pc98_check_msr;
531 static void pc98_set_baud_rate __P((struct com_s *com, int count));
532 static void pc98_i8251_reset __P((struct com_s *com, int mode, int command));
533 static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod));
534 static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
535 static int pc98_check_i8251_interrupt __P((struct com_s *com));
536 static int pc98_i8251_get_cmd __P((struct com_s *com));
537 static int pc98_i8251_get_mod __P((struct com_s *com));
538 static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
539 static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
540 static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
541 static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
542 static int pc98_check_if_type __P((struct isa_device *dev, struct siodev *iod));
543 static void pc98_check_sysclock __P((void));
544 static int pc98_set_ioport __P((struct com_s *com, int id_flags));
546 #define com_int_Tx_disable(com) \
547 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
548 #define com_int_Tx_enable(com) \
549 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
550 #define com_int_Rx_disable(com) \
551 pc98_disable_i8251_interrupt(com,IEN_Rx)
552 #define com_int_Rx_enable(com) \
553 pc98_enable_i8251_interrupt(com,IEN_Rx)
554 #define com_int_TxRx_disable(com) \
555 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
556 #define com_int_TxRx_enable(com) \
557 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
558 #define com_send_break_on(com) \
559 pc98_i8251_or_cmd(com,CMD8251_SBRK)
560 #define com_send_break_off(com) \
561 pc98_i8251_clear_cmd(com,CMD8251_SBRK)
563 static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
585 static struct speedtab pc98fast_speedtab[] = {
586 9600, 0x80 | COMBRD(9600),
587 19200, 0x80 | COMBRD(19200),
588 38400, 0x80 | COMBRD(38400),
589 57600, 0x80 | COMBRD(57600),
590 115200, 0x80 | COMBRD(115200),
593 static struct speedtab comspeedtab_pio9032b[] = {
604 static struct speedtab comspeedtab_b98_01[] = {
619 static struct speedtab comspeedtab_mc16550[] = {
635 static struct speedtab comspeedtab_rsb384[] = {
656 static struct speedtab comspeedtab_rsa[] = {
658 { 50, COMBRD_RSA(50) },
659 { 75, COMBRD_RSA(75) },
660 { 110, COMBRD_RSA(110) },
661 { 134, COMBRD_RSA(134) },
662 { 150, COMBRD_RSA(150) },
663 { 200, COMBRD_RSA(200) },
664 { 300, COMBRD_RSA(300) },
665 { 600, COMBRD_RSA(600) },
666 { 1200, COMBRD_RSA(1200) },
667 { 1800, COMBRD_RSA(1800) },
668 { 2400, COMBRD_RSA(2400) },
669 { 4800, COMBRD_RSA(4800) },
670 { 9600, COMBRD_RSA(9600) },
671 { 19200, COMBRD_RSA(19200) },
672 { 38400, COMBRD_RSA(38400) },
673 { 57600, COMBRD_RSA(57600) },
674 { 115200, COMBRD_RSA(115200) },
675 { 230400, COMBRD_RSA(230400) },
676 { 460800, COMBRD_RSA(460800) },
677 { 921600, COMBRD_RSA(921600) },
682 static struct speedtab comspeedtab[] = {
686 { 110, COMBRD(110) },
687 { 134, COMBRD(134) },
688 { 150, COMBRD(150) },
689 { 200, COMBRD(200) },
690 { 300, COMBRD(300) },
691 { 600, COMBRD(600) },
692 { 1200, COMBRD(1200) },
693 { 1800, COMBRD(1800) },
694 { 2400, COMBRD(2400) },
695 { 4800, COMBRD(4800) },
696 { 9600, COMBRD(9600) },
697 { 19200, COMBRD(19200) },
698 { 38400, COMBRD(38400) },
699 { 57600, COMBRD(57600) },
700 { 115200, COMBRD(115200) },
709 struct speedtab *speedtab;
712 /* COM_IF_INTERNAL */
713 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
714 -1, pc98speedtab, 1 },
715 /* COM_IF_PC9861K_1 */
716 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
718 /* COM_IF_PC9861K_2 */
719 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
721 /* COM_IF_IND_SS_1 */
722 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
723 3, comspeedtab_mc16550, 1 },
724 /* COM_IF_IND_SS_2 */
725 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
726 3, comspeedtab_mc16550, 1 },
727 /* COM_IF_PIO9032B_1 */
728 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
729 7, comspeedtab_pio9032b, 1 },
730 /* COM_IF_PIO9032B_2 */
731 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
732 7, comspeedtab_pio9032b, 1 },
733 /* COM_IF_B98_01_1 */
734 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
735 7, comspeedtab_b98_01, 0 },
736 /* COM_IF_B98_01_2 */
737 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
738 7, comspeedtab_b98_01, 0 },
740 #define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
741 #define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
742 #define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
743 #define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
744 #define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
745 #define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
746 #define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
754 struct speedtab *speedtab;
755 } if_16550a_type[] = {
757 { " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab },
759 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
760 /* COM_IF_SECOND_CCU */
761 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
762 /* COM_IF_MC16550II */
763 { " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
765 { " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
767 { " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
769 { " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
770 /* COM_IF_MODEM_CARD */
771 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
772 /* COM_IF_RSA98III */
773 { " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa },
775 { " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 },
782 /* XXX configure this properly. */
783 static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
784 static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
786 #define ESP98_CMD1 (ESP_CMD1 * 0x100)
787 #define ESP98_CMD2 (ESP_CMD2 * 0x100)
788 #define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
789 #define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
793 /* XXX configure this properly. */
794 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
795 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
801 * handle sysctl read/write requests for console speed
803 * In addition to setting comdefaultrate for I/O through /dev/console,
804 * also set the initial and lock values for the /dev/ttyXX device
805 * if there is one associated with the console. Finally, if the /dev/tty
806 * device has already been open, change the speed on the open running port
811 sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS
818 newspeed = comdefaultrate;
820 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
821 if (error || !req->newptr)
824 comdefaultrate = newspeed;
826 if (comconsole < 0) /* serial console not selected? */
829 com = com_addr(comconsole);
834 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
835 * (note, the lock rates really are boolean -- if non-zero, disallow
838 com->it_in.c_ispeed = com->it_in.c_ospeed =
839 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
840 com->it_out.c_ispeed = com->it_out.c_ospeed =
841 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate;
844 * if we're open, change the running rate too
847 if (tp && (tp->t_state & TS_ISOPEN)) {
848 tp->t_termios.c_ispeed =
849 tp->t_termios.c_ospeed = comdefaultrate;
851 error = comparam(tp, &tp->t_termios);
857 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
858 0, 0, sysctl_machdep_comdefaultrate, "I", "");
862 * PC-Card (PCMCIA) specific code.
864 static int sioinit __P((struct pccard_devinfo *));
865 static void siounload __P((struct pccard_devinfo *));
866 static int card_intr __P((struct pccard_devinfo *));
868 PCCARD_MODULE(sio, sioinit, siounload, card_intr, 0, tty_imask);
871 * Initialize the device - called from Slot manager.
874 sioinit(struct pccard_devinfo *devi)
877 /* validate unit number. */
878 if (devi->isahd.id_unit >= (NSIOTOT))
880 /* Make sure it isn't already probed. */
881 if (com_addr(devi->isahd.id_unit))
884 /* It's already probed as serial by Upper */
885 devi->isahd.id_flags |= COM_C_NOPROBE;
888 * Probe the device. If a value is returned, the
889 * device was found at the location.
891 if (sioprobe(&devi->isahd) == 0)
893 if (sioattach(&devi->isahd) == 0)
900 * siounload - unload the driver and clear the table.
902 * This is usually called when the card is ejected, but
903 * can be caused by a modunload of a controller driver.
904 * The idea is to reset the driver's view of the device
905 * and ensure that any driver entry points such as
906 * read and write do not hang.
909 siounload(struct pccard_devinfo *devi)
914 printf("NULL devi in siounload\n");
917 com = com_addr(devi->isahd.id_unit);
919 printf("NULL com in siounload\n");
923 printf("sio%d already unloaded!\n",devi->isahd.id_unit);
926 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {
928 printf("sio%d: unload\n", devi->isahd.id_unit);
934 com_addr(com->unit) = NULL;
936 bzero(com->ibuf1, com->CE_INPUT_OFFSET * 6);
938 bzero(com, sizeof *com);
940 printf("sio%d: unload,gone\n", devi->isahd.id_unit);
945 * card_intr - Shared interrupt called from
946 * front end of PC-Card handler.
949 card_intr(struct pccard_devinfo *devi)
954 com = com_addr(devi->isahd.id_unit);
955 if (com && !com->gone)
956 siointr1(com_addr(devi->isahd.id_unit));
960 #endif /* NCARD > 0 */
964 struct isa_device *dev;
966 static bool_t already_init;
969 struct isa_device *idev;
971 intrmask_t irqmap[4];
975 struct isa_device *xdev;
982 Port_t rsabase = NULL;
987 * Turn off MCR_IENABLE for all likely serial ports. An unused
988 * port with its MCR_IENABLE gate open will inhibit interrupts
989 * from any used port that shares the interrupt vector.
990 * XXX the gate enable is elsewhere for some multiports.
992 for (xdev = isa_devtab_tty; xdev->id_driver != NULL; xdev++)
994 if (xdev->id_driver == &siodriver && xdev->id_enabled) {
995 tmp = (xdev->id_flags >> 24) & 0xff;
997 outb((xdev->id_iobase & 0xff00) | PC98SIO_cmd_port(tmp & 0x0f), 0xf2);
999 if (tmp == COM_IF_RSA98III) {
1000 rsabase = xdev->id_iobase & 0xfff0;
1002 if (rsabase != xdev->id_iobase)
1005 outb(xdev->id_iobase + 8 + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1007 outb(xdev->id_iobase + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1010 if (xdev->id_driver == &siodriver && xdev->id_enabled)
1011 outb(xdev->id_iobase + com_mcr, 0);
1013 already_init = TRUE;
1016 if (COM_LLCONSOLE(dev)) {
1017 printf("sio%d: reserved for low-level i/o\n", dev->id_unit);
1025 * If the port is i8251 UART (internal, B98_01)
1027 if (pc98_check_if_type(dev, &iod) == -1)
1030 dev->id_irq = 1 << iod.irq;
1031 if (IS_8251(iod.if_type)) {
1038 outb(iod.cmd, CMD8251_RESET);
1039 DELAY(1000); /* for a while...*/
1040 outb(iod.cmd, 0xf2); /* MODE (dummy) */
1042 outb(iod.cmd, 0x01); /* CMD (dummy) */
1043 DELAY(1000); /* for a while...*/
1044 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
1047 if (if_8251_type[iod.if_type & 0x0f].check_irq) {
1049 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
1050 outb( iod.ctrl, tmp|IEN_TxEMP );
1052 ret = isa_irq_pending() ? 4 : 0;
1053 outb( iod.ctrl, tmp );
1057 * B98_01 doesn't activate TxEMP interrupt line
1058 * when being reset, so we can't check irq pending.
1062 if (epson_machine_id==0x20) { /* XXX */
1069 * If the device is on a multiport card and has an AST/4
1070 * compatible interrupt control register, initialize this
1071 * register and prepare to leave MCR_IENABLE clear in the mcr.
1072 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1073 * Point idev to the device struct giving the correct id_irq.
1074 * This is the struct for the master device if there is one.
1077 mcr_image = MCR_IENABLE;
1079 if (iod.if_type == COM_IF_RSA98III) {
1081 rsabase = idev->id_iobase & 0xfff0;
1082 if (rsabase != idev->id_iobase)
1084 outb(rsabase + rsa_msr, 0x04);
1085 outb(rsabase + rsa_frr, 0x00);
1086 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36)
1088 outb(rsabase + rsa_ier, 0x00);
1089 outb(rsabase + rsa_frr, 0x00);
1090 outb(rsabase + rsa_tivsr, 0x00);
1091 outb(rsabase + rsa_tcr, 0x00);
1094 #ifdef COM_MULTIPORT
1095 if (COM_ISMULTIPORT(dev)) {
1096 idev = find_isadev(isa_devtab_tty, &siodriver,
1099 printf("sio%d: master device %d not configured\n",
1100 dev->id_unit, COM_MPMASTER(dev));
1105 if (!COM_NOTAST4(dev)) {
1106 outb(idev->id_iobase + com_scr,
1107 idev->id_irq ? 0x80 : 0);
1112 #endif /* COM_MULTIPORT */
1113 if (idev->id_irq == 0)
1117 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1120 switch (idev->id_irq) {
1121 case IRQ3: irqout = 4; break;
1122 case IRQ5: irqout = 5; break;
1123 case IRQ6: irqout = 6; break;
1124 case IRQ12: irqout = 7; break;
1126 printf("sio%d: irq configuration error\n", dev->id_unit);
1129 outb((dev->id_iobase & 0x00ff) | tmp, irqout);
1131 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift;
1133 bzero(failures, sizeof failures);
1135 if (iod.if_type == COM_IF_RSA98III)
1136 iobase = dev->id_iobase + 8;
1139 iobase = dev->id_iobase;
1142 * We don't want to get actual interrupts, just masked ones.
1143 * Interrupts from this line should already be masked in the ICU,
1144 * but mask them in the processor as well in case there are some
1145 * (misconfigured) shared interrupts.
1151 * Initialize the speed and the word size and wait long enough to
1152 * drain the maximum of 16 bytes of junk in device output queues.
1153 * The speed is undefined after a master reset and must be set
1154 * before relying on anything related to output. There may be
1155 * junk after a (very fast) soft reboot and (apparently) after
1157 * XXX what about the UART bug avoided by waiting in comparam()?
1158 * We don't want to to wait long enough to drain at 2 bps.
1160 if (iobase == siocniobase)
1161 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1164 tmp = ttspeedtab(SIO_TEST_SPEED,
1165 if_16550a_type[iod.if_type & 0x0f].speedtab);
1166 outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS);
1167 outb(iobase + (com_dlbl << port_shift), tmp & 0xff);
1168 outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff);
1169 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1171 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
1172 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
1173 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
1174 outb(iobase + com_cfcr, CFCR_8BITS);
1176 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1180 * Enable the interrupt gate and disable device interupts. This
1181 * should leave the device driving the interrupt line low and
1182 * guarantee an edge trigger if an interrupt can be generated.
1186 outb(iobase + (com_mcr << port_shift), mcr_image);
1187 outb(iobase + (com_ier << port_shift), 0);
1189 outb(iobase + com_mcr, mcr_image);
1190 outb(iobase + com_ier, 0);
1192 DELAY(1000); /* XXX */
1193 irqmap[0] = isa_irq_pending();
1196 * Attempt to set loopback mode so that we can send a null byte
1197 * without annoying any external device.
1201 outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK);
1203 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK);
1207 * Attempt to generate an output interrupt. On 8250's, setting
1208 * IER_ETXRDY generates an interrupt independent of the current
1209 * setting and independent of whether the THR is empty. On 16450's,
1210 * setting IER_ETXRDY generates an interrupt independent of the
1211 * current setting. On 16550A's, setting IER_ETXRDY only
1212 * generates an interrupt when IER_ETXRDY is not already set.
1215 outb(iobase + (com_ier << port_shift), IER_ETXRDY);
1216 if (iod.if_type == COM_IF_RSA98III) {
1217 outb(rsabase + rsa_ier, 0x04);
1220 outb(iobase + com_ier, IER_ETXRDY);
1224 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1225 * an interrupt. They'd better generate one for actually doing
1226 * output. Loopback may be broken on the same incompatibles but
1227 * it's unlikely to do more than allow the null byte out.
1230 outb(iobase + (com_data << port_shift), 0);
1232 outb(iobase + com_data, 0);
1234 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1237 * Turn off loopback mode so that the interrupt gate works again
1238 * (MCR_IENABLE was hidden). This should leave the device driving
1239 * an interrupt line high. It doesn't matter if the interrupt
1240 * line oscillates while we are not looking at it, since interrupts
1245 outb(iobase + (com_mcr << port_shift), mcr_image);
1247 outb(iobase + com_mcr, mcr_image);
1251 * It's a definitly Serial PCMCIA(16550A), but still be required
1252 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1254 if ( COM_NOPROBE(dev) ) {
1255 /* Reading IIR register twice */
1256 for ( fn = 0; fn < 2; fn ++ ) {
1259 failures[6] = inb(iobase + (com_iir << port_shift));
1261 failures[6] = inb(iobase + com_iir);
1264 /* Check IIR_TXRDY clear ? */
1266 result = if_16550a_type[iod.if_type & 0x0f].io_size;
1268 result = IO_COMSIZE;
1270 if ( failures[6] & IIR_TXRDY ) {
1271 /* Nop, Double check with clearing IER */
1273 outb(iobase + (com_ier << port_shift), 0);
1275 (com_iir << port_shift)) & IIR_NOPEND) {
1277 outb(iobase + com_ier, 0);
1278 if ( inb(iobase + com_iir) & IIR_NOPEND ) {
1280 /* Ok. we're familia this gang */
1281 dev->id_flags |= COM_C_IIR_TXRDYBUG; /* Set IIR_TXRDYBUG */
1283 /* Unknow, Just omit this chip.. XXX*/
1287 /* OK. this is well-known guys */
1288 dev->id_flags &= ~COM_C_IIR_TXRDYBUG; /*Clear IIR_TXRDYBUG*/
1291 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1293 outb(iobase + com_cfcr, CFCR_8BITS);
1296 return (iobase == siocniobase ? IO_COMSIZE : result);
1301 * o the CFCR, IER and MCR in UART hold the values written to them
1302 * (the values happen to be all distinct - this is good for
1303 * avoiding false positive tests from bus echoes).
1304 * o an output interrupt is generated and its vector is correct.
1305 * o the interrupt goes away when the IIR in the UART is read.
1309 failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS;
1310 failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY;
1311 failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image;
1313 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS;
1314 failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
1315 failures[2] = inb(iobase + com_mcr) - mcr_image;
1317 DELAY(10000); /* Some internal modems need this time */
1318 irqmap[1] = isa_irq_pending();
1320 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1322 if (iod.if_type == COM_IF_RSA98III) {
1323 inb(rsabase + rsa_srr);
1326 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
1328 DELAY(1000); /* XXX */
1329 irqmap[2] = isa_irq_pending();
1331 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1333 if (iod.if_type == COM_IF_RSA98III) {
1334 inb(rsabase + rsa_srr);
1337 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1341 * Turn off all device interrupts and check that they go off properly.
1342 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1343 * the OUT2 output of the UART to
1344 * the ICU input. Closing the gate would give a floating ICU input
1345 * (unless there is another device driving it) and spurious interrupts.
1346 * (On the system that this was first tested on, the input floats high
1347 * and gives a (masked) interrupt as soon as the gate is closed.)
1350 outb(iobase + (com_ier << port_shift), 0);
1351 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1352 failures[7] = inb(iobase + (com_ier << port_shift));
1353 if (iod.if_type == COM_IF_RSA98III) {
1354 outb(rsabase + rsa_ier, 0x00);
1357 outb(iobase + com_ier, 0);
1358 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1359 failures[7] = inb(iobase + com_ier);
1361 DELAY(1000); /* XXX */
1362 irqmap[3] = isa_irq_pending();
1364 failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1366 if (iod.if_type == COM_IF_RSA98III) {
1367 inb(rsabase + rsa_srr);
1368 outb(rsabase + rsa_frr, 0x00);
1371 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1376 irqs = irqmap[1] & ~irqmap[0];
1377 if (idev->id_irq != 0 && (idev->id_irq & irqs) == 0)
1379 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
1380 dev->id_unit, ffs(idev->id_irq) - 1, irqs);
1382 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1383 dev->id_unit, irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1386 result = if_16550a_type[iod.if_type & 0x0f].io_size;
1388 result = IO_COMSIZE;
1390 for (fn = 0; fn < sizeof failures; ++fn)
1393 outb(iobase + (com_mcr << port_shift), 0);
1395 outb(iobase + com_mcr, 0);
1399 printf("sio%d: probe failed test(s):",
1401 for (fn = 0; fn < sizeof failures; ++fn)
1408 return (iobase == siocniobase ? IO_COMSIZE : result);
1413 espattach(isdp, com, esp_port)
1414 struct isa_device *isdp;
1422 * Check the ESP-specific I/O port to see if we're an ESP
1423 * card. If not, return failure immediately.
1425 if ((inb(esp_port) & 0xf3) == 0) {
1426 printf(" port 0x%x is not an ESP board?\n", esp_port);
1431 * We've got something that claims to be a Hayes ESP card.
1435 /* Get the dip-switch configuration */
1437 outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1438 dips = inb(esp_port + ESP98_STATUS1);
1440 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1441 dips = inb(esp_port + ESP_STATUS1);
1445 * Bits 0,1 of dips say which COM port we are.
1448 if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03])
1450 if (com->iobase == likely_com_ports[dips & 0x03])
1454 printf(" esp_port has com %d\n", dips & 0x03);
1459 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1462 outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1463 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
1464 val = inb(esp_port + ESP98_STATUS2);
1466 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1467 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1468 val = inb(esp_port + ESP_STATUS2);
1470 if ((val & 0x70) < 0x20) {
1471 printf("-old (%o)", val & 0x70);
1476 * Check for ability to emulate 16550: bit 7 == 1
1478 if ((dips & 0x80) == 0) {
1484 * Okay, we seem to be a Hayes ESP card. Whee.
1487 com->esp_port = esp_port;
1490 #endif /* COM_ESP */
1494 struct isa_device *isdp;
1509 isdp->id_ointr = siointr;
1510 isdp->id_ri_flags |= RI_FAST;
1512 if (((isdp->id_flags >> 24) & 0xff) == COM_IF_RSA98III)
1513 iobase = isdp->id_iobase + 8;
1516 iobase = isdp->id_iobase;
1517 unit = isdp->id_unit;
1519 com = malloc(sizeof *com, M_TTYS, M_NOWAIT);
1521 ibufsize = RS_IBUFSIZE;
1522 if (((isdp->id_flags >> 24) & 0xff) == COM_IF_RSA98III)
1524 com = malloc((sizeof *com) + ibufsize * 6, M_TTYS, M_NOWAIT);
1530 * sioprobe() has initialized the device registers as follows:
1531 * o cfcr = CFCR_8BITS.
1532 * It is most important that CFCR_DLAB is off, so that the
1533 * data port is not hidden when we enable interrupts.
1535 * Interrupts are only enabled when the line is open.
1536 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1537 * interrupt control register or the config specifies no irq.
1538 * Keeping MCR_DTR and MCR_RTS off might stop the external
1539 * device from sending before we are ready.
1541 bzero(com, sizeof *com);
1543 com->CE_INPUT_OFFSET = ibufsize;
1544 com->ibuf1 = (u_char *)com + (sizeof *com);
1545 com->ibuf2 = com->ibuf1 + (ibufsize * 2);
1546 com->obuf1 = com->ibuf2 + (ibufsize * 2);
1547 com->obuf2 = com->obuf1 + ibufsize;
1548 bzero(com->ibuf1, ibufsize * 6);
1551 com->cfcr_image = CFCR_8BITS;
1552 com->dtr_wait = 3 * hz;
1553 com->loses_outints = COM_LOSESOUTINTS(isdp) != 0;
1554 com->no_irq = isdp->id_irq == 0;
1555 com->tx_fifo_size = 1;
1556 com->iptr = com->ibuf = com->ibuf1;
1558 com->ibufend = com->ibuf1 + RS_IBUFSIZE;
1559 com->ihighwater = com->ibuf1 + RS_IHIGHWATER;
1561 com->ibufend = com->ibuf1 + com->CE_INPUT_OFFSET;
1562 com->ihighwater = com->ibuf1 + (3 * com->CE_INPUT_OFFSET / 4);
1564 com->obufs[0].l_head = com->obuf1;
1565 com->obufs[1].l_head = com->obuf2;
1567 com->iobase = iobase;
1569 if (pc98_set_ioport(com, isdp->id_flags) == -1) {
1570 com->pc98_if_type = (isdp->id_flags >> 24) & 0xff;
1571 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1572 com->data_port = iobase + (com_data << port_shift);
1573 com->int_id_port = iobase + (com_iir << port_shift);
1574 com->modem_ctl_port = iobase + (com_mcr << port_shift);
1575 com->mcr_image = inb(com->modem_ctl_port);
1576 com->line_status_port = iobase + (com_lsr << port_shift);
1577 com->modem_status_port = iobase + (com_msr << port_shift);
1578 com->intr_ctl_port = iobase + (com_ier << port_shift);
1580 #else /* not PC98 */
1581 com->data_port = iobase + com_data;
1582 com->int_id_port = iobase + com_iir;
1583 com->modem_ctl_port = iobase + com_mcr;
1584 com->mcr_image = inb(com->modem_ctl_port);
1585 com->line_status_port = iobase + com_lsr;
1586 com->modem_status_port = iobase + com_msr;
1587 com->intr_ctl_port = iobase + com_ier;
1591 * We don't use all the flags from <sys/ttydefaults.h> since they
1592 * are only relevant for logins. It's important to have echo off
1593 * initially so that the line doesn't start blathering before the
1594 * echo flag can be turned off.
1596 com->it_in.c_iflag = 0;
1597 com->it_in.c_oflag = 0;
1598 com->it_in.c_cflag = TTYDEF_CFLAG;
1599 com->it_in.c_lflag = 0;
1600 if (unit == comconsole) {
1602 if (IS_8251(com->pc98_if_type))
1605 com->it_in.c_iflag = TTYDEF_IFLAG;
1606 com->it_in.c_oflag = TTYDEF_OFLAG;
1607 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL;
1608 com->it_in.c_lflag = TTYDEF_LFLAG;
1609 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL;
1610 com->lt_out.c_ispeed = com->lt_out.c_ospeed =
1611 com->lt_in.c_ispeed = com->lt_in.c_ospeed =
1612 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate;
1614 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED;
1615 termioschars(&com->it_in);
1616 com->it_out = com->it_in;
1618 /* attempt to determine UART type */
1619 printf("sio%d: type", unit);
1623 #ifdef COM_MULTIPORT
1624 if (!COM_ISMULTIPORT(isdp) && !COM_IIR_TXRDYBUG(isdp))
1626 if (!COM_IIR_TXRDYBUG(isdp))
1633 scr = inb(iobase + com_scr);
1634 outb(iobase + com_scr, 0xa5);
1635 scr1 = inb(iobase + com_scr);
1636 outb(iobase + com_scr, 0x5a);
1637 scr2 = inb(iobase + com_scr);
1638 outb(iobase + com_scr, scr);
1639 if (scr1 != 0xa5 || scr2 != 0x5a) {
1641 goto determined_type;
1646 if (IS_8251(com->pc98_if_type)) {
1647 com_int_TxRx_disable( com );
1648 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate );
1649 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1650 com_send_break_off( com );
1651 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1653 outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH);
1655 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1659 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1670 if (COM_NOFIFO(isdp)) {
1671 printf(" 16550A fifo disabled");
1673 com->hasfifo = TRUE;
1675 com->tx_fifo_size = 0; /* XXX flag conflicts. */
1678 if (COM_ST16650A(isdp)) {
1680 com->tx_fifo_size = 32;
1681 printf(" ST16650A");
1683 com->tx_fifo_size = COM_FIFOSIZE(isdp);
1689 if (com->pc98_if_type == COM_IF_RSA98III) {
1690 com->tx_fifo_size = 2048;
1691 com->rsabase = isdp->id_iobase;
1692 outb(com->rsabase + rsa_ier, 0x00);
1693 outb(com->rsabase + rsa_frr, 0x00);
1699 if (com->pc98_if_type == COM_IF_ESP98)
1701 for (espp = likely_esp_ports; *espp != 0; espp++)
1702 if (espattach(isdp, com, *espp)) {
1703 com->tx_fifo_size = 1024;
1707 if (!com->st16650a) {
1708 if (!com->tx_fifo_size)
1709 com->tx_fifo_size = 16;
1711 printf(" lookalike with %d bytes FIFO",
1719 if (com->pc98_if_type == COM_IF_RSB3000) {
1720 /* Set RSB-2000/3000 Extended Buffer mode. */
1722 lcr = inb(iobase + (com_cfcr << port_shift));
1723 outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB);
1724 outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE);
1725 outb(iobase + (com_cfcr << port_shift), lcr);
1732 * Set 16550 compatibility mode.
1733 * We don't use the ESP_MODE_SCALE bit to increase the
1734 * fifo trigger levels because we can't handle large
1736 * XXX flow control should be set in comparam(), not here.
1739 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
1740 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1742 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1743 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1746 /* Set RTS/CTS flow control. */
1748 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
1749 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
1750 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
1752 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1753 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1754 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1757 /* Set flow-control levels. */
1759 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
1760 outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
1761 outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
1762 outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
1763 outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
1765 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1766 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1767 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1768 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1769 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1773 /* Set UART clock prescaler. */
1774 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
1775 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
1778 #endif /* COM_ESP */
1780 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1781 outb(iobase + (com_fifo << port_shift), 0);
1783 outb(iobase + com_fifo, 0);
1787 #ifdef COM_MULTIPORT
1788 if (COM_ISMULTIPORT(isdp)) {
1789 com->multiport = TRUE;
1790 printf(" (multiport");
1791 if (unit == COM_MPMASTER(isdp))
1794 com->no_irq = find_isadev(isa_devtab_tty, &siodriver,
1795 COM_MPMASTER(isdp))->id_irq == 0;
1797 #endif /* COM_MULTIPORT */
1801 if (unit == comconsole)
1802 printf(", console");
1803 if ( COM_IIR_TXRDYBUG(isdp) )
1804 printf(" with a bogus IIR_TXRDY register");
1808 com_addr(unit) = com;
1811 if (!sio_registered) {
1812 dev = makedev(CDEV_MAJOR, 0);
1813 cdevsw_add(&dev, &sio_cdevsw, NULL);
1814 register_swi(SWI_TTY, siopoll);
1815 sio_registered = TRUE;
1818 com->devfs_token_ttyd = devfs_add_devswf(&sio_cdevsw,
1820 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1821 com->devfs_token_ttyi = devfs_add_devswf(&sio_cdevsw,
1822 unit | CONTROL_INIT_STATE, DV_CHR,
1823 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit);
1824 com->devfs_token_ttyl = devfs_add_devswf(&sio_cdevsw,
1825 unit | CONTROL_LOCK_STATE, DV_CHR,
1826 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit);
1827 com->devfs_token_cuaa = devfs_add_devswf(&sio_cdevsw,
1828 unit | CALLOUT_MASK, DV_CHR,
1829 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1830 com->devfs_token_cuai = devfs_add_devswf(&sio_cdevsw,
1831 unit | CALLOUT_MASK | CONTROL_INIT_STATE, DV_CHR,
1832 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1833 com->devfs_token_cual = devfs_add_devswf(&sio_cdevsw,
1834 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, DV_CHR,
1835 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1837 com->id_flags = isdp->id_flags; /* Heritate id_flags for later */
1842 sioopen(dev, flag, mode, p)
1860 unit = MINOR_TO_UNIT(mynor);
1861 if ((u_int) unit >= NSIOTOT || (com = com_addr(unit)) == NULL)
1865 if (mynor & CONTROL_MASK)
1868 tp = com->tp = sio_tty[unit] = ttymalloc(sio_tty[unit]);
1870 tp = com->tp = &sio_tty[unit];
1875 if (!IS_8251(com->pc98_if_type))
1876 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1879 * We jump to this label after all non-interrupted sleeps to pick
1880 * up any changes of the device state.
1883 while (com->state & CS_DTR_OFF) {
1884 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
1885 if (com_addr(unit) == NULL)
1887 if (error != 0 || com->gone)
1890 if (tp->t_state & TS_ISOPEN) {
1892 * The device is open, so everything has been initialized.
1895 if (mynor & CALLOUT_MASK) {
1896 if (!com->active_out) {
1901 if (com->active_out) {
1902 if (flag & O_NONBLOCK) {
1906 error = tsleep(&com->active_out,
1907 TTIPRI | PCATCH, "siobi", 0);
1908 if (com_addr(unit) == NULL)
1910 if (error != 0 || com->gone)
1915 if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) {
1921 * The device isn't open, so there are no conflicts.
1922 * Initialize it. Initialization is done twice in many
1923 * cases: to preempt sleeping callin opens if we are
1924 * callout, and to complete a callin open after DCD rises.
1926 tp->t_oproc = comstart;
1927 tp->t_param = comparam;
1929 tp->t_termios = mynor & CALLOUT_MASK
1930 ? com->it_out : com->it_in;
1932 tp->t_ififosize = 2 * RS_IBUFSIZE;
1934 tp->t_ififosize = 2 * com->CE_INPUT_OFFSET;
1936 tp->t_ispeedwat = (speed_t)-1;
1937 tp->t_ospeedwat = (speed_t)-1;
1939 if (!IS_8251(com->pc98_if_type))
1941 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
1942 com->poll = com->no_irq;
1943 com->poll_output = com->loses_outints;
1945 error = comparam(tp, &tp->t_termios);
1950 if (IS_8251(com->pc98_if_type)) {
1951 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
1952 pc98_msrint_start(dev);
1956 * XXX we should goto open_top if comparam() slept.
1958 iobase = com->iobase;
1961 * (Re)enable and drain fifos.
1963 * Certain SMC chips cause problems if the fifos
1964 * are enabled while input is ready. Turn off the
1965 * fifo if necessary to clear the input. We test
1966 * the input ready bit after enabling the fifos
1967 * since we've already enabled them in comparam()
1968 * and to handle races between enabling and fresh
1973 outb(iobase + (com_fifo << port_shift),
1974 FIFO_RCV_RST | FIFO_XMT_RST
1976 if (com->pc98_if_type == COM_IF_RSA98III)
1977 outb(com->rsabase + rsa_frr , 0x00);
1979 outb(iobase + com_fifo,
1980 FIFO_RCV_RST | FIFO_XMT_RST
1984 * XXX the delays are for superstitious
1985 * historical reasons. It must be less than
1986 * the character time at the maximum
1987 * supported speed (87 usec at 115200 bps
1988 * 8N1). Otherwise we might loop endlessly
1989 * if data is streaming in. We used to use
1990 * delays of 100. That usually worked
1991 * because DELAY(100) used to usually delay
1992 * for about 85 usec instead of 100.
1996 if (!(inb(com->line_status_port) & LSR_RXRDY))
1998 if (com->pc98_if_type == COM_IF_RSA98III
1999 ? !(inb(com->rsabase + rsa_srr) & 0x08)
2000 : !(inb(com->line_status_port) & LSR_RXRDY))
2004 outb(iobase + (com_fifo << port_shift), 0);
2006 outb(iobase + com_fifo, 0);
2009 (void) inb(com->data_port);
2015 if (IS_8251(com->pc98_if_type)) {
2016 com_tiocm_bis(com, TIOCM_LE);
2017 com->pc98_prev_modem_status = pc98_get_modem_status(com);
2018 com_int_Rx_enable(com);
2021 (void) inb(com->line_status_port);
2022 (void) inb(com->data_port);
2023 com->prev_modem_status = com->last_modem_status
2024 = inb(com->modem_status_port);
2025 if (COM_IIR_TXRDYBUG(com)) {
2026 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
2029 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
2030 | IER_ERLS | IER_EMSC);
2033 if (com->pc98_if_type == COM_IF_RSA98III) {
2034 outb(com->rsabase + rsa_ier, 0x1d);
2035 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC);
2043 * Handle initial DCD. Callout devices get a fake initial
2044 * DCD (trapdoor DCD). If we are callout, then any sleeping
2045 * callin opens get woken up and resume sleeping on "siobi"
2046 * instead of "siodcd".
2049 * XXX `mynor & CALLOUT_MASK' should be
2050 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where
2051 * TRAPDOOR_CARRIER is the default initial state for callout
2052 * devices and SOFT_CARRIER is like CLOCAL except it hides
2056 if ((IS_8251(com->pc98_if_type) &&
2057 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
2058 (!IS_8251(com->pc98_if_type) &&
2059 (com->prev_modem_status & MSR_DCD)) ||
2060 mynor & CALLOUT_MASK)
2062 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2064 (*linesw[tp->t_line].l_modem)(tp, 1);
2067 * Wait for DCD if necessary.
2069 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2070 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2072 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);
2073 if (com_addr(unit) == NULL)
2076 if (error != 0 || com->gone)
2080 error = (*linesw[tp->t_line].l_open)(dev, tp);
2081 disc_optim(tp, &tp->t_termios, com);
2082 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK)
2083 com->active_out = TRUE;
2087 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0)
2093 sioclose(dev, flag, mode, p)
2105 if (mynor & CONTROL_MASK)
2107 com = com_addr(MINOR_TO_UNIT(mynor));
2110 (*linesw[tp->t_line].l_close)(tp, flag);
2112 com->modem_checking = 0;
2114 disc_optim(tp, &tp->t_termios, com);
2115 siostop(tp, FREAD | FWRITE);
2121 printf("sio%d: gone\n", com->unit);
2123 com_addr(com->unit) = 0;
2124 bzero(tp,sizeof *tp);
2125 bzero(com,sizeof *com);
2145 iobase = com->iobase;
2148 com->poll_output = FALSE;
2149 com->do_timestamp = FALSE;
2150 com->do_dcd_timestamp = FALSE;
2152 if (IS_8251(com->pc98_if_type))
2153 com_send_break_off(com);
2155 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2156 outb(iobase + (com_cfcr << port_shift),
2157 com->cfcr_image &= ~CFCR_SBREAK);
2160 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2165 if (IS_8251(com->pc98_if_type))
2166 com_int_TxRx_disable(com);
2168 outb(iobase + (com_ier << port_shift), 0);
2169 if (com->pc98_if_type == COM_IF_RSA98III) {
2170 outb(com->rsabase + rsa_ier, 0x00);
2173 outb(iobase + com_ier, 0);
2177 if (IS_8251(com->pc98_if_type))
2178 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2180 tmp = com->prev_modem_status & MSR_DCD;
2182 if (tp->t_cflag & HUPCL
2184 * XXX we will miss any carrier drop between here and the
2185 * next open. Perhaps we should watch DCD even when the
2186 * port is closed; it is not sufficient to check it at
2187 * the next open because it might go up and down while
2188 * we're not watching.
2194 && !(com->prev_modem_status & MSR_DCD)
2196 && !(com->it_in.c_cflag & CLOCAL)
2197 || !(tp->t_state & TS_ISOPEN)) {
2199 if (IS_8251(com->pc98_if_type))
2200 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2203 (void)commctl(com, TIOCM_DTR, DMBIC);
2204 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
2205 timeout(siodtrwakeup, com, com->dtr_wait);
2206 com->state |= CS_DTR_OFF;
2211 if (IS_8251(com->pc98_if_type))
2212 com_tiocm_bic(com, TIOCM_LE );
2218 * Disable fifos so that they are off after controlled
2219 * reboots. Some BIOSes fail to detect 16550s when the
2220 * fifos are enabled.
2223 outb(iobase + (com_fifo << port_shift), 0);
2225 outb(iobase + com_fifo, 0);
2228 com->active_out = FALSE;
2229 wakeup(&com->active_out);
2230 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
2235 sioread(dev, uio, flag)
2245 if (mynor & CONTROL_MASK)
2247 unit = MINOR_TO_UNIT(mynor);
2248 if (com_addr(unit)->gone)
2250 tp = com_addr(unit)->tp;
2251 return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
2255 siowrite(dev, uio, flag)
2265 if (mynor & CONTROL_MASK)
2268 unit = MINOR_TO_UNIT(mynor);
2269 if (com_addr(unit)->gone)
2271 tp = com_addr(unit)->tp;
2273 * (XXX) We disallow virtual consoles if the physical console is
2274 * a serial port. This is in case there is a display attached that
2275 * is not the console. In that situation we don't need/want the X
2276 * server taking over the console.
2278 if (constty != NULL && unit == comconsole)
2280 return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
2290 com = (struct com_s *)chan;
2293 * Clear TS_BUSY if low-level output is complete.
2294 * spl locking is sufficient because siointr1() does not set CS_BUSY.
2295 * If siointr1() clears CS_BUSY after we look at it, then we'll get
2296 * called again. Reading the line status port outside of siointr1()
2297 * is safe because CS_BUSY is clear so there are no output interrupts
2301 if (com->state & CS_BUSY)
2302 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
2304 else if (IS_8251(com->pc98_if_type) &&
2305 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2306 == (STS8251_TxRDY | STS8251_TxEMP) ||
2307 (inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2308 == (LSR_TSRE | LSR_TXRDY)) {
2310 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2311 == (LSR_TSRE | LSR_TXRDY)) {
2313 com->tp->t_state &= ~TS_BUSY;
2315 com->extra_state &= ~CSE_BUSYCHECK;
2317 timeout(siobusycheck, com, hz / 100);
2327 com = (struct com_s *)chan;
2328 com->state &= ~CS_DTR_OFF;
2329 wakeup(&com->dtr_wait);
2336 #ifndef COM_MULTIPORT
2338 siointr1(com_addr(unit));
2340 #else /* COM_MULTIPORT */
2342 bool_t possibly_more_intrs;
2344 u_char rsa_buf_status;
2348 * Loop until there is no activity on any port. This is necessary
2349 * to get an interrupt edge more than to avoid another interrupt.
2350 * If the IRQ signal is just an OR of the IRQ signals from several
2351 * devices, then the edge from one may be lost because another is
2356 possibly_more_intrs = FALSE;
2357 for (unit = 0; unit < NSIOTOT; ++unit) {
2358 com = com_addr(unit);
2361 * would it work here, or be counter-productive?
2366 && IS_8251(com->pc98_if_type)){
2373 && com->pc98_if_type == COM_IF_RSA98III) {
2374 rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9;
2375 if ((rsa_buf_status & 0xc8)
2376 || !(rsa_buf_status & 0x01)) {
2379 != (inb(com->rsabase + rsa_srr) & 0xc9))
2380 possibly_more_intrs = TRUE;
2386 && (inb(com->int_id_port) & IIR_IMASK)
2389 possibly_more_intrs = TRUE;
2391 /* XXX COM_UNLOCK(); */
2393 } while (possibly_more_intrs);
2395 #endif /* COM_MULTIPORT */
2403 u_char modem_status;
2411 u_char rsa_buf_status = 0;
2412 int rsa_tx_fifo_size=0;
2416 int_ctl = inb(com->intr_ctl_port);
2417 int_ctl_new = int_ctl;
2419 while (!com->gone) {
2422 if (IS_8251(com->pc98_if_type)) {
2423 tmp = inb(com->sts_port);
2426 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
2427 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
2428 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
2429 if (tmp & STS8251_PE) line_status |= LSR_PE;
2430 if (tmp & STS8251_OE) line_status |= LSR_OE;
2431 if (tmp & STS8251_FE) line_status |= LSR_FE;
2432 if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
2435 line_status = inb(com->line_status_port);
2437 if (com->pc98_if_type == COM_IF_RSA98III)
2438 rsa_buf_status = inb(com->rsabase + rsa_srr);
2441 /* input event? (check first to help avoid overruns) */
2443 while (line_status & LSR_RCV_MASK) {
2445 while ((line_status & LSR_RCV_MASK)
2446 || (com->pc98_if_type == COM_IF_RSA98III
2447 && (rsa_buf_status & 0x08))) {
2449 /* break/unnattached error bits or real input? */
2451 if (IS_8251(com->pc98_if_type)) {
2452 recv_data = inb(com->data_port);
2454 pc98_i8251_or_cmd(com,CMD8251_ER);
2460 if (com->pc98_if_type == COM_IF_RSA98III) {
2461 if (!(rsa_buf_status & 0x08))
2464 recv_data = inb(com->data_port);
2468 if (!(line_status & LSR_RXRDY))
2471 recv_data = inb(com->data_port);
2475 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2477 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2478 * Otherwise, push the work to a higher level
2479 * (to handle PARMRK) if we're bypassing.
2480 * Otherwise, convert BI/FE and PE+INPCK to 0.
2482 * This makes bypassing work right in the
2483 * usual "raw" case (IGNBRK set, and IGNPAR
2486 * Note: BI together with FE/PE means just BI.
2488 if (line_status & LSR_BI) {
2489 #if defined(DDB) && defined(BREAK_TO_DEBUGGER)
2490 if (com->unit == comconsole) {
2496 || com->tp->t_iflag & IGNBRK)
2500 || com->tp->t_iflag & IGNPAR)
2503 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2504 && (line_status & (LSR_BI | LSR_FE)
2505 || com->tp->t_iflag & INPCK))
2509 if (com->hotchar != 0 && recv_data == com->hotchar)
2512 if (ioptr >= com->ibufend)
2513 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2515 if (com->do_timestamp)
2516 microtime(&com->timestamp);
2519 #if 0 /* for testing input latency vs efficiency */
2520 if (com->iptr - com->ibuf == 8)
2523 ioptr[0] = recv_data;
2525 ioptr[com->CE_INPUT_OFFSET] = line_status;
2527 ioptr[CE_INPUT_OFFSET] = line_status;
2529 com->iptr = ++ioptr;
2530 if (ioptr == com->ihighwater
2531 && com->state & CS_RTS_IFLOW)
2533 if (IS_8251(com->pc98_if_type))
2534 com_tiocm_bic(com, TIOCM_RTS);
2537 outb(com->modem_ctl_port,
2538 com->mcr_image &= ~MCR_RTS);
2539 if (line_status & LSR_OE)
2540 CE_RECORD(com, CE_OVERRUN);
2544 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2545 * jump from the top of the loop to here
2548 if (IS_8251(com->pc98_if_type))
2552 line_status = inb(com->line_status_port) & 0x7F;
2554 if (com->pc98_if_type == COM_IF_RSA98III)
2555 rsa_buf_status = inb(com->rsabase + rsa_srr);
2559 /* modem status change? (always check before doing output) */
2561 if (!IS_8251(com->pc98_if_type)) {
2563 modem_status = inb(com->modem_status_port);
2564 if (modem_status != com->last_modem_status) {
2565 if (com->do_dcd_timestamp
2566 && !(com->last_modem_status & MSR_DCD)
2567 && modem_status & MSR_DCD)
2568 microtime(&com->dcd_timestamp);
2571 * Schedule high level to handle DCD changes. Note
2572 * that we don't use the delta bits anywhere. Some
2573 * UARTs mess them up, and it's easy to remember the
2574 * previous bits and calculate the delta.
2576 com->last_modem_status = modem_status;
2577 if (!(com->state & CS_CHECKMSR)) {
2578 com_events += LOTS_OF_EVENTS;
2579 com->state |= CS_CHECKMSR;
2583 /* handle CTS change immediately for crisp flow ctl */
2584 if (com->state & CS_CTS_OFLOW) {
2585 if (modem_status & MSR_CTS)
2586 com->state |= CS_ODEVREADY;
2588 com->state &= ~CS_ODEVREADY;
2595 /* output queued and everything ready? */
2597 if (line_status & LSR_TXRDY
2598 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2600 if (((com->pc98_if_type == COM_IF_RSA98III)
2601 ? (rsa_buf_status & 0x02)
2602 : (line_status & LSR_TXRDY))
2603 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2605 ioptr = com->obufq.l_head;
2606 if (com->tx_fifo_size > 1) {
2609 ocount = com->obufq.l_tail - ioptr;
2611 if (com->pc98_if_type == COM_IF_RSA98III) {
2612 rsa_buf_status = inb(com->rsabase + rsa_srr);
2613 rsa_tx_fifo_size = 1024;
2614 if (!(rsa_buf_status & 0x01))
2615 rsa_tx_fifo_size = 2048;
2616 if (ocount > rsa_tx_fifo_size)
2617 ocount = rsa_tx_fifo_size;
2620 if (ocount > com->tx_fifo_size)
2621 ocount = com->tx_fifo_size;
2622 com->bytes_out += ocount;
2624 outb(com->data_port, *ioptr++);
2625 while (--ocount != 0);
2627 outb(com->data_port, *ioptr++);
2631 if (IS_8251(com->pc98_if_type))
2632 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2633 com_int_Tx_enable(com);
2635 com->obufq.l_head = ioptr;
2636 if (COM_IIR_TXRDYBUG(com)) {
2637 int_ctl_new = int_ctl | IER_ETXRDY;
2639 if (ioptr >= com->obufq.l_tail) {
2642 qp = com->obufq.l_next;
2643 qp->l_queued = FALSE;
2646 com->obufq.l_head = qp->l_head;
2647 com->obufq.l_tail = qp->l_tail;
2648 com->obufq.l_next = qp;
2650 /* output just completed */
2651 if ( COM_IIR_TXRDYBUG(com) ) {
2652 int_ctl_new = int_ctl & ~IER_ETXRDY;
2654 com->state &= ~CS_BUSY;
2656 if (IS_8251(com->pc98_if_type))
2657 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2658 com_int_Tx_disable(com);
2661 if (!(com->state & CS_ODONE)) {
2662 com_events += LOTS_OF_EVENTS;
2663 com->state |= CS_ODONE;
2664 setsofttty(); /* handle at high level ASAP */
2667 if ( COM_IIR_TXRDYBUG(com) && (int_ctl != int_ctl_new)) {
2668 if (com->pc98_if_type == COM_IF_RSA98III) {
2669 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2670 outb(com->intr_ctl_port, int_ctl_new);
2671 outb(com->rsabase + rsa_ier, 0x1d);
2673 outb(com->intr_ctl_port, int_ctl_new);
2677 else if (line_status & LSR_TXRDY) {
2678 if (IS_8251(com->pc98_if_type))
2679 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2680 com_int_Tx_disable(com);
2682 if (IS_8251(com->pc98_if_type))
2683 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
2688 #ifndef COM_MULTIPORT
2690 if (IS_8251(com->pc98_if_type))
2693 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2694 #endif /* COM_MULTIPORT */
2700 sioioctl(dev, cmd, data, flag, p)
2713 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2715 struct termios term;
2719 com = com_addr(MINOR_TO_UNIT(mynor));
2722 iobase = com->iobase;
2723 if (mynor & CONTROL_MASK) {
2726 switch (mynor & CONTROL_MASK) {
2727 case CONTROL_INIT_STATE:
2728 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
2730 case CONTROL_LOCK_STATE:
2731 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in;
2734 return (ENODEV); /* /dev/nodev */
2738 error = suser(p->p_ucred, &p->p_acflag);
2741 *ct = *(struct termios *)data;
2744 *(struct termios *)data = *ct;
2747 *(int *)data = TTYDISC;
2750 bzero(data, sizeof(struct winsize));
2757 #if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2758 term = tp->t_termios;
2760 error = ttsetcompat(tp, &cmd, data, &term);
2764 data = (caddr_t)&term;
2766 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) {
2768 struct termios *dt = (struct termios *)data;
2769 struct termios *lt = mynor & CALLOUT_MASK
2770 ? &com->lt_out : &com->lt_in;
2772 dt->c_iflag = (tp->t_iflag & lt->c_iflag)
2773 | (dt->c_iflag & ~lt->c_iflag);
2774 dt->c_oflag = (tp->t_oflag & lt->c_oflag)
2775 | (dt->c_oflag & ~lt->c_oflag);
2776 dt->c_cflag = (tp->t_cflag & lt->c_cflag)
2777 | (dt->c_cflag & ~lt->c_cflag);
2778 dt->c_lflag = (tp->t_lflag & lt->c_lflag)
2779 | (dt->c_lflag & ~lt->c_lflag);
2780 for (cc = 0; cc < NCCS; ++cc)
2781 if (lt->c_cc[cc] != 0)
2782 dt->c_cc[cc] = tp->t_cc[cc];
2783 if (lt->c_ispeed != 0)
2784 dt->c_ispeed = tp->t_ispeed;
2785 if (lt->c_ospeed != 0)
2786 dt->c_ospeed = tp->t_ospeed;
2788 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
2789 if (error != ENOIOCTL)
2792 error = ttioctl(tp, cmd, data, flag);
2793 disc_optim(tp, &tp->t_termios, com);
2794 if (error != ENOIOCTL) {
2799 if (IS_8251(com->pc98_if_type)) {
2802 com_send_break_on( com );
2805 com_send_break_off( com );
2808 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS );
2811 com_tiocm_bic(com, TIOCM_DTR);
2814 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2815 * changes get undone on the next call to comparam().
2818 com_tiocm_set( com, *(int *)data );
2821 com_tiocm_bis( com, *(int *)data );
2824 com_tiocm_bic( com, *(int *)data );
2827 *(int *)data = com_tiocm_get(com);
2830 /* must be root since the wait applies to following logins */
2831 error = suser(p->p_ucred, &p->p_acflag);
2836 com->dtr_wait = *(int *)data * hz / 100;
2839 *(int *)data = com->dtr_wait * 100 / hz;
2842 com->do_timestamp = TRUE;
2843 *(struct timeval *)data = com->timestamp;
2845 case TIOCDCDTIMESTAMP:
2846 com->do_dcd_timestamp = TRUE;
2847 *(struct timeval *)data = com->dcd_timestamp;
2855 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2860 outb(iobase + (com_cfcr << port_shift),
2861 com->cfcr_image |= CFCR_SBREAK);
2863 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2868 outb(iobase + (com_cfcr << port_shift),
2869 com->cfcr_image &= ~CFCR_SBREAK);
2871 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2875 (void)commctl(com, TIOCM_DTR, DMBIS);
2878 (void)commctl(com, TIOCM_DTR, DMBIC);
2881 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
2882 * changes get undone on the next call to comparam().
2885 (void)commctl(com, *(int *)data, DMSET);
2888 (void)commctl(com, *(int *)data, DMBIS);
2891 (void)commctl(com, *(int *)data, DMBIC);
2894 *(int *)data = commctl(com, 0, DMGET);
2897 /* must be root since the wait applies to following logins */
2898 error = suser(p->p_ucred, &p->p_acflag);
2903 com->dtr_wait = *(int *)data * hz / 100;
2906 *(int *)data = com->dtr_wait * 100 / hz;
2909 com->do_timestamp = TRUE;
2910 *(struct timeval *)data = com->timestamp;
2912 case TIOCDCDTIMESTAMP:
2913 com->do_dcd_timestamp = TRUE;
2914 *(struct timeval *)data = com->dcd_timestamp;
2932 if (com_events == 0)
2935 for (unit = 0; unit < NSIOTOT; ++unit) {
2945 com = com_addr(unit);
2949 if (tp == NULL || com->gone) {
2951 * Discard any events related to never-opened or
2952 * going-away devices.
2955 incc = com->iptr - com->ibuf;
2956 com->iptr = com->ibuf;
2957 if (com->state & CS_CHECKMSR) {
2958 incc += LOTS_OF_EVENTS;
2959 com->state &= ~CS_CHECKMSR;
2966 /* switch the role of the low-level input buffers */
2967 if (com->iptr == (ibuf = com->ibuf)) {
2968 buf = NULL; /* not used, but compiler can't tell */
2973 incc = com->iptr - buf;
2975 if (ibuf == com->ibuf1)
2980 com->ibufend = ibuf + RS_IBUFSIZE;
2981 com->ihighwater = ibuf + RS_IHIGHWATER;
2983 com->ibufend = ibuf + com->CE_INPUT_OFFSET;
2984 com->ihighwater = ibuf + (3 * com->CE_INPUT_OFFSET / 4);
2989 * There is now room for another low-level buffer full
2990 * of input, so enable RTS if it is now disabled and
2991 * there is room in the high-level buffer.
2994 if (IS_8251(com->pc98_if_type))
2995 tmp = com_tiocm_get(com) & TIOCM_RTS;
2997 tmp = com->mcr_image & MCR_RTS;
2999 if ((com->state & CS_RTS_IFLOW)
3003 && !(com->mcr_image & MCR_RTS)
3005 && !(tp->t_state & TS_TBLOCK))
3007 if (IS_8251(com->pc98_if_type))
3008 com_tiocm_bis(com, TIOCM_RTS);
3011 outb(com->modem_ctl_port,
3012 com->mcr_image |= MCR_RTS);
3017 if (com->state & CS_CHECKMSR) {
3018 u_char delta_modem_status;
3021 if (!IS_8251(com->pc98_if_type)) {
3024 delta_modem_status = com->last_modem_status
3025 ^ com->prev_modem_status;
3026 com->prev_modem_status = com->last_modem_status;
3027 com_events -= LOTS_OF_EVENTS;
3028 com->state &= ~CS_CHECKMSR;
3030 if (delta_modem_status & MSR_DCD)
3031 (*linesw[tp->t_line].l_modem)
3032 (tp, com->prev_modem_status & MSR_DCD);
3037 if (com->state & CS_ODONE) {
3039 com_events -= LOTS_OF_EVENTS;
3040 com->state &= ~CS_ODONE;
3042 if (!(com->state & CS_BUSY)
3043 && !(com->extra_state & CSE_BUSYCHECK)) {
3044 timeout(siobusycheck, com, hz / 100);
3045 com->extra_state |= CSE_BUSYCHECK;
3047 (*linesw[tp->t_line].l_start)(tp);
3049 if (incc <= 0 || !(tp->t_state & TS_ISOPEN) ||
3050 !(tp->t_cflag & CREAD))
3053 * Avoid the grotesquely inefficient lineswitch routine
3054 * (ttyinput) in "raw" mode. It usually takes about 450
3055 * instructions (that's without canonical processing or echo!).
3056 * slinput is reasonably fast (usually 40 instructions plus
3059 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
3060 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
3061 && (com->state & CS_RTS_IFLOW
3062 || tp->t_iflag & IXOFF)
3063 && !(tp->t_state & TS_TBLOCK))
3067 tp->t_rawcc += incc;
3068 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
3069 += b_to_q((char *)buf, incc, &tp->t_rawq);
3071 if (tp->t_state & TS_TTSTOP
3072 && (tp->t_iflag & IXANY
3073 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
3074 tp->t_state &= ~TS_TTSTOP;
3075 tp->t_lflag &= ~FLUSHO;
3084 line_status = (u_char) buf[CE_INPUT_OFFSET];
3086 line_status = (u_char) buf[com->CE_INPUT_OFFSET];
3088 recv_data = (u_char) *buf++;
3090 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
3091 if (line_status & LSR_BI)
3092 recv_data |= TTY_BI;
3093 if (line_status & LSR_FE)
3094 recv_data |= TTY_FE;
3095 if (line_status & LSR_OE)
3096 recv_data |= TTY_OE;
3097 if (line_status & LSR_PE)
3098 recv_data |= TTY_PE;
3100 (*linesw[tp->t_line].l_rint)(recv_data, tp);
3101 } while (--incc > 0);
3103 if (com_events == 0)
3106 if (com_events >= LOTS_OF_EVENTS)
3133 unit = DEV_TO_UNIT(tp->t_dev);
3134 com = com_addr(unit);
3135 iobase = com->iobase;
3136 if (IS_8251(com->pc98_if_type)) {
3137 divisor = pc98_ttspeedtab(com, t->c_ospeed);
3139 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3141 /* do historical conversions */
3142 if (t->c_ispeed == 0)
3143 t->c_ispeed = t->c_ospeed;
3145 /* check requested parameters */
3146 divisor = ttspeedtab(t->c_ospeed,
3147 if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
3150 /* do historical conversions */
3151 if (t->c_ispeed == 0)
3152 t->c_ispeed = t->c_ospeed;
3154 /* check requested parameters */
3155 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
3157 if (divisor < 0 || divisor > 0 && t->c_ispeed != t->c_ospeed)
3160 /* parameters are OK, convert them to the com struct and the device */
3162 unit = DEV_TO_UNIT(tp->t_dev);
3163 com = com_addr(unit);
3164 iobase = com->iobase;
3168 if (IS_8251(com->pc98_if_type)) {
3170 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3172 com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3176 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
3178 (void)commctl(com, TIOCM_DTR, DMBIS);
3184 if (!IS_8251(com->pc98_if_type)) {
3186 switch (cflag & CSIZE) {
3200 if (cflag & PARENB) {
3202 if (!(cflag & PARODD))
3208 if (com->hasfifo && divisor != 0) {
3210 * Use a fifo trigger level low enough so that the input
3211 * latency from the fifo is less than about 16 msec and
3212 * the total latency is less than about 30 msec. These
3213 * latencies are reasonable for humans. Serial comms
3214 * protocols shouldn't expect anything better since modem
3215 * latencies are larger.
3217 com->fifo_image = t->c_ospeed <= 4800
3218 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH;
3221 * The Hayes ESP card needs the fifo DMA mode bit set
3222 * in compatibility mode. If not, it will interrupt
3223 * for each character received.
3226 com->fifo_image |= FIFO_DMA_MODE;
3229 outb(iobase + (com_fifo << port_shift), com->fifo_image);
3231 outb(iobase + com_fifo, com->fifo_image);
3238 disable_intr(); /* very important while com_data is hidden */
3241 if (IS_8251(com->pc98_if_type))
3242 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3247 outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB);
3249 outb(iobase + com_cfcr, cfcr | CFCR_DLAB);
3252 * Only set the divisor registers if they would change,
3253 * since on some 16550 incompatibles (UMC8669F), setting
3254 * them while input is arriving them loses sync until
3255 * data stops arriving.
3257 dlbl = divisor & 0xFF;
3259 if (inb(iobase + (com_dlbl << port_shift)) != dlbl)
3260 outb(iobase + (com_dlbl << port_shift), dlbl);
3261 dlbh = (u_int) divisor >> 8;
3262 if (inb(iobase + (com_dlbh << port_shift)) != dlbh)
3263 outb(iobase + (com_dlbh << port_shift), dlbh);
3265 if (inb(iobase + com_dlbl) != dlbl)
3266 outb(iobase + com_dlbl, dlbl);
3267 dlbh = (u_int) divisor >> 8;
3268 if (inb(iobase + com_dlbh) != dlbh)
3269 outb(iobase + com_dlbh, dlbh);
3276 outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr);
3278 outb(iobase + com_cfcr, com->cfcr_image = cfcr);
3281 if (!(tp->t_state & TS_TTSTOP))
3282 com->state |= CS_TTGO;
3284 if (cflag & CRTS_IFLOW) {
3285 if (com->st16650a) {
3286 outb(iobase + com_cfcr, 0xbf);
3287 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40);
3289 com->state |= CS_RTS_IFLOW;
3291 * If CS_RTS_IFLOW just changed from off to on, the change
3292 * needs to be propagated to MCR_RTS. This isn't urgent,
3293 * so do it later by calling comstart() instead of repeating
3294 * a lot of code from comstart() here.
3296 } else if (com->state & CS_RTS_IFLOW) {
3297 com->state &= ~CS_RTS_IFLOW;
3299 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
3300 * on here, since comstart() won't do it later.
3303 if (IS_8251(com->pc98_if_type))
3304 com_tiocm_bis(com, TIOCM_RTS);
3307 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3308 if (com->st16650a) {
3309 outb(iobase + com_cfcr, 0xbf);
3310 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40);
3316 * Set up state to handle output flow control.
3317 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3318 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3320 com->state |= CS_ODEVREADY;
3321 com->state &= ~CS_CTS_OFLOW;
3323 if (com->pc98_if_type == COM_IF_RSA98III) {
3324 param = inb(com->rsabase + rsa_msr);
3325 outb(com->rsabase + rsa_msr, param & 0x14);
3328 if (cflag & CCTS_OFLOW) {
3329 com->state |= CS_CTS_OFLOW;
3331 if (IS_8251(com->pc98_if_type)) {
3332 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3333 com->state &= ~CS_ODEVREADY;
3337 if (com->pc98_if_type == COM_IF_RSA98III) {
3338 /* Set automatic flow control mode */
3339 outb(com->rsabase + rsa_msr, param | 0x08);
3342 if (!(com->last_modem_status & MSR_CTS))
3343 com->state &= ~CS_ODEVREADY;
3344 if (com->st16650a) {
3345 outb(iobase + com_cfcr, 0xbf);
3346 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80);
3352 if (com->st16650a) {
3353 outb(iobase + com_cfcr, 0xbf);
3354 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80);
3360 outb(iobase + (com_cfcr << port_shift), com->cfcr_image);
3362 outb(iobase + com_cfcr, com->cfcr_image);
3366 /* XXX shouldn't call functions while intrs are disabled. */
3367 disc_optim(tp, t, com);
3369 * Recover from fiddling with CS_TTGO. We used to call siointr1()
3370 * unconditionally, but that defeated the careful discarding of
3371 * stale input in sioopen().
3373 if (com->state >= (CS_BUSY | CS_TTGO))
3393 unit = DEV_TO_UNIT(tp->t_dev);
3394 com = com_addr(unit);
3397 if (tp->t_state & TS_TTSTOP)
3398 com->state &= ~CS_TTGO;
3400 com->state |= CS_TTGO;
3401 if (tp->t_state & TS_TBLOCK) {
3403 if (IS_8251(com->pc98_if_type))
3404 tmp = com_tiocm_get(com) & TIOCM_RTS;
3406 tmp = com->mcr_image & MCR_RTS;
3407 if (tmp && (com->state & CS_RTS_IFLOW))
3409 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3412 if (IS_8251(com->pc98_if_type))
3413 com_tiocm_bic(com, TIOCM_RTS);
3416 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3419 if (IS_8251(com->pc98_if_type))
3420 tmp = com_tiocm_get(com) & TIOCM_RTS;
3422 tmp = com->mcr_image & MCR_RTS;
3423 if (!(tmp) && com->iptr < com->ihighwater
3424 && com->state & CS_RTS_IFLOW)
3426 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3427 && com->state & CS_RTS_IFLOW)
3430 if (IS_8251(com->pc98_if_type))
3431 com_tiocm_bis(com, TIOCM_RTS);
3434 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3437 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3440 /* if(IS_8251(com->pc98_if_type))
3441 com_int_Tx_enable(com); */
3446 if (tp->t_outq.c_cc != 0) {
3450 if (!com->obufs[0].l_queued) {
3451 com->obufs[0].l_tail
3452 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3456 com->CE_INPUT_OFFSET);
3458 com->obufs[0].l_next = NULL;
3459 com->obufs[0].l_queued = TRUE;
3461 if (com->state & CS_BUSY) {
3462 qp = com->obufq.l_next;
3463 while ((next = qp->l_next) != NULL)
3465 qp->l_next = &com->obufs[0];
3467 com->obufq.l_head = com->obufs[0].l_head;
3468 com->obufq.l_tail = com->obufs[0].l_tail;
3469 com->obufq.l_next = &com->obufs[0];
3470 com->state |= CS_BUSY;
3474 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3475 com->obufs[1].l_tail
3476 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3480 com->CE_INPUT_OFFSET);
3482 com->obufs[1].l_next = NULL;
3483 com->obufs[1].l_queued = TRUE;
3485 if (com->state & CS_BUSY) {
3486 qp = com->obufq.l_next;
3487 while ((next = qp->l_next) != NULL)
3489 qp->l_next = &com->obufs[1];
3491 com->obufq.l_head = com->obufs[1].l_head;
3492 com->obufq.l_tail = com->obufs[1].l_tail;
3493 com->obufq.l_next = &com->obufs[1];
3494 com->state |= CS_BUSY;
3498 tp->t_state |= TS_BUSY;
3501 if (com->state >= (CS_BUSY | CS_TTGO))
3502 siointr1(com); /* fake interrupt to start output */
3505 /* if(IS_8251(com->pc98_if_type))
3506 com_int_Tx_enable(com); */
3523 com = com_addr(DEV_TO_UNIT(tp->t_dev));
3527 if (IS_8251(com->pc98_if_type))
3528 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3534 /* XXX avoid h/w bug. */
3538 outb(com->iobase + (com_fifo << port_shift),
3539 FIFO_XMT_RST | com->fifo_image);
3540 if (com->pc98_if_type == COM_IF_RSA98III)
3541 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3542 outb(com->iobase + (com_fifo << port_shift),
3543 FIFO_XMT_RST | com->fifo_image);
3545 outb(com->iobase + com_fifo,
3546 FIFO_XMT_RST | com->fifo_image);
3548 com->obufs[0].l_queued = FALSE;
3549 com->obufs[1].l_queued = FALSE;
3550 if (com->state & CS_ODONE)
3551 com_events -= LOTS_OF_EVENTS;
3552 com->state &= ~(CS_ODONE | CS_BUSY);
3553 com->tp->t_state &= ~TS_BUSY;
3558 /* XXX avoid h/w bug. */
3562 if (com->pc98_if_type == COM_IF_RSA98III) {
3563 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3564 inb(com->data_port);
3566 outb(com->iobase + (com_fifo << port_shift),
3567 FIFO_RCV_RST | com->fifo_image);
3569 outb(com->iobase + com_fifo,
3570 FIFO_RCV_RST | com->fifo_image);
3572 com_events -= (com->iptr - com->ibuf);
3573 com->iptr = com->ibuf;
3587 if (mynor & CONTROL_MASK)
3589 unit = MINOR_TO_UNIT(mynor);
3590 if ((u_int) unit >= NSIOTOT)
3592 return (&sio_tty[unit]);
3596 commctl(com, bits, how)
3605 bits = TIOCM_LE; /* XXX - always enabled while open */
3606 mcr = com->mcr_image;
3611 msr = com->prev_modem_status;
3619 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI
3620 * more volatile by reading the modem status a lot. Perhaps
3621 * we should latch both bits until the status is read here.
3623 if (msr & (MSR_RI | MSR_TERI))
3628 if (bits & TIOCM_DTR)
3630 if (bits & TIOCM_RTS)
3637 outb(com->modem_ctl_port,
3638 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE));
3641 outb(com->modem_ctl_port, com->mcr_image |= mcr);
3644 outb(com->modem_ctl_port, com->mcr_image &= ~mcr);
3659 * Set our timeout period to 1 second if no polled devices are open.
3660 * Otherwise set it to max(1/200, 1/hz).
3661 * Enable timeouts iff some device is open.
3663 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3666 for (unit = 0; unit < NSIOTOT; ++unit) {
3667 com = com_addr(unit);
3668 if (com != NULL && com->tp != NULL
3669 && com->tp->t_state & TS_ISOPEN && !com->gone) {
3671 if (com->poll || com->poll_output) {
3672 sio_timeout = hz > 200 ? hz / 200 : 1;
3678 sio_timeouts_until_log = hz / sio_timeout;
3679 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3682 /* Flush error messages, if any. */
3683 sio_timeouts_until_log = 1;
3684 comwakeup((void *)NULL);
3685 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3696 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
3699 * Recover from lost output interrupts.
3700 * Poll any lines that don't use interrupts.
3702 for (unit = 0; unit < NSIOTOT; ++unit) {
3703 com = com_addr(unit);
3704 if (com != NULL && !com->gone
3705 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
3713 * Check for and log errors, but not too often.
3715 if (--sio_timeouts_until_log > 0)
3717 sio_timeouts_until_log = hz / sio_timeout;
3718 for (unit = 0; unit < NSIOTOT; ++unit) {
3721 com = com_addr(unit);
3726 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
3731 delta = com->delta_error_counts[errnum];
3732 com->delta_error_counts[errnum] = 0;
3736 total = com->error_counts[errnum] += delta;
3737 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
3738 unit, delta, error_desc[errnum],
3739 delta == 1 ? "" : "s", total);
3745 /* commint is called when modem control line changes */
3749 register struct tty *tp;
3755 unit = MINOR_TO_UNIT(mynor);
3756 com = com_addr(unit);
3759 stat = com_tiocm_get(com);
3760 delta = com_tiocm_get_delta(com);
3762 if (com->state & CS_CTS_OFLOW) {
3763 if (stat & TIOCM_CTS)
3764 com->state |= CS_ODEVREADY;
3766 com->state &= ~CS_ODEVREADY;
3768 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) {
3769 if (stat & TIOCM_CAR )
3770 (void)(*linesw[tp->t_line].l_modem)(tp, 1);
3771 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
3772 /* negate DTR, RTS */
3773 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
3774 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
3775 /* disable IENABLE */
3776 com_int_TxRx_disable( com );
3783 disc_optim(tp, t, com)
3788 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
3789 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
3790 && (!(t->c_iflag & PARMRK)
3791 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
3792 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
3793 && linesw[tp->t_line].l_rint == ttyinput)
3794 tp->t_state |= TS_CAN_BYPASS_L_RINT;
3796 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
3797 com->hotchar = linesw[tp->t_line].l_hotchar;
3801 * Following are all routines needed for SIO to act as console
3803 #include <machine/cons.h>
3813 static speed_t siocngetspeed __P((Port_t, struct speedtab *));
3814 static void siocnclose __P((struct siocnstate *sp));
3815 static void siocnopen __P((struct siocnstate *sp));
3816 static void siocntxwait __P((void));
3819 * XXX: sciocnget() and sciocnputc() are not declared static, as they are
3820 * referred to from i386/i386/i386-gdbstub.c.
3822 static cn_probe_t siocnprobe;
3823 static cn_init_t siocninit;
3824 static cn_checkc_t siocncheckc;
3825 cn_getc_t siocngetc;
3826 cn_putc_t siocnputc;
3828 CONS_DRIVER(sio, siocnprobe, siocninit, siocngetc, siocncheckc, siocnputc);
3836 * Wait for any pending transmission to finish. Required to avoid
3837 * the UART lockup bug when the speed is changed, and for normal
3841 while ((inb(siocniobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3842 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3847 * Read the serial port specified and try to figure out what speed
3848 * it's currently running at. We're assuming the serial port has
3849 * been initialized and is basicly idle. This routine is only intended
3850 * to be run at system startup.
3852 * If the value read from the serial port doesn't make sense, return 0.
3856 siocngetspeed(iobase, table)
3858 struct speedtab *table;
3865 cfcr = inb(iobase + com_cfcr);
3866 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3868 dlbl = inb(iobase + com_dlbl);
3869 dlbh = inb(iobase + com_dlbh);
3871 outb(iobase + com_cfcr, cfcr);
3873 code = dlbh << 8 | dlbl;
3875 for ( ; table->sp_speed != -1; table++)
3876 if (table->sp_code == code)
3877 return (table->sp_speed);
3879 return 0; /* didn't match anything sane */
3884 struct siocnstate *sp;
3892 * Save all the device control registers except the fifo register
3893 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3894 * We can't save the fifo register since it is read-only.
3896 iobase = siocniobase;
3897 sp->ier = inb(iobase + com_ier);
3898 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3900 sp->cfcr = inb(iobase + com_cfcr);
3901 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3902 sp->dlbl = inb(iobase + com_dlbl);
3903 sp->dlbh = inb(iobase + com_dlbh);
3905 * Only set the divisor registers if they would change, since on
3906 * some 16550 incompatibles (Startech), setting them clears the
3907 * data input register. This also reduces the effects of the
3910 divisor = ttspeedtab(comdefaultrate, comspeedtab);
3911 dlbl = divisor & 0xFF;
3912 if (sp->dlbl != dlbl)
3913 outb(iobase + com_dlbl, dlbl);
3914 dlbh = (u_int) divisor >> 8;
3915 if (sp->dlbh != dlbh)
3916 outb(iobase + com_dlbh, dlbh);
3917 outb(iobase + com_cfcr, CFCR_8BITS);
3918 sp->mcr = inb(iobase + com_mcr);
3920 * We don't want interrupts, but must be careful not to "disable"
3921 * them by clearing the MCR_IENABLE bit, since that might cause
3922 * an interrupt by floating the IRQ line.
3924 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
3929 struct siocnstate *sp;
3934 * Restore the device control registers.
3937 iobase = siocniobase;
3938 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3939 if (sp->dlbl != inb(iobase + com_dlbl))
3940 outb(iobase + com_dlbl, sp->dlbl);
3941 if (sp->dlbh != inb(iobase + com_dlbh))
3942 outb(iobase + com_dlbh, sp->dlbh);
3943 outb(iobase + com_cfcr, sp->cfcr);
3945 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
3947 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
3948 outb(iobase + com_ier, sp->ier);
3957 struct isa_device *dvp;
3959 struct siocnstate sp;
3962 * Find our first enabled console, if any. If it is a high-level
3963 * console device, then initialize it and return successfully.
3964 * If it is a low-level console device, then initialize it and
3965 * return unsuccessfully. It must be initialized in both cases
3966 * for early use by console drivers and debuggers. Initializing
3967 * the hardware is not necessary in all cases, since the i/o
3968 * routines initialize it on the fly, but it is necessary if
3969 * input might arrive while the hardware is switched back to an
3970 * uninitialized state. We can't handle multiple console devices
3971 * yet because our low-level routines don't take a device arg.
3972 * We trust the user to set the console flags properly so that we
3973 * don't need to probe.
3975 cp->cn_pri = CN_DEAD;
3976 for (dvp = isa_devtab_tty; dvp->id_driver != NULL; dvp++)
3977 if (dvp->id_driver == &siodriver && dvp->id_enabled
3978 && COM_CONSOLE(dvp)) {
3979 siocniobase = dvp->id_iobase;
3981 if (boothowto & RB_SERIAL) {
3982 boot_speed = siocngetspeed(siocniobase,
3985 comdefaultrate = boot_speed;
3989 * Initialize the divisor latch. We can't rely on
3990 * siocnopen() to do this the first time, since it
3991 * avoids writing to the latch if the latch appears
3992 * to have the correct value. Also, if we didn't
3993 * just read the speed from the hardware, then we
3994 * need to set the speed in hardware so that
3995 * switching it later is null.
3997 cfcr = inb(siocniobase + com_cfcr);
3998 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
3999 outb(siocniobase + com_dlbl,
4000 COMBRD(comdefaultrate) & 0xff);
4001 outb(siocniobase + com_dlbh,
4002 (u_int) COMBRD(comdefaultrate) >> 8);
4003 outb(siocniobase + com_cfcr, cfcr);
4007 if (!COM_LLCONSOLE(dvp)) {
4008 cp->cn_dev = makedev(CDEV_MAJOR, dvp->id_unit);
4009 cp->cn_pri = COM_FORCECONSOLE(dvp)
4010 || boothowto & RB_SERIAL
4011 ? CN_REMOTE : CN_NORMAL;
4021 comconsole = DEV_TO_UNIT(cp->cn_dev);
4031 struct siocnstate sp;
4033 iobase = siocniobase;
4036 if (inb(iobase + com_lsr) & LSR_RXRDY)
4037 c = inb(iobase + com_data);
4053 struct siocnstate sp;
4055 iobase = siocniobase;
4058 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4060 c = inb(iobase + com_data);
4072 struct siocnstate sp;
4077 outb(siocniobase + com_data, c);
4084 * support PnP cards if we are using 'em
4089 static pnpid_t siopnp_ids[] = {
4090 { 0x5015f435, "MOT1550"},
4091 { 0x8113b04e, "Supra1381"},
4092 { 0x9012b04e, "Supra1290"},
4093 { 0x7121b04e, "SupraExpress 56i Sp"},
4094 { 0x11007256, "USR0011"},
4095 { 0x30207256, "USR2030"},
4096 { 0x31307256, "USR3031"},
4100 static char *siopnp_probe(u_long csn, u_long vend_id);
4101 static void siopnp_attach(u_long csn, u_long vend_id, char *name,
4102 struct isa_device *dev);
4103 static u_long nsiopnp = NSIO;
4105 static struct pnp_device siopnp = {
4112 DATA_SET (pnpdevice_set, siopnp);
4115 siopnp_probe(u_long csn, u_long vend_id)
4120 for(id = siopnp_ids; id->vend_id != 0; id++) {
4121 if (vend_id == id->vend_id) {
4129 read_pnp_parms(&d, 0);
4130 if (d.enable == 0 || d.flags & 1) {
4131 printf("CSN %lu is disabled.\n", csn);
4141 siopnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev)
4144 struct isa_device *dvp;
4146 if (dev->id_unit >= NSIOTOT)
4149 if (read_pnp_parms(&d, 0) == 0) {
4150 printf("failed to read pnp parms\n");
4154 write_pnp_parms(&d, 0);
4158 dev->id_iobase = d.port[0];
4159 dev->id_irq = (1 << d.irq[0]);
4160 dev->id_ointr = siointr;
4161 dev->id_ri_flags = RI_FAST;
4164 if (dev->id_driver == NULL) {
4165 dev->id_driver = &siodriver;
4166 dvp = find_isadev(isa_devtab_tty, &siodriver, 0);
4168 dev->id_id = dvp->id_id;
4171 if ((dev->id_alive = sioprobe(dev)) != 0)
4174 printf("sio%d: probe failed\n", dev->id_unit);
4180 * pc98 local function
4184 com_tiocm_set(struct com_s *com, int msr)
4188 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS;
4191 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) )
4192 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4193 tmp |= (CMD8251_TxEN|CMD8251_RxEN);
4194 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4195 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4196 pc98_i8251_clear_or_cmd( com, mask, tmp );
4201 com_tiocm_bis(struct com_s *com, int msr)
4207 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4208 tmp |= CMD8251_TxEN|CMD8251_RxEN;
4209 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4210 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4212 pc98_i8251_or_cmd( com, tmp );
4217 com_tiocm_bic(struct com_s *com, int msr)
4223 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
4224 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
4225 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
4227 pc98_i8251_clear_cmd( com, tmp );
4232 com_tiocm_get(struct com_s *com)
4234 return( com->pc98_prev_modem_status );
4238 com_tiocm_get_delta(struct com_s *com)
4242 tmp = com->pc98_modem_delta;
4243 com->pc98_modem_delta = 0;
4247 /* convert to TIOCM_?? ( ioctl.h ) */
4249 pc98_get_modem_status(struct com_s *com)
4254 stat = inb(com->sts_port);
4255 stat2 = inb(com->in_modem_port);
4256 msr = com->pc98_prev_modem_status
4257 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4258 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
4259 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
4260 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
4261 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
4262 #if COM_CARRIER_DETECT_EMULATE
4263 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
4271 pc98_check_msr(void* chan)
4275 register struct tty *tp;
4283 unit = MINOR_TO_UNIT(mynor);
4284 com = com_addr(unit);
4288 msr = pc98_get_modem_status(com);
4289 /* make change flag */
4290 delta = msr ^ com->pc98_prev_modem_status;
4291 if ( delta & TIOCM_CAR ) {
4292 if ( com->modem_car_chg_timer ) {
4293 if ( -- com->modem_car_chg_timer )
4296 if ( com->modem_car_chg_timer = ( msr & TIOCM_CAR ) ?
4297 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE )
4301 com->modem_car_chg_timer = 0;
4302 delta = ( msr ^ com->pc98_prev_modem_status ) &
4303 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
4304 com->pc98_prev_modem_status = msr;
4305 delta = ( com->pc98_modem_delta |= delta );
4307 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
4311 timeout(pc98_check_msr, (caddr_t)dev,
4312 PC98_CHECK_MODEM_INTERVAL);
4314 com->modem_checking = 0;
4319 pc98_msrint_start(dev_t dev)
4327 unit = MINOR_TO_UNIT(mynor);
4328 com = com_addr(unit);
4329 /* modem control line check routine envoke interval is 1/10 sec */
4330 if ( com->modem_checking == 0 ) {
4331 com->pc98_prev_modem_status = pc98_get_modem_status(com);
4332 com->pc98_modem_delta = 0;
4333 timeout(pc98_check_msr, (caddr_t)dev,
4334 PC98_CHECK_MODEM_INTERVAL);
4335 com->modem_checking = 1;
4341 pc98_disable_i8251_interrupt(struct com_s *com, int mod)
4343 /* disable interrupt */
4346 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4348 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4349 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
4354 pc98_enable_i8251_interrupt(struct com_s *com, int mod)
4359 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
4360 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
4365 pc98_check_i8251_interrupt(struct com_s *com)
4367 return ( com->intr_enable & 0x07 );
4371 pc98_i8251_clear_cmd(struct com_s *com, int x)
4376 tmp = com->pc98_prev_siocmd & ~(x);
4377 outb(com->cmd_port, tmp);
4378 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4383 pc98_i8251_or_cmd(struct com_s *com, int x)
4388 tmp = com->pc98_prev_siocmd | (x);
4389 outb(com->cmd_port, tmp);
4390 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4395 pc98_i8251_set_cmd(struct com_s *com, int x)
4401 outb(com->cmd_port, tmp);
4402 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4407 pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4411 tmp = com->pc98_prev_siocmd & ~(clr);
4413 outb(com->cmd_port, tmp);
4414 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4419 pc98_i8251_get_cmd(struct com_s *com)
4421 return com->pc98_prev_siocmd;
4425 pc98_i8251_get_mod(struct com_s *com)
4427 return com->pc98_prev_siomod;
4431 pc98_i8251_reset(struct com_s *com, int mode, int command)
4433 outb(com->cmd_port, 0); /* dummy */
4435 outb(com->cmd_port, 0); /* dummy */
4437 outb(com->cmd_port, 0); /* dummy */
4439 outb(com->cmd_port, CMD8251_RESET); /* internal reset */
4441 outb(com->cmd_port, mode ); /* mode register */
4442 com->pc98_prev_siomod = mode;
4444 pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4448 pc98_check_sysclock(void)
4450 /* get system clock from port */
4451 if ( pc98_machine_type & M_8M ) {
4452 /* 8 MHz system & H98 */
4461 com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4466 count = pc98_ttspeedtab( com, speed );
4467 if ( count < 0 ) return;
4469 previnterrupt = pc98_check_i8251_interrupt(com);
4470 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4472 switch ( cflag&CSIZE ) {
4474 cfcr = MOD8251_5BITS; break;
4476 cfcr = MOD8251_6BITS; break;
4478 cfcr = MOD8251_7BITS; break;
4480 cfcr = MOD8251_8BITS; break;
4482 if ( cflag&PARENB ) {
4484 cfcr |= MOD8251_PODD;
4486 cfcr |= MOD8251_PEVEN;
4488 cfcr |= MOD8251_PDISAB;
4491 cfcr |= MOD8251_STOP2;
4493 cfcr |= MOD8251_STOP1;
4495 if ( count & 0x10000 )
4496 cfcr |= MOD8251_CLKX1;
4498 cfcr |= MOD8251_CLKX16;
4500 if (epson_machine_id != 0x20) { /* XXX */
4502 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4505 /* set baud rate from ospeed */
4506 pc98_set_baud_rate( com, count );
4508 if ( cfcr != pc98_i8251_get_mod(com) )
4509 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4511 pc98_enable_i8251_interrupt( com, previnterrupt );
4515 pc98_ttspeedtab(struct com_s *com, int speed)
4517 int if_type, effect_sp, count = -1, mod;
4519 if_type = com->pc98_if_type & 0x0f;
4521 switch (com->pc98_if_type) {
4522 case COM_IF_INTERNAL:
4523 if (PC98SIO_baud_rate_port(if_type) != -1) {
4524 count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4526 count |= COM1_EXT_CLOCK;
4531 /* for *1CLK asynchronous! mode, TEFUTEFU */
4532 mod = (sysclock == 5) ? 2457600 : 1996800;
4533 effect_sp = ttspeedtab( speed, pc98speedtab );
4534 if ( effect_sp < 0 ) /* XXX */
4535 effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4536 if ( effect_sp <= 0 )
4538 if ( effect_sp == speed )
4540 if ( mod % effect_sp )
4542 count = mod / effect_sp;
4543 if ( count > 65535 )
4545 if ( effect_sp != speed )
4548 case COM_IF_PC9861K_1:
4549 case COM_IF_PC9861K_2:
4552 case COM_IF_IND_SS_1:
4553 case COM_IF_IND_SS_2:
4554 case COM_IF_PIO9032B_1:
4555 case COM_IF_PIO9032B_2:
4556 if ( speed == 0 ) return 0;
4557 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4559 case COM_IF_B98_01_1:
4560 case COM_IF_B98_01_2:
4561 if ( speed == 0 ) return 0;
4562 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4564 if (count == 0 || count == 1) {
4566 count |= 0x20000; /* x1 mode for 76800 and 153600 */
4576 pc98_set_baud_rate( struct com_s *com, int count )
4580 if_type = com->pc98_if_type & 0x0f;
4581 io = com->iobase & 0xff00;
4583 switch (com->pc98_if_type) {
4584 case COM_IF_INTERNAL:
4585 if (PC98SIO_baud_rate_port(if_type) != -1) {
4586 if (count & COM1_EXT_CLOCK) {
4587 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
4590 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
4595 printf( "[ Illegal count : %d ]", count );
4597 } else if ( count == 0 )
4606 outb( 0x75, count & 0xff );
4608 outb( 0x75, (count >> 8) & 0xff );
4611 case COM_IF_IND_SS_1:
4612 case COM_IF_IND_SS_2:
4613 outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
4614 outb(io | PC98SIO_baud_rate_port(if_type), 0);
4615 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
4616 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
4617 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
4619 case COM_IF_PIO9032B_1:
4620 case COM_IF_PIO9032B_2:
4621 outb(io | PC98SIO_baud_rate_port(if_type), count);
4623 case COM_IF_B98_01_1:
4624 case COM_IF_B98_01_2:
4625 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
4628 * Some old B98_01 board should be controlled
4629 * in different way, but this hasn't been tested yet.
4631 outb(io | PC98SIO_func_port(if_type),
4632 (count & 0x20000) ? 0xf0 : 0xf2);
4638 pc98_check_if_type(struct isa_device *dev, struct siodev *iod)
4640 int irr, io, if_type, tmp;
4641 static short irq_tab[2][8] = {
4642 { 3, 5, 6, 9, 10, 12, 13, -1},
4643 { 3, 10, 12, 13, 5, 6, 9, -1}
4646 iod->if_type = if_type = (dev->id_flags >> 24) & 0xff;
4647 if ((if_type < 0 || if_type > COM_IF_END1) &&
4648 (if_type < 0x10 || if_type > COM_IF_END2))
4652 io = dev->id_iobase & 0xff00;
4654 if (IS_8251(iod->if_type)) {
4655 if (PC98SIO_func_port(if_type) != -1) {
4656 outb(io | PC98SIO_func_port(if_type), 0xf2);
4657 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4658 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4659 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4662 iod->cmd = io | PC98SIO_cmd_port(if_type);
4663 iod->sts = io | PC98SIO_sts_port(if_type);
4664 iod->mod = io | PC98SIO_in_modem_port(if_type);
4665 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
4667 if (iod->if_type == COM_IF_INTERNAL) {
4670 /* XXX check new internal port. */
4673 for (tmp = 0; tmp < 100; tmp++) {
4674 if ((inb(0x138) & 1) == 0) {
4675 PC98SIO_baud_rate_port(if_type) = 0x13a;
4676 if_8251_type[if_type].name = " (internal fast)";
4677 if_8251_type[if_type].speedtab = pc98fast_speedtab;
4683 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4684 if ((dev->id_iobase & 0xff) == IO_COM2)
4685 iod->irq = irq_tab[0][tmp];
4687 iod->irq = irq_tab[1][tmp];
4690 irr = if_16550a_type[if_type].irr_read;
4691 #ifdef COM_MULTIPORT
4692 if (!COM_ISMULTIPORT(dev) || dev->id_unit == COM_MPMASTER(dev))
4695 tmp = inb(io | irr);
4696 if (dev->id_iobase & 0x01) /* XXX depend on RSB-384 */
4697 iod->irq = irq_tab[1][tmp >> 3];
4699 iod->irq = irq_tab[0][tmp & 0x07];
4702 if ( iod->irq == -1 ) return -1;
4707 pc98_set_ioport( struct com_s *com, int id_flags )
4711 if_type = (id_flags >> 24) & 0xff;
4712 if (IS_8251(if_type)) {
4713 pc98_check_sysclock();
4714 io = com->iobase & 0xff00;
4715 com->pc98_if_type = if_type;
4717 com->data_port = io | PC98SIO_data_port(if_type);
4718 com->cmd_port = io | PC98SIO_cmd_port(if_type);
4719 com->sts_port = io | PC98SIO_sts_port(if_type);
4720 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
4721 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
4727 #endif /* PC98 defined */