2 * i82365.h - Definitions for Intel 82365 PCIC
3 * PCMCIA Card Interface Controller
5 * originally by Barry Jaspan; hacked over by Keith Moore
6 * hacked to unrecognisability by Andrew McRae (andrew@mega.com.au)
8 * Updated 3/3/95 to include Cirrus Logic stuff.
9 *-------------------------------------------------------------------------
11 * Copyright (c) 2001 M. Warner Losh. All rights reserved.
12 * Copyright (c) 1995 Andrew McRae. All rights reserved.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. The name of the author may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #define PCIC_I82365 0 /* Intel i82365SL-A/B or clone */
40 #define PCIC_IBM 1 /* IBM clone */
41 #define PCIC_VLSI 2 /* VLSI chip */
42 #define PCIC_PD6722 3 /* Cirrus logic PD6722 */
43 #define PCIC_PD6710 4 /* Cirrus logic PD6710 */
44 #define PCIC_VG365 5 /* Vadem 365 */
45 #define PCIC_VG465 6 /* Vadem 465 */
46 #define PCIC_VG468 7 /* Vadem 468 */
47 #define PCIC_VG469 8 /* Vadem 469 */
48 #define PCIC_RF5C296 9 /* Ricoh RF5C296 */
49 #define PCIC_RF5C396 10 /* Ricoh RF5C396 */
50 #define PCIC_IBM_KING 11 /* IBM KING PCMCIA Controller */
51 #define PCIC_I82365SL_DF 12 /* Intel i82365sl-DF step */
52 #define PCIC_PD6729 13 /* Cirrus Logic PD6729 */
53 #define PCIC_PD673X 14 /* Cirrus Logic PD673x */
56 * Address of the controllers. Each controller can manage
57 * two PCMCIA slots. Up to 8 slots are supported in total.
58 * The PCIC controller is accessed via an index port and a
59 * data port. The index port has the 8 bit address of the
60 * register accessed via the data port. How I long for
61 * real memory mapped I/O!
62 * The top two bits of the index address are used to
63 * identify the port number, and the lower 6 bits
64 * select one of the 64 possible data registers.
66 #define PCIC_INDEX 0 /* Index register */
67 #define PCIC_DATA 1 /* Data register */
68 #define PCIC_NPORT 2 /* Number of ports */
69 #define PCIC_PORT_0 0x3e0 /* index reg, chips 0 and 1 */
72 * Register index addresses.
74 #define PCIC_ID_REV 0x00 /* Identification and Revision */
75 #define PCIC_STATUS 0x01 /* Interface Status */
76 #define PCIC_POWER 0x02 /* Power and RESETDRV control */
77 #define PCIC_INT_GEN 0x03 /* Interrupt and General Control */
78 #define PCIC_STAT_CHG 0x04 /* Card Status Change */
79 #define PCIC_STAT_INT 0x05 /* Card Status Change Interrupt Config */
80 #define PCIC_ADDRWINE 0x06 /* Address Window Enable */
81 #define PCIC_IOCTL 0x07 /* I/O Control */
82 #define PCIC_IO0 0x08 /* I/O Address 0 */
83 #define PCIC_IO1 0x0c /* I/O Address 1 */
84 #define PCIC_MEMBASE 0x10 /* Base of memory window registers */
85 #define PCIC_CDGC 0x16 /* Card Detect and General Control */
86 #define PCIC_MISC1 0x16 /* PD67xx: Misc control register 1 per slot */
87 #define PCIC_GLO_CTRL 0x1e /* Global Control Register */
88 #define PCIC_MISC2 0x1e /* PD67xx: Misc control register 2 per chip */
89 #define PCIC_CLCHIP 0x1f /* PD67xx: Chip I/D */
90 #define PCIC_EXT_IND 0x2e /* PD67xx: Extended Index */
91 #define PCIC_EXTENDED 0x2f /* PD67xx: Extended register */
92 #define PCIC_CVSR 0x2f /* Vadem: Voltage select register */
93 #define PCIC_RICOH_MCR2 0x2f /* Ricoh: Mode Control Register 2 */
95 #define PCIC_VMISC 0x3a /* Vadem: Misc control register */
96 #define PCIC_RICOH_ID 0x3a /* Ricoh: ID register */
98 #define PCIC_TOPIC_FCR 0x3e /* Toshiba ToPIC: Function Control Register */
100 #define PCIC_TIME_SETUP0 0x3a
101 #define PCIC_TIME_CMD0 0x3b
102 #define PCIC_TIME_RECOV0 0x3c
103 #define PCIC_TIME_SETUP1 0x3d
104 #define PCIC_TIME_CMD1 0x3e
105 #define PCIC_TIME_RECOV1 0x3f
107 /* Yenta only registers */
108 #define PCIC_MEMORY_HIGH0 0x40 /* A31..A25 of mapping addres for */
109 #define PCIC_MEMORY_HIGH1 0x41 /* the memory windows. */
110 #define PCIC_MEMORY_HIGH2 0x42
111 #define PCIC_MEMORY_HIGH3 0x43
114 #define PCIC_SLOT_SIZE 0x40 /* Size of register set for one slot */
116 /* Now register bits, ordered by reg # */
118 /* For Identification and Revision (PCIC_ID_REV) */
119 #define PCIC_INTEL0 0x82 /* Intel 82365SL Rev. 0; Both Memory and I/O */
120 #define PCIC_INTEL1 0x83 /* Intel 82365SL Rev. 1; Both Memory and I/O */
121 #define PCIC_INTEL2 0x84 /* Intel 82365SL step D */
122 #define PCIC_VLSI82C146 0x84 /* VLSI 82C146 */
123 #define PCIC_IBM1 0x88 /* IBM PCIC clone; Both Memory and I/O */
124 #define PCIC_IBM2 0x89 /* IBM PCIC clone; Both Memory and I/O */
125 #define PCIC_IBM3 0x8a /* IBM KING PCIC clone; Both Memory and I/O */
127 /* For Interface Status register (PCIC_STATUS) */
128 #define PCIC_VPPV 0x80 /* Vpp_valid or reserved*/
129 #define PCIC_RICOH_5VCARD 0x80 /* 5V card detected */
130 #define PCIC_POW 0x40 /* PC Card power active */
131 #define PCIC_READY 0x20 /* Ready/~Busy */
132 #define PCIC_MWP 0x10 /* Memory Write Protect */
133 #define PCIC_CD 0x0C /* Both card detect bits */
134 #define PCIC_BVD 0x03 /* Both Battery Voltage Detect bits */
136 /* For the Power and RESETDRV register (PCIC_POWER) */
137 #define PCIC_OUTENA 0x80 /* Output Enable */
138 #define PCIC_DISRST 0x40 /* Disable RESETDRV */
139 #define PCIC_APSENA 0x20 /* Auto Pwer Switch Enable */
140 #define PCIC_PCPWRE 0x10 /* PC Card Power Enable */
141 #define PCIC_VCC 0x18 /* Vcc control bits */
142 #define PCIC_VCC_5V 0x10 /* 5 volts */
143 #define PCIC_VCC_ON 0x10 /* Turn on VCC on some chips. */
144 #define PCIC_VCC_3V 0x18 /* 3 volts */
145 #define PCIC_VCC_5V_KING 0x14 /* 5 volts for KING PCIC */
146 #define PCIC_VPP 0x03 /* Vpp control bits */
147 #define PCIC_VPP_5V 0x01 /* 5 volts */
148 #define PCIC_VPP_12V 0x02 /* 12 volts */
150 /* For the Interrupt and General Control register (PCIC_INT_GEN) */
151 #define PCIC_CARDRESET 0x40 /* Card reset 0 = Reset, 1 = Normal */
152 #define PCIC_CARDTYPE 0x20 /* Card Type 0 = memory, 1 = I/O */
153 #define PCIC_IOCARD 0x20
154 #define PCIC_MEMCARD 0x00
155 #define PCIC_INTR_ENA 0x10 /* PCI CSC Interrupt enable */
157 /* For the Card Status Change register (PCIC_STAT_CHG) */
158 #define PCIC_CDTCH 0x08 /* Card Detect Change */
159 #define PCIC_RDYCH 0x04 /* Ready Change */
160 #define PCIC_BATWRN 0x02 /* Battery Warning */
161 #define PCIC_BATDED 0x01 /* Battery Dead */
163 /* For the Card status change interrupt PCIC_STAT_INT */
164 #define PCIC_CSCSELECT 0xf0 /* CSCSELECT */
165 #define PCIC_SI_IRQ_SHIFT 4
166 #define PCIC_CDEN 0x8
167 #define PCIC_READYEN 0x4
168 #define PCIC_BATWARNEN 0x2
169 #define PCIC_BATDEADEN 0x1
172 * For the Address Window Enable Register (PCIC_ADDRWINE)
173 * The lower 5 bits contain enable bits for the memory
174 * windows (LSB = memory window 0).
176 #define PCIC_MEMCS16 0x20 /* ~MEMCS16 Decode A23-A12 */
177 #define PCIC_IO0_EN 0x40 /* I/O Window 0 Enable */
178 #define PCIC_IO1_EN 0x80 /* I/O Window 1 Enable */
181 * For the I/O Control Register (PCIC_IOCTL)
182 * The lower nybble is the flags for I/O window 0
183 * The upper nybble is the flags for I/O window 1
185 #define PCIC_IO_16BIT 0x01 /* I/O to this segment is 16 bit */
186 #define PCIC_IO_CS16 0x02 /* I/O cs16 source is the card */
187 #define PCIC_IO_0WS 0x04 /* zero wait states added on 8 bit cycles */
188 #define PCIC_IO_WS 0x08 /* Wait states added for 16 bit cycles */
191 * The memory window registers contain the start and end
192 * physical host address that the PCIC maps to the card,
193 * and an offset calculated from the card memory address.
194 * All values are shifted down 12 bits, so allocation is
195 * done in 4Kb blocks. Only 12 bits of each value is
196 * stored, limiting the range to the ISA address size of
197 * 24 bits. The upper 4 bits of the most significant byte
198 * within the values are used for various flags.
202 * base+0 : lower 8 bits of system memory start address
203 * base+1 : upper 4 bits of system memory start address + flags
204 * base+2 : lower 8 bits of system memory end address
205 * base+3 : upper 4 bits of system memory end address + flags
206 * base+4 : lower 8 bits of offset to card address
207 * base+5 : upper 4 bits of offset to card address + flags
209 * The following two bytes are reserved for other use.
211 #define PCIC_MEMSIZE 8
213 * Flags for system memory start address upper byte
215 #define PCIC_ZEROWS 0x40 /* Zero wait states */
216 #define PCIC_DATA16 0x80 /* Data width is 16 bits */
219 * Flags for system memory end address upper byte
221 #define PCIC_MW0 0x40 /* Wait state bit 0 */
222 #define PCIC_MW1 0x80 /* Wait state bit 1 */
225 * Flags for card offset upper byte
227 #define PCIC_REG 0x40 /* Attribute/Common select (why called Reg?) */
228 #define PCIC_WP 0x80 /* Write-protect this window */
230 /* For Card Detect and General Control register (PCIC_CDGC) */
231 #define PCIC_16_DL_INH 0x01 /* 16-bit memory delay inhibit */
232 #define PCIC_CNFG_RST_EN 0x02 /* configuration reset enable */
233 #define PCIC_GPI_EN 0x04 /* GPI Enable */
234 #define PCIC_GPI_TRANS 0x08 /* GPI Transition Control */
235 #define PCIC_CDRES_EN 0x10 /* card detect resume enable */
236 #define PCIC_SW_CD_INT 0x20 /* s/w card detect interrupt */
237 #define PCIC_VS1STAT 0x40 /* 0 VS1# low, 1 VS1# high */
238 #define PCIC_VS2STAT 0x80 /* 0 VS2# low, 1 VS2# high */
240 /* CL-PD67[12]x: For 3.3V cards, etc. (PCIC_MISC1) */
241 #define PCIC_MISC1_5V_DETECT 0x01 /* PD6710 only */
242 #define PCIC_MISC1_VCC_33 0x02 /* Set Vcc is 3.3V, else 5.0V */
243 #define PCIC_MISC1_PMINT 0x04 /* Pulse management intr */
244 #define PCIC_MISC1_PCINT 0x08 /* Pulse card interrupt */
245 #define PCIC_MISC1_SPEAKER 0x10 /* Enable speaker */
246 #define PCIC_MISC1_INPACK 0x80 /* INPACK throttles data */
248 /* i82365B and newer (!PD67xx) Global Control register (PCIC_GLO_CTRL) */
249 #define PCIC_PWR_DOWN 0x01 /* power down */
250 #define PCIC_LVL_MODE 0x02 /* level mode interrupt enable */
251 #define PCIC_WB_CSCINT 0x04 /* explicit write-back csc intr */
253 #define PCIC_IRQ0_LEVEL 0x08 /* irq 14 pulse mode enable */
254 #define PCIC_IRQ1_LEVEL 0x10
256 /* CL-PD67[12]x: For Misc. Control Register 2 (PCIC_MISC2) */
257 #define PCIC_LPDM_EN 0x02 /* Cirrus PD672x: low power dynamic mode */
259 /* CL-PD67[12]x: Chip info (PCIC_CLCHIP) */
260 #define PCIC_CLC_TOGGLE 0xc0 /* These bits toggle 1 -> 0 */
261 #define PCIC_CLC_DUAL 0x20 /* Single/dual socket version */
263 /* Cirrus Logic: Extended Registers (PCIC_EXT_IND) */
264 #define PCIC_EXT_DATA 0x0a /* External Data */
267 #define PCIC_VS1A 0x01
268 #define PCIC_VS2A 0x02
269 #define PCIC_VS1B 0x04
270 #define PCIC_VS2B 0x08
272 /* Cirrus Logic: Extended register Extension Control 1 */
273 #define PCIC_EXTCTRL1 0x03
274 #define PCIC_EC1_VCC_LOCK 0x1 /* Vcc Power locked to s/w change */
275 #define PCIC_EC1_AUTO_POWER_CLEAR 0x2 /* Vcc power cleared on eject? */
276 #define PCIC_EC1_LED_ENABLE 0x4 /* LED activity enable */
277 #define PCIC_EC1_CARD_IRQ_INV 0x8 /* Card IRQ level inverted for pci? */
278 #define PCIC_EC1_CSC_IRQ_INV 0x10 /* CSC IRQ level inverted for pci? */
279 #define PCIC_EC1_PULLUP 0x20 /* Dis pullup when 1. */
281 /* Vadem: Card Voltage Select register (PCIC_CVSR) */
282 #define PCIC_CVSR_VS 0x03 /* Voltage select */
283 #define PCIC_CVSR_VS_5 0x00 /* 5.0 V */
284 #define PCIC_CVSR_VS_33a 0x01 /* alt 3.3V */
285 #define PCIC_CVSR_VS_XX 0x02 /* X.XV when available */
286 #define PCIC_CVSR_VS_33 0x03 /* 3.3V */
288 /* Ricoh: Misc Control Register 2 (PCIC_RICOH_MCR2) */
289 #define PCIC_MCR2_VCC_33 0x01 /* 3.3V */
291 /* Vadem: misc register (PCIC_VMISC) */
292 #define PCIC_VADEMREV 0x40
294 /* Ricoh: ID register values (PCIC_RICOH_ID) */
295 #define PCIC_RID_296 0x32
296 #define PCIC_RID_396 0xb2
298 /* Toshiba ToPIC: Function Control Register */
299 #define PCIC_FCR_3V_EN 0x01 /* Enable 3V cards */
300 #define PCIC_FCR_VS_EN 0x02 /* Voltage Sense enable */
303 * Mask of allowable interrupts.
305 * For IBM-AT machines, irqs 3, 4, 5, 7, 9, 10, 11, 12, 14, 15 are
306 * allowed. Nearly all IBM-AT machines with pcic cards or bridges
307 * wire these interrupts (or a subset thereof) to the corresponding
308 * pins on the ISA bus. Some older laptops are reported to not route
309 * all the interrupt pins to the bus because the designers knew that
310 * some would conflict with builtin devices.
312 * For NEC PC98 machines, irq 3, 5, 6, 9, 10, 11, 12, 13 are allowed.
313 * These correspond to the C-BUS signals INT 0, 1, 2, 3, 41, 42, 5, 6
314 * respectively. This is with the desktop C-BUS addin card.
316 * Hiroshi TSUKADA-san writes in FreeBSD98-testers that cbus IRQ
317 * 6 is routed to the IRQ 7 pin of the pcic in pc98 cbus based
318 * cards. I do not know how pc98 laptop models are wired.
321 #define PCIC_INT_MASK_ALLOWED 0x3E68 /* PC98 */
323 #define PCIC_INT_MASK_ALLOWED 0xDEB8 /* AT */
326 #define PCIC_IO_WIN 2
327 #define PCIC_MEM_WIN 5
329 #define PCIC_CARD_SLOTS 4
330 #define PCIC_MAX_CARDS 2
331 #define PCIC_MAX_SLOTS (PCIC_MAX_CARDS * PCIC_CARD_SLOTS)