2 * Copyright (c) 2001 M. Warner Losh. All Rights Reserved.
3 * Copyright (c) 1997 Ted Faber All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice immediately at the beginning of the file, without modification,
11 * this list of conditions, and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Absolutely no warranty of function or purpose is made by the author
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/sysctl.h>
37 #include <sys/systm.h>
39 #if __FreeBSD_version < 500000
40 #include <pci/pcireg.h>
41 #include <pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
47 #include <pccard/pcic_pci.h>
48 #include <pccard/i82365.h>
49 #include <pccard/cardinfo.h>
50 #include <pccard/slot.h>
51 #include <pccard/pcicvar.h>
53 #include <dev/pccard/pccardvar.h>
56 #define PRVERB(x) do { \
57 if (bootverbose) { device_printf x; } \
60 static int pcic_pci_get_memory(device_t dev);
62 SYSCTL_DECL(_hw_pcic);
64 static int pcic_ignore_function_1 = 0;
65 TUNABLE_INT("hw.pcic.ignore_function_1", &pcic_ignore_function_1);
66 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_function_1, CTLFLAG_RD,
67 &pcic_ignore_function_1, 0,
68 "When set, driver ignores pci function 1 of the bridge. This option\n\
69 is obsolete and will be deleted before FreeBSD 4.8.");
72 * The following should be a hint, so we can do it on a per device
73 * instance, but this is convenient. Do not set this unless pci
74 * routing doesn't work. It is purposely vague and undocumented
75 * at the moment. Sadly, this seems to be needed way too often.
77 static int pcic_intr_path = (int)pcic_iw_pci;
78 TUNABLE_INT("hw.pcic.intr_path", &pcic_intr_path);
79 SYSCTL_INT(_hw_pcic, OID_AUTO, intr_path, CTLFLAG_RD, &pcic_intr_path, 0,
80 "Which path to send the interrupts over. Normally interrupts for\n\
81 cardbus bridges are routed over the PCI bus (2). However, some laptops\n\
82 will hang when using PCI interrupts due to bugs in this code. Those\n\
83 bugs can be worked around by forcings ISA interrupts (1).");
85 static int pcic_init_routing = 0;
86 TUNABLE_INT("hw.pcic.init_routing", &pcic_init_routing);
87 SYSCTL_INT(_hw_pcic, OID_AUTO, init_routing, CTLFLAG_RD,
88 &pcic_init_routing, 0,
89 "Force the interrupt routing to be initialized on those bridges where\n\
90 doing so will cause probelms. This is very rare and generally is not\n\
91 needed. The default of 0 is almost always appropriate. Only set to 1 if\n\
92 instructed to do so for debugging. Only TI bridges are affected by this\n\
93 option, and what the code does is of dubious value. This option is obsolete\n\
94 and will be deleted before FreeBSD 4.8.");
96 static int pcic_ignore_pci = 0;
97 TUNABLE_INT("hw.pcic.ignore_pci", &pcic_ignore_pci);
98 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_pci, CTLFLAG_RD,
100 "When set, driver ignores pci cardbus bridges it would otherwise claim.\n\
101 Generally speaking, this option is not needed for anything other than as an\n\
104 static int pcic_pd6729_intr_path = (int)pcic_iw_isa;
105 TUNABLE_INT("hw.pcic.pd6729_intr_path", &pcic_pd6729_intr_path);
106 SYSCTL_INT(_hw_pcic, OID_AUTO, pd6729_intr_path, CTLFLAG_RD,
107 &pcic_pd6729_intr_path, 0,
108 "Determine the interrupt path or method for Cirrus Logic PD6729 and\n\
109 similar I/O space based pcmcia bridge. Chips on a PCI expansion card need\n\
110 a value of 2, while chips installed in a laptop need a value of 1 (which is\n\
111 also the default). This is similar to hw.pcic.intr_path, but separate so\n\
112 that it can default to ISA when intr_path defaults to PCI.");
114 static void pcic_pci_cardbus_init(device_t);
115 static pcic_intr_way_t pcic_pci_gen_func;
116 static pcic_intr_way_t pcic_pci_gen_csc;
117 static pcic_intr_mapirq_t pcic_pci_gen_mapirq;
119 static pcic_intr_way_t pcic_pci_oz67xx_func;
120 static pcic_intr_way_t pcic_pci_oz67xx_csc;
121 static pcic_init_t pcic_pci_oz67xx_init;
123 static pcic_intr_way_t pcic_pci_oz68xx_func;
124 static pcic_intr_way_t pcic_pci_oz68xx_csc;
125 static pcic_init_t pcic_pci_oz68xx_init;
127 static pcic_intr_way_t pcic_pci_pd67xx_func;
128 static pcic_intr_way_t pcic_pci_pd67xx_csc;
129 static pcic_init_t pcic_pci_pd67xx_init;
131 static pcic_intr_way_t pcic_pci_pd68xx_func;
132 static pcic_intr_way_t pcic_pci_pd68xx_csc;
133 static pcic_init_t pcic_pci_pd68xx_init;
135 static pcic_intr_way_t pcic_pci_ricoh_func;
136 static pcic_intr_way_t pcic_pci_ricoh_csc;
137 static pcic_init_t pcic_pci_ricoh_init;
139 static pcic_intr_way_t pcic_pci_ti113x_func;
140 static pcic_intr_way_t pcic_pci_ti113x_csc;
141 static pcic_init_t pcic_pci_ti_init;
143 static pcic_intr_way_t pcic_pci_ti12xx_func;
144 static pcic_intr_way_t pcic_pci_ti12xx_csc;
146 static pcic_intr_way_t pcic_pci_topic_func;
147 static pcic_intr_way_t pcic_pci_topic_csc;
148 static pcic_init_t pcic_pci_topic_init;
150 static struct pcic_chip pcic_pci_oz67xx_chip = {
151 pcic_pci_oz67xx_func,
157 static struct pcic_chip pcic_pci_oz68xx_chip = {
158 pcic_pci_oz68xx_func,
164 static struct pcic_chip pcic_pci_pd67xx_chip = {
165 pcic_pci_pd67xx_func,
171 static struct pcic_chip pcic_pci_pd68xx_chip = {
172 pcic_pci_pd68xx_func,
178 static struct pcic_chip pcic_pci_ricoh_chip = {
185 static struct pcic_chip pcic_pci_ti113x_chip = {
186 pcic_pci_ti113x_func,
192 static struct pcic_chip pcic_pci_ti12xx_chip = {
193 pcic_pci_ti12xx_func,
199 static struct pcic_chip pcic_pci_topic_chip = {
206 static struct pcic_chip pcic_pci_generic_chip = {
210 pcic_pci_cardbus_init
213 /* Chipset specific flags */
214 #define TI_NO_MFUNC 0x10000
216 struct pcic_pci_table
222 struct pcic_chip *chip;
223 } pcic_pci_devs[] = {
224 { PCIC_ID_OMEGA_82C094, "Omega 82C094G",
225 PCIC_I82365, PCIC_DF_POWER, &pcic_pci_pd67xx_chip },
226 { PCIC_ID_CLPD6729, "Cirrus Logic PD6729/6730 PCI-PCMCIA Bridge",
227 PCIC_PD6729, PCIC_PD_POWER, &pcic_pci_pd67xx_chip },
228 { PCIC_ID_CLPD6832, "Cirrus Logic PD6832 PCI-CardBus Bridge",
229 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
230 { PCIC_ID_CLPD6833, "Cirrus Logic PD6833 PCI-CardBus Bridge",
231 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
232 { PCIC_ID_CLPD6834, "Cirrus Logic PD6834 PCI-CardBus Bridge",
233 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
234 { PCIC_ID_OZ6729, "O2micro OZ6729 PC-Card Bridge",
235 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
236 { PCIC_ID_OZ6730, "O2micro OZ6730 PC-Card Bridge",
237 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
238 { PCIC_ID_OZ6832, "O2micro 6832/6833 PCI-Cardbus Bridge",
239 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
240 { PCIC_ID_OZ6860, "O2micro 6836/6860 PCI-Cardbus Bridge",
241 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
242 { PCIC_ID_OZ6872, "O2micro 6812/6872 PCI-Cardbus Bridge",
243 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
244 { PCIC_ID_OZ6912, "O2micro 6912 PCI-Cardbus Bridge",
245 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
246 { PCIC_ID_OZ6922, "O2micro 6922 PCI-Cardbus Bridge",
247 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
248 { PCIC_ID_OZ6933, "O2micro 6933 PCI-Cardbus Bridge",
249 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
250 { PCIC_ID_RICOH_RL5C465, "Ricoh RL5C465 PCI-CardBus Bridge",
251 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
252 { PCIC_ID_RICOH_RL5C475, "Ricoh RL5C475 PCI-CardBus Bridge",
253 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
254 { PCIC_ID_RICOH_RL5C476, "Ricoh RL5C476 PCI-CardBus Bridge",
255 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
256 { PCIC_ID_RICOH_RL5C477, "Ricoh RL5C477 PCI-CardBus Bridge",
257 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
258 { PCIC_ID_RICOH_RL5C478, "Ricoh RL5C478 PCI-CardBus Bridge",
259 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
260 { PCIC_ID_TI1031, "TI PCI-1031 PCI-PCMCIA Bridge",
261 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
262 { PCIC_ID_TI1130, "TI PCI-1130 PCI-CardBus Bridge",
263 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
264 { PCIC_ID_TI1131, "TI PCI-1131 PCI-CardBus Bridge",
265 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
266 { PCIC_ID_TI1210, "TI PCI-1210 PCI-CardBus Bridge",
267 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
268 { PCIC_ID_TI1211, "TI PCI-1211 PCI-CardBus Bridge",
269 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
270 { PCIC_ID_TI1220, "TI PCI-1220 PCI-CardBus Bridge",
271 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
272 { PCIC_ID_TI1221, "TI PCI-1221 PCI-CardBus Bridge",
273 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
274 { PCIC_ID_TI1225, "TI PCI-1225 PCI-CardBus Bridge",
275 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
276 { PCIC_ID_TI1250, "TI PCI-1250 PCI-CardBus Bridge",
277 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
278 &pcic_pci_ti12xx_chip },
279 { PCIC_ID_TI1251, "TI PCI-1251 PCI-CardBus Bridge",
280 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
281 &pcic_pci_ti12xx_chip },
282 { PCIC_ID_TI1251B, "TI PCI-1251B PCI-CardBus Bridge",
283 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
284 &pcic_pci_ti12xx_chip },
285 { PCIC_ID_TI1260, "TI PCI-1260 PCI-CardBus Bridge",
286 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
287 { PCIC_ID_TI1260B, "TI PCI-1260B PCI-CardBus Bridge",
288 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
289 { PCIC_ID_TI1410, "TI PCI-1410 PCI-CardBus Bridge",
290 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
291 { PCIC_ID_TI1420, "TI PCI-1420 PCI-CardBus Bridge",
292 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
293 { PCIC_ID_TI1421, "TI PCI-1421 PCI-CardBus Bridge",
294 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
295 { PCIC_ID_TI1450, "TI PCI-1450 PCI-CardBus Bridge",
296 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER | TI_NO_MFUNC,
297 &pcic_pci_ti12xx_chip },
298 { PCIC_ID_TI1451, "TI PCI-1451 PCI-CardBus Bridge",
299 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
300 { PCIC_ID_TI1510, "TI PCI-1510 PCI-CardBus Bridge",
301 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
302 { PCIC_ID_TI1520, "TI PCI-1520 PCI-CardBus Bridge",
303 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
304 { PCIC_ID_TI4410, "TI PCI-4410 PCI-CardBus Bridge",
305 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
306 { PCIC_ID_TI4450, "TI PCI-4450 PCI-CardBus Bridge",
307 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
308 { PCIC_ID_TI4451, "TI PCI-4451 PCI-CardBus Bridge",
309 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
310 { PCIC_ID_TI4510, "TI PCI-4510 PCI-CardBus Bridge",
311 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
312 { PCIC_ID_TOPIC95, "Toshiba ToPIC95 PCI-CardBus Bridge",
313 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
314 { PCIC_ID_TOPIC95B, "Toshiba ToPIC95B PCI-CardBus Bridge",
315 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
316 { PCIC_ID_TOPIC97, "Toshiba ToPIC97 PCI-CardBus Bridge",
317 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
318 { PCIC_ID_TOPIC100, "Toshiba ToPIC100 PCI-CardBus Bridge",
319 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
320 { 0, NULL, 0, 0, NULL }
324 * Read a register from the PCIC.
327 pcic_pci_getb2(struct pcic_slot *sp, int reg)
329 return (bus_space_read_1(sp->bst, sp->bsh, sp->offset + reg));
333 * Write a register on the PCIC
336 pcic_pci_putb2(struct pcic_slot *sp, int reg, unsigned char val)
338 bus_space_write_1(sp->bst, sp->bsh, sp->offset + reg, val);
342 * lookup inside the table
344 static struct pcic_pci_table *
345 pcic_pci_lookup(u_int32_t devid, struct pcic_pci_table *tbl)
348 if (tbl->devid == devid)
356 * The standard way to control fuction interrupts is via bit 7 in the BCR
357 * register. Some data sheets indicate that this is just for "intterupts"
358 * while others are clear that it is for function interrupts. When this
359 * bit is set, function interrupts are routed via the ExCA register. When
360 * this bit is clear, they are routed via the PCI bus, usually via the int
361 * in the INTPIN register.
364 pcic_pci_gen_func(struct pcic_slot *sp, enum pcic_intr_way way)
368 bcr = pci_read_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, 2);
369 if (way == pcic_iw_pci)
370 bcr &= ~CB_BCR_INT_EXCA;
372 bcr |= CB_BCR_INT_EXCA;
373 pci_write_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
378 pcic_pci_gen_csc(struct pcic_slot *sp, enum pcic_intr_way way)
384 * The O2micro OZ67xx chips functions.
387 pcic_pci_oz67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
389 return (pcic_pci_gen_func(sp, way));
393 pcic_pci_oz67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
396 * Need datasheet to find out what's going on. However, the
397 * 68xx datasheets are so vague that it is hard to know what
398 * the right thing to do is.
406 pcic_pci_oz67xx_init(device_t dev)
408 device_printf(dev, "Warning: O2micro OZ67xx chips may not work\n");
409 pcic_pci_cardbus_init(dev);
413 * The O2micro OZ68xx chips functions.
416 pcic_pci_oz68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
418 return (pcic_pci_gen_func(sp, way));
422 pcic_pci_oz68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
425 * The 68xx datasheets make it hard to know what the right thing
426 * to do here is. We do what we know, which is nothing, and
434 pcic_pci_oz68xx_init(device_t dev)
437 * This is almost certainly incomplete.
439 device_printf(dev, "Warning: O2micro OZ68xx chips may not work\n");
440 pcic_pci_cardbus_init(dev);
444 * The Cirrus Logic PD6729/30. These are weird beasts, so be careful.
445 * They are ISA parts glued to the PCI bus and do not follow the yenta
446 * specification for cardbus bridges. They seem to be similar to the
447 * intel parts that were also cloned by o2micro and maybe others, but
448 * they are so much more common that the author doesn't have experience
449 * with them to know for sure.
452 pcic_pci_pd67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
455 * For pci interrupts, we need to set bit 3 of extension register
456 * 3 to 1. For ISA interrupts, we need to clear it.
458 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
459 if (way == pcic_iw_pci)
460 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
462 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
468 pcic_pci_pd67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
471 * For pci interrupts, we need to set bit 4 of extension register
472 * 3 to 1. For ISA interrupts, we need to clear it.
474 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
475 if (way == pcic_iw_pci)
476 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
478 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
485 pcic_pci_pd67xx_init(device_t dev)
487 struct pcic_softc *sc = device_get_softc(dev);
489 if (sc->csc_route == pcic_iw_pci || sc->func_route == pcic_iw_pci)
490 device_printf(dev, "PD67xx maybe broken for PCI routing.\n");
494 * Set up the CL-PD6832, 6833 and 6834.
497 pcic_pci_pd68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
499 return (pcic_pci_gen_func(sp, way));
503 pcic_pci_pd68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
505 struct pcic_softc *sc = sp->sc;
506 device_t dev = sc->dev;
507 u_int32_t device_id = pci_get_devid(dev);
512 * CLPD6832 management interrupt enable bit is bit 11
513 * (MGMT_IRQ_ENA) in bridge control register(offset 0x3d).
514 * When on, card status interrupts are ISA controlled by
515 * the ExCA register 0x05.
517 * The CLPD6833 does things differently. It doesn't have bit
518 * 11 in the bridge control register. Instead, this
519 * functionality appears to be in the "Configuration
520 * Miscellaneous 1" register bit 1.
522 * I'm assuming that the CLPD6834 does things like the '33
524 if (device_id == PCIC_ID_CLPD6832) {
525 bcr = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
526 if (way == pcic_iw_pci)
527 bcr &= ~CLPD6832_BCR_MGMT_IRQ_ENA;
529 bcr |= CLPD6832_BCR_MGMT_IRQ_ENA;
530 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
532 if (device_id != PCIC_ID_CLPD6832) {
533 cm1 = pci_read_config(dev, CLPD6833_CFG_MISC_1, 4);
534 if (way == pcic_iw_pci)
535 cm1 &= ~CLPD6833_CM1_MGMT_EXCA_ENA;
537 cm1 |= CLPD6833_CM1_MGMT_EXCA_ENA;
538 pci_write_config(dev, CLPD6833_CFG_MISC_1, cm1, 4);
544 pcic_pci_pd68xx_init(device_t dev)
546 pcic_pci_cardbus_init(dev);
550 pcic_pci_ricoh_func(struct pcic_slot *sp, enum pcic_intr_way way)
552 return (pcic_pci_gen_func(sp, way));
556 pcic_pci_ricoh_csc(struct pcic_slot *sp, enum pcic_intr_way way)
558 struct pcic_softc *sc = sp->sc;
559 device_t dev = sc->dev;
563 * For CSC interrupts via ISA, we can't do that exactly.
564 * However, we can disable INT# routing, which is usually what
565 * we want. This is bit 7 in the field. Note, bit 6 looks
566 * interesting, but appears to be unnecessary.
568 mcr2 = pci_read_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, 2);
569 if (way == pcic_iw_pci)
570 mcr2 &= ~R5C47X_MCR2_CSC_TO_INTX_DISABLE;
572 mcr2 |= R5C47X_MCR2_CSC_TO_INTX_DISABLE;
573 pci_write_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, mcr2, 2);
579 pcic_pci_ricoh_init(device_t dev)
582 u_int32_t device_id = pci_get_devid(dev);
585 case PCIC_ID_RICOH_RL5C465:
586 case PCIC_ID_RICOH_RL5C466:
588 * Ricoh chips have a legacy bridge enable different than most
589 * Code cribbed from NEWBUS's bridge code since I can't find a
590 * datasheet for them that has register definitions.
592 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
593 brgcntl &= ~(CB_BCR_RL_3E2_EN | CB_BCR_RL_3E0_EN);
594 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
597 pcic_pci_cardbus_init(dev);
601 * TI 1030, 1130, and 1131.
604 pcic_pci_ti113x_func(struct pcic_slot *sp, enum pcic_intr_way way)
607 device_t dev = sp->sc->dev;
610 * The TI-1130 (and 1030 and 1131) have a different interrupt
611 * routing control than the newer cards. assume we're not
612 * routing PCI, but enable as necessary when we find someone
613 * uses PCI interrupts. In order to get any pci interrupts,
614 * PCI_IRQ_ENA (bit 5) must be set. If either PCI_IREQ (bit
615 * 4) or PCI_CSC (bit 3) are set, then set bit 5 at the same
616 * time, since setting them enables the PCI interrupt routing.
618 * It also appears necessary to set the function routing bit
619 * in the bridge control register, but cardbus_init does that
622 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
623 if (way == pcic_iw_pci)
624 cardcntl |= TI113X_CARDCNTL_PCI_IREQ;
626 cardcntl &= ~TI113X_CARDCNTL_PCI_IREQ;
627 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
628 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
630 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
631 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
633 return (pcic_pci_gen_func(sp, way));
637 pcic_pci_ti113x_csc(struct pcic_slot *sp, enum pcic_intr_way way)
640 device_t dev = sp->sc->dev;
643 * The TI-1130 (and 1030 and 1131) have a different interrupt
644 * routing control than the newer cards. assume we're not
645 * routing PCI, but enable as necessary when we find someone
646 * uses PCI interrupts. In order to get any pci interrupts,
647 * PCI_IRQ_ENA (bit 5) must be set. If either PCI_IREQ (bit
648 * 4) or PCI_CSC (bit 3) are set, then set bit 5 at the same
649 * time, since setting them enables the PCI interrupt routing.
651 * It also appears necessary to set the function routing bit
652 * in the bridge control register, but cardbus_init does that
655 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
656 if (way == pcic_iw_pci)
657 cardcntl |= TI113X_CARDCNTL_PCI_CSC;
659 cardcntl &= ~TI113X_CARDCNTL_PCI_CSC;
660 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
661 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
663 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
664 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
670 pcic_pci_ti12xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
672 u_int32_t syscntl, devcntl, cardcntl, mfunc;
673 device_t dev = sp->sc->dev;
675 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
676 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
677 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
680 * Special code for the Orinoco cards (and a few others). They
681 * seem to need this special code to make them work only over pci
682 * interrupts. Sadly, doing this code also causes problems for
683 * many laptops, so we have to make it controlled by a tunable.
684 * Actually, experience has shown that this rarely, if ever,
687 if (way == pcic_iw_pci) {
689 * pcic_init_routing seems to do nothing useful towards
690 * fixing the hang problems. I plan on removing it in
693 if (pcic_init_routing) {
694 devcntl &= ~TI113X_DEVCNTL_INTR_MASK;
695 pci_write_config(dev, TI113X_PCI_DEVICE_CONTROL,
697 syscntl |= TI113X_SYSCNTL_INTRTIE;
700 * I'm not sure that this helps/hurts things at all and
701 * plan on removing it in the 4.8 time frame unless someone
702 * can show that it really helps.
704 syscntl &= ~TI113X_SYSCNTL_SMIENB;
705 pci_write_config(dev, TI113X_PCI_SYSTEM_CONTROL, syscntl, 1);
708 * Some PCI add-in cards don't have good EEPROMs on them,
709 * so they get this MUX register wrong. The MUX register
710 * defaults to 0, which is usually wrong for this register,
711 * so we initialize it to make sense.
713 * We don't bother to turn it off in the ISA case since it
714 * is an initialization issue.
716 * A few weird TI bridges don't have MFUNC, so filter
719 if ((sp->sc->flags & TI_NO_MFUNC) == 0) {
720 mfunc = pci_read_config(dev, TI12XX_PCI_MFUNC, 4);
722 mfunc = (mfunc & ~TI12XX_MFUNC_PIN0) |
723 TI12XX_MFUNC_PIN0_INTA;
724 if ((syscntl & TI113X_SYSCNTL_INTRTIE) == 0)
725 mfunc = (mfunc & ~TI12XX_MFUNC_PIN1) |
726 TI12XX_MFUNC_PIN1_INTB;
727 pci_write_config(dev, TI12XX_PCI_MFUNC, mfunc,
733 return (pcic_pci_gen_func(sp, way));
737 pcic_pci_ti12xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
740 * Nothing happens here. The TI12xx parts will route the
741 * CSC interrupt via PCI if ExCA register tells it to use
742 * interrupt 0. And via IRQ otherwise (except for reserved
743 * values which may or may not do anything).
745 * We just hope for the best here that doing nothing is the
752 * TI PCI-CardBus Host Adapter specific function code.
753 * This function is separated from pcic_pci_attach().
754 * Takeshi Shibagaki(shiba@jp.freebsd.org).
757 pcic_pci_ti_init(device_t dev)
759 u_int32_t syscntl, diagctl, devcntl, cardcntl;
760 u_int32_t device_id = pci_get_devid(dev);
761 int ti113x = (device_id == PCIC_ID_TI1031) ||
762 (device_id == PCIC_ID_TI1130) ||
763 (device_id == PCIC_ID_TI1131);
765 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
766 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
767 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
770 device_printf(dev, "TI113X PCI Config Reg: ");
771 if (syscntl & TI113X_SYSCNTL_CLKRUN_ENA) {
772 if (syscntl & TI113X_SYSCNTL_CLKRUN_SEL)
773 printf("[clkrun irq 12]");
775 printf("[clkrun irq 10]");
778 device_printf(dev, "TI12XX PCI Config Reg: ");
781 * Turn on async CSC interrupts. This appears to
782 * be the default, but the old, pre pci-aware, code
783 * did this and it appears PAO does as well.
785 diagctl = pci_read_config(dev, TI12XX_PCI_DIAGNOSTIC, 1);
786 diagctl |= TI12XX_DIAG_CSC_INTR;
787 pci_write_config(dev, TI12XX_PCI_DIAGNOSTIC, diagctl, 1);
790 * Turn off Zoom Video. Some cards have this enabled,
791 * some do not but it causes problems when enabled. This
792 * register doesn't exist on the 1130 (and likely the 1131,
793 * but without a datasheet it is impossible to know).
794 * Some 12xx chips may not have it, but setting it is
795 * believed to be harmless on those models.
797 pci_write_config(dev, TI12XX_PCI_MULTIMEDIA_CONTROL, 0, 4);
799 if (cardcntl & TI113X_CARDCNTL_RING_ENA)
800 printf("[ring enable]");
801 if (cardcntl & TI113X_CARDCNTL_SPKR_ENA)
802 printf("[speaker enable]");
803 if (syscntl & TI113X_SYSCNTL_PWRSAVINGS)
804 printf("[pwr save]");
805 switch(devcntl & TI113X_DEVCNTL_INTR_MASK){
806 case TI113X_DEVCNTL_INTR_ISA :
807 printf("[CSC parallel isa irq]");
809 case TI113X_DEVCNTL_INTR_SERIAL :
810 printf("[CSC serial isa irq]");
812 case TI113X_DEVCNTL_INTR_NONE :
813 printf("[pci only]");
815 case TI12XX_DEVCNTL_INTR_ALLSERIAL :
816 printf("[FUNC pci int + CSC serial isa irq]");
820 pcic_pci_cardbus_init(dev);
824 * Code for TOPIC chips
827 pcic_pci_topic_func(struct pcic_slot *sp, enum pcic_intr_way way)
829 #ifdef THIS_BRAEKS_THINGS
830 device_t dev = sp->sc->dev;
833 scr = pci_read_config(dev, TOPIC_SOCKET_CTRL, 4);
834 if (way == pcic_iw_pci)
835 scr |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
837 scr &= ~TOPIC_SOCKET_CTRL_SCR_IRQSEL;
838 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
840 return (pcic_pci_gen_func(sp, way));
844 pcic_pci_topic_csc(struct pcic_slot *sp, enum pcic_intr_way way)
846 device_t dev = sp->sc->dev;
850 device_id = pci_get_devid(dev);
851 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
852 scr = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
853 if (way == pcic_iw_pci)
854 scr |= TOPIC97_SLOT_CTRL_PCIINT;
856 scr &= ~TOPIC97_SLOT_CTRL_PCIINT;
857 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
864 pcic_pci_topic_init(device_t dev)
866 struct pcic_softc *sc = device_get_softc(dev);
870 device_id = pci_get_devid(dev);
871 reg = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
872 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
873 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
874 reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
875 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
876 reg |= TOPIC97_SLOT_CTRL_PCIINT;
877 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
879 pci_write_config(dev, TOPIC_SLOT_CTRL, reg, 4);
880 pcic_pci_cardbus_init(dev);
882 if (device_id == PCIC_ID_TOPIC100 || device_id == PCIC_ID_TOPIC97) {
884 * We need to enable voltage sense and 3V cards explicitly
885 * in the bridge. The datasheets I have for both the
886 * ToPIC 97 and 100 both lists these ports. Without
887 * datasheets for the ToPIC95s, I can't tell if we need
888 * to do it there or not.
890 pcic_setb(&sc->slots[0], PCIC_TOPIC_FCR,
891 PCIC_FCR_3V_EN | PCIC_FCR_VS_EN);
896 pcic_pci_cardbus_init(device_t dev)
898 struct pcic_softc *sc = device_get_softc(dev);
902 unit = device_get_unit(dev);
904 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
905 brgcntl |= CB_BCR_WRITE_POST_EN | CB_BCR_MASTER_ABORT;
906 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
908 /* Turn off legacy address */
909 pci_write_config(dev, CB_PCI_LEGACY16_IOADDR, 0, 2);
912 * Write zeros into the remaining memory I/O windows. This
913 * seems to turn off the pci configuration of these things and
914 * make the cardbus bridge use the values for memory
915 * programmed into the pcic registers.
917 pci_write_config(dev, CB_PCI_MEMBASE0, 0, 4);
918 pci_write_config(dev, CB_PCI_MEMLIMIT0, 0, 4);
919 pci_write_config(dev, CB_PCI_MEMBASE1, 0, 4);
920 pci_write_config(dev, CB_PCI_MEMLIMIT1, 0, 4);
921 pci_write_config(dev, CB_PCI_IOBASE0, 0, 4);
922 pci_write_config(dev, CB_PCI_IOLIMIT0, 0, 4);
923 pci_write_config(dev, CB_PCI_IOBASE1, 0, 4);
924 pci_write_config(dev, CB_PCI_IOLIMIT1, 0, 4);
927 * Tell the chip to do its routing thing.
929 sc->chip->func_intr_way(&sc->slots[0], sc->func_route);
930 sc->chip->csc_intr_way(&sc->slots[0], sc->csc_route);
936 pcic_pci_cardtype(u_int32_t stat)
938 if (stat & CB_SS_NOTCARD)
939 return ("unrecognized by bridge");
940 if ((stat & (CB_SS_16BIT | CB_SS_CB)) == (CB_SS_16BIT | CB_SS_CB))
941 return ("16-bit and 32-bit (can't happen)");
942 if (stat & CB_SS_16BIT)
943 return ("16-bit pccard");
945 return ("32-bit cardbus");
946 return ("none (can't happen)");
950 * Card insertion and removal code. The insertion events need to be
951 * debounced so that the noisy insertion/removal events don't result
952 * in the hardware being initialized many times, only to be torn down
953 * as well. This may also cause races with pccardd. Instead, we wait
954 * for the insertion signal to be stable for 0.5 seconds before we declare
955 * it to be a real insertion event. Removal is also debounced. We turn
956 * off interrupt servicing during the settling time to prevent infinite
957 * loops in the driver.
959 * Note: We only handle the card detect change events. We don't handle
960 * power events and status change events.
963 pcic_cd_change(void *arg)
965 struct pcic_softc *sc = (struct pcic_softc *) arg;
966 struct pcic_slot *sp = &sc->slots[0];
970 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
972 /* Status changed while present; remove the card from the system. */
973 if (sc->cd_present) {
975 pccard_event(sp->slt, card_removed);
977 /* Nothing to do if the debounced state is 'not present'. */
978 if ((stat & CB_SS_CD) != 0)
982 if (bootverbose && (stat & CB_SS_BADVCC) != 0)
983 device_printf(sc->dev, "BAD Vcc request: 0x%x\n", stat);
984 if ((stat & CB_SS_16BIT) == 0)
985 device_printf(sp->sc->dev, "Card type %s is unsupported\n",
986 pcic_pci_cardtype(stat));
988 pccard_event(sp->slt, card_inserted);
992 pcic_pci_intr(void *arg)
994 struct pcic_softc *sc = (struct pcic_softc *) arg;
995 struct pcic_slot *sp = &sc->slots[0];
998 event = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_EVENT);
1001 device_printf(sc->dev, "Event mask 0x%x\n", event);
1004 * Treat all card-detect signal transitions the same way
1005 * since we can't reliably tell if this is an insert or a
1006 * remove event. Stop the card from getting interrupts and
1007 * defer the insert/remove event until the CB_SOCKET_STATE
1008 * signals have had time to settle.
1010 if ((event & CB_SE_CD) != 0) {
1011 if (sc->cd_pending) {
1012 untimeout(pcic_cd_change, arg, sc->cd_ch);
1016 sc->cd_ch = timeout(pcic_cd_change, arg, hz/2);
1017 sc->func_intr = NULL;
1020 /* Ack the interrupt */
1021 bus_space_write_4(sp->bst, sp->bsh, 0, event);
1025 * Some TI chips also require us to read the old ExCA register for
1026 * card status change when we route CSC via PCI! So, we go ahead
1027 * and read it to clear the bits. Maybe we should check the status
1028 * ala the ISA interrupt handler, but those changes should be caught
1031 * We have to check it every interrupt because these bits can sometimes
1032 * show up indepentently of the CB_SOCKET_EVENT register above.
1034 sp->getb(sp, PCIC_STAT_CHG);
1038 * Return the ID string for the controller if the vendor/product id
1039 * matches, NULL otherwise.
1042 pcic_pci_probe(device_t dev)
1047 u_int32_t device_id;
1048 struct pcic_pci_table *itm;
1049 struct resource *res;
1052 if (pcic_ignore_pci)
1054 device_id = pci_get_devid(dev);
1056 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1057 if (pcic_ignore_function_1 && pci_get_function(dev) == 1) {
1059 PRVERB((dev, "Ignoring function 1\n"));
1064 if (desc == NULL && pci_get_class(dev) == PCIC_BRIDGE) {
1065 subclass = pci_get_subclass(dev);
1066 progif = pci_get_progif(dev);
1067 if (subclass == PCIS_BRIDGE_PCMCIA && progif == 0)
1068 desc = "Generic PCI-PCMCIA Bridge";
1069 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0)
1070 desc = "YENTA PCI-CardBus Bridge";
1071 if (bootverbose && desc)
1072 printf("Found unknown %s devid 0x%x\n", desc, device_id);
1076 device_set_desc(dev, desc);
1079 * Take us out of power down mode, if necessary. It also
1080 * appears that even reading the power register is enough on
1081 * some systems to cause correct behavior.
1083 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1084 /* Reset the power state. */
1085 device_printf(dev, "chip is in D%d power mode "
1086 "-- setting to D0\n", pci_get_powerstate(dev));
1087 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1091 * Allocated/deallocate interrupt. This forces the PCI BIOS or
1092 * other MD method to route the interrupts to this card.
1093 * This so we get the interrupt number in the probe message.
1094 * We only need to route interrupts when we're doing pci
1095 * parallel interrupt routing.
1097 * We use two different variables for the memory based and I/O
1098 * based cards, so the check here is a little more complex than
1099 * one would otherwise hope.
1101 * XXX The bus code for PCI really should do this for us.
1103 if ((pcic_intr_path == pcic_iw_pci &&
1104 device_id != PCIC_ID_CLPD6729) ||
1105 (pcic_pd6729_intr_path == pcic_iw_pci &&
1106 device_id == PCIC_ID_CLPD6729)) {
1110 * IRQ 0 is invalid on x86, but not other platforms.
1111 * If we have irq 0, then write 255 to force a new, non-
1112 * bogus one to be assigned. I think that in -current
1113 * the code in this ifdef may be obsolete with the new
1114 * invalid mapping that we're doing in the pci layer -- imp
1116 if (pci_get_irq(dev) == 0) {
1117 pci_set_irq(dev, 255);
1118 pci_write_config(dev, PCIR_INTLINE, 255, 1);
1121 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1124 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
1131 pcic_pci_shutdown(device_t dev)
1134 * More reports of things working w/o this code than with it.
1137 struct pcic_softc *sc;
1138 struct pcic_slot *sp;
1140 sc = (struct pcic_softc *) device_get_softc(dev);
1144 * Turn off the power to the slot in an attempt to
1145 * keep the system from hanging on reboot. We also turn off
1146 * card interrupts in an attempt to control interrupt storms.
1147 * on some (all?) this has the effect of also turning off
1148 * card status change interrupts. A side effect of writing 0
1149 * to INT_GEN is that the card is placed into "reset" mode
1150 * where nothing happens until it is taken out of "reset"
1153 * Also, turn off the generation of status interrupts too.
1155 sp->putb(sp, PCIC_INT_GEN, 0);
1156 sp->putb(sp, PCIC_STAT_INT, 0);
1157 sp->putb(sp, PCIC_POWER, 0);
1161 * Writing to INT_GEN can cause an interrupt, so we blindly
1162 * ack all possible interrupts here. Reading the stat change
1163 * shouldn't be necessary, but some TI chipsets need it in the
1164 * normal course of operations, so we do it here too. We can't
1165 * lose any interrupts after this point, so go ahead and ack
1166 * everything. The bits in INT_GEN clear upon reading them.
1167 * We also set the interrupt mask to 0, in an effort to avoid
1168 * getting further interrupts.
1170 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_MASK, 0);
1171 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_EVENT, 0xffffffff);
1172 sp->getb(sp, PCIC_STAT_CHG);
1177 * Print out the config space
1180 pcic_pci_print_config(device_t dev)
1184 device_printf(dev, "PCI Configuration space:");
1185 for (i = 0; i < 256; i += 4) {
1187 printf("\n 0x%02x: ", i);
1188 printf("0x%08x ", pci_read_config(dev, i, 4));
1194 * Generic pci interrupt attach routine. It tries to understand all parts,
1195 * and do sane things for those parts it does not understand.
1198 pcic_pci_attach(device_t dev)
1200 u_int32_t device_id = pci_get_devid(dev);
1202 struct pcic_slot *sp;
1203 struct pcic_softc *sc;
1206 struct pcic_pci_table *itm;
1209 struct resource *r = NULL;
1212 driver_intr_t *intr = NULL;
1215 * In sys/pci/pcireg.h, PCIR_COMMAND must be separated
1216 * PCI_COMMAND_REG(0x04) and PCI_STATUS_REG(0x06).
1217 * Takeshi Shibagaki(shiba@jp.freebsd.org).
1219 command = pci_read_config(dev, PCIR_COMMAND, 4);
1220 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN;
1221 pci_write_config(dev, PCIR_COMMAND, command, 4);
1223 sc = (struct pcic_softc *) device_get_softc(dev);
1226 sockbase = pci_read_config(dev, 0x10, 4);
1227 if (sockbase & 0x1) {
1228 sc->iorid = CB_PCI_SOCKET_BASE;
1229 sc->iores = bus_alloc_resource(dev, SYS_RES_IOPORT,
1230 &sc->iorid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
1231 if (sc->iores == NULL)
1234 sc->flags = PCIC_PD_POWER;
1235 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1236 for (i = 0; i < 2; i++) {
1237 sp[i].bst = rman_get_bustag(sc->iores);
1238 sp[i].bsh = rman_get_bushandle(sc->iores);
1241 sp[i].getb = pcic_getb_io;
1242 sp[i].putb = pcic_putb_io;
1243 sp[i].offset = i * PCIC_SLOT_SIZE;
1244 sp[i].controller = itm ? itm->type : PCIC_PD6729;
1245 if ((sp[i].getb(&sp[i], PCIC_ID_REV) & 0xc0) == 0x80)
1246 sp[i].slt = (struct slot *) 1;
1248 sc->csc_route = sc->func_route = pcic_pd6729_intr_path;
1250 sc->flags = itm->flags;
1252 * We have to use the ISA interrupt routine for status
1253 * changes since we don't have any "yenta" pci registers.
1254 * We have to do this even when we're using pci type
1255 * interrupts because on these cards the interrupts are
1256 * cleared in the same way that the ISA cards clear them.
1258 intr = pcic_isa_intr;
1260 sc->memrid = CB_PCI_SOCKET_BASE;
1261 sc->memres = bus_alloc_resource(dev, SYS_RES_MEMORY,
1262 &sc->memrid, 0, ~0, 1, RF_ACTIVE);
1263 if (sc->memres == NULL && pcic_pci_get_memory(dev) != 0)
1265 sp->getb = pcic_pci_getb2;
1266 sp->putb = pcic_pci_putb2;
1267 sp->offset = CB_EXCA_OFFSET;
1268 sp->bst = rman_get_bustag(sc->memres);
1269 sp->bsh = rman_get_bushandle(sc->memres);
1270 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1272 sp->controller = itm->type;
1274 sc->flags = itm->flags;
1276 /* By default, assume we're a D step compatible */
1277 sp->controller = PCIC_I82365SL_DF;
1279 sc->flags = PCIC_CARDBUS_POWER;
1281 /* All memory mapped cardbus bridges have these registers */
1282 sc->flags |= PCIC_YENTA_HIGH_MEMORY;
1283 sp->slt = (struct slot *) 1;
1284 sc->csc_route = pcic_intr_path;
1285 sc->func_route = pcic_intr_path;
1286 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1287 sc->cd_present = (stat & CB_SS_CD) == 0;
1291 sc->chip = itm->chip;
1293 sc->chip = &pcic_pci_generic_chip;
1295 if (sc->csc_route == pcic_iw_pci) {
1297 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1298 RF_ACTIVE | RF_SHAREABLE);
1300 sc->csc_route = pcic_iw_isa;
1301 sc->func_route = pcic_iw_isa;
1303 "No PCI interrupt routed, trying ISA.\n");
1306 intr = pcic_pci_intr;
1307 irq = rman_get_start(r);
1310 if (sc->csc_route == pcic_iw_isa) {
1312 irq = pcic_override_irq;
1314 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, irq,
1318 "Can't route ISA CSC interrupt.\n");
1323 "Management interrupt on ISA IRQ %ld\n", irq);
1325 intr = pcic_isa_intr;
1327 sc->slot_poll = pcic_timeout;
1328 sc->timeout_ch = timeout(sc->slot_poll, sc, hz/2);
1329 device_printf(dev, "Polling mode\n");
1335 * Initialize AFTER we figure out what kind of interrupt we're
1336 * going to be using, if any.
1339 panic("Bug: sc->chip not set!\n");
1340 sc->chip->init(dev);
1343 * Now install the interrupt handler, if necessary.
1349 error = bus_setup_intr(dev, r, INTR_TYPE_AV, intr, sc, &sc->ih);
1356 pcic_pci_print_config(dev);
1357 return (pcic_attach(dev));
1361 pcic_pci_detach(device_t dev)
1363 return (EBUSY); /* Can't detach this device */
1367 * The PCI bus should do this for us. However, it doesn't quite yet, so
1368 * we cope by doing it ourselves. If it ever does, this code can go quietly
1369 * into that good night.
1372 pcic_pci_get_memory(device_t dev)
1374 struct pcic_softc *sc;
1377 sc = (struct pcic_softc *) device_get_softc(dev);
1378 sockbase = pci_read_config(dev, sc->memrid, 4);
1379 if (sockbase >= 0x100000 && sockbase < 0xfffffff0) {
1380 device_printf(dev, "Could not map register memory\n");
1383 pci_write_config(dev, sc->memrid, 0xffffffff, 4);
1384 sockbase = pci_read_config(dev, sc->memrid, 4);
1385 sockbase = (sockbase & 0xfffffff0) & -(sockbase & 0xfffffff0);
1386 #define CARDBUS_SYS_RES_MEMORY_START 0x88000000
1387 #define CARDBUS_SYS_RES_MEMORY_END 0xFFFFFFFF
1388 sc->memres = bus_generic_alloc_resource(device_get_parent(dev),
1389 dev, SYS_RES_MEMORY, &sc->memrid,
1390 CARDBUS_SYS_RES_MEMORY_START, CARDBUS_SYS_RES_MEMORY_END,
1391 sockbase, RF_ACTIVE | rman_make_alignment_flags(sockbase));
1392 if (sc->memres == NULL) {
1393 device_printf(dev, "Could not grab register memory\n");
1396 sockbase = rman_get_start(sc->memres);
1397 pci_write_config(dev, sc->memrid, sockbase, 4);
1398 device_printf(dev, "PCI Memory allocated: 0x%08x\n", sockbase);
1403 pcic_pci_gen_mapirq(struct pcic_slot *sp, int irq)
1406 * If we're doing ISA interrupt routing, then just go to the
1407 * generic ISA routine. Also, irq 0 means turn off the interrupts
1410 if (sp->sc->func_route == pcic_iw_isa || irq == 0)
1411 return (pcic_isa_mapirq(sp, irq));
1414 * Ohterwise we're doing PCI interrupts. For those cardbus bridges
1415 * that follow yenta (and the one pcmcia bridge that does), we don't
1416 * do a thing to get the IRQ mapped into the system. However,
1417 * for other controllers that are PCI, but not yetna compliant, we
1418 * need to do some special mapping.
1420 if (sp->controller == PCIC_PD6729) {
1427 sp->putb(sp, PCIC_INT_GEN, /* Assume INTA# */
1428 (sp->getb(sp, PCIC_INT_GEN) & 0xF0) | 3);
1435 pcic_pci_func_intr(void *arg)
1437 struct pcic_softc *sc = (struct pcic_softc *) arg;
1438 struct pcic_slot *sp = &sc->slots[0];
1443 * The 6729 controller is a weird one, and we have to use
1444 * the ISA registers to check to see if the card is there.
1445 * Otherwise we look at the PCI state register to find out
1446 * if the card is there.
1448 if (sp->controller == PCIC_PD6729) {
1449 if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) == PCIC_CD)
1453 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1454 if ((stat & CB_SS_CD) == 0 && sc->func_intr != 0)
1457 if (doit && sc->func_intr != NULL)
1458 sc->func_intr(sc->func_arg);
1462 pcic_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
1463 int flags, driver_intr_t *intr, void *arg, void **cookiep)
1465 struct pcic_softc *sc = device_get_softc(dev);
1466 struct pcic_slot *sp = &sc->slots[0];
1469 if (sc->func_route == pcic_iw_isa)
1470 return(pcic_setup_intr(dev, child, irq, flags, intr, arg,
1473 #if __FreeBSD_version >= 500000
1474 if ((flags & INTR_FAST) != 0)
1476 if ((flags & INTR_TYPE_FAST) != 0)
1479 if (sc->func_intr != NULL) {
1480 device_printf(child, "Can't establish another ISR\n");
1484 err = bus_generic_setup_intr(dev, child, irq, flags,
1485 pcic_pci_func_intr, sc, cookiep);
1488 sc->chip->map_irq(sp, rman_get_start(irq));
1489 sc->func_intr = intr;
1495 pcic_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
1498 struct pcic_softc *sc = device_get_softc(dev);
1500 if (sc->func_route == pcic_iw_isa)
1501 return (pcic_teardown_intr(dev, child, irq, cookie));
1502 sc->func_intr = NULL;
1503 return (bus_generic_teardown_intr(dev, child, irq, cookie));
1507 pcic_pci_resume(device_t dev)
1509 struct pcic_softc *sc = device_get_softc(dev);
1512 * Some BIOSes will not save the BARs for the pci chips, so we
1513 * must do it ourselves. If the BAR is reset to 0 for an I/O
1514 * device, it will read back as 0x1, so no explicit test for
1515 * memory devices are needed.
1517 * Note: The PCI bus code should do this automatically for us on
1518 * suspend/resume, but until it does, we have to cope.
1520 if (pci_read_config(dev, CB_PCI_SOCKET_BASE, 4) == 0)
1521 pci_write_config(dev, CB_PCI_SOCKET_BASE,
1522 rman_get_start(sc->memres), 4);
1523 return (bus_generic_resume(dev));
1526 static device_method_t pcic_pci_methods[] = {
1527 /* Device interface */
1528 DEVMETHOD(device_probe, pcic_pci_probe),
1529 DEVMETHOD(device_attach, pcic_pci_attach),
1530 DEVMETHOD(device_detach, pcic_pci_detach),
1531 DEVMETHOD(device_suspend, bus_generic_suspend),
1532 DEVMETHOD(device_resume, pcic_pci_resume),
1533 DEVMETHOD(device_shutdown, pcic_pci_shutdown),
1536 DEVMETHOD(bus_print_child, bus_generic_print_child),
1537 DEVMETHOD(bus_alloc_resource, pcic_alloc_resource),
1538 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1539 DEVMETHOD(bus_activate_resource, pcic_activate_resource),
1540 DEVMETHOD(bus_deactivate_resource, pcic_deactivate_resource),
1541 DEVMETHOD(bus_setup_intr, pcic_pci_setup_intr),
1542 DEVMETHOD(bus_teardown_intr, pcic_pci_teardown_intr),
1544 /* Card interface */
1545 DEVMETHOD(card_set_res_flags, pcic_set_res_flags),
1546 DEVMETHOD(card_get_res_flags, pcic_get_res_flags),
1547 DEVMETHOD(card_set_memory_offset, pcic_set_memory_offset),
1548 DEVMETHOD(card_get_memory_offset, pcic_get_memory_offset),
1553 static driver_t pcic_pci_driver = {
1556 sizeof(struct pcic_softc)
1559 DRIVER_MODULE(pcic, pci, pcic_pci_driver, pcic_devclass, 0, 0);