2 * Copyright (c) 2001 M. Warner Losh. All Rights Reserved.
3 * Copyright (c) 1997 Ted Faber All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice immediately at the beginning of the file, without modification,
11 * this list of conditions, and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Absolutely no warranty of function or purpose is made by the author
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/sysctl.h>
37 #include <sys/systm.h>
39 #if __FreeBSD_version < 500000
40 #include <pci/pcireg.h>
41 #include <pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
47 #include <pccard/pcic_pci.h>
48 #include <pccard/i82365.h>
49 #include <pccard/cardinfo.h>
50 #include <pccard/slot.h>
51 #include <pccard/pcicvar.h>
53 #include <dev/pccard/pccardvar.h>
56 #define PRVERB(x) do { \
57 if (bootverbose) { device_printf x; } \
60 static int pcic_pci_get_memory(device_t dev);
62 SYSCTL_DECL(_hw_pcic);
64 static int pcic_ignore_function_1 = 0;
65 TUNABLE_INT("hw.pcic.ignore_function_1", &pcic_ignore_function_1);
66 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_function_1, CTLFLAG_RD,
67 &pcic_ignore_function_1, 0,
68 "When set, driver ignores pci function 1 of the bridge. This option\n\
69 is obsolete and will be deleted before FreeBSD 4.8.");
72 * The following should be a hint, so we can do it on a per device
73 * instance, but this is convenient. Do not set this unless pci
74 * routing doesn't work. It is purposely vague and undocumented
75 * at the moment. Sadly, this seems to be needed way too often.
77 static int pcic_intr_path = (int)pcic_iw_pci;
78 TUNABLE_INT("hw.pcic.intr_path", &pcic_intr_path);
79 SYSCTL_INT(_hw_pcic, OID_AUTO, intr_path, CTLFLAG_RD, &pcic_intr_path, 0,
80 "Which path to send the interrupts over. Normally interrupts for\n\
81 cardbus bridges are routed over the PCI bus (2). However, some laptops\n\
82 will hang when using PCI interrupts due to bugs in this code. Those\n\
83 bugs can be worked around by forcings ISA interrupts (1).");
85 static int pcic_init_routing = 0;
86 TUNABLE_INT("hw.pcic.init_routing", &pcic_init_routing);
87 SYSCTL_INT(_hw_pcic, OID_AUTO, init_routing, CTLFLAG_RD,
88 &pcic_init_routing, 0,
89 "Force the interrupt routing to be initialized on those bridges where\n\
90 doing so will cause probelms. This is very rare and generally is not\n\
91 needed. The default of 0 is almost always appropriate. Only set to 1 if\n\
92 instructed to do so for debugging. Only TI bridges are affected by this\n\
93 option, and what the code does is of dubious value. This option is obsolete\n\
94 and will be deleted before FreeBSD 4.8.");
96 static int pcic_ignore_pci = 0;
97 TUNABLE_INT("hw.pcic.ignore_pci", &pcic_ignore_pci);
98 SYSCTL_INT(_hw_pcic, OID_AUTO, ignore_pci, CTLFLAG_RD,
100 "When set, driver ignores pci cardbus bridges it would otherwise claim.\n\
101 Generally speaking, this option is not needed for anything other than as an\n\
104 static int pcic_pd6729_intr_path = (int)pcic_iw_isa;
105 TUNABLE_INT("hw.pcic.pd6729_intr_path", &pcic_pd6729_intr_path);
106 SYSCTL_INT(_hw_pcic, OID_AUTO, pd6729_intr_path, CTLFLAG_RD,
107 &pcic_pd6729_intr_path, 0,
108 "Determine the interrupt path or method for Cirrus Logic PD6729 and\n\
109 similar I/O space based pcmcia bridge. Chips on a PCI expansion card need\n\
110 a value of 2, while chips installed in a laptop need a value of 1 (which is\n\
111 also the default). This is similar to hw.pcic.intr_path, but separate so\n\
112 that it can default to ISA when intr_path defaults to PCI.");
114 static void pcic_pci_cardbus_init(device_t);
115 static pcic_intr_way_t pcic_pci_gen_func;
116 static pcic_intr_way_t pcic_pci_gen_csc;
117 static pcic_intr_mapirq_t pcic_pci_gen_mapirq;
119 static pcic_intr_way_t pcic_pci_oz67xx_func;
120 static pcic_intr_way_t pcic_pci_oz67xx_csc;
121 static pcic_init_t pcic_pci_oz67xx_init;
123 static pcic_intr_way_t pcic_pci_oz68xx_func;
124 static pcic_intr_way_t pcic_pci_oz68xx_csc;
125 static pcic_init_t pcic_pci_oz68xx_init;
127 static pcic_intr_way_t pcic_pci_pd67xx_func;
128 static pcic_intr_way_t pcic_pci_pd67xx_csc;
129 static pcic_init_t pcic_pci_pd67xx_init;
131 static pcic_intr_way_t pcic_pci_pd68xx_func;
132 static pcic_intr_way_t pcic_pci_pd68xx_csc;
133 static pcic_init_t pcic_pci_pd68xx_init;
135 static pcic_intr_way_t pcic_pci_ricoh_func;
136 static pcic_intr_way_t pcic_pci_ricoh_csc;
137 static pcic_init_t pcic_pci_ricoh_init;
139 static pcic_intr_way_t pcic_pci_ti113x_func;
140 static pcic_intr_way_t pcic_pci_ti113x_csc;
141 static pcic_init_t pcic_pci_ti_init;
143 static pcic_intr_way_t pcic_pci_ti12xx_func;
144 static pcic_intr_way_t pcic_pci_ti12xx_csc;
146 static pcic_intr_way_t pcic_pci_topic_func;
147 static pcic_intr_way_t pcic_pci_topic_csc;
148 static pcic_init_t pcic_pci_topic_init;
150 static struct pcic_chip pcic_pci_oz67xx_chip = {
151 pcic_pci_oz67xx_func,
157 static struct pcic_chip pcic_pci_oz68xx_chip = {
158 pcic_pci_oz68xx_func,
164 static struct pcic_chip pcic_pci_pd67xx_chip = {
165 pcic_pci_pd67xx_func,
171 static struct pcic_chip pcic_pci_pd68xx_chip = {
172 pcic_pci_pd68xx_func,
178 static struct pcic_chip pcic_pci_ricoh_chip = {
185 static struct pcic_chip pcic_pci_ti113x_chip = {
186 pcic_pci_ti113x_func,
192 static struct pcic_chip pcic_pci_ti12xx_chip = {
193 pcic_pci_ti12xx_func,
199 static struct pcic_chip pcic_pci_topic_chip = {
206 static struct pcic_chip pcic_pci_generic_chip = {
210 pcic_pci_cardbus_init
213 struct pcic_pci_table
219 struct pcic_chip *chip;
220 } pcic_pci_devs[] = {
221 { PCI_DEVICE_ID_OMEGA_82C094,
223 PCIC_I82365, PCIC_DF_POWER, &pcic_pci_pd67xx_chip },
224 { PCI_DEVICE_ID_PCIC_CLPD6729,
225 "Cirrus Logic PD6729/6730 PC-Card Controller",
226 PCIC_PD6729, PCIC_PD_POWER, &pcic_pci_pd67xx_chip },
227 { PCI_DEVICE_ID_PCIC_CLPD6832,
228 "Cirrus Logic PD6832 PCI-CardBus Bridge",
229 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
230 { PCI_DEVICE_ID_PCIC_CLPD6833,
231 "Cirrus Logic PD6833 PCI-CardBus Bridge",
232 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
233 { PCI_DEVICE_ID_PCIC_CLPD6834,
234 "Cirrus Logic PD6834 PCI-CardBus Bridge",
235 PCIC_PD673X, PCIC_CARDBUS_POWER, &pcic_pci_pd68xx_chip },
236 { PCI_DEVICE_ID_PCIC_OZ6729,
237 "O2micro OZ6729 PC-Card Bridge",
238 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
239 { PCI_DEVICE_ID_PCIC_OZ6730,
240 "O2micro OZ6730 PC-Card Bridge",
241 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz67xx_chip },
242 { PCI_DEVICE_ID_PCIC_OZ6832,
243 "O2micro 6832/6833 PCI-Cardbus Bridge",
244 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
245 { PCI_DEVICE_ID_PCIC_OZ6860,
246 "O2micro 6836/6860 PCI-Cardbus Bridge",
247 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
248 { PCI_DEVICE_ID_PCIC_OZ6872,
249 "O2micro 6812/6872 PCI-Cardbus Bridge",
250 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
251 { PCI_DEVICE_ID_PCIC_OZ6912,
252 "O2micro 6912 PCI-Cardbus Bridge",
253 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_oz68xx_chip },
254 { PCI_DEVICE_ID_PCIC_OZ6922,
255 "O2micro 6922 PCI-Cardbus Bridge",
256 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
257 { PCI_DEVICE_ID_PCIC_OZ6933,
258 "O2micro 6933 PCI-Cardbus Bridge",
259 PCIC_I82365, PCIC_AB_POWER, &pcic_pci_oz68xx_chip },
260 { PCI_DEVICE_ID_RICOH_RL5C465,
261 "Ricoh RL5C465 PCI-CardBus Bridge",
262 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
263 { PCI_DEVICE_ID_RICOH_RL5C475,
264 "Ricoh RL5C475 PCI-CardBus Bridge",
265 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
266 { PCI_DEVICE_ID_RICOH_RL5C476,
267 "Ricoh RL5C476 PCI-CardBus Bridge",
268 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
269 { PCI_DEVICE_ID_RICOH_RL5C477,
270 "Ricoh RL5C477 PCI-CardBus Bridge",
271 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
272 { PCI_DEVICE_ID_RICOH_RL5C478,
273 "Ricoh RL5C478 PCI-CardBus Bridge",
274 PCIC_RF5C296, PCIC_CARDBUS_POWER, &pcic_pci_ricoh_chip },
275 { PCI_DEVICE_ID_PCIC_TI1031,
276 "TI PCI-1031 PCI-PCMCIA Bridge",
277 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
278 { PCI_DEVICE_ID_PCIC_TI1130,
279 "TI PCI-1130 PCI-CardBus Bridge",
280 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
281 { PCI_DEVICE_ID_PCIC_TI1131,
282 "TI PCI-1131 PCI-CardBus Bridge",
283 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti113x_chip },
284 { PCI_DEVICE_ID_PCIC_TI1210,
285 "TI PCI-1210 PCI-CardBus Bridge",
286 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
287 { PCI_DEVICE_ID_PCIC_TI1211,
288 "TI PCI-1211 PCI-CardBus Bridge",
289 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
290 { PCI_DEVICE_ID_PCIC_TI1220,
291 "TI PCI-1220 PCI-CardBus Bridge",
292 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
293 { PCI_DEVICE_ID_PCIC_TI1221,
294 "TI PCI-1221 PCI-CardBus Bridge",
295 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
296 { PCI_DEVICE_ID_PCIC_TI1225,
297 "TI PCI-1225 PCI-CardBus Bridge",
298 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
299 { PCI_DEVICE_ID_PCIC_TI1250,
300 "TI PCI-1250 PCI-CardBus Bridge",
301 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
302 { PCI_DEVICE_ID_PCIC_TI1251,
303 "TI PCI-1251 PCI-CardBus Bridge",
304 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
305 { PCI_DEVICE_ID_PCIC_TI1251B,
306 "TI PCI-1251B PCI-CardBus Bridge",
307 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
308 { PCI_DEVICE_ID_PCIC_TI1260,
309 "TI PCI-1260 PCI-CardBus Bridge",
310 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
311 { PCI_DEVICE_ID_PCIC_TI1260B,
312 "TI PCI-1260B PCI-CardBus Bridge",
313 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
314 { PCI_DEVICE_ID_PCIC_TI1410,
315 "TI PCI-1410 PCI-CardBus Bridge",
316 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
317 { PCI_DEVICE_ID_PCIC_TI1420,
318 "TI PCI-1420 PCI-CardBus Bridge",
319 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
320 { PCI_DEVICE_ID_PCIC_TI1421,
321 "TI PCI-1421 PCI-CardBus Bridge",
322 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
323 { PCI_DEVICE_ID_PCIC_TI1450,
324 "TI PCI-1450 PCI-CardBus Bridge",
325 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
326 { PCI_DEVICE_ID_PCIC_TI1451,
327 "TI PCI-1451 PCI-CardBus Bridge",
328 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
329 { PCI_DEVICE_ID_PCIC_TI4410,
330 "TI PCI-4410 PCI-CardBus Bridge",
331 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
332 { PCI_DEVICE_ID_PCIC_TI4450,
333 "TI PCI-4450 PCI-CardBus Bridge",
334 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
335 { PCI_DEVICE_ID_PCIC_TI4451,
336 "TI PCI-4451 PCI-CardBus Bridge",
337 PCIC_I82365SL_DF, PCIC_CARDBUS_POWER, &pcic_pci_ti12xx_chip },
338 { PCI_DEVICE_ID_TOSHIBA_TOPIC95,
339 "Toshiba ToPIC95 PCI-CardBus Bridge",
340 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
341 { PCI_DEVICE_ID_TOSHIBA_TOPIC95B,
342 "Toshiba ToPIC95B PCI-CardBus Bridge",
343 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
344 { PCI_DEVICE_ID_TOSHIBA_TOPIC97,
345 "Toshiba ToPIC97 PCI-CardBus Bridge",
346 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
347 { PCI_DEVICE_ID_TOSHIBA_TOPIC100,
348 "Toshiba ToPIC100 PCI-CardBus Bridge",
349 PCIC_I82365, PCIC_CARDBUS_POWER, &pcic_pci_topic_chip },
350 { 0, NULL, 0, 0, NULL }
354 * Read a register from the PCIC.
357 pcic_pci_getb2(struct pcic_slot *sp, int reg)
359 return (bus_space_read_1(sp->bst, sp->bsh, sp->offset + reg));
363 * Write a register on the PCIC
366 pcic_pci_putb2(struct pcic_slot *sp, int reg, unsigned char val)
368 bus_space_write_1(sp->bst, sp->bsh, sp->offset + reg, val);
372 * lookup inside the table
374 static struct pcic_pci_table *
375 pcic_pci_lookup(u_int32_t devid, struct pcic_pci_table *tbl)
378 if (tbl->devid == devid)
386 * The standard way to control fuction interrupts is via bit 7 in the BCR
387 * register. Some data sheets indicate that this is just for "intterupts"
388 * while others are clear that it is for function interrupts. When this
389 * bit is set, function interrupts are routed via the ExCA register. When
390 * this bit is clear, they are routed via the PCI bus, usually via the int
391 * in the INTPIN register.
394 pcic_pci_gen_func(struct pcic_slot *sp, enum pcic_intr_way way)
398 bcr = pci_read_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, 2);
399 if (way == pcic_iw_pci)
400 bcr &= ~CB_BCR_INT_EXCA;
402 bcr |= CB_BCR_INT_EXCA;
403 pci_write_config(sp->sc->dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
408 pcic_pci_gen_csc(struct pcic_slot *sp, enum pcic_intr_way way)
414 * The O2micro OZ67xx chips functions.
417 pcic_pci_oz67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
419 return (pcic_pci_gen_func(sp, way));
423 pcic_pci_oz67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
426 * Need datasheet to find out what's going on. However, the
427 * 68xx datasheets are so vague that it is hard to know what
428 * the right thing to do is.
436 pcic_pci_oz67xx_init(device_t dev)
438 device_printf(dev, "Warning: O2micro OZ67xx chips may not work\n");
439 pcic_pci_cardbus_init(dev);
443 * The O2micro OZ68xx chips functions.
446 pcic_pci_oz68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
448 return (pcic_pci_gen_func(sp, way));
452 pcic_pci_oz68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
455 * The 68xx datasheets make it hard to know what the right thing
456 * to do here is. We do what we know, which is nothing, and
464 pcic_pci_oz68xx_init(device_t dev)
467 * This is almost certainly incomplete.
469 device_printf(dev, "Warning: O2micro OZ68xx chips may not work\n");
470 pcic_pci_cardbus_init(dev);
474 * The Cirrus Logic PD6729/30. These are weird beasts, so be careful.
475 * They are ISA parts glued to the PCI bus and do not follow the yenta
476 * specification for cardbus bridges. They seem to be similar to the
477 * intel parts that were also cloned by o2micro and maybe others, but
478 * they are so much more common that the author doesn't have experience
479 * with them to know for sure.
482 pcic_pci_pd67xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
485 * For pci interrupts, we need to set bit 3 of extension register
486 * 3 to 1. For ISA interrupts, we need to clear it.
488 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
489 if (way == pcic_iw_pci)
490 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
492 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CARD_IRQ_INV);
498 pcic_pci_pd67xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
501 * For pci interrupts, we need to set bit 4 of extension register
502 * 3 to 1. For ISA interrupts, we need to clear it.
504 sp->putb(sp, PCIC_EXT_IND, PCIC_EXTCTRL1);
505 if (way == pcic_iw_pci)
506 pcic_setb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
508 pcic_clrb(sp, PCIC_EXTENDED, PCIC_EC1_CSC_IRQ_INV);
515 pcic_pci_pd67xx_init(device_t dev)
517 struct pcic_softc *sc = device_get_softc(dev);
519 if (sc->csc_route == pcic_iw_pci || sc->func_route == pcic_iw_pci)
520 device_printf(dev, "PD67xx maybe broken for PCI routing.\n");
524 * Set up the CL-PD6832, 6833 and 6834.
527 pcic_pci_pd68xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
529 return (pcic_pci_gen_func(sp, way));
533 pcic_pci_pd68xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
535 struct pcic_softc *sc = sp->sc;
536 device_t dev = sc->dev;
537 u_int32_t device_id = pci_get_devid(dev);
542 * CLPD6832 management interrupt enable bit is bit 11
543 * (MGMT_IRQ_ENA) in bridge control register(offset 0x3d).
544 * When on, card status interrupts are ISA controlled by
545 * the ExCA register 0x05.
547 * The CLPD6833 does things differently. It doesn't have bit
548 * 11 in the bridge control register. Instead, this
549 * functionality appears to be in the "Configuration
550 * Miscellaneous 1" register bit 1.
552 * I'm assuming that the CLPD6834 does things like the '33
554 if (device_id == PCI_DEVICE_ID_PCIC_CLPD6832) {
555 bcr = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
556 if (way == pcic_iw_pci)
557 bcr &= ~CLPD6832_BCR_MGMT_IRQ_ENA;
559 bcr |= CLPD6832_BCR_MGMT_IRQ_ENA;
560 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, bcr, 2);
562 if (device_id != PCI_DEVICE_ID_PCIC_CLPD6832) {
563 cm1 = pci_read_config(dev, CLPD6833_CFG_MISC_1, 4);
564 if (way == pcic_iw_pci)
565 cm1 &= ~CLPD6833_CM1_MGMT_EXCA_ENA;
567 cm1 |= CLPD6833_CM1_MGMT_EXCA_ENA;
568 pci_write_config(dev, CLPD6833_CFG_MISC_1, cm1, 4);
574 pcic_pci_pd68xx_init(device_t dev)
576 pcic_pci_cardbus_init(dev);
580 pcic_pci_ricoh_func(struct pcic_slot *sp, enum pcic_intr_way way)
582 return (pcic_pci_gen_func(sp, way));
586 pcic_pci_ricoh_csc(struct pcic_slot *sp, enum pcic_intr_way way)
588 struct pcic_softc *sc = sp->sc;
589 device_t dev = sc->dev;
593 * For CSC interrupts via ISA, we can't do that exactly.
594 * However, we can disable INT# routing, which is usually what
595 * we want. This is bit 7 in the field. Note, bit 6 looks
596 * interesting, but appears to be unnecessary.
598 mcr2 = pci_read_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, 2);
599 if (way == pcic_iw_pci)
600 mcr2 &= ~R5C47X_MCR2_CSC_TO_INTX_DISABLE;
602 mcr2 |= R5C47X_MCR2_CSC_TO_INTX_DISABLE;
603 pci_write_config(dev, R5C47X_MISC_CONTROL_REGISTER_2, mcr2, 2);
609 pcic_pci_ricoh_init(device_t dev)
612 u_int32_t device_id = pci_get_devid(dev);
615 case PCI_DEVICE_ID_RICOH_RL5C465:
616 case PCI_DEVICE_ID_RICOH_RL5C466:
618 * Ricoh chips have a legacy bridge enable different than most
619 * Code cribbed from NEWBUS's bridge code since I can't find a
620 * datasheet for them that has register definitions.
622 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
623 brgcntl &= ~(CB_BCR_RL_3E2_EN | CB_BCR_RL_3E0_EN);
624 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
627 pcic_pci_cardbus_init(dev);
631 * TI 1030, 1130, and 1131.
634 pcic_pci_ti113x_func(struct pcic_slot *sp, enum pcic_intr_way way)
637 device_t dev = sp->sc->dev;
640 * The TI-1130 (and 1030 and 1131) have a different interrupt
641 * routing control than the newer cards. assume we're not
642 * routing PCI, but enable as necessary when we find someone
643 * uses PCI interrupts. In order to get any pci interrupts,
644 * PCI_IRQ_ENA (bit 5) must be set. If either PCI_IREQ (bit
645 * 4) or PCI_CSC (bit 3) are set, then set bit 5 at the same
646 * time, since setting them enables the PCI interrupt routing.
648 * It also appears necessary to set the function routing bit
649 * in the bridge control register, but cardbus_init does that
652 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
653 if (way == pcic_iw_pci)
654 cardcntl |= TI113X_CARDCNTL_PCI_IREQ;
656 cardcntl &= ~TI113X_CARDCNTL_PCI_IREQ;
657 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
658 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
660 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
661 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
663 return (pcic_pci_gen_func(sp, way));
667 pcic_pci_ti113x_csc(struct pcic_slot *sp, enum pcic_intr_way way)
670 device_t dev = sp->sc->dev;
673 * The TI-1130 (and 1030 and 1131) have a different interrupt
674 * routing control than the newer cards. assume we're not
675 * routing PCI, but enable as necessary when we find someone
676 * uses PCI interrupts. In order to get any pci interrupts,
677 * PCI_IRQ_ENA (bit 5) must be set. If either PCI_IREQ (bit
678 * 4) or PCI_CSC (bit 3) are set, then set bit 5 at the same
679 * time, since setting them enables the PCI interrupt routing.
681 * It also appears necessary to set the function routing bit
682 * in the bridge control register, but cardbus_init does that
685 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
686 if (way == pcic_iw_pci)
687 cardcntl |= TI113X_CARDCNTL_PCI_CSC;
689 cardcntl &= ~TI113X_CARDCNTL_PCI_CSC;
690 if (cardcntl & (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC))
691 cardcntl |= TI113X_CARDCNTL_PCI_IRQ_ENA;
693 cardcntl &= ~TI113X_CARDCNTL_PCI_IRQ_ENA;
694 pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
700 pcic_pci_ti12xx_func(struct pcic_slot *sp, enum pcic_intr_way way)
702 return (pcic_pci_gen_func(sp, way));
706 pcic_pci_ti12xx_csc(struct pcic_slot *sp, enum pcic_intr_way way)
709 * Nothing happens here. The TI12xx parts will route the
710 * CSC interrupt via PCI if ExCA register tells it to use
711 * interrupt 0. And via IRQ otherwise (except for reserved
712 * values which may or may not do anything).
714 * We just hope for the best here that doing nothing is the
721 * TI PCI-CardBus Host Adapter specific function code.
722 * This function is separated from pcic_pci_attach().
723 * Takeshi Shibagaki(shiba@jp.freebsd.org).
726 pcic_pci_ti_init(device_t dev)
728 u_int32_t syscntl, diagctl, devcntl, cardcntl;
729 u_int32_t device_id = pci_get_devid(dev);
730 struct pcic_softc *sc = device_get_softc(dev);
731 int ti113x = (device_id == PCI_DEVICE_ID_PCIC_TI1031) ||
732 (device_id == PCI_DEVICE_ID_PCIC_TI1130) ||
733 (device_id == PCI_DEVICE_ID_PCIC_TI1131);
735 syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
736 devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
737 cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
740 device_printf(dev, "TI113X PCI Config Reg: ");
741 if (syscntl & TI113X_SYSCNTL_CLKRUN_ENA) {
742 if (syscntl & TI113X_SYSCNTL_CLKRUN_SEL)
743 printf("[clkrun irq 12]");
745 printf("[clkrun irq 10]");
748 device_printf(dev, "TI12XX PCI Config Reg: ");
751 * Turn on async CSC interrupts. This appears to
752 * be the default, but the old, pre pci-aware, code
753 * did this and it appears PAO does as well.
755 diagctl = pci_read_config(dev, TI12XX_PCI_DIAGNOSTIC, 1);
756 diagctl |= TI12XX_DIAG_CSC_INTR;
757 pci_write_config(dev, TI12XX_PCI_DIAGNOSTIC, diagctl, 1);
760 * Turn off Zoom Video. Some cards have this enabled,
761 * some do not but it causes problems when enabled. This
762 * register doesn't exist on the 1130 (and likely the 1131,
763 * but without a datasheet it is impossible to know).
764 * Some 12xx chips may not have it, but setting it is
765 * believed to be harmless.
767 pci_write_config(dev, TI12XX_PCI_MULTIMEDIA_CONTROL, 0, 4);
770 * Special code for the Orinoco cards (and a few others). They
771 * seem to need this special code to make them work only over pci
772 * interrupts. Sadly, doing this code also causes problems for
773 * many laptops, so we have to make it controlled by a tunable.
775 if (sc->func_route == pcic_iw_pci) {
776 if (pcic_init_routing) {
777 devcntl &= ~TI113X_DEVCNTL_INTR_MASK;
778 pci_write_config(dev, TI113X_PCI_DEVICE_CONTROL,
780 devcntl = pci_read_config(dev,
781 TI113X_PCI_DEVICE_CONTROL, 1);
782 syscntl |= TI113X_SYSCNTL_INTRTIE;
784 syscntl &= ~TI113X_SYSCNTL_SMIENB;
785 pci_write_config(dev, TI113X_PCI_SYSTEM_CONTROL, syscntl, 1);
787 if (cardcntl & TI113X_CARDCNTL_RING_ENA)
788 printf("[ring enable]");
789 if (cardcntl & TI113X_CARDCNTL_SPKR_ENA)
790 printf("[speaker enable]");
791 if (syscntl & TI113X_SYSCNTL_PWRSAVINGS)
792 printf("[pwr save]");
793 switch(devcntl & TI113X_DEVCNTL_INTR_MASK){
794 case TI113X_DEVCNTL_INTR_ISA :
795 printf("[CSC parallel isa irq]");
797 case TI113X_DEVCNTL_INTR_SERIAL :
798 printf("[CSC serial isa irq]");
800 case TI113X_DEVCNTL_INTR_NONE :
801 printf("[pci only]");
803 case TI12XX_DEVCNTL_INTR_ALLSERIAL :
804 printf("[FUNC pci int + CSC serial isa irq]");
808 pcic_pci_cardbus_init(dev);
812 * Code for TOPIC chips
815 pcic_pci_topic_func(struct pcic_slot *sp, enum pcic_intr_way way)
817 #ifdef THIS_BRAEKS_THINGS
818 device_t dev = sp->sc->dev;
821 scr = pci_read_config(dev, TOPIC_SOCKET_CTRL, 4);
822 if (way == pcic_iw_pci)
823 scr |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
825 scr &= ~TOPIC_SOCKET_CTRL_SCR_IRQSEL;
826 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
828 return (pcic_pci_gen_func(sp, way));
832 pcic_pci_topic_csc(struct pcic_slot *sp, enum pcic_intr_way way)
834 device_t dev = sp->sc->dev;
838 device_id = pci_get_devid(dev);
839 if (device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC100 ||
840 device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC97) {
841 scr = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
842 if (way == pcic_iw_pci)
843 scr |= TOPIC97_SLOT_CTRL_PCIINT;
845 scr &= ~TOPIC97_SLOT_CTRL_PCIINT;
846 pci_write_config(dev, TOPIC_SLOT_CTRL, scr, 4);
853 pcic_pci_topic_init(device_t dev)
855 struct pcic_softc *sc = device_get_softc(dev);
859 device_id = pci_get_devid(dev);
860 reg = pci_read_config(dev, TOPIC_SLOT_CTRL, 4);
861 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
862 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
863 reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
864 if (device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC100 ||
865 device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC97) {
866 reg |= TOPIC97_SLOT_CTRL_PCIINT;
867 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
869 pci_write_config(dev, TOPIC_SLOT_CTRL, reg, 4);
870 pcic_pci_cardbus_init(dev);
872 if (device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC100 ||
873 device_id == PCI_DEVICE_ID_TOSHIBA_TOPIC97) {
875 * We need to enable voltage sense and 3V cards explicitly
876 * in the bridge. The datasheets I have for both the
877 * ToPIC 97 and 100 both lists these ports. Without
878 * datasheets for the ToPIC95s, I can't tell if we need
879 * to do it there or not.
881 pcic_setb(&sc->slots[0], PCIC_TOPIC_FCR,
882 PCIC_FCR_3V_EN | PCIC_FCR_VS_EN);
887 pcic_pci_cardbus_init(device_t dev)
889 struct pcic_softc *sc = device_get_softc(dev);
893 unit = device_get_unit(dev);
895 brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
896 brgcntl |= CB_BCR_WRITE_POST_EN | CB_BCR_MASTER_ABORT;
897 pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
899 /* Turn off legacy address */
900 pci_write_config(dev, CB_PCI_LEGACY16_IOADDR, 0, 2);
903 * Write zeros into the remaining memory I/O windows. This
904 * seems to turn off the pci configuration of these things and
905 * make the cardbus bridge use the values for memory
906 * programmed into the pcic registers.
908 pci_write_config(dev, CB_PCI_MEMBASE0, 0, 4);
909 pci_write_config(dev, CB_PCI_MEMLIMIT0, 0, 4);
910 pci_write_config(dev, CB_PCI_MEMBASE1, 0, 4);
911 pci_write_config(dev, CB_PCI_MEMLIMIT1, 0, 4);
912 pci_write_config(dev, CB_PCI_IOBASE0, 0, 4);
913 pci_write_config(dev, CB_PCI_IOLIMIT0, 0, 4);
914 pci_write_config(dev, CB_PCI_IOBASE1, 0, 4);
915 pci_write_config(dev, CB_PCI_IOLIMIT1, 0, 4);
918 * Tell the chip to do its routing thing.
920 sc->chip->func_intr_way(&sc->slots[0], sc->func_route);
921 sc->chip->csc_intr_way(&sc->slots[0], sc->csc_route);
927 pcic_pci_cardtype(u_int32_t stat)
929 if (stat & CB_SS_NOTCARD)
930 return ("unrecognized by bridge");
931 if ((stat & (CB_SS_16BIT | CB_SS_CB)) == (CB_SS_16BIT | CB_SS_CB))
932 return ("16-bit and 32-bit (can't happen)");
933 if (stat & CB_SS_16BIT)
934 return ("16-bit pccard");
936 return ("32-bit cardbus");
937 return ("none (can't happen)");
941 * Card insertion and removal code. The insertion events need to be
942 * debounced so that the noisy insertion/removal events don't result
943 * in the hardware being initialized many times, only to be torn down
944 * as well. This may also cause races with pccardd. Instead, we wait
945 * for the insertion signal to be stable for 0.5 seconds before we declare
946 * it to be a real insertion event. Removal is also debounced. We turn
947 * off interrupt servicing during the settling time to prevent infinite
948 * loops in the driver.
950 * Note: We only handle the card detect change events. We don't handle
951 * power events and status change events.
954 pcic_cd_change(void *arg)
956 struct pcic_softc *sc = (struct pcic_softc *) arg;
957 struct pcic_slot *sp = &sc->slots[0];
961 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
963 /* Status changed while present; remove the card from the system. */
964 if (sc->cd_present) {
966 pccard_event(sp->slt, card_removed);
968 /* Nothing to do if the debounced state is 'not present'. */
969 if ((stat & CB_SS_CD) != 0)
973 if (bootverbose && (stat & CB_SS_BADVCC) != 0)
974 device_printf(sc->dev, "BAD Vcc request: 0x%x\n", stat);
975 if ((stat & CB_SS_16BIT) == 0)
976 device_printf(sp->sc->dev, "Card type %s is unsupported\n",
977 pcic_pci_cardtype(stat));
979 pccard_event(sp->slt, card_inserted);
983 pcic_pci_intr(void *arg)
985 struct pcic_softc *sc = (struct pcic_softc *) arg;
986 struct pcic_slot *sp = &sc->slots[0];
989 event = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_EVENT);
992 device_printf(sc->dev, "Event mask 0x%x\n", event);
995 * Treat all card-detect signal transitions the same way
996 * since we can't reliably tell if this is an insert or a
997 * remove event. Stop the card from getting interrupts and
998 * defer the insert/remove event until the CB_SOCKET_STATE
999 * signals have had time to settle.
1001 if ((event & CB_SE_CD) != 0) {
1002 if (sc->cd_pending) {
1003 untimeout(pcic_cd_change, arg, sc->cd_ch);
1007 sc->cd_ch = timeout(pcic_cd_change, arg, hz/2);
1008 sc->func_intr = NULL;
1011 /* Ack the interrupt */
1012 bus_space_write_4(sp->bst, sp->bsh, 0, event);
1016 * Some TI chips also require us to read the old ExCA register for
1017 * card status change when we route CSC via PCI! So, we go ahead
1018 * and read it to clear the bits. Maybe we should check the status
1019 * ala the ISA interrupt handler, but those changes should be caught
1022 * We have to check it every interrupt because these bits can sometimes
1023 * show up indepentently of the CB_SOCKET_EVENT register above.
1025 sp->getb(sp, PCIC_STAT_CHG);
1029 * Return the ID string for the controller if the vendor/product id
1030 * matches, NULL otherwise.
1033 pcic_pci_probe(device_t dev)
1038 u_int32_t device_id;
1039 struct pcic_pci_table *itm;
1040 struct resource *res;
1043 if (pcic_ignore_pci)
1045 device_id = pci_get_devid(dev);
1047 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1048 if (pcic_ignore_function_1 && pci_get_function(dev) == 1) {
1050 PRVERB((dev, "Ignoring function 1\n"));
1055 if (desc == NULL && pci_get_class(dev) == PCIC_BRIDGE) {
1056 subclass = pci_get_subclass(dev);
1057 progif = pci_get_progif(dev);
1058 if (subclass == PCIS_BRIDGE_PCMCIA && progif == 0)
1059 desc = "Generic PCI-PCMCIA Bridge";
1060 if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0)
1061 desc = "YENTA PCI-CardBus Bridge";
1062 if (bootverbose && desc)
1063 printf("Found unknown %s devid 0x%x\n", desc, device_id);
1067 device_set_desc(dev, desc);
1070 * Take us out of power down mode, if necessary. It also
1071 * appears that even reading the power register is enough on
1072 * some systems to cause correct behavior.
1074 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1075 /* Reset the power state. */
1076 device_printf(dev, "chip is in D%d power mode "
1077 "-- setting to D0\n", pci_get_powerstate(dev));
1078 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1082 * Allocated/deallocate interrupt. This forces the PCI BIOS or
1083 * other MD method to route the interrupts to this card.
1084 * This so we get the interrupt number in the probe message.
1085 * We only need to route interrupts when we're doing pci
1086 * parallel interrupt routing.
1088 * We use two different variables for the memory based and I/O
1089 * based cards, so the check here is a little more complex than
1090 * one would otherwise hope.
1092 * XXX The bus code for PCI really should do this for us.
1094 if ((pcic_intr_path == pcic_iw_pci &&
1095 device_id != PCI_DEVICE_ID_PCIC_CLPD6729) ||
1096 (pcic_pd6729_intr_path == pcic_iw_pci &&
1097 device_id == PCI_DEVICE_ID_PCIC_CLPD6729)) {
1101 * IRQ 0 is invalid on x86, but not other platforms.
1102 * If we have irq 0, then write 255 to force a new, non-
1103 * bogus one to be assigned. I think that in -current
1104 * the code in this ifdef may be obsolete with the new
1105 * invalid mapping that we're doing in the pci layer -- imp
1107 if (pci_get_irq(dev) == 0) {
1108 pci_set_irq(dev, 255);
1109 pci_write_config(dev, PCIR_INTLINE, 255, 1);
1112 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1115 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
1122 pcic_pci_shutdown(device_t dev)
1125 * More reports of things working w/o this code than with it.
1128 struct pcic_softc *sc;
1129 struct pcic_slot *sp;
1131 sc = (struct pcic_softc *) device_get_softc(dev);
1135 * Turn off the power to the slot in an attempt to
1136 * keep the system from hanging on reboot. We also turn off
1137 * card interrupts in an attempt to control interrupt storms.
1138 * on some (all?) this has the effect of also turning off
1139 * card status change interrupts. A side effect of writing 0
1140 * to INT_GEN is that the card is placed into "reset" mode
1141 * where nothing happens until it is taken out of "reset"
1144 * Also, turn off the generation of status interrupts too.
1146 sp->putb(sp, PCIC_INT_GEN, 0);
1147 sp->putb(sp, PCIC_STAT_INT, 0);
1148 sp->putb(sp, PCIC_POWER, 0);
1152 * Writing to INT_GEN can cause an interrupt, so we blindly
1153 * ack all possible interrupts here. Reading the stat change
1154 * shouldn't be necessary, but some TI chipsets need it in the
1155 * normal course of operations, so we do it here too. We can't
1156 * lose any interrupts after this point, so go ahead and ack
1157 * everything. The bits in INT_GEN clear upon reading them.
1158 * We also set the interrupt mask to 0, in an effort to avoid
1159 * getting further interrupts.
1161 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_MASK, 0);
1162 bus_space_write_4(sp->bst, sp->bsh, CB_SOCKET_EVENT, 0xffffffff);
1163 sp->getb(sp, PCIC_STAT_CHG);
1168 * Print out the config space
1171 pcic_pci_print_config(device_t dev)
1175 device_printf(dev, "PCI Configuration space:");
1176 for (i = 0; i < 256; i += 4) {
1178 printf("\n 0x%02x: ", i);
1179 printf("0x%08x ", pci_read_config(dev, i, 4));
1185 * Generic pci interrupt attach routine. It tries to understand all parts,
1186 * and do sane things for those parts it does not understand.
1189 pcic_pci_attach(device_t dev)
1191 u_int32_t device_id = pci_get_devid(dev);
1193 struct pcic_slot *sp;
1194 struct pcic_softc *sc;
1197 struct pcic_pci_table *itm;
1200 struct resource *r = NULL;
1203 driver_intr_t *intr = NULL;
1206 * In sys/pci/pcireg.h, PCIR_COMMAND must be separated
1207 * PCI_COMMAND_REG(0x04) and PCI_STATUS_REG(0x06).
1208 * Takeshi Shibagaki(shiba@jp.freebsd.org).
1210 command = pci_read_config(dev, PCIR_COMMAND, 4);
1211 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN;
1212 pci_write_config(dev, PCIR_COMMAND, command, 4);
1214 sc = (struct pcic_softc *) device_get_softc(dev);
1217 sockbase = pci_read_config(dev, 0x10, 4);
1218 if (sockbase & 0x1) {
1219 sc->iorid = CB_PCI_SOCKET_BASE;
1220 sc->iores = bus_alloc_resource(dev, SYS_RES_IOPORT,
1221 &sc->iorid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
1222 if (sc->iores == NULL)
1225 sc->flags = PCIC_PD_POWER;
1226 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1227 for (i = 0; i < 2; i++) {
1228 sp[i].bst = rman_get_bustag(sc->iores);
1229 sp[i].bsh = rman_get_bushandle(sc->iores);
1232 sp[i].getb = pcic_getb_io;
1233 sp[i].putb = pcic_putb_io;
1234 sp[i].offset = i * PCIC_SLOT_SIZE;
1235 sp[i].controller = itm ? itm->type : PCIC_PD6729;
1236 if ((sp[i].getb(&sp[i], PCIC_ID_REV) & 0xc0) == 0x80)
1237 sp[i].slt = (struct slot *) 1;
1239 sc->csc_route = sc->func_route = pcic_pd6729_intr_path;
1241 sc->flags = itm->flags;
1243 * We have to use the ISA interrupt routine for status
1244 * changes since we don't have any "yenta" pci registers.
1245 * We have to do this even when we're using pci type
1246 * interrupts because on these cards the interrupts are
1247 * cleared in the same way that the ISA cards clear them.
1249 intr = pcic_isa_intr;
1251 sc->memrid = CB_PCI_SOCKET_BASE;
1252 sc->memres = bus_alloc_resource(dev, SYS_RES_MEMORY,
1253 &sc->memrid, 0, ~0, 1, RF_ACTIVE);
1254 if (sc->memres == NULL && pcic_pci_get_memory(dev) != 0)
1256 sp->getb = pcic_pci_getb2;
1257 sp->putb = pcic_pci_putb2;
1258 sp->offset = CB_EXCA_OFFSET;
1259 sp->bst = rman_get_bustag(sc->memres);
1260 sp->bsh = rman_get_bushandle(sc->memres);
1261 itm = pcic_pci_lookup(device_id, &pcic_pci_devs[0]);
1263 sp->controller = itm->type;
1265 sc->flags = itm->flags;
1267 /* By default, assume we're a D step compatible */
1268 sp->controller = PCIC_I82365SL_DF;
1270 sc->flags = PCIC_CARDBUS_POWER;
1272 /* All memory mapped cardbus bridges have these registers */
1273 sc->flags |= PCIC_YENTA_HIGH_MEMORY;
1274 sp->slt = (struct slot *) 1;
1275 sc->csc_route = pcic_intr_path;
1276 sc->func_route = pcic_intr_path;
1277 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1278 sc->cd_present = (stat & CB_SS_CD) == 0;
1282 sc->chip = itm->chip;
1284 sc->chip = &pcic_pci_generic_chip;
1286 if (sc->csc_route == pcic_iw_pci) {
1288 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1289 RF_ACTIVE | RF_SHAREABLE);
1291 sc->csc_route = pcic_iw_isa;
1292 sc->func_route = pcic_iw_isa;
1294 "No PCI interrupt routed, trying ISA.\n");
1297 intr = pcic_pci_intr;
1298 irq = rman_get_start(r);
1301 if (sc->csc_route == pcic_iw_isa) {
1303 irq = pcic_override_irq;
1305 r = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, irq,
1309 "Can't route ISA CSC interrupt.\n");
1314 "Management interrupt on ISA IRQ %ld\n", irq);
1316 intr = pcic_isa_intr;
1318 sc->slot_poll = pcic_timeout;
1319 sc->timeout_ch = timeout(sc->slot_poll, sc, hz/2);
1320 device_printf(dev, "Polling mode\n");
1326 * Initialize AFTER we figure out what kind of interrupt we're
1327 * going to be using, if any.
1330 panic("Bug: sc->chip not set!\n");
1331 sc->chip->init(dev);
1334 * Now install the interrupt handler, if necessary.
1340 error = bus_setup_intr(dev, r, INTR_TYPE_AV, intr, sc, &sc->ih);
1347 pcic_pci_print_config(dev);
1348 return (pcic_attach(dev));
1352 pcic_pci_detach(device_t dev)
1354 return (EBUSY); /* Can't detach this device */
1358 * The PCI bus should do this for us. However, it doesn't quite yet, so
1359 * we cope by doing it ourselves. If it ever does, this code can go quietly
1360 * into that good night.
1363 pcic_pci_get_memory(device_t dev)
1365 struct pcic_softc *sc;
1368 sc = (struct pcic_softc *) device_get_softc(dev);
1369 sockbase = pci_read_config(dev, sc->memrid, 4);
1370 if (sockbase >= 0x100000 && sockbase < 0xfffffff0) {
1371 device_printf(dev, "Could not map register memory\n");
1374 pci_write_config(dev, sc->memrid, 0xffffffff, 4);
1375 sockbase = pci_read_config(dev, sc->memrid, 4);
1376 sockbase = (sockbase & 0xfffffff0) & -(sockbase & 0xfffffff0);
1377 #define CARDBUS_SYS_RES_MEMORY_START 0x88000000
1378 #define CARDBUS_SYS_RES_MEMORY_END 0xFFFFFFFF
1379 sc->memres = bus_generic_alloc_resource(device_get_parent(dev),
1380 dev, SYS_RES_MEMORY, &sc->memrid,
1381 CARDBUS_SYS_RES_MEMORY_START, CARDBUS_SYS_RES_MEMORY_END,
1382 sockbase, RF_ACTIVE | rman_make_alignment_flags(sockbase));
1383 if (sc->memres == NULL) {
1384 device_printf(dev, "Could not grab register memory\n");
1387 sockbase = rman_get_start(sc->memres);
1388 pci_write_config(dev, sc->memrid, sockbase, 4);
1389 device_printf(dev, "PCI Memory allocated: 0x%08x\n", sockbase);
1394 pcic_pci_gen_mapirq(struct pcic_slot *sp, int irq)
1397 * If we're doing ISA interrupt routing, then just go to the
1398 * generic ISA routine. Also, irq 0 means turn off the interrupts
1401 if (sp->sc->func_route == pcic_iw_isa || irq == 0)
1402 return (pcic_isa_mapirq(sp, irq));
1405 * Ohterwise we're doing PCI interrupts. For those cardbus bridges
1406 * that follow yenta (and the one pcmcia bridge that does), we don't
1407 * do a thing to get the IRQ mapped into the system. However,
1408 * for other controllers that are PCI, but not yetna compliant, we
1409 * need to do some special mapping.
1411 if (sp->controller == PCIC_PD6729) {
1418 sp->putb(sp, PCIC_INT_GEN, /* Assume INTA# */
1419 (sp->getb(sp, PCIC_INT_GEN) & 0xF0) | 3);
1426 pcic_pci_func_intr(void *arg)
1428 struct pcic_softc *sc = (struct pcic_softc *) arg;
1429 struct pcic_slot *sp = &sc->slots[0];
1434 * The 6729 controller is a weird one, and we have to use
1435 * the ISA registers to check to see if the card is there.
1436 * Otherwise we look at the PCI state register to find out
1437 * if the card is there.
1439 if (sp->controller == PCIC_PD6729) {
1440 if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) == PCIC_CD)
1444 stat = bus_space_read_4(sp->bst, sp->bsh, CB_SOCKET_STATE);
1445 if ((stat & CB_SS_CD) == 0 && sc->func_intr != 0)
1448 if (doit && sc->func_intr != NULL)
1449 sc->func_intr(sc->func_arg);
1453 pcic_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
1454 int flags, driver_intr_t *intr, void *arg, void **cookiep)
1456 struct pcic_softc *sc = device_get_softc(dev);
1457 struct pcic_slot *sp = &sc->slots[0];
1460 if (sc->func_route == pcic_iw_isa)
1461 return(pcic_setup_intr(dev, child, irq, flags, intr, arg,
1464 #if __FreeBSD_version >= 500000
1465 if ((flags & INTR_FAST) != 0)
1467 if ((flags & INTR_TYPE_FAST) != 0)
1470 if (sc->func_intr != NULL) {
1471 device_printf(child, "Can't establish another ISR\n");
1475 err = bus_generic_setup_intr(dev, child, irq, flags,
1476 pcic_pci_func_intr, sc, cookiep);
1479 sc->chip->map_irq(sp, rman_get_start(irq));
1480 sc->func_intr = intr;
1486 pcic_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
1489 struct pcic_softc *sc = device_get_softc(dev);
1491 if (sc->func_route == pcic_iw_isa)
1492 return (pcic_teardown_intr(dev, child, irq, cookie));
1493 sc->func_intr = NULL;
1494 return (bus_generic_teardown_intr(dev, child, irq, cookie));
1498 pcic_pci_resume(device_t dev)
1500 struct pcic_softc *sc = device_get_softc(dev);
1503 * Some BIOSes will not save the BARs for the pci chips, so we
1504 * must do it ourselves. If the BAR is reset to 0 for an I/O
1505 * device, it will read back as 0x1, so no explicit test for
1506 * memory devices are needed.
1508 * Note: The PCI bus code should do this automatically for us on
1509 * suspend/resume, but until it does, we have to cope.
1511 if (pci_read_config(dev, CB_PCI_SOCKET_BASE, 4) == 0)
1512 pci_write_config(dev, CB_PCI_SOCKET_BASE,
1513 rman_get_start(sc->memres), 4);
1514 return (bus_generic_resume(dev));
1517 static device_method_t pcic_pci_methods[] = {
1518 /* Device interface */
1519 DEVMETHOD(device_probe, pcic_pci_probe),
1520 DEVMETHOD(device_attach, pcic_pci_attach),
1521 DEVMETHOD(device_detach, pcic_pci_detach),
1522 DEVMETHOD(device_suspend, bus_generic_suspend),
1523 DEVMETHOD(device_resume, pcic_pci_resume),
1524 DEVMETHOD(device_shutdown, pcic_pci_shutdown),
1527 DEVMETHOD(bus_print_child, bus_generic_print_child),
1528 DEVMETHOD(bus_alloc_resource, pcic_alloc_resource),
1529 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
1530 DEVMETHOD(bus_activate_resource, pcic_activate_resource),
1531 DEVMETHOD(bus_deactivate_resource, pcic_deactivate_resource),
1532 DEVMETHOD(bus_setup_intr, pcic_pci_setup_intr),
1533 DEVMETHOD(bus_teardown_intr, pcic_pci_teardown_intr),
1535 /* Card interface */
1536 DEVMETHOD(card_set_res_flags, pcic_set_res_flags),
1537 DEVMETHOD(card_get_res_flags, pcic_get_res_flags),
1538 DEVMETHOD(card_set_memory_offset, pcic_set_memory_offset),
1539 DEVMETHOD(card_get_memory_offset, pcic_get_memory_offset),
1544 static driver_t pcic_pci_driver = {
1547 sizeof(struct pcic_softc)
1550 DRIVER_MODULE(pcic, pci, pcic_pci_driver, pcic_devclass, 0, 0);