2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
30 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
45 #include <sys/mutex.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <pci/agppriv.h>
51 #include <pci/agpreg.h>
54 #include <vm/vm_object.h>
55 #include <vm/vm_page.h>
56 #include <vm/vm_pageout.h>
59 #include <machine/bus.h>
60 #include <machine/resource.h>
63 MALLOC_DECLARE(M_AGP);
65 #define READ1(off) bus_space_read_1(sc->bst, sc->bsh, off)
66 #define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off)
67 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v)
68 #define WRITEGTT(off,v) bus_space_write_4(sc->gtt_bst, sc->gtt_bsh, off, v)
70 #define CHIP_I810 0 /* i810/i815 */
71 #define CHIP_I830 1 /* 830M/845G */
72 #define CHIP_I855 2 /* 852GM/855GM/865G */
73 #define CHIP_I915 3 /* 915G/915GM */
75 struct agp_i810_softc {
77 u_int32_t initial_aperture; /* aperture size at startup */
78 struct agp_gatt *gatt;
79 int chiptype; /* i810-like or i830 */
80 u_int32_t dcache_size; /* i810 only */
81 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
82 device_t bdev; /* bridge device */
84 struct resource *regs; /* memory mapped GC registers */
85 bus_space_tag_t bst; /* bus_space tag */
86 bus_space_handle_t bsh; /* bus_space handle */
88 struct resource *gtt; /* memory mapped GATT entries */
89 bus_space_tag_t gtt_bst; /* bus_space tag */
90 bus_space_handle_t gtt_bsh; /* bus_space handle */
92 struct resource *gm; /* unmapped (but allocated) aperture */
94 void *argb_cursor; /* contigmalloc area for ARGB cursor */
97 /* For adding new devices, devid is the id of the graphics controller
98 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
99 * second head should never be added. The bridge_offset is the offset to
100 * subtract from devid to get the id of the hostb that the device is on.
102 static const struct agp_i810_match {
107 } agp_i810_matches[] = {
108 {0x71218086, CHIP_I810, 0x00010000,
109 "Intel 82810 (i810 GMCH) SVGA controller"},
110 {0x71238086, CHIP_I810, 0x00010000,
111 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
112 {0x71258086, CHIP_I810, 0x00010000,
113 "Intel 82810E (i810E GMCH) SVGA controller"},
114 {0x11328086, CHIP_I810, 0x00020000,
115 "Intel 82815 (i815 GMCH) SVGA controller"},
116 {0x35778086, CHIP_I830, 0x00020000,
117 "Intel 82830M (830M GMCH) SVGA controller"},
118 {0x35828086, CHIP_I855, 0x00020000,
120 {0x25728086, CHIP_I855, 0x00020000,
121 "Intel 82865G (865G GMCH) SVGA controller"},
122 {0x25828086, CHIP_I915, 0x00020000,
123 "Intel 82915G (915G GMCH) SVGA controller"},
124 {0x25928086, CHIP_I915, 0x00020000,
125 "Intel 82915GM (915GM GMCH) SVGA controller"},
126 {0x27728086, CHIP_I915, 0x00020000,
127 "Intel 82945G (945G GMCH) SVGA controller"},
128 {0x27A28086, CHIP_I915, 0x00020000,
129 "Intel 82945GM (945GM GMCH) SVGA controller"},
133 static const struct agp_i810_match*
134 agp_i810_match(device_t dev)
138 if (pci_get_class(dev) != PCIC_DISPLAY
139 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
142 devid = pci_get_devid(dev);
143 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
144 if (agp_i810_matches[i].devid == devid)
147 if (agp_i810_matches[i].devid == 0)
150 return &agp_i810_matches[i];
154 * Find bridge device.
157 agp_i810_find_bridge(device_t dev)
159 device_t *children, child;
162 const struct agp_i810_match *match;
164 match = agp_i810_match(dev);
165 devid = match->devid - match->bridge_offset;
167 if (device_get_children(device_get_parent(device_get_parent(dev)),
168 &children, &nchildren))
171 for (i = 0; i < nchildren; i++) {
174 if (pci_get_devid(child) == devid) {
175 free(children, M_TEMP);
179 free(children, M_TEMP);
184 agp_i810_identify(driver_t *driver, device_t parent)
187 if (device_find_child(parent, "agp", -1) == NULL &&
188 agp_i810_match(parent))
189 device_add_child(parent, "agp", -1);
193 agp_i810_probe(device_t dev)
196 const struct agp_i810_match *match;
198 if (resource_disabled("agp", device_get_unit(dev)))
200 match = agp_i810_match(dev);
204 bdev = agp_i810_find_bridge(dev);
207 printf("I810: can't find bridge device\n");
212 * checking whether internal graphics device has been activated.
214 if (match->chiptype == CHIP_I810) {
217 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
218 if ((smram & AGP_I810_SMRAM_GMS)
219 == AGP_I810_SMRAM_GMS_DISABLED) {
221 printf("I810: disabled, not probing\n");
224 } else if (match->chiptype == CHIP_I830 ||
225 match->chiptype == CHIP_I855) {
228 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
229 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
230 AGP_I830_GCC1_DEV2_DISABLED) {
232 printf("I830: disabled, not probing\n");
235 } else if (match->chiptype == CHIP_I915) {
238 gcc1 = pci_read_config(bdev, AGP_I915_DEVEN, 4);
239 if ((gcc1 & AGP_I915_DEVEN_D2F0) ==
240 AGP_I915_DEVEN_D2F0_DISABLED) {
242 printf("I915: disabled, not probing\n");
247 if (match->devid == 0x35828086) {
248 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
251 "Intel 82855GME (855GME GMCH) SVGA controller");
255 "Intel 82855GM (855GM GMCH) SVGA controller");
259 "Intel 82852GME (852GME GMCH) SVGA controller");
263 "Intel 82852GM (852GM GMCH) SVGA controller");
267 "Intel 8285xM (85xGM GMCH) SVGA controller");
271 device_set_desc(dev, match->name);
274 return BUS_PROBE_DEFAULT;
278 agp_i810_attach(device_t dev)
280 struct agp_i810_softc *sc = device_get_softc(dev);
281 struct agp_gatt *gatt;
282 const struct agp_i810_match *match;
285 sc->bdev = agp_i810_find_bridge(dev);
289 error = agp_generic_attach(dev);
293 match = agp_i810_match(dev);
294 sc->chiptype = match->chiptype;
296 /* Same for i810 and i830 */
297 if (sc->chiptype == CHIP_I915)
298 rid = AGP_I915_MMADR;
300 rid = AGP_I810_MMADR;
302 sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
305 agp_generic_detach(dev);
308 sc->bst = rman_get_bustag(sc->regs);
309 sc->bsh = rman_get_bushandle(sc->regs);
311 if (sc->chiptype == CHIP_I915) {
312 rid = AGP_I915_GTTADR;
313 sc->gtt = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
316 bus_release_resource(dev, SYS_RES_MEMORY,
317 AGP_I915_MMADR, sc->regs);
318 agp_generic_detach(dev);
321 sc->gtt_bst = rman_get_bustag(sc->gtt);
322 sc->gtt_bsh = rman_get_bushandle(sc->gtt);
324 /* While agp_generic_attach allocates the AGP_APBASE resource
325 * to try to reserve the aperture, on the 915 the aperture
326 * isn't in PCIR_BAR(0), it's in PCIR_BAR(2), so it allocated
327 * the registers that we just mapped anyway. So, allocate the
328 * aperture here, which also gives us easy access to it for the
329 * agp_i810_get_aperture().
331 rid = AGP_I915_GMADR;
332 sc->gm = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0);
333 if (sc->gm == NULL) {
334 bus_release_resource(dev, SYS_RES_MEMORY,
335 AGP_I915_MMADR, sc->regs);
336 bus_release_resource(dev, SYS_RES_MEMORY,
337 AGP_I915_GTTADR, sc->regs);
338 agp_generic_detach(dev);
343 sc->initial_aperture = AGP_GET_APERTURE(dev);
345 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
347 agp_generic_detach(dev);
352 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
354 if ( sc->chiptype == CHIP_I810 ) {
355 /* Some i810s have on-chip memory called dcache */
356 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED)
357 sc->dcache_size = 4 * 1024 * 1024;
361 /* According to the specs the gatt on the i810 must be 64k */
362 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
363 0, ~0, PAGE_SIZE, 0);
364 if (!gatt->ag_virtual) {
366 device_printf(dev, "contiguous allocation failed\n");
368 agp_generic_detach(dev);
371 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
373 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
375 /* Install the GATT. */
376 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1);
377 } else if ( sc->chiptype == CHIP_I830 ) {
378 /* The i830 automatically initializes the 128k gatt on boot. */
379 unsigned int gcc1, pgtblctl;
381 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
382 switch (gcc1 & AGP_I830_GCC1_GMS) {
383 case AGP_I830_GCC1_GMS_STOLEN_512:
384 sc->stolen = (512 - 132) * 1024 / 4096;
386 case AGP_I830_GCC1_GMS_STOLEN_1024:
387 sc->stolen = (1024 - 132) * 1024 / 4096;
389 case AGP_I830_GCC1_GMS_STOLEN_8192:
390 sc->stolen = (8192 - 132) * 1024 / 4096;
394 device_printf(dev, "unknown memory configuration, disabling\n");
395 agp_generic_detach(dev);
399 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
400 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
402 /* GATT address is already in there, make sure it's enabled */
403 pgtblctl = READ4(AGP_I810_PGTBL_CTL);
405 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
407 gatt->ag_physical = pgtblctl & ~1;
408 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915) { /* CHIP_I855 */
409 unsigned int gcc1, pgtblctl, stolen;
411 /* Stolen memory is set up at the beginning of the aperture by
412 * the BIOS, consisting of the GATT followed by 4kb for the BIOS
415 if (sc->chiptype == CHIP_I855)
420 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
421 switch (gcc1 & AGP_I855_GCC1_GMS) {
422 case AGP_I855_GCC1_GMS_STOLEN_1M:
423 sc->stolen = (1024 - stolen) * 1024 / 4096;
425 case AGP_I855_GCC1_GMS_STOLEN_4M:
426 sc->stolen = (4096 - stolen) * 1024 / 4096;
428 case AGP_I855_GCC1_GMS_STOLEN_8M:
429 sc->stolen = (8192 - stolen) * 1024 / 4096;
431 case AGP_I855_GCC1_GMS_STOLEN_16M:
432 sc->stolen = (16384 - stolen) * 1024 / 4096;
434 case AGP_I855_GCC1_GMS_STOLEN_32M:
435 sc->stolen = (32768 - stolen) * 1024 / 4096;
437 case AGP_I915_GCC1_GMS_STOLEN_48M:
438 sc->stolen = (49152 - stolen) * 1024 / 4096;
440 case AGP_I915_GCC1_GMS_STOLEN_64M:
441 sc->stolen = (65536 - stolen) * 1024 / 4096;
445 device_printf(dev, "unknown memory configuration, disabling\n");
446 agp_generic_detach(dev);
450 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
451 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
453 /* GATT address is already in there, make sure it's enabled */
454 pgtblctl = READ4(AGP_I810_PGTBL_CTL);
456 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
458 gatt->ag_physical = pgtblctl & ~1;
465 agp_i810_detach(device_t dev)
467 struct agp_i810_softc *sc = device_get_softc(dev);
470 error = agp_generic_detach(dev);
474 /* Clear the GATT base. */
475 if ( sc->chiptype == CHIP_I810 ) {
476 WRITE4(AGP_I810_PGTBL_CTL, 0);
478 unsigned int pgtblctl;
479 pgtblctl = READ4(AGP_I810_PGTBL_CTL);
481 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
484 /* Put the aperture back the way it started. */
485 AGP_SET_APERTURE(dev, sc->initial_aperture);
487 if ( sc->chiptype == CHIP_I810 ) {
488 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
490 free(sc->gatt, M_AGP);
492 if (sc->chiptype == CHIP_I915) {
493 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_GMADR,
495 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_GTTADR,
497 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_MMADR,
500 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I810_MMADR,
508 agp_i810_get_aperture(device_t dev)
510 struct agp_i810_softc *sc = device_get_softc(dev);
514 switch (sc->chiptype) {
516 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
517 if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32)
518 return 32 * 1024 * 1024;
520 return 64 * 1024 * 1024;
522 temp = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
523 if ((temp & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
524 return 64 * 1024 * 1024;
526 return 128 * 1024 * 1024;
528 return 128 * 1024 * 1024;
530 /* The documentation states that AGP_I915_MSAC should have bit
531 * 1 set if the aperture is 128MB instead of 256. However,
532 * that bit appears to not get set, so we instead use the
533 * aperture resource size, which should always be correct.
535 return rman_get_size(sc->gm);
542 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
544 struct agp_i810_softc *sc = device_get_softc(dev);
545 u_int16_t miscc, gcc1;
548 switch (sc->chiptype) {
551 * Double check for sanity.
553 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
554 device_printf(dev, "bad aperture size %d\n", aperture);
558 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
559 miscc &= ~AGP_I810_MISCC_WINSIZE;
560 if (aperture == 32 * 1024 * 1024)
561 miscc |= AGP_I810_MISCC_WINSIZE_32;
563 miscc |= AGP_I810_MISCC_WINSIZE_64;
565 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
568 if (aperture != 64 * 1024 * 1024 &&
569 aperture != 128 * 1024 * 1024) {
570 device_printf(dev, "bad aperture size %d\n", aperture);
573 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
574 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
575 if (aperture == 64 * 1024 * 1024)
576 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
578 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
580 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
583 if (aperture != 128 * 1024 * 1024) {
584 device_printf(dev, "bad aperture size %d\n", aperture);
589 temp = pci_read_config(dev, AGP_I915_MSAC, 1);
590 temp &= ~AGP_I915_MSAC_GMASIZE;
593 case 128 * 1024 * 1024:
594 temp |= AGP_I915_MSAC_GMASIZE_128;
596 case 256 * 1024 * 1024:
597 temp |= AGP_I915_MSAC_GMASIZE_256;
600 device_printf(dev, "bad aperture size %d\n", aperture);
604 pci_write_config(dev, AGP_I915_MSAC, temp, 1);
612 agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
614 struct agp_i810_softc *sc = device_get_softc(dev);
616 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
617 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
621 if ( sc->chiptype != CHIP_I810 ) {
622 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
623 device_printf(dev, "trying to bind into stolen memory");
628 if (sc->chiptype == CHIP_I915) {
629 WRITEGTT((offset >> AGP_PAGE_SHIFT) * 4, physical | 1);
631 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, physical | 1);
638 agp_i810_unbind_page(device_t dev, int offset)
640 struct agp_i810_softc *sc = device_get_softc(dev);
642 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
645 if ( sc->chiptype != CHIP_I810 ) {
646 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
647 device_printf(dev, "trying to unbind from stolen memory");
652 if (sc->chiptype == CHIP_I915) {
653 WRITEGTT((offset >> AGP_PAGE_SHIFT) * 4, 0);
655 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 0);
662 * Writing via memory mapped registers already flushes all TLBs.
665 agp_i810_flush_tlb(device_t dev)
670 agp_i810_enable(device_t dev, u_int32_t mode)
676 static struct agp_memory *
677 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
679 struct agp_i810_softc *sc = device_get_softc(dev);
680 struct agp_memory *mem;
682 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
685 if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
690 * Mapping local DRAM into GATT.
692 if ( sc->chiptype != CHIP_I810 )
694 if (size != sc->dcache_size)
696 } else if (type == 2) {
698 * Type 2 is the contiguous physical memory type, that hands
699 * back a physical address. This is used for cursors on i810.
700 * Hand back as many single pages with physical as the user
701 * wants, but only allow one larger allocation (ARGB cursor)
704 if (size != AGP_PAGE_SIZE) {
705 if (sc->argb_cursor != NULL)
708 /* Allocate memory for ARGB cursor, if we can. */
709 sc->argb_cursor = contigmalloc(size, M_AGP,
710 0, 0, ~0, PAGE_SIZE, 0);
711 if (sc->argb_cursor == NULL)
716 mem = malloc(sizeof *mem, M_AGP, M_WAITOK);
717 mem->am_id = sc->agp.as_nextid++;
720 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
721 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
722 atop(round_page(size)));
727 if (size == AGP_PAGE_SIZE) {
729 * Allocate and wire down the page now so that we can
730 * get its physical address.
734 VM_OBJECT_LOCK(mem->am_obj);
735 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY |
736 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY);
737 VM_OBJECT_UNLOCK(mem->am_obj);
738 mem->am_physical = VM_PAGE_TO_PHYS(m);
740 /* Our allocation is already nicely wired down for us.
741 * Just grab the physical address.
743 mem->am_physical = vtophys(sc->argb_cursor);
746 mem->am_physical = 0;
750 mem->am_is_bound = 0;
751 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
752 sc->agp.as_allocated += size;
758 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
760 struct agp_i810_softc *sc = device_get_softc(dev);
762 if (mem->am_is_bound)
765 if (mem->am_type == 2) {
766 if (mem->am_size == AGP_PAGE_SIZE) {
768 * Unwire the page which we wired in alloc_memory.
772 VM_OBJECT_LOCK(mem->am_obj);
773 m = vm_page_lookup(mem->am_obj, 0);
774 VM_OBJECT_UNLOCK(mem->am_obj);
775 vm_page_lock_queues();
776 vm_page_unwire(m, 0);
777 vm_page_unlock_queues();
779 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
780 sc->argb_cursor = NULL;
784 sc->agp.as_allocated -= mem->am_size;
785 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
787 vm_object_deallocate(mem->am_obj);
793 agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
796 struct agp_i810_softc *sc = device_get_softc(dev);
799 /* Do some sanity checks first. */
800 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
801 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
802 device_printf(dev, "binding memory at bad offset %#x\n",
807 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
808 mtx_lock(&sc->agp.as_lock);
809 if (mem->am_is_bound) {
810 mtx_unlock(&sc->agp.as_lock);
813 /* The memory's already wired down, just stick it in the GTT. */
814 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
815 u_int32_t physical = mem->am_physical + i;
817 if (sc->chiptype == CHIP_I915) {
818 WRITEGTT(((offset + i) >> AGP_PAGE_SHIFT) * 4,
821 WRITE4(AGP_I810_GTT +
822 ((offset + i) >> AGP_PAGE_SHIFT) * 4,
827 mem->am_offset = offset;
828 mem->am_is_bound = 1;
829 mtx_unlock(&sc->agp.as_lock);
833 if (mem->am_type != 1)
834 return agp_generic_bind_memory(dev, mem, offset);
836 if ( sc->chiptype != CHIP_I810 )
839 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
840 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4,
848 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
850 struct agp_i810_softc *sc = device_get_softc(dev);
853 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
854 mtx_lock(&sc->agp.as_lock);
855 if (!mem->am_is_bound) {
856 mtx_unlock(&sc->agp.as_lock);
860 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
861 vm_offset_t offset = mem->am_offset;
863 if (sc->chiptype == CHIP_I915) {
864 WRITEGTT(((offset + i) >> AGP_PAGE_SHIFT) * 4,
867 WRITE4(AGP_I810_GTT +
868 ((offset + i) >> AGP_PAGE_SHIFT) * 4, 0);
872 mem->am_is_bound = 0;
873 mtx_unlock(&sc->agp.as_lock);
877 if (mem->am_type != 1)
878 return agp_generic_unbind_memory(dev, mem);
880 if ( sc->chiptype != CHIP_I810 )
883 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
884 WRITE4(AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
889 static device_method_t agp_i810_methods[] = {
890 /* Device interface */
891 DEVMETHOD(device_identify, agp_i810_identify),
892 DEVMETHOD(device_probe, agp_i810_probe),
893 DEVMETHOD(device_attach, agp_i810_attach),
894 DEVMETHOD(device_detach, agp_i810_detach),
897 DEVMETHOD(agp_get_aperture, agp_i810_get_aperture),
898 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
899 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
900 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
901 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
902 DEVMETHOD(agp_enable, agp_i810_enable),
903 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
904 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
905 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
906 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
911 static driver_t agp_i810_driver = {
914 sizeof(struct agp_i810_softc),
917 static devclass_t agp_devclass;
919 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0);
920 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
921 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);