2 * Copyright (c) 2000 Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/mutex.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <pci/agppriv.h>
45 #include <pci/agpreg.h>
48 #include <vm/vm_object.h>
51 #define MAX_APSIZE 0x3f /* 256 MB */
53 struct agp_intel_softc {
55 u_int32_t initial_aperture; /* aperture size at startup */
56 struct agp_gatt *gatt;
61 agp_intel_match(device_t dev)
63 if (pci_get_class(dev) != PCIC_BRIDGE
64 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
67 if (agp_find_caps(dev) == 0)
70 switch (pci_get_devid(dev)) {
71 /* Intel -- vendor 0x8086 */
73 return ("Intel 82443LX (440 LX) host to PCI bridge");
76 return ("Intel 82443BX (440 BX) host to PCI bridge");
79 return ("Intel 82443GX host to PCI bridge");
82 return ("Intel 82443GX host to AGP bridge");
85 return ("Intel 82815 (i815 GMCH) host to PCI bridge");
89 return ("Intel 82820 host to AGP bridge");
92 return ("Intel 82830 host to AGP bridge");
95 return ("Intel 82840 host to AGP bridge");
98 return ("Intel 82845 host to AGP bridge");
101 return ("Intel 82850 host to AGP bridge");
104 return ("Intel 82855 host to AGP bridge");
107 return ("Intel 82860 host to AGP bridge");
110 return ("Intel 82865 host to AGP bridge");
113 return ("Intel E7205 host to AGP bridge");
116 return ("Intel 82875P host to AGP bridge");
118 case 0x25608086: /* i845G */
119 return ("Intel 82845G host to AGP bridge");
126 agp_intel_probe(device_t dev)
130 if (resource_disabled("agp", device_get_unit(dev)))
132 desc = agp_intel_match(dev);
135 device_set_desc(dev, desc);
136 return BUS_PROBE_DEFAULT;
143 agp_intel_attach(device_t dev)
145 struct agp_intel_softc *sc = device_get_softc(dev);
146 struct agp_gatt *gatt;
147 u_int32_t type = pci_get_devid(dev);
151 error = agp_generic_attach(dev);
155 /* Determine maximum supported aperture size. */
156 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
157 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1);
158 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
160 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
161 sc->initial_aperture = AGP_GET_APERTURE(dev);
164 gatt = agp_alloc_gatt(dev);
169 * Probably contigmalloc failure. Try reducing the
170 * aperture so that the gatt size reduces.
172 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
173 agp_generic_detach(dev);
179 /* Install the gatt. */
180 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
182 /* Enable the GLTB and setup the control register. */
184 case 0x71908086: /* 440LX/EX */
185 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4);
187 case 0x71808086: /* 440BX */
189 * XXX: Should be 0xa080? Bit 9 is undefined, and
190 * bit 13 being on and bit 15 being clear is illegal.
192 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
195 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
196 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
199 /* Enable things, clear errors etc. */
201 case 0x1a218086: /* i840 */
202 case 0x25308086: /* i850 */
203 case 0x25318086: /* i860 */
204 pci_write_config(dev, AGP_INTEL_MCHCFG,
205 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
209 case 0x25008086: /* i820 */
210 case 0x25018086: /* i820 */
211 pci_write_config(dev, AGP_INTEL_I820_RDCR,
212 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
216 case 0x1a308086: /* i845 */
217 case 0x33408086: /* i855 */
218 case 0x255d8086: /* E7205 */
219 case 0x25708086: /* i865 */
220 case 0x25788086: /* i875P */
221 case 0x25608086: /* i845G */
222 pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
223 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
227 default: /* Intel Generic (maybe) */
228 pci_write_config(dev, AGP_INTEL_NBXCFG,
229 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
230 & ~(1 << 10)) | (1 << 9), 4);
234 case 0x1a218086: /* i840 */
235 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
238 case 0x25008086: /* i820 */
239 case 0x25018086: /* i820 */
240 case 0x1a308086: /* i845 */
241 case 0x25308086: /* i850 */
242 case 0x33408086: /* i855 */
243 case 0x255d8086: /* E7205 */
244 case 0x25318086: /* i860 */
245 case 0x25708086: /* i865 */
246 case 0x25788086: /* i875P */
247 case 0x25608086: /* i845G */
248 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
251 default: /* Intel Generic (maybe) */
252 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
259 agp_intel_detach(device_t dev)
261 struct agp_intel_softc *sc = device_get_softc(dev);
262 u_int32_t type = pci_get_devid(dev);
265 error = agp_generic_detach(dev);
270 case 0x1a218086: /* i840 */
271 case 0x25308086: /* i850 */
272 case 0x25318086: /* i860 */
273 printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
274 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
276 pci_write_config(dev, AGP_INTEL_MCHCFG,
277 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
280 case 0x25008086: /* i820 */
281 case 0x25018086: /* i820 */
282 printf("%s: set RDCR to %x\n", __func__, (unsigned)
283 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
285 pci_write_config(dev, AGP_INTEL_I820_RDCR,
286 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
289 case 0x1a308086: /* i845 */
290 case 0x25608086: /* i845G */
291 case 0x33408086: /* i855 */
292 case 0x255d8086: /* E7205 */
293 case 0x25708086: /* i865 */
294 case 0x25788086: /* i875P */
295 printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
296 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
298 pci_write_config(dev, AGP_INTEL_MCHCFG,
299 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
302 default: /* Intel Generic (maybe) */
303 printf("%s: set NBXCFG to %x\n", __func__,
304 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
306 pci_write_config(dev, AGP_INTEL_NBXCFG,
307 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
310 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
311 AGP_SET_APERTURE(dev, sc->initial_aperture);
312 agp_free_gatt(sc->gatt);
318 agp_intel_get_aperture(device_t dev)
320 struct agp_intel_softc *sc = device_get_softc(dev);
323 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
326 * The size is determined by the number of low bits of
327 * register APBASE which are forced to zero. The low 22 bits
328 * are always forced to zero and each zero bit in the apsize
329 * field just read forces the corresponding bit in the 27:22
330 * to be zero. We calculate the aperture size accordingly.
332 return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
336 agp_intel_set_aperture(device_t dev, u_int32_t aperture)
338 struct agp_intel_softc *sc = device_get_softc(dev);
342 * Reverse the magic from get_aperture.
344 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask;
347 * Double check for sanity.
349 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
352 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
358 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical)
360 struct agp_intel_softc *sc = device_get_softc(dev);
362 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
365 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
370 agp_intel_unbind_page(device_t dev, int offset)
372 struct agp_intel_softc *sc = device_get_softc(dev);
374 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
377 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
382 agp_intel_flush_tlb(device_t dev)
386 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
387 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4);
388 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4);
391 static device_method_t agp_intel_methods[] = {
392 /* Device interface */
393 DEVMETHOD(device_probe, agp_intel_probe),
394 DEVMETHOD(device_attach, agp_intel_attach),
395 DEVMETHOD(device_detach, agp_intel_detach),
396 DEVMETHOD(device_shutdown, bus_generic_shutdown),
397 DEVMETHOD(device_suspend, bus_generic_suspend),
398 DEVMETHOD(device_resume, bus_generic_resume),
401 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture),
402 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture),
403 DEVMETHOD(agp_bind_page, agp_intel_bind_page),
404 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page),
405 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb),
406 DEVMETHOD(agp_enable, agp_generic_enable),
407 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
408 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
409 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
410 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
415 static driver_t agp_intel_driver = {
418 sizeof(struct agp_intel_softc),
421 static devclass_t agp_devclass;
423 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0);
424 MODULE_DEPEND(agp_intel, agp, 1, 1, 1);
425 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);