2 * Copyright (c) 2000 Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _PCI_AGPREG_H_
30 #define _PCI_AGPREG_H_
33 * Offsets for various AGP configuration registers.
35 #define AGP_APBASE PCIR_BAR(0)
38 * Offsets from the AGP Capability pointer.
41 #define AGP_STATUS 0x4
42 #define AGP_COMMAND 0x8
43 #define AGP_STATUS_AGP3 0x0008
44 #define AGP_STATUS_RQ_MASK 0xff000000
45 #define AGP_COMMAND_RQ_MASK 0xff000000
46 #define AGP_STATUS_ARQSZ_MASK 0xe000
47 #define AGP_COMMAND_ARQSZ_MASK 0xe000
48 #define AGP_STATUS_CAL_MASK 0x1c00
49 #define AGP_COMMAND_CAL_MASK 0x1c00
50 #define AGP_STATUS_ISOCH 0x10000
51 #define AGP_STATUS_SBA 0x0200
52 #define AGP_STATUS_ITA_COH 0x0100
53 #define AGP_STATUS_GART64 0x0080
54 #define AGP_STATUS_HTRANS 0x0040
55 #define AGP_STATUS_64BIT 0x0020
56 #define AGP_STATUS_FW 0x0010
57 #define AGP_COMMAND_RQ_MASK 0xff000000
58 #define AGP_COMMAND_ARQSZ_MASK 0xe000
59 #define AGP_COMMAND_CAL_MASK 0x1c00
60 #define AGP_COMMAND_SBA 0x0200
61 #define AGP_COMMAND_AGP 0x0100
62 #define AGP_COMMAND_GART64 0x0080
63 #define AGP_COMMAND_64BIT 0x0020
64 #define AGP_COMMAND_FW 0x0010
67 * Config offsets for Intel AGP chipsets.
69 #define AGP_INTEL_NBXCFG 0x50
70 #define AGP_INTEL_ERRSTS 0x91
71 #define AGP_INTEL_AGPCTRL 0xb0
72 #define AGP_INTEL_APSIZE 0xb4
73 #define AGP_INTEL_ATTBASE 0xb8
76 * Config offsets for Intel i8xx/E7xxx AGP chipsets.
78 #define AGP_INTEL_MCHCFG 0x50
79 #define AGP_INTEL_I820_RDCR 0x51
80 #define AGP_INTEL_I845_AGPM 0x51
81 #define AGP_INTEL_I8XX_ERRSTS 0xc8
84 * Config offsets for VIA AGP 2.x chipsets.
86 #define AGP_VIA_GARTCTRL 0x80
87 #define AGP_VIA_APSIZE 0x84
88 #define AGP_VIA_ATTBASE 0x88
91 * Config offsets for VIA AGP 3.0 chipsets.
93 #define AGP3_VIA_GARTCTRL 0x90
94 #define AGP3_VIA_APSIZE 0x94
95 #define AGP3_VIA_ATTBASE 0x98
96 #define AGP_VIA_AGPSEL 0xfd
99 * Config offsets for SiS AGP chipsets.
101 #define AGP_SIS_ATTBASE 0x90
102 #define AGP_SIS_WINCTRL 0x94
103 #define AGP_SIS_TLBCTRL 0x97
104 #define AGP_SIS_TLBFLUSH 0x98
107 * Config offsets for Ali AGP chipsets.
109 #define AGP_ALI_AGPCTRL 0xb8
110 #define AGP_ALI_ATTBASE 0xbc
111 #define AGP_ALI_TLBCTRL 0xc0
114 * Config offsets for the AMD 751 chipset.
116 #define AGP_AMD751_APBASE 0x10
117 #define AGP_AMD751_REGISTERS 0x14
118 #define AGP_AMD751_APCTRL 0xac
119 #define AGP_AMD751_MODECTRL 0xb0
120 #define AGP_AMD751_MODECTRL_SYNEN 0x80
121 #define AGP_AMD751_MODECTRL2 0xb2
122 #define AGP_AMD751_MODECTRL2_G1LM 0x01
123 #define AGP_AMD751_MODECTRL2_GPDCE 0x02
124 #define AGP_AMD751_MODECTRL2_NGSE 0x08
127 * Memory mapped register offsets for AMD 751 chipset.
129 #define AGP_AMD751_CAPS 0x00
130 #define AGP_AMD751_CAPS_EHI 0x0800
131 #define AGP_AMD751_CAPS_P2P 0x0400
132 #define AGP_AMD751_CAPS_MPC 0x0200
133 #define AGP_AMD751_CAPS_VBE 0x0100
134 #define AGP_AMD751_CAPS_REV 0x00ff
135 #define AGP_AMD751_STATUS 0x02
136 #define AGP_AMD751_STATUS_P2PS 0x0800
137 #define AGP_AMD751_STATUS_GCS 0x0400
138 #define AGP_AMD751_STATUS_MPS 0x0200
139 #define AGP_AMD751_STATUS_VBES 0x0100
140 #define AGP_AMD751_STATUS_P2PE 0x0008
141 #define AGP_AMD751_STATUS_GCE 0x0004
142 #define AGP_AMD751_STATUS_VBEE 0x0001
143 #define AGP_AMD751_ATTBASE 0x04
144 #define AGP_AMD751_TLBCTRL 0x0c
147 * Config registers for i810 device 0
149 #define AGP_I810_SMRAM 0x70
150 #define AGP_I810_SMRAM_GMS 0xc0
151 #define AGP_I810_SMRAM_GMS_DISABLED 0x00
152 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40
153 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80
154 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0
155 #define AGP_I810_MISCC 0x72
156 #define AGP_I810_MISCC_WINSIZE 0x0001
157 #define AGP_I810_MISCC_WINSIZE_64 0x0000
158 #define AGP_I810_MISCC_WINSIZE_32 0x0001
159 #define AGP_I810_MISCC_PLCK 0x0008
160 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000
161 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008
162 #define AGP_I810_MISCC_WPTC 0x0030
163 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000
164 #define AGP_I810_MISCC_WPTC_62 0x0010
165 #define AGP_I810_MISCC_WPTC_50 0x0020
166 #define AGP_I810_MISCC_WPTC_37 0x0030
167 #define AGP_I810_MISCC_RPTC 0x00c0
168 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000
169 #define AGP_I810_MISCC_RPTC_62 0x0040
170 #define AGP_I810_MISCC_RPTC_50 0x0080
171 #define AGP_I810_MISCC_RPTC_37 0x00c0
174 * Config registers for i810 device 1
176 #define AGP_I810_GMADR 0x10
177 #define AGP_I810_MMADR 0x14
180 * Memory mapped register offsets for i810 chipset.
182 #define AGP_I810_PGTBL_CTL 0x2020
184 * This field determines the actual size of the global GTT on the 965
187 #define AGP_I810_PGTBL_SIZE_MASK 0x0000000e
188 #define AGP_I810_PGTBL_SIZE_512KB (0 << 1)
189 #define AGP_I810_PGTBL_SIZE_256KB (1 << 1)
190 #define AGP_I810_PGTBL_SIZE_128KB (2 << 1)
191 #define AGP_I810_DRT 0x3000
192 #define AGP_I810_DRT_UNPOPULATED 0x00
193 #define AGP_I810_DRT_POPULATED 0x01
194 #define AGP_I810_GTT 0x10000
197 * Config registers for i830MG device 0
199 #define AGP_I830_GCC1 0x52
200 #define AGP_I830_GCC1_DEV2 0x08
201 #define AGP_I830_GCC1_DEV2_ENABLED 0x00
202 #define AGP_I830_GCC1_DEV2_DISABLED 0x08
203 #define AGP_I830_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */
204 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20
205 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30
206 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40
207 #define AGP_I830_GCC1_GMASIZE 0x01
208 #define AGP_I830_GCC1_GMASIZE_64 0x01
209 #define AGP_I830_GCC1_GMASIZE_128 0x00
212 * Config registers for 852GM/855GM/865G device 0
214 #define AGP_I855_GCC1 0x52
215 #define AGP_I855_GCC1_DEV2 0x08
216 #define AGP_I855_GCC1_DEV2_ENABLED 0x00
217 #define AGP_I855_GCC1_DEV2_DISABLED 0x08
218 #define AGP_I855_GCC1_GMS 0x70
219 #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00
220 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10
221 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20
222 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30
223 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40
224 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50
227 * 852GM/855GM variant identification
229 #define AGP_I85X_CAPID 0x44
230 #define AGP_I85X_VARIANT_MASK 0x7
231 #define AGP_I85X_VARIANT_SHIFT 5
232 #define AGP_I855_GME 0x0
233 #define AGP_I855_GM 0x4
234 #define AGP_I852_GME 0x2
235 #define AGP_I852_GM 0x5
240 #define AGP_I915_GMADR 0x18
241 #define AGP_I915_MMADR 0x10
242 #define AGP_I915_GTTADR 0x1C
243 #define AGP_I915_GCC1_GMS_STOLEN_48M 0x60
244 #define AGP_I915_GCC1_GMS_STOLEN_64M 0x70
245 #define AGP_I915_DEVEN 0x54
246 #define AGP_I915_DEVEN_D2F0 0x08
247 #define AGP_I915_DEVEN_D2F0_ENABLED 0x08
248 #define AGP_I915_DEVEN_D2F0_DISABLED 0x00
249 #define AGP_I915_MSAC 0x62
250 #define AGP_I915_MSAC_GMASIZE 0x02
251 #define AGP_I915_MSAC_GMASIZE_128 0x02
252 #define AGP_I915_MSAC_GMASIZE_256 0x00
257 #define AGP_I965_GTTMMADR 0x10
258 #define AGP_I965_MSAC 0x62
259 #define AGP_I965_MSAC_GMASIZE_128 0x00
260 #define AGP_I965_MSAC_GMASIZE_256 0x02
261 #define AGP_I965_MSAC_GMASIZE_512 0x06
266 #define AGP_G33_GCC1_GMS_STOLEN_128M 0x80
267 #define AGP_G33_GCC1_GMS_STOLEN_256M 0x90
270 * NVIDIA nForce/nForce2 registers
272 #define AGP_NVIDIA_0_APBASE 0x10
273 #define AGP_NVIDIA_0_APSIZE 0x80
274 #define AGP_NVIDIA_1_WBC 0xf0
275 #define AGP_NVIDIA_2_GARTCTRL 0xd0
276 #define AGP_NVIDIA_2_APBASE 0xd8
277 #define AGP_NVIDIA_2_APLIMIT 0xdc
278 #define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
279 #define AGP_NVIDIA_3_APBASE 0x50
280 #define AGP_NVIDIA_3_APLIMIT 0x54
283 * AMD64 GART registers
285 #define AGP_AMD64_APCTRL 0x90
286 #define AGP_AMD64_APBASE 0x94
287 #define AGP_AMD64_ATTBASE 0x98
288 #define AGP_AMD64_CACHECTRL 0x9c
289 #define AGP_AMD64_APCTRL_GARTEN 0x00000001
290 #define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
291 #define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
292 #define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
293 #define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
294 #define AGP_AMD64_APBASE_MASK 0x00007fff
295 #define AGP_AMD64_ATTBASE_MASK 0xfffffff0
296 #define AGP_AMD64_CACHECTRL_INVGART 0x00000001
297 #define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
300 * NVIDIA nForce3 registers
302 #define AGP_AMD64_NVIDIA_0_APBASE 0x10
303 #define AGP_AMD64_NVIDIA_1_APBASE1 0x50
304 #define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54
305 #define AGP_AMD64_NVIDIA_1_APSIZE 0xa8
306 #define AGP_AMD64_NVIDIA_1_APBASE2 0xd8
307 #define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc
310 * ULi M1689 registers
312 #define AGP_AMD64_ULI_APBASE 0x10
313 #define AGP_AMD64_ULI_HTT_FEATURE 0x50
314 #define AGP_AMD64_ULI_ENU_SCR 0x54
319 #define ATI_GART_MMADDR 0x14
320 #define ATI_RS100_APSIZE 0xac
321 #define ATI_RS100_IG_AGPMODE 0xb0
322 #define ATI_RS300_APSIZE 0xf8
323 #define ATI_RS300_IG_AGPMODE 0xfc
324 #define ATI_GART_FEATURE_ID 0x00
325 #define ATI_GART_BASE 0x04
326 #define ATI_GART_CACHE_CNTRL 0x0c
328 #endif /* !_PCI_AGPREG_H_ */