2 * Copyright (c) 2000 Matthew C. Forman
4 * Based (heavily) on alpm.c which is:
6 * Copyright (c) 1998, 1999 Nicolas Souchu
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Power management function/SMBus function support for the AMD 756 chip.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/kernel.h>
40 #include <sys/systm.h>
41 #include <sys/module.h>
45 #include <machine/bus.h>
46 #include <machine/clock.h>
47 #include <machine/resource.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
53 #include <dev/iicbus/iiconf.h>
54 #include <dev/smbus/smbconf.h>
57 #define AMDPM_DEBUG(x) if (amdpm_debug) (x)
60 static int amdpm_debug = 1;
62 static int amdpm_debug = 0;
65 #define AMDPM_VENDORID_AMD 0x1022
66 #define AMDPM_DEVICEID_AMD756PM 0x740b
67 #define AMDPM_DEVICEID_AMD766PM 0x7413
68 #define AMDPM_DEVICEID_AMD768PM 0x7443
69 #define AMDPM_DEVICEID_AMD8111PM 0x746A
71 /* nVidia nForce chipset */
72 #define AMDPM_VENDORID_NVIDIA 0x10de
73 #define AMDPM_DEVICEID_NF_SMB 0x01b4
75 /* PCI Configuration space registers */
76 #define AMDPCI_PMBASE 0x58
77 #define NFPCI_PMBASE 0x14
79 #define AMDPCI_GEN_CONFIG_PM 0x41
80 #define AMDPCI_PMIOEN (1<<7)
82 #define AMDPCI_SCIINT_CONFIG_PM 0x42
83 #define AMDPCI_SCISEL_IRQ11 11
85 #define AMDPCI_REVID 0x08
89 * Base address programmed via AMDPCI_PMBASE.
92 #define AMDSMB_GLOBAL_STATUS (0x00)
93 #define AMDSMB_GS_TO_STS (1<<5)
94 #define AMDSMB_GS_HCYC_STS (1<<4)
95 #define AMDSMB_GS_HST_STS (1<<3)
96 #define AMDSMB_GS_PRERR_STS (1<<2)
97 #define AMDSMB_GS_COL_STS (1<<1)
98 #define AMDSMB_GS_ABRT_STS (1<<0)
99 #define AMDSMB_GS_CLEAR_STS (AMDSMB_GS_TO_STS|AMDSMB_GS_HCYC_STS|AMDSMB_GS_PRERR_STS|AMDSMB_GS_COL_STS|AMDSMB_GS_ABRT_STS)
101 #define AMDSMB_GLOBAL_ENABLE (0x02)
102 #define AMDSMB_GE_ABORT (1<<5)
103 #define AMDSMB_GE_HCYC_EN (1<<4)
104 #define AMDSMB_GE_HOST_STC (1<<3)
105 #define AMDSMB_GE_CYC_QUICK 0
106 #define AMDSMB_GE_CYC_BYTE 1
107 #define AMDSMB_GE_CYC_BDATA 2
108 #define AMDSMB_GE_CYC_WDATA 3
109 #define AMDSMB_GE_CYC_PROCCALL 4
110 #define AMDSMB_GE_CYC_BLOCK 5
112 #define AMDSMB_HSTADDR (0x04)
113 #define AMDSMB_HSTDATA (0x06)
114 #define AMDSMB_HSTCMD (0x08)
115 #define AMDSMB_HSTDFIFO (0x09)
116 #define AMDSMB_HSLVDATA (0x0A)
117 #define AMDSMB_HSLVDA (0x0C)
118 #define AMDSMB_HSLVDDR (0x0E)
119 #define AMDSMB_SNPADDR (0x0F)
124 struct resource *res;
125 bus_space_tag_t smbst;
126 bus_space_handle_t smbsh;
131 #define AMDPM_SMBINB(amdpm,register) \
132 (bus_space_read_1(amdpm->smbst, amdpm->smbsh, register))
133 #define AMDPM_SMBOUTB(amdpm,register,value) \
134 (bus_space_write_1(amdpm->smbst, amdpm->smbsh, register, value))
135 #define AMDPM_SMBINW(amdpm,register) \
136 (bus_space_read_2(amdpm->smbst, amdpm->smbsh, register))
137 #define AMDPM_SMBOUTW(amdpm,register,value) \
138 (bus_space_write_2(amdpm->smbst, amdpm->smbsh, register, value))
141 amdpm_probe(device_t dev)
147 vid = pci_get_vendor(dev);
148 did = pci_get_device(dev);
149 if ((vid == AMDPM_VENDORID_AMD) &&
150 ((did == AMDPM_DEVICEID_AMD756PM) ||
151 (did == AMDPM_DEVICEID_AMD766PM) ||
152 (did == AMDPM_DEVICEID_AMD768PM) ||
153 (did == AMDPM_DEVICEID_AMD8111PM))) {
154 device_set_desc(dev, "AMD 756/766/768/8111 Power Management Controller");
157 * We have to do this, since the BIOS won't give us the
158 * resource info (not mine, anyway).
160 base = pci_read_config(dev, AMDPCI_PMBASE, 4);
162 bus_set_resource(dev, SYS_RES_IOPORT, AMDPCI_PMBASE,
164 return (BUS_PROBE_DEFAULT);
167 if ((vid == AMDPM_VENDORID_NVIDIA) &&
168 (did == AMDPM_DEVICEID_NF_SMB)) {
169 device_set_desc(dev, "nForce SMBus Controller");
172 * We have to do this, since the BIOS won't give us the
173 * resource info (not mine, anyway).
175 base = pci_read_config(dev, NFPCI_PMBASE, 4);
177 bus_set_resource(dev, SYS_RES_IOPORT, NFPCI_PMBASE,
180 return (BUS_PROBE_DEFAULT);
187 amdpm_attach(device_t dev)
189 struct amdpm_softc *amdpm_sc = device_get_softc(dev);
192 /* Enable I/O block access */
193 val_b = pci_read_config(dev, AMDPCI_GEN_CONFIG_PM, 1);
194 pci_write_config(dev, AMDPCI_GEN_CONFIG_PM, val_b | AMDPCI_PMIOEN, 1);
196 /* Allocate I/O space */
197 if (pci_get_vendor(dev) == AMDPM_VENDORID_AMD)
198 amdpm_sc->rid = AMDPCI_PMBASE;
200 amdpm_sc->rid = NFPCI_PMBASE;
201 amdpm_sc->res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
202 &amdpm_sc->rid, RF_ACTIVE);
204 if (amdpm_sc->res == NULL) {
205 device_printf(dev, "could not map i/o space\n");
209 amdpm_sc->smbst = rman_get_bustag(amdpm_sc->res);
210 amdpm_sc->smbsh = rman_get_bushandle(amdpm_sc->res);
212 /* Allocate a new smbus device */
213 amdpm_sc->smbus = device_add_child(dev, "smbus", -1);
214 if (!amdpm_sc->smbus)
217 bus_generic_attach(dev);
223 amdpm_detach(device_t dev)
225 struct amdpm_softc *amdpm_sc = device_get_softc(dev);
227 if (amdpm_sc->smbus) {
228 device_delete_child(dev, amdpm_sc->smbus);
229 amdpm_sc->smbus = NULL;
233 bus_release_resource(dev, SYS_RES_IOPORT, amdpm_sc->rid,
240 amdpm_callback(device_t dev, int index, caddr_t *data)
245 case SMB_REQUEST_BUS:
246 case SMB_RELEASE_BUS:
256 amdpm_clear(struct amdpm_softc *sc)
258 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_STATUS, AMDSMB_GS_CLEAR_STS);
266 amdpm_abort(struct amdpm_softc *sc)
270 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
271 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, l | AMDSMB_GE_ABORT);
278 amdpm_idle(struct amdpm_softc *sc)
282 sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
284 AMDPM_DEBUG(printf("amdpm: busy? STS=0x%x\n", sts));
286 return (~(sts & AMDSMB_GS_HST_STS));
290 * Poll the SMBus controller
293 amdpm_wait(struct amdpm_softc *sc)
299 /* Wait for command to complete (SMBus controller is idle) */
302 sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
303 if (!(sts & AMDSMB_GS_HST_STS))
307 AMDPM_DEBUG(printf("amdpm: STS=0x%x (count=%d)\n", sts, count));
312 error |= SMB_ETIMEOUT;
314 if (sts & AMDSMB_GS_ABRT_STS)
317 if (sts & AMDSMB_GS_COL_STS)
320 if (sts & AMDSMB_GS_PRERR_STS)
321 error |= SMB_EBUSERR;
323 if (error != SMB_ENOERR)
330 amdpm_quick(device_t dev, u_char slave, int how)
332 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
342 AMDPM_DEBUG(printf("amdpm: QWRITE to 0x%x", slave));
343 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
346 AMDPM_DEBUG(printf("amdpm: QREAD to 0x%x", slave));
347 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
350 panic("%s: unknown QUICK command (%x)!", __func__, how);
352 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
353 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_QUICK | AMDSMB_GE_HOST_STC);
355 error = amdpm_wait(sc);
357 AMDPM_DEBUG(printf(", error=0x%x\n", error));
363 amdpm_sendb(device_t dev, u_char slave, char byte)
365 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
373 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
374 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
375 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
376 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
378 error = amdpm_wait(sc);
380 AMDPM_DEBUG(printf("amdpm: SENDB to 0x%x, byte=0x%x, error=0x%x\n", slave, byte, error));
386 amdpm_recvb(device_t dev, u_char slave, char *byte)
388 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
396 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
397 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
398 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
400 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
401 *byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
403 AMDPM_DEBUG(printf("amdpm: RECVB from 0x%x, byte=0x%x, error=0x%x\n", slave, *byte, error));
409 amdpm_writeb(device_t dev, u_char slave, char cmd, char byte)
411 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
419 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
420 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
421 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
422 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
423 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
425 error = amdpm_wait(sc);
427 AMDPM_DEBUG(printf("amdpm: WRITEB to 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, byte, error));
433 amdpm_readb(device_t dev, u_char slave, char cmd, char *byte)
435 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
443 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
444 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
445 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
446 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
448 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
449 *byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
451 AMDPM_DEBUG(printf("amdpm: READB from 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, *byte, error));
457 amdpm_writew(device_t dev, u_char slave, char cmd, short word)
459 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
467 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
468 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, word);
469 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
470 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
471 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
473 error = amdpm_wait(sc);
475 AMDPM_DEBUG(printf("amdpm: WRITEW to 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, word, error));
481 amdpm_readw(device_t dev, u_char slave, char cmd, short *word)
483 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
491 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
492 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
493 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
494 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
496 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
497 *word = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
499 AMDPM_DEBUG(printf("amdpm: READW from 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, *word, error));
505 amdpm_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
507 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
508 u_char remain, len, i;
509 int error = SMB_ENOERR;
518 len = min(remain, 32);
520 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
523 * Do we have to reset the internal 32-byte buffer?
524 * Can't see how to do this from the data sheet.
527 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, len);
529 /* Fill the 32-byte internal buffer */
530 for (i=0; i<len; i++) {
531 AMDPM_SMBOUTB(sc, AMDSMB_HSTDFIFO, buf[count-remain+i]);
534 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
535 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
536 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
538 if ((error = amdpm_wait(sc)) != SMB_ENOERR)
545 AMDPM_DEBUG(printf("amdpm: WRITEBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, count, cmd, error));
551 amdpm_bread(device_t dev, u_char slave, char cmd, u_char count, char *buf)
553 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
554 u_char remain, len, i;
555 int error = SMB_ENOERR;
564 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
566 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
568 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
569 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
571 if ((error = amdpm_wait(sc)) != SMB_ENOERR)
574 len = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
576 /* Read the 32-byte internal buffer */
577 for (i=0; i<len; i++) {
578 buf[count-remain+i] = AMDPM_SMBINB(sc, AMDSMB_HSTDFIFO);
585 AMDPM_DEBUG(printf("amdpm: READBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, count, cmd, error));
590 static devclass_t amdpm_devclass;
592 static device_method_t amdpm_methods[] = {
593 /* Device interface */
594 DEVMETHOD(device_probe, amdpm_probe),
595 DEVMETHOD(device_attach, amdpm_attach),
596 DEVMETHOD(device_detach, amdpm_detach),
598 /* SMBus interface */
599 DEVMETHOD(smbus_callback, amdpm_callback),
600 DEVMETHOD(smbus_quick, amdpm_quick),
601 DEVMETHOD(smbus_sendb, amdpm_sendb),
602 DEVMETHOD(smbus_recvb, amdpm_recvb),
603 DEVMETHOD(smbus_writeb, amdpm_writeb),
604 DEVMETHOD(smbus_readb, amdpm_readb),
605 DEVMETHOD(smbus_writew, amdpm_writew),
606 DEVMETHOD(smbus_readw, amdpm_readw),
607 DEVMETHOD(smbus_bwrite, amdpm_bwrite),
608 DEVMETHOD(smbus_bread, amdpm_bread),
613 static driver_t amdpm_driver = {
616 sizeof(struct amdpm_softc),
619 DRIVER_MODULE(amdpm, pci, amdpm_driver, amdpm_devclass, 0, 0);
621 MODULE_DEPEND(amdpm, pci, 1, 1, 1);
622 MODULE_DEPEND(amdpm, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
623 MODULE_VERSION(amdpm, 1);