2 * Copyright (c) 2000 Matthew C. Forman
4 * Based (heavily) on alpm.c which is:
6 * Copyright (c) 1998, 1999 Nicolas Souchu
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Power management function/SMBus function support for the AMD 756 chip.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/kernel.h>
40 #include <sys/systm.h>
41 #include <sys/module.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
52 #include <dev/iicbus/iiconf.h>
53 #include <dev/smbus/smbconf.h>
56 #define AMDPM_DEBUG(x) if (amdpm_debug) (x)
59 static int amdpm_debug = 1;
61 static int amdpm_debug = 0;
64 #define AMDPM_VENDORID_AMD 0x1022
65 #define AMDPM_DEVICEID_AMD756PM 0x740b
66 #define AMDPM_DEVICEID_AMD766PM 0x7413
67 #define AMDPM_DEVICEID_AMD768PM 0x7443
68 #define AMDPM_DEVICEID_AMD8111PM 0x746B
70 /* nVidia nForce chipset */
71 #define AMDPM_VENDORID_NVIDIA 0x10de
72 #define AMDPM_DEVICEID_NF_SMB 0x01b4
74 /* PCI Configuration space registers */
75 #define AMDPCI_PMBASE 0x58
76 #define NFPCI_PMBASE 0x14
78 #define AMDPCI_GEN_CONFIG_PM 0x41
79 #define AMDPCI_PMIOEN (1<<7)
81 #define AMDPCI_SCIINT_CONFIG_PM 0x42
82 #define AMDPCI_SCISEL_IRQ11 11
84 #define AMDPCI_REVID 0x08
88 * Base address programmed via AMDPCI_PMBASE.
91 #define AMDSMB_GLOBAL_STATUS (0x00)
92 #define AMDSMB_GS_TO_STS (1<<5)
93 #define AMDSMB_GS_HCYC_STS (1<<4)
94 #define AMDSMB_GS_HST_STS (1<<3)
95 #define AMDSMB_GS_PRERR_STS (1<<2)
96 #define AMDSMB_GS_COL_STS (1<<1)
97 #define AMDSMB_GS_ABRT_STS (1<<0)
98 #define AMDSMB_GS_CLEAR_STS (AMDSMB_GS_TO_STS|AMDSMB_GS_HCYC_STS|AMDSMB_GS_PRERR_STS|AMDSMB_GS_COL_STS|AMDSMB_GS_ABRT_STS)
100 #define AMDSMB_GLOBAL_ENABLE (0x02)
101 #define AMDSMB_GE_ABORT (1<<5)
102 #define AMDSMB_GE_HCYC_EN (1<<4)
103 #define AMDSMB_GE_HOST_STC (1<<3)
104 #define AMDSMB_GE_CYC_QUICK 0
105 #define AMDSMB_GE_CYC_BYTE 1
106 #define AMDSMB_GE_CYC_BDATA 2
107 #define AMDSMB_GE_CYC_WDATA 3
108 #define AMDSMB_GE_CYC_PROCCALL 4
109 #define AMDSMB_GE_CYC_BLOCK 5
111 #define AMDSMB_HSTADDR (0x04)
112 #define AMDSMB_HSTDATA (0x06)
113 #define AMDSMB_HSTCMD (0x08)
114 #define AMDSMB_HSTDFIFO (0x09)
115 #define AMDSMB_HSLVDATA (0x0A)
116 #define AMDSMB_HSLVDA (0x0C)
117 #define AMDSMB_HSLVDDR (0x0E)
118 #define AMDSMB_SNPADDR (0x0F)
123 struct resource *res;
124 bus_space_tag_t smbst;
125 bus_space_handle_t smbsh;
130 #define AMDPM_SMBINB(amdpm,register) \
131 (bus_space_read_1(amdpm->smbst, amdpm->smbsh, register))
132 #define AMDPM_SMBOUTB(amdpm,register,value) \
133 (bus_space_write_1(amdpm->smbst, amdpm->smbsh, register, value))
134 #define AMDPM_SMBINW(amdpm,register) \
135 (bus_space_read_2(amdpm->smbst, amdpm->smbsh, register))
136 #define AMDPM_SMBOUTW(amdpm,register,value) \
137 (bus_space_write_2(amdpm->smbst, amdpm->smbsh, register, value))
140 amdpm_probe(device_t dev)
146 vid = pci_get_vendor(dev);
147 did = pci_get_device(dev);
148 if ((vid == AMDPM_VENDORID_AMD) &&
149 ((did == AMDPM_DEVICEID_AMD756PM) ||
150 (did == AMDPM_DEVICEID_AMD766PM) ||
151 (did == AMDPM_DEVICEID_AMD768PM) ||
152 (did == AMDPM_DEVICEID_AMD8111PM))) {
153 device_set_desc(dev, "AMD 756/766/768/8111 Power Management Controller");
156 * We have to do this, since the BIOS won't give us the
157 * resource info (not mine, anyway).
159 base = pci_read_config(dev, AMDPCI_PMBASE, 4);
161 bus_set_resource(dev, SYS_RES_IOPORT, AMDPCI_PMBASE,
163 return (BUS_PROBE_DEFAULT);
166 if ((vid == AMDPM_VENDORID_NVIDIA) &&
167 (did == AMDPM_DEVICEID_NF_SMB)) {
168 device_set_desc(dev, "nForce SMBus Controller");
171 * We have to do this, since the BIOS won't give us the
172 * resource info (not mine, anyway).
174 base = pci_read_config(dev, NFPCI_PMBASE, 4);
176 bus_set_resource(dev, SYS_RES_IOPORT, NFPCI_PMBASE,
179 return (BUS_PROBE_DEFAULT);
186 amdpm_attach(device_t dev)
188 struct amdpm_softc *amdpm_sc = device_get_softc(dev);
191 /* Enable I/O block access */
192 val_b = pci_read_config(dev, AMDPCI_GEN_CONFIG_PM, 1);
193 pci_write_config(dev, AMDPCI_GEN_CONFIG_PM, val_b | AMDPCI_PMIOEN, 1);
195 /* Allocate I/O space */
196 if (pci_get_vendor(dev) == AMDPM_VENDORID_AMD)
197 amdpm_sc->rid = AMDPCI_PMBASE;
199 amdpm_sc->rid = NFPCI_PMBASE;
200 amdpm_sc->res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
201 &amdpm_sc->rid, RF_ACTIVE);
203 if (amdpm_sc->res == NULL) {
204 device_printf(dev, "could not map i/o space\n");
208 amdpm_sc->smbst = rman_get_bustag(amdpm_sc->res);
209 amdpm_sc->smbsh = rman_get_bushandle(amdpm_sc->res);
211 /* Allocate a new smbus device */
212 amdpm_sc->smbus = device_add_child(dev, "smbus", -1);
213 if (!amdpm_sc->smbus)
216 bus_generic_attach(dev);
222 amdpm_detach(device_t dev)
224 struct amdpm_softc *amdpm_sc = device_get_softc(dev);
226 if (amdpm_sc->smbus) {
227 device_delete_child(dev, amdpm_sc->smbus);
228 amdpm_sc->smbus = NULL;
232 bus_release_resource(dev, SYS_RES_IOPORT, amdpm_sc->rid,
239 amdpm_callback(device_t dev, int index, caddr_t *data)
244 case SMB_REQUEST_BUS:
245 case SMB_RELEASE_BUS:
255 amdpm_clear(struct amdpm_softc *sc)
257 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_STATUS, AMDSMB_GS_CLEAR_STS);
265 amdpm_abort(struct amdpm_softc *sc)
269 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
270 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, l | AMDSMB_GE_ABORT);
277 amdpm_idle(struct amdpm_softc *sc)
281 sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
283 AMDPM_DEBUG(printf("amdpm: busy? STS=0x%x\n", sts));
285 return (~(sts & AMDSMB_GS_HST_STS));
289 * Poll the SMBus controller
292 amdpm_wait(struct amdpm_softc *sc)
298 /* Wait for command to complete (SMBus controller is idle) */
301 sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
302 if (!(sts & AMDSMB_GS_HST_STS))
306 AMDPM_DEBUG(printf("amdpm: STS=0x%x (count=%d)\n", sts, count));
311 error |= SMB_ETIMEOUT;
313 if (sts & AMDSMB_GS_ABRT_STS)
316 if (sts & AMDSMB_GS_COL_STS)
319 if (sts & AMDSMB_GS_PRERR_STS)
320 error |= SMB_EBUSERR;
322 if (error != SMB_ENOERR)
329 amdpm_quick(device_t dev, u_char slave, int how)
331 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
341 AMDPM_DEBUG(printf("amdpm: QWRITE to 0x%x", slave));
342 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
345 AMDPM_DEBUG(printf("amdpm: QREAD to 0x%x", slave));
346 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
349 panic("%s: unknown QUICK command (%x)!", __func__, how);
351 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
352 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_QUICK | AMDSMB_GE_HOST_STC);
354 error = amdpm_wait(sc);
356 AMDPM_DEBUG(printf(", error=0x%x\n", error));
362 amdpm_sendb(device_t dev, u_char slave, char byte)
364 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
372 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
373 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
374 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
375 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
377 error = amdpm_wait(sc);
379 AMDPM_DEBUG(printf("amdpm: SENDB to 0x%x, byte=0x%x, error=0x%x\n", slave, byte, error));
385 amdpm_recvb(device_t dev, u_char slave, char *byte)
387 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
395 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
396 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
397 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
399 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
400 *byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
402 AMDPM_DEBUG(printf("amdpm: RECVB from 0x%x, byte=0x%x, error=0x%x\n", slave, *byte, error));
408 amdpm_writeb(device_t dev, u_char slave, char cmd, char byte)
410 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
418 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
419 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
420 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
421 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
422 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
424 error = amdpm_wait(sc);
426 AMDPM_DEBUG(printf("amdpm: WRITEB to 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, byte, error));
432 amdpm_readb(device_t dev, u_char slave, char cmd, char *byte)
434 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
442 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
443 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
444 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
445 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
447 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
448 *byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
450 AMDPM_DEBUG(printf("amdpm: READB from 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, *byte, error));
456 amdpm_writew(device_t dev, u_char slave, char cmd, short word)
458 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
466 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
467 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, word);
468 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
469 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
470 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
472 error = amdpm_wait(sc);
474 AMDPM_DEBUG(printf("amdpm: WRITEW to 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, word, error));
480 amdpm_readw(device_t dev, u_char slave, char cmd, short *word)
482 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
490 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
491 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
492 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
493 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
495 if ((error = amdpm_wait(sc)) == SMB_ENOERR)
496 *word = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
498 AMDPM_DEBUG(printf("amdpm: READW from 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, *word, error));
504 amdpm_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
506 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
507 u_char remain, len, i;
508 int error = SMB_ENOERR;
517 len = min(remain, 32);
519 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
522 * Do we have to reset the internal 32-byte buffer?
523 * Can't see how to do this from the data sheet.
526 AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, len);
528 /* Fill the 32-byte internal buffer */
529 for (i=0; i<len; i++) {
530 AMDPM_SMBOUTB(sc, AMDSMB_HSTDFIFO, buf[count-remain+i]);
533 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
534 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
535 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
537 if ((error = amdpm_wait(sc)) != SMB_ENOERR)
544 AMDPM_DEBUG(printf("amdpm: WRITEBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, count, cmd, error));
550 amdpm_bread(device_t dev, u_char slave, char cmd, u_char count, char *buf)
552 struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
553 u_char remain, len, i;
554 int error = SMB_ENOERR;
563 AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
565 AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
567 l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
568 AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
570 if ((error = amdpm_wait(sc)) != SMB_ENOERR)
573 len = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
575 /* Read the 32-byte internal buffer */
576 for (i=0; i<len; i++) {
577 buf[count-remain+i] = AMDPM_SMBINB(sc, AMDSMB_HSTDFIFO);
584 AMDPM_DEBUG(printf("amdpm: READBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, count, cmd, error));
589 static devclass_t amdpm_devclass;
591 static device_method_t amdpm_methods[] = {
592 /* Device interface */
593 DEVMETHOD(device_probe, amdpm_probe),
594 DEVMETHOD(device_attach, amdpm_attach),
595 DEVMETHOD(device_detach, amdpm_detach),
597 /* SMBus interface */
598 DEVMETHOD(smbus_callback, amdpm_callback),
599 DEVMETHOD(smbus_quick, amdpm_quick),
600 DEVMETHOD(smbus_sendb, amdpm_sendb),
601 DEVMETHOD(smbus_recvb, amdpm_recvb),
602 DEVMETHOD(smbus_writeb, amdpm_writeb),
603 DEVMETHOD(smbus_readb, amdpm_readb),
604 DEVMETHOD(smbus_writew, amdpm_writew),
605 DEVMETHOD(smbus_readw, amdpm_readw),
606 DEVMETHOD(smbus_bwrite, amdpm_bwrite),
607 DEVMETHOD(smbus_bread, amdpm_bread),
612 static driver_t amdpm_driver = {
615 sizeof(struct amdpm_softc),
618 DRIVER_MODULE(amdpm, pci, amdpm_driver, amdpm_devclass, 0, 0);
620 MODULE_DEPEND(amdpm, pci, 1, 1, 1);
621 MODULE_DEPEND(amdpm, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
622 MODULE_VERSION(amdpm, 1);