2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
49 * Accton EN1217 (www.accton.com)
50 * Xircom X3201 (www.xircom.com)
52 * Conexant LANfinity (www.conexant.com)
53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
55 * Datasheets for the 21143 are available at developer.intel.com.
56 * Datasheets for the clone parts can be found at their respective sites.
57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
58 * The PNIC II is essentially a Macronix 98715A chip; the only difference
59 * worth noting is that its multicast hash table is only 128 bits wide
62 * Written by Bill Paul <wpaul@ee.columbia.edu>
63 * Electrical Engineering Department
64 * Columbia University, New York City
67 * The Intel 21143 is the successor to the DEC 21140. It is basically
68 * the same as the 21140 but with a few new features. The 21143 supports
69 * three kinds of media attachments:
71 * o MII port, for 10Mbps and 100Mbps support and NWAY
72 * autonegotiation provided by an external PHY.
73 * o SYM port, for symbol mode 100Mbps support.
77 * The 100Mbps SYM port and 10baseT port can be used together in
78 * combination with the internal NWAY support to create a 10/100
79 * autosensing configuration.
81 * Note that not all tulip workalikes are handled in this driver: we only
82 * deal with those which are relatively well behaved. The Winbond is
83 * handled separately due to its different register offsets and the
84 * special handling needed for its various bugs. The PNIC is handled
85 * here, but I'm not thrilled about it.
87 * All of the workalike chips use some form of MII transceiver support
88 * with the exception of the Macronix chips, which also have a SYM port.
89 * The ASIX AX88140A is also documented to have a SYM port, but all
90 * the cards I've seen use an MII transceiver, probably because the
91 * AX88140A doesn't support internal NWAY.
94 #include <sys/param.h>
95 #include <sys/endian.h>
96 #include <sys/systm.h>
97 #include <sys/sockio.h>
99 #include <sys/malloc.h>
100 #include <sys/kernel.h>
101 #include <sys/module.h>
102 #include <sys/socket.h>
103 #include <sys/sysctl.h>
106 #include <net/if_arp.h>
107 #include <net/ethernet.h>
108 #include <net/if_dl.h>
109 #include <net/if_media.h>
110 #include <net/if_types.h>
111 #include <net/if_vlan_var.h>
115 #include <machine/bus_pio.h>
116 #include <machine/bus_memio.h>
117 #include <machine/bus.h>
118 #include <machine/resource.h>
120 #include <sys/rman.h>
122 #include <dev/mii/mii.h>
123 #include <dev/mii/miivar.h>
125 #include <dev/pci/pcireg.h>
126 #include <dev/pci/pcivar.h>
128 #define DC_USEIOSPACE
133 #include <pci/if_dcreg.h>
136 #include <dev/ofw/openfirm.h>
137 #include <machine/ofw_machdep.h>
140 MODULE_DEPEND(dc, pci, 1, 1, 1);
141 MODULE_DEPEND(dc, ether, 1, 1, 1);
142 MODULE_DEPEND(dc, miibus, 1, 1, 1);
144 /* "controller miibus0" required. See GENERIC if you get errors here. */
145 #include "miibus_if.h"
148 * Various supported device vendors/types and their names.
150 static struct dc_type dc_devs[] = {
151 { DC_VENDORID_DEC, DC_DEVICEID_21143,
152 "Intel 21143 10/100BaseTX" },
153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
154 "Davicom DM9009 10/100BaseTX" },
155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
156 "Davicom DM9100 10/100BaseTX" },
157 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
158 "Davicom DM9102 10/100BaseTX" },
159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
160 "Davicom DM9102A 10/100BaseTX" },
161 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
162 "ADMtek AL981 10/100BaseTX" },
163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
164 "ADMtek AN985 10/100BaseTX" },
165 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511,
166 "ADMtek ADM9511 10/100BaseTX" },
167 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513,
168 "ADMtek ADM9513 10/100BaseTX" },
169 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511,
170 "Netgear FA511 10/100BaseTX" },
171 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
172 "ASIX AX88140A 10/100BaseTX" },
173 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
174 "ASIX AX88141 10/100BaseTX" },
175 { DC_VENDORID_MX, DC_DEVICEID_98713,
176 "Macronix 98713 10/100BaseTX" },
177 { DC_VENDORID_MX, DC_DEVICEID_98713,
178 "Macronix 98713A 10/100BaseTX" },
179 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
180 "Compex RL100-TX 10/100BaseTX" },
181 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
182 "Compex RL100-TX 10/100BaseTX" },
183 { DC_VENDORID_MX, DC_DEVICEID_987x5,
184 "Macronix 98715/98715A 10/100BaseTX" },
185 { DC_VENDORID_MX, DC_DEVICEID_987x5,
186 "Macronix 98715AEC-C 10/100BaseTX" },
187 { DC_VENDORID_MX, DC_DEVICEID_987x5,
188 "Macronix 98725 10/100BaseTX" },
189 { DC_VENDORID_MX, DC_DEVICEID_98727,
190 "Macronix 98727/98732 10/100BaseTX" },
191 { DC_VENDORID_LO, DC_DEVICEID_82C115,
192 "LC82C115 PNIC II 10/100BaseTX" },
193 { DC_VENDORID_LO, DC_DEVICEID_82C168,
194 "82c168 PNIC 10/100BaseTX" },
195 { DC_VENDORID_LO, DC_DEVICEID_82C168,
196 "82c169 PNIC 10/100BaseTX" },
197 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
198 "Accton EN1217 10/100BaseTX" },
199 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
200 "Accton EN2242 MiniPCI 10/100BaseTX" },
201 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201,
202 "Xircom X3201 10/100BaseTX" },
203 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500,
204 "Abocom FE2500 10/100BaseTX" },
205 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX,
206 "Abocom FE2500MX 10/100BaseTX" },
207 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
208 "Conexant LANfinity MiniPCI 10/100BaseTX" },
209 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX,
210 "Hawking CB102 CardBus 10/100" },
211 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T,
212 "PlaneX FNW-3602-T CardBus 10/100" },
213 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
214 "3Com OfficeConnect 10/100B" },
215 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120,
216 "Microsoft MN-120 CardBus 10/100" },
217 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130,
218 "Microsoft MN-130 10/100" },
219 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE,
220 "Microsoft MN-130 10/100" },
224 static int dc_probe(device_t);
225 static int dc_attach(device_t);
226 static int dc_detach(device_t);
227 static int dc_suspend(device_t);
228 static int dc_resume(device_t);
229 static struct dc_type *dc_devtype(device_t);
230 static int dc_newbuf(struct dc_softc *, int, int);
231 static int dc_encap(struct dc_softc *, struct mbuf **);
232 static void dc_pnic_rx_bug_war(struct dc_softc *, int);
233 static int dc_rx_resync(struct dc_softc *);
234 static void dc_rxeof(struct dc_softc *);
235 static void dc_txeof(struct dc_softc *);
236 static void dc_tick(void *);
237 static void dc_tx_underrun(struct dc_softc *);
238 static void dc_intr(void *);
239 static void dc_start(struct ifnet *);
240 static int dc_ioctl(struct ifnet *, u_long, caddr_t);
241 static void dc_init(void *);
242 static void dc_stop(struct dc_softc *);
243 static void dc_watchdog(struct ifnet *);
244 static void dc_shutdown(device_t);
245 static int dc_ifmedia_upd(struct ifnet *);
246 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
248 static void dc_delay(struct dc_softc *);
249 static void dc_eeprom_idle(struct dc_softc *);
250 static void dc_eeprom_putbyte(struct dc_softc *, int);
251 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
252 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
253 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
254 static void dc_eeprom_width(struct dc_softc *);
255 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
257 static void dc_mii_writebit(struct dc_softc *, int);
258 static int dc_mii_readbit(struct dc_softc *);
259 static void dc_mii_sync(struct dc_softc *);
260 static void dc_mii_send(struct dc_softc *, u_int32_t, int);
261 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
262 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
263 static int dc_miibus_readreg(device_t, int, int);
264 static int dc_miibus_writereg(device_t, int, int, int);
265 static void dc_miibus_statchg(device_t);
266 static void dc_miibus_mediainit(device_t);
268 static void dc_setcfg(struct dc_softc *, int);
269 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
270 static uint32_t dc_mchash_be(const uint8_t *);
271 static void dc_setfilt_21143(struct dc_softc *);
272 static void dc_setfilt_asix(struct dc_softc *);
273 static void dc_setfilt_admtek(struct dc_softc *);
274 static void dc_setfilt_xircom(struct dc_softc *);
276 static void dc_setfilt(struct dc_softc *);
278 static void dc_reset(struct dc_softc *);
279 static int dc_list_rx_init(struct dc_softc *);
280 static int dc_list_tx_init(struct dc_softc *);
282 static void dc_read_srom(struct dc_softc *, int);
283 static void dc_parse_21143_srom(struct dc_softc *);
284 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
285 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
286 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
287 static void dc_apply_fixup(struct dc_softc *, int);
289 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
290 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
293 #define DC_RES SYS_RES_IOPORT
294 #define DC_RID DC_PCI_CFBIO
296 #define DC_RES SYS_RES_MEMORY
297 #define DC_RID DC_PCI_CFBMA
300 static device_method_t dc_methods[] = {
301 /* Device interface */
302 DEVMETHOD(device_probe, dc_probe),
303 DEVMETHOD(device_attach, dc_attach),
304 DEVMETHOD(device_detach, dc_detach),
305 DEVMETHOD(device_suspend, dc_suspend),
306 DEVMETHOD(device_resume, dc_resume),
307 DEVMETHOD(device_shutdown, dc_shutdown),
310 DEVMETHOD(bus_print_child, bus_generic_print_child),
311 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
314 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
315 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
316 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
317 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
322 static driver_t dc_driver = {
325 sizeof(struct dc_softc)
328 static devclass_t dc_devclass;
330 static int dc_quick = 1;
331 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0,
332 "do not m_devget() in dc driver");
335 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0);
336 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
337 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
339 #define DC_SETBIT(sc, reg, x) \
340 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
342 #define DC_CLRBIT(sc, reg, x) \
343 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
345 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
346 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
351 dc_delay(struct dc_softc *sc)
355 for (idx = (300 / 33) + 1; idx > 0; idx--)
356 CSR_READ_4(sc, DC_BUSCTL);
360 dc_eeprom_width(struct dc_softc *sc)
364 /* Force EEPROM to idle state. */
367 /* Enter EEPROM access mode. */
368 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
370 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
372 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
374 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
379 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
381 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
385 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
389 for (i = 1; i <= 12; i++) {
390 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
392 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
393 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
401 /* Turn off EEPROM access mode. */
409 /* Enter EEPROM access mode. */
410 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
412 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
416 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
419 /* Turn off EEPROM access mode. */
424 dc_eeprom_idle(struct dc_softc *sc)
428 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
430 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
432 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
434 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
437 for (i = 0; i < 25; i++) {
438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
448 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
452 * Send a read command and address to the EEPROM, check for ACK.
455 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
459 d = DC_EECMD_READ >> 6;
462 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
464 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
466 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
473 * Feed in each bit and strobe the clock.
475 for (i = sc->dc_romwidth; i--;) {
476 if (addr & (1 << i)) {
477 SIO_SET(DC_SIO_EE_DATAIN);
479 SIO_CLR(DC_SIO_EE_DATAIN);
482 SIO_SET(DC_SIO_EE_CLK);
484 SIO_CLR(DC_SIO_EE_CLK);
490 * Read a word of data stored in the EEPROM at address 'addr.'
491 * The PNIC 82c168/82c169 has its own non-standard way to read
495 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
500 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
502 for (i = 0; i < DC_TIMEOUT; i++) {
504 r = CSR_READ_4(sc, DC_SIO);
505 if (!(r & DC_PN_SIOCTL_BUSY)) {
506 *dest = (u_int16_t)(r & 0xFFFF);
513 * Read a word of data stored in the EEPROM at address 'addr.'
514 * The Xircom X3201 has its own non-standard way to read
518 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
521 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
524 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
525 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
527 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
528 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
530 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
534 * Read a word of data stored in the EEPROM at address 'addr.'
537 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
542 /* Force EEPROM to idle state. */
545 /* Enter EEPROM access mode. */
546 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
548 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
550 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
552 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
556 * Send address of word we want to read.
558 dc_eeprom_putbyte(sc, addr);
561 * Start reading bits from EEPROM.
563 for (i = 0x8000; i; i >>= 1) {
564 SIO_SET(DC_SIO_EE_CLK);
566 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
569 SIO_CLR(DC_SIO_EE_CLK);
573 /* Turn off EEPROM access mode. */
580 * Read a sequence of words from the EEPROM.
583 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
586 u_int16_t word = 0, *ptr;
588 for (i = 0; i < cnt; i++) {
590 dc_eeprom_getword_pnic(sc, off + i, &word);
591 else if (DC_IS_XIRCOM(sc))
592 dc_eeprom_getword_xircom(sc, off + i, &word);
594 dc_eeprom_getword(sc, off + i, &word);
595 ptr = (u_int16_t *)(dest + (i * 2));
597 *ptr = be16toh(word);
599 *ptr = le16toh(word);
604 * The following two routines are taken from the Macronix 98713
605 * Application Notes pp.19-21.
608 * Write a bit to the MII bus.
611 dc_mii_writebit(struct dc_softc *sc, int bit)
615 CSR_WRITE_4(sc, DC_SIO,
616 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT);
618 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
620 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
621 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
625 * Read a bit from the MII bus.
628 dc_mii_readbit(struct dc_softc *sc)
631 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR);
632 CSR_READ_4(sc, DC_SIO);
633 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
634 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
635 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
642 * Sync the PHYs by setting data bit and strobing the clock 32 times.
645 dc_mii_sync(struct dc_softc *sc)
649 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
651 for (i = 0; i < 32; i++)
652 dc_mii_writebit(sc, 1);
656 * Clock a series of bits through the MII.
659 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
663 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
664 dc_mii_writebit(sc, bits & i);
668 * Read an PHY register through the MII.
671 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
678 * Set up frame for RX.
680 frame->mii_stdelim = DC_MII_STARTDELIM;
681 frame->mii_opcode = DC_MII_READOP;
682 frame->mii_turnaround = 0;
691 * Send command/address info.
693 dc_mii_send(sc, frame->mii_stdelim, 2);
694 dc_mii_send(sc, frame->mii_opcode, 2);
695 dc_mii_send(sc, frame->mii_phyaddr, 5);
696 dc_mii_send(sc, frame->mii_regaddr, 5);
700 dc_mii_writebit(sc, 1);
701 dc_mii_writebit(sc, 0);
705 ack = dc_mii_readbit(sc);
708 * Now try reading data bits. If the ack failed, we still
709 * need to clock through 16 cycles to keep the PHY(s) in sync.
712 for (i = 0; i < 16; i++)
717 for (i = 0x8000; i; i >>= 1) {
719 if (dc_mii_readbit(sc))
720 frame->mii_data |= i;
726 dc_mii_writebit(sc, 0);
727 dc_mii_writebit(sc, 0);
737 * Write to a PHY register through the MII.
740 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
745 * Set up frame for TX.
748 frame->mii_stdelim = DC_MII_STARTDELIM;
749 frame->mii_opcode = DC_MII_WRITEOP;
750 frame->mii_turnaround = DC_MII_TURNAROUND;
757 dc_mii_send(sc, frame->mii_stdelim, 2);
758 dc_mii_send(sc, frame->mii_opcode, 2);
759 dc_mii_send(sc, frame->mii_phyaddr, 5);
760 dc_mii_send(sc, frame->mii_regaddr, 5);
761 dc_mii_send(sc, frame->mii_turnaround, 2);
762 dc_mii_send(sc, frame->mii_data, 16);
765 dc_mii_writebit(sc, 0);
766 dc_mii_writebit(sc, 0);
774 dc_miibus_readreg(device_t dev, int phy, int reg)
776 struct dc_mii_frame frame;
778 int i, rval, phy_reg = 0;
780 sc = device_get_softc(dev);
781 bzero(&frame, sizeof(frame));
784 * Note: both the AL981 and AN985 have internal PHYs,
785 * however the AL981 provides direct access to the PHY
786 * registers while the AN985 uses a serial MII interface.
787 * The AN985's MII interface is also buggy in that you
788 * can read from any MII address (0 to 31), but only address 1
789 * behaves normally. To deal with both cases, we pretend
790 * that the PHY is at MII address 1.
792 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
796 * Note: the ukphy probes of the RS7112 report a PHY at
797 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
798 * so we only respond to correct one.
800 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
803 if (sc->dc_pmode != DC_PMODE_MII) {
804 if (phy == (MII_NPHY - 1)) {
808 * Fake something to make the probe
809 * code think there's a PHY here.
811 return (BMSR_MEDIAMASK);
815 return (DC_VENDORID_LO);
816 return (DC_VENDORID_DEC);
820 return (DC_DEVICEID_82C168);
821 return (DC_DEVICEID_21143);
831 if (DC_IS_PNIC(sc)) {
832 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
833 (phy << 23) | (reg << 18));
834 for (i = 0; i < DC_TIMEOUT; i++) {
836 rval = CSR_READ_4(sc, DC_PN_MII);
837 if (!(rval & DC_PN_MII_BUSY)) {
839 return (rval == 0xFFFF ? 0 : rval);
845 if (DC_IS_COMET(sc)) {
848 phy_reg = DC_AL_BMCR;
851 phy_reg = DC_AL_BMSR;
854 phy_reg = DC_AL_VENID;
857 phy_reg = DC_AL_DEVID;
860 phy_reg = DC_AL_ANAR;
863 phy_reg = DC_AL_LPAR;
866 phy_reg = DC_AL_ANER;
869 printf("dc%d: phy_read: bad phy register %x\n",
875 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
882 frame.mii_phyaddr = phy;
883 frame.mii_regaddr = reg;
884 if (sc->dc_type == DC_TYPE_98713) {
885 phy_reg = CSR_READ_4(sc, DC_NETCFG);
886 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
888 dc_mii_readreg(sc, &frame);
889 if (sc->dc_type == DC_TYPE_98713)
890 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
892 return (frame.mii_data);
896 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
899 struct dc_mii_frame frame;
902 sc = device_get_softc(dev);
903 bzero(&frame, sizeof(frame));
905 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
908 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
911 if (DC_IS_PNIC(sc)) {
912 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
913 (phy << 23) | (reg << 10) | data);
914 for (i = 0; i < DC_TIMEOUT; i++) {
915 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
921 if (DC_IS_COMET(sc)) {
924 phy_reg = DC_AL_BMCR;
927 phy_reg = DC_AL_BMSR;
930 phy_reg = DC_AL_VENID;
933 phy_reg = DC_AL_DEVID;
936 phy_reg = DC_AL_ANAR;
939 phy_reg = DC_AL_LPAR;
942 phy_reg = DC_AL_ANER;
945 printf("dc%d: phy_write: bad phy register %x\n",
951 CSR_WRITE_4(sc, phy_reg, data);
955 frame.mii_phyaddr = phy;
956 frame.mii_regaddr = reg;
957 frame.mii_data = data;
959 if (sc->dc_type == DC_TYPE_98713) {
960 phy_reg = CSR_READ_4(sc, DC_NETCFG);
961 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
963 dc_mii_writereg(sc, &frame);
964 if (sc->dc_type == DC_TYPE_98713)
965 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
971 dc_miibus_statchg(device_t dev)
974 struct mii_data *mii;
977 sc = device_get_softc(dev);
978 if (DC_IS_ADMTEK(sc))
981 mii = device_get_softc(sc->dc_miibus);
982 ifm = &mii->mii_media;
983 if (DC_IS_DAVICOM(sc) &&
984 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
985 dc_setcfg(sc, ifm->ifm_media);
986 sc->dc_if_media = ifm->ifm_media;
988 dc_setcfg(sc, mii->mii_media_active);
989 sc->dc_if_media = mii->mii_media_active;
994 * Special support for DM9102A cards with HomePNA PHYs. Note:
995 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
996 * to be impossible to talk to the management interface of the DM9801
997 * PHY (its MDIO pin is not connected to anything). Consequently,
998 * the driver has to just 'know' about the additional mode and deal
999 * with it itself. *sigh*
1002 dc_miibus_mediainit(device_t dev)
1004 struct dc_softc *sc;
1005 struct mii_data *mii;
1006 struct ifmedia *ifm;
1009 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1011 sc = device_get_softc(dev);
1012 mii = device_get_softc(sc->dc_miibus);
1013 ifm = &mii->mii_media;
1015 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1016 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1019 #define DC_BITS_512 9
1020 #define DC_BITS_128 7
1021 #define DC_BITS_64 6
1024 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
1028 /* Compute CRC for the address value. */
1029 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
1032 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1033 * chips is only 128 bits wide.
1035 if (sc->dc_flags & DC_128BIT_HASH)
1036 return (crc & ((1 << DC_BITS_128) - 1));
1038 /* The hash table on the MX98715BEC is only 64 bits wide. */
1039 if (sc->dc_flags & DC_64BIT_HASH)
1040 return (crc & ((1 << DC_BITS_64) - 1));
1042 /* Xircom's hash filtering table is different (read: weird) */
1043 /* Xircom uses the LEAST significant bits */
1044 if (DC_IS_XIRCOM(sc)) {
1045 if ((crc & 0x180) == 0x180)
1046 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
1048 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
1052 return (crc & ((1 << DC_BITS_512) - 1));
1056 * Calculate CRC of a multicast group address, return the lower 6 bits.
1059 dc_mchash_be(const uint8_t *addr)
1063 /* Compute CRC for the address value. */
1064 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
1066 /* Return the filter bit position. */
1067 return ((crc >> 26) & 0x0000003F);
1071 * 21143-style RX filter setup routine. Filter programming is done by
1072 * downloading a special setup frame into the TX engine. 21143, Macronix,
1073 * PNIC, PNIC II and Davicom chips are programmed this way.
1075 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1076 * address (our node address) and a 512-bit hash filter for multicast
1077 * frames. We also sneak the broadcast address into the hash filter since
1081 dc_setfilt_21143(struct dc_softc *sc)
1083 struct dc_desc *sframe;
1085 struct ifmultiaddr *ifma;
1089 ifp = &sc->arpcom.ac_if;
1091 i = sc->dc_cdata.dc_tx_prod;
1092 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1093 sc->dc_cdata.dc_tx_cnt++;
1094 sframe = &sc->dc_ldata->dc_tx_list[i];
1095 sp = sc->dc_cdata.dc_sbuf;
1096 bzero(sp, DC_SFRAME_LEN);
1098 sframe->dc_data = htole32(sc->dc_saddr);
1099 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1100 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1102 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1104 /* If we want promiscuous mode, set the allframes bit. */
1105 if (ifp->if_flags & IFF_PROMISC)
1106 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1108 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1110 if (ifp->if_flags & IFF_ALLMULTI)
1111 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1113 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1115 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1116 if (ifma->ifma_addr->sa_family != AF_LINK)
1118 h = dc_mchash_le(sc,
1119 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1120 sp[h >> 4] |= htole32(1 << (h & 0xF));
1123 if (ifp->if_flags & IFF_BROADCAST) {
1124 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1125 sp[h >> 4] |= htole32(1 << (h & 0xF));
1128 /* Set our MAC address */
1129 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1130 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1131 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1133 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1134 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1137 * The PNIC takes an exceedingly long time to process its
1138 * setup frame; wait 10ms after posting the setup frame
1139 * before proceeding, just so it has time to swallow its
1148 dc_setfilt_admtek(struct dc_softc *sc)
1151 struct ifmultiaddr *ifma;
1153 u_int32_t hashes[2] = { 0, 0 };
1155 ifp = &sc->arpcom.ac_if;
1157 /* Init our MAC address. */
1158 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1159 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1161 /* If we want promiscuous mode, set the allframes bit. */
1162 if (ifp->if_flags & IFF_PROMISC)
1163 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1165 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1167 if (ifp->if_flags & IFF_ALLMULTI)
1168 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1170 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1172 /* First, zot all the existing hash bits. */
1173 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1174 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1177 * If we're already in promisc or allmulti mode, we
1178 * don't have to bother programming the multicast filter.
1180 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1183 /* Now program new ones. */
1184 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1185 if (ifma->ifma_addr->sa_family != AF_LINK)
1187 if (DC_IS_CENTAUR(sc))
1188 h = dc_mchash_le(sc,
1189 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1192 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1194 hashes[0] |= (1 << h);
1196 hashes[1] |= (1 << (h - 32));
1199 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1200 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1204 dc_setfilt_asix(struct dc_softc *sc)
1207 struct ifmultiaddr *ifma;
1209 u_int32_t hashes[2] = { 0, 0 };
1211 ifp = &sc->arpcom.ac_if;
1213 /* Init our MAC address */
1214 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1215 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1216 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1217 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1218 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1219 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1221 /* If we want promiscuous mode, set the allframes bit. */
1222 if (ifp->if_flags & IFF_PROMISC)
1223 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1225 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1227 if (ifp->if_flags & IFF_ALLMULTI)
1228 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1230 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1233 * The ASIX chip has a special bit to enable reception
1234 * of broadcast frames.
1236 if (ifp->if_flags & IFF_BROADCAST)
1237 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1239 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1241 /* first, zot all the existing hash bits */
1242 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1243 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1244 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1245 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1248 * If we're already in promisc or allmulti mode, we
1249 * don't have to bother programming the multicast filter.
1251 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1254 /* now program new ones */
1255 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1256 if (ifma->ifma_addr->sa_family != AF_LINK)
1258 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1260 hashes[0] |= (1 << h);
1262 hashes[1] |= (1 << (h - 32));
1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1267 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1268 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1272 dc_setfilt_xircom(struct dc_softc *sc)
1275 struct ifmultiaddr *ifma;
1276 struct dc_desc *sframe;
1280 ifp = &sc->arpcom.ac_if;
1281 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1283 i = sc->dc_cdata.dc_tx_prod;
1284 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1285 sc->dc_cdata.dc_tx_cnt++;
1286 sframe = &sc->dc_ldata->dc_tx_list[i];
1287 sp = sc->dc_cdata.dc_sbuf;
1288 bzero(sp, DC_SFRAME_LEN);
1290 sframe->dc_data = htole32(sc->dc_saddr);
1291 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1292 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1294 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1296 /* If we want promiscuous mode, set the allframes bit. */
1297 if (ifp->if_flags & IFF_PROMISC)
1298 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1300 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1302 if (ifp->if_flags & IFF_ALLMULTI)
1303 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1305 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1307 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1308 if (ifma->ifma_addr->sa_family != AF_LINK)
1310 h = dc_mchash_le(sc,
1311 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1312 sp[h >> 4] |= htole32(1 << (h & 0xF));
1315 if (ifp->if_flags & IFF_BROADCAST) {
1316 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1317 sp[h >> 4] |= htole32(1 << (h & 0xF));
1320 /* Set our MAC address */
1321 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1322 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1323 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1325 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1326 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1327 ifp->if_flags |= IFF_RUNNING;
1328 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1329 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1340 dc_setfilt(struct dc_softc *sc)
1343 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1344 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1345 dc_setfilt_21143(sc);
1348 dc_setfilt_asix(sc);
1350 if (DC_IS_ADMTEK(sc))
1351 dc_setfilt_admtek(sc);
1353 if (DC_IS_XIRCOM(sc))
1354 dc_setfilt_xircom(sc);
1358 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1359 * the netconfig register, we first have to put the transmit and/or
1360 * receive logic in the idle state.
1363 dc_setcfg(struct dc_softc *sc, int media)
1365 int i, restart = 0, watchdogreg;
1368 if (IFM_SUBTYPE(media) == IFM_NONE)
1371 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1373 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1375 for (i = 0; i < DC_TIMEOUT; i++) {
1376 isr = CSR_READ_4(sc, DC_ISR);
1377 if (isr & DC_ISR_TX_IDLE &&
1378 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1379 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1384 if (i == DC_TIMEOUT)
1385 printf("dc%d: failed to force tx and "
1386 "rx to idle state\n", sc->dc_unit);
1389 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1390 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1391 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1392 if (sc->dc_pmode == DC_PMODE_MII) {
1393 if (DC_IS_INTEL(sc)) {
1394 /* There's a write enable bit here that reads as 1. */
1395 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1396 watchdogreg &= ~DC_WDOG_CTLWREN;
1397 watchdogreg |= DC_WDOG_JABBERDIS;
1398 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1400 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1402 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1403 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1404 if (sc->dc_type == DC_TYPE_98713)
1405 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1406 DC_NETCFG_SCRAMBLER));
1407 if (!DC_IS_DAVICOM(sc))
1408 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1409 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1410 if (DC_IS_INTEL(sc))
1411 dc_apply_fixup(sc, IFM_AUTO);
1413 if (DC_IS_PNIC(sc)) {
1414 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1415 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1416 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1419 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1421 if (DC_IS_INTEL(sc))
1423 (media & IFM_GMASK) == IFM_FDX ?
1424 IFM_100_TX | IFM_FDX : IFM_100_TX);
1428 if (IFM_SUBTYPE(media) == IFM_10_T) {
1429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1430 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1431 if (sc->dc_pmode == DC_PMODE_MII) {
1432 /* There's a write enable bit here that reads as 1. */
1433 if (DC_IS_INTEL(sc)) {
1434 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1435 watchdogreg &= ~DC_WDOG_CTLWREN;
1436 watchdogreg |= DC_WDOG_JABBERDIS;
1437 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1439 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1441 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1442 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1443 if (sc->dc_type == DC_TYPE_98713)
1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1445 if (!DC_IS_DAVICOM(sc))
1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1447 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1448 if (DC_IS_INTEL(sc))
1449 dc_apply_fixup(sc, IFM_AUTO);
1451 if (DC_IS_PNIC(sc)) {
1452 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1453 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1454 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1456 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1457 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1458 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1459 if (DC_IS_INTEL(sc)) {
1460 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1461 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1462 if ((media & IFM_GMASK) == IFM_FDX)
1463 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1465 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1466 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1467 DC_CLRBIT(sc, DC_10BTCTRL,
1468 DC_TCTL_AUTONEGENBL);
1470 (media & IFM_GMASK) == IFM_FDX ?
1471 IFM_10_T | IFM_FDX : IFM_10_T);
1478 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1479 * PHY and we want HomePNA mode, set the portsel bit to turn
1480 * on the external MII port.
1482 if (DC_IS_DAVICOM(sc)) {
1483 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1484 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1487 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1491 if ((media & IFM_GMASK) == IFM_FDX) {
1492 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1493 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1494 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1496 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1497 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1498 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1502 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1506 dc_reset(struct dc_softc *sc)
1510 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1512 for (i = 0; i < DC_TIMEOUT; i++) {
1514 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1518 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1519 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
1521 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1525 if (i == DC_TIMEOUT)
1526 printf("dc%d: reset never completed!\n", sc->dc_unit);
1528 /* Wait a little while for the chip to get its brains in order. */
1531 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1532 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1533 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1536 * Bring the SIA out of reset. In some cases, it looks
1537 * like failing to unreset the SIA soon enough gets it
1538 * into a state where it will never come out of reset
1539 * until we reset the whole chip again.
1541 if (DC_IS_INTEL(sc)) {
1542 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1543 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1544 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1548 static struct dc_type *
1549 dc_devtype(device_t dev)
1556 while (t->dc_name != NULL) {
1557 if ((pci_get_vendor(dev) == t->dc_vid) &&
1558 (pci_get_device(dev) == t->dc_did)) {
1559 /* Check the PCI revision */
1560 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1561 if (t->dc_did == DC_DEVICEID_98713 &&
1562 rev >= DC_REVISION_98713A)
1564 if (t->dc_did == DC_DEVICEID_98713_CP &&
1565 rev >= DC_REVISION_98713A)
1567 if (t->dc_did == DC_DEVICEID_987x5 &&
1568 rev >= DC_REVISION_98715AEC_C)
1570 if (t->dc_did == DC_DEVICEID_987x5 &&
1571 rev >= DC_REVISION_98725)
1573 if (t->dc_did == DC_DEVICEID_AX88140A &&
1574 rev >= DC_REVISION_88141)
1576 if (t->dc_did == DC_DEVICEID_82C168 &&
1577 rev >= DC_REVISION_82C169)
1579 if (t->dc_did == DC_DEVICEID_DM9102 &&
1580 rev >= DC_REVISION_DM9102A)
1583 * The Microsoft MN-130 has a device ID of 0x0002,
1584 * which happens to be the same as the PNIC 82c168.
1585 * To keep dc_attach() from getting confused, we
1586 * pretend its ID is something different.
1587 * XXX: ideally, dc_attach() should be checking
1588 * vendorid+deviceid together to avoid such
1591 if (t->dc_vid == DC_VENDORID_MICROSOFT &&
1592 t->dc_did == DC_DEVICEID_MSMN130)
1603 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1604 * IDs against our list and return a device name if we find a match.
1605 * We do a little bit of extra work to identify the exact type of
1606 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1607 * but different revision IDs. The same is true for 98715/98715A
1608 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1609 * cases, the exact chip revision affects driver behavior.
1612 dc_probe(device_t dev)
1616 t = dc_devtype(dev);
1619 device_set_desc(dev, t->dc_name);
1620 return (BUS_PROBE_DEFAULT);
1627 dc_apply_fixup(struct dc_softc *sc, int media)
1629 struct dc_mediainfo *m;
1637 if (m->dc_media == media)
1645 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1646 reg = (p[0] | (p[1] << 8)) << 16;
1647 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1650 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1651 reg = (p[0] | (p[1] << 8)) << 16;
1652 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1657 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1659 struct dc_mediainfo *m;
1661 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1662 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1663 case DC_SIA_CODE_10BT:
1664 m->dc_media = IFM_10_T;
1666 case DC_SIA_CODE_10BT_FDX:
1667 m->dc_media = IFM_10_T | IFM_FDX;
1669 case DC_SIA_CODE_10B2:
1670 m->dc_media = IFM_10_2;
1672 case DC_SIA_CODE_10B5:
1673 m->dc_media = IFM_10_5;
1680 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1681 * Things apparently already work for cards that do
1682 * supply Media Specific Data.
1684 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1687 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1691 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1694 m->dc_next = sc->dc_mi;
1697 sc->dc_pmode = DC_PMODE_SIA;
1701 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1703 struct dc_mediainfo *m;
1705 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1706 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1707 m->dc_media = IFM_100_TX;
1709 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1710 m->dc_media = IFM_100_TX | IFM_FDX;
1713 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1715 m->dc_next = sc->dc_mi;
1718 sc->dc_pmode = DC_PMODE_SYM;
1722 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1724 struct dc_mediainfo *m;
1727 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1728 /* We abuse IFM_AUTO to represent MII. */
1729 m->dc_media = IFM_AUTO;
1730 m->dc_gp_len = l->dc_gpr_len;
1733 p += sizeof(struct dc_eblock_mii);
1735 p += 2 * l->dc_gpr_len;
1736 m->dc_reset_len = *p;
1738 m->dc_reset_ptr = p;
1740 m->dc_next = sc->dc_mi;
1745 dc_read_srom(struct dc_softc *sc, int bits)
1750 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1751 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1755 dc_parse_21143_srom(struct dc_softc *sc)
1757 struct dc_leaf_hdr *lhdr;
1758 struct dc_eblock_hdr *hdr;
1759 int have_mii, i, loff;
1763 loff = sc->dc_srom[27];
1764 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1767 ptr += sizeof(struct dc_leaf_hdr) - 1;
1769 * Look if we got a MII media block.
1771 for (i = 0; i < lhdr->dc_mcnt; i++) {
1772 hdr = (struct dc_eblock_hdr *)ptr;
1773 if (hdr->dc_type == DC_EBLOCK_MII)
1776 ptr += (hdr->dc_len & 0x7F);
1781 * Do the same thing again. Only use SIA and SYM media
1782 * blocks if no MII media block is available.
1785 ptr += sizeof(struct dc_leaf_hdr) - 1;
1786 for (i = 0; i < lhdr->dc_mcnt; i++) {
1787 hdr = (struct dc_eblock_hdr *)ptr;
1788 switch (hdr->dc_type) {
1790 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1794 dc_decode_leaf_sia(sc,
1795 (struct dc_eblock_sia *)hdr);
1799 dc_decode_leaf_sym(sc,
1800 (struct dc_eblock_sym *)hdr);
1803 /* Don't care. Yet. */
1806 ptr += (hdr->dc_len & 0x7F);
1812 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1816 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1818 *paddr = segs->ds_addr;
1822 * Attach the interface. Allocate softc structures, do ifmedia
1823 * setup and ethernet/BPF attach.
1826 dc_attach(device_t dev)
1829 u_char eaddr[ETHER_ADDR_LEN];
1831 struct dc_softc *sc;
1834 int unit, error = 0, rid, mac_offset;
1838 sc = device_get_softc(dev);
1839 unit = device_get_unit(dev);
1841 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1842 MTX_DEF | MTX_RECURSE);
1845 * Map control/status registers.
1847 pci_enable_busmaster(dev);
1850 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1852 if (sc->dc_res == NULL) {
1853 printf("dc%d: couldn't map ports/memory\n", unit);
1858 sc->dc_btag = rman_get_bustag(sc->dc_res);
1859 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1861 /* Allocate interrupt. */
1863 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1864 RF_SHAREABLE | RF_ACTIVE);
1866 if (sc->dc_irq == NULL) {
1867 printf("dc%d: couldn't map interrupt\n", unit);
1872 /* Need this info to decide on a chip type. */
1873 sc->dc_info = dc_devtype(dev);
1874 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF;
1876 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1877 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 &&
1878 sc->dc_info->dc_did != DC_DEVICEID_X3201)
1879 dc_eeprom_width(sc);
1881 switch (sc->dc_info->dc_did) {
1882 case DC_DEVICEID_21143:
1883 sc->dc_type = DC_TYPE_21143;
1884 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1885 sc->dc_flags |= DC_REDUCED_MII_POLL;
1886 /* Save EEPROM contents so we can parse them later. */
1887 dc_read_srom(sc, sc->dc_romwidth);
1889 case DC_DEVICEID_DM9009:
1890 case DC_DEVICEID_DM9100:
1891 case DC_DEVICEID_DM9102:
1892 sc->dc_type = DC_TYPE_DM9102;
1893 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
1894 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
1895 sc->dc_flags |= DC_TX_ALIGN;
1896 sc->dc_pmode = DC_PMODE_MII;
1897 /* Increase the latency timer value. */
1898 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1899 command &= 0xFFFF00FF;
1900 command |= 0x00008000;
1901 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1903 case DC_DEVICEID_AL981:
1904 sc->dc_type = DC_TYPE_AL981;
1905 sc->dc_flags |= DC_TX_USE_TX_INTR;
1906 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1907 sc->dc_pmode = DC_PMODE_MII;
1908 dc_read_srom(sc, sc->dc_romwidth);
1910 case DC_DEVICEID_AN985:
1911 case DC_DEVICEID_ADM9511:
1912 case DC_DEVICEID_ADM9513:
1913 case DC_DEVICEID_FA511:
1914 case DC_DEVICEID_FE2500:
1915 case DC_DEVICEID_EN2242:
1916 case DC_DEVICEID_HAWKING_PN672TX:
1917 case DC_DEVICEID_3CSOHOB:
1918 case DC_DEVICEID_MSMN120:
1919 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/
1920 sc->dc_type = DC_TYPE_AN985;
1921 sc->dc_flags |= DC_64BIT_HASH;
1922 sc->dc_flags |= DC_TX_USE_TX_INTR;
1923 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1924 sc->dc_pmode = DC_PMODE_MII;
1925 /* Don't read SROM for - auto-loaded on reset */
1927 case DC_DEVICEID_98713:
1928 case DC_DEVICEID_98713_CP:
1929 if (revision < DC_REVISION_98713A) {
1930 sc->dc_type = DC_TYPE_98713;
1932 if (revision >= DC_REVISION_98713A) {
1933 sc->dc_type = DC_TYPE_98713A;
1934 sc->dc_flags |= DC_21143_NWAY;
1936 sc->dc_flags |= DC_REDUCED_MII_POLL;
1937 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1939 case DC_DEVICEID_987x5:
1940 case DC_DEVICEID_EN1217:
1942 * Macronix MX98715AEC-C/D/E parts have only a
1943 * 128-bit hash table. We need to deal with these
1944 * in the same manner as the PNIC II so that we
1945 * get the right number of bits out of the
1948 if (revision >= DC_REVISION_98715AEC_C &&
1949 revision < DC_REVISION_98725)
1950 sc->dc_flags |= DC_128BIT_HASH;
1951 sc->dc_type = DC_TYPE_987x5;
1952 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1953 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1955 case DC_DEVICEID_98727:
1956 sc->dc_type = DC_TYPE_987x5;
1957 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1958 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1960 case DC_DEVICEID_82C115:
1961 sc->dc_type = DC_TYPE_PNICII;
1962 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
1963 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1965 case DC_DEVICEID_82C168:
1966 sc->dc_type = DC_TYPE_PNIC;
1967 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
1968 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1969 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
1970 if (revision < DC_REVISION_82C169)
1971 sc->dc_pmode = DC_PMODE_SYM;
1973 case DC_DEVICEID_AX88140A:
1974 sc->dc_type = DC_TYPE_ASIX;
1975 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
1976 sc->dc_flags |= DC_REDUCED_MII_POLL;
1977 sc->dc_pmode = DC_PMODE_MII;
1979 case DC_DEVICEID_X3201:
1980 sc->dc_type = DC_TYPE_XIRCOM;
1981 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
1984 * We don't actually need to coalesce, but we're doing
1985 * it to obtain a double word aligned buffer.
1986 * The DC_TX_COALESCE flag is required.
1988 sc->dc_pmode = DC_PMODE_MII;
1990 case DC_DEVICEID_RS7112:
1991 sc->dc_type = DC_TYPE_CONEXANT;
1992 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1993 sc->dc_flags |= DC_REDUCED_MII_POLL;
1994 sc->dc_pmode = DC_PMODE_MII;
1995 dc_read_srom(sc, sc->dc_romwidth);
1998 printf("dc%d: unknown device: %x\n", sc->dc_unit,
1999 sc->dc_info->dc_did);
2003 /* Save the cache line size. */
2004 if (DC_IS_DAVICOM(sc))
2005 sc->dc_cachesize = 0;
2007 sc->dc_cachesize = pci_read_config(dev,
2008 DC_PCI_CFLT, 4) & 0xFF;
2010 /* Reset the adapter. */
2013 /* Take 21143 out of snooze mode */
2014 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2015 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2016 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2017 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2021 * Try to learn something about the supported media.
2022 * We know that ASIX and ADMtek and Davicom devices
2023 * will *always* be using MII media, so that's a no-brainer.
2024 * The tricky ones are the Macronix/PNIC II and the
2027 if (DC_IS_INTEL(sc))
2028 dc_parse_21143_srom(sc);
2029 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2030 if (sc->dc_type == DC_TYPE_98713)
2031 sc->dc_pmode = DC_PMODE_MII;
2033 sc->dc_pmode = DC_PMODE_SYM;
2034 } else if (!sc->dc_pmode)
2035 sc->dc_pmode = DC_PMODE_MII;
2038 * Get station address from the EEPROM.
2040 switch(sc->dc_type) {
2042 case DC_TYPE_98713A:
2044 case DC_TYPE_PNICII:
2045 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2046 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2047 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2050 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2052 case DC_TYPE_DM9102:
2053 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2056 * If this is an onboard dc(4) the station address read from
2057 * the EEPROM is all zero and we have to get it from the fcode.
2059 for (i = 0; i < ETHER_ADDR_LEN; i++)
2060 if (eaddr[i] != 0x00)
2062 if (i >= ETHER_ADDR_LEN)
2063 OF_getetheraddr(dev, eaddr);
2068 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2072 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0);
2073 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1);
2075 case DC_TYPE_CONEXANT:
2076 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2079 case DC_TYPE_XIRCOM:
2080 /* The MAC comes from the CIS. */
2081 mac = pci_get_ether(dev);
2083 device_printf(dev, "No station address in CIS!\n");
2087 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2090 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2095 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
2097 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
2098 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
2099 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1,
2100 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag);
2102 printf("dc%d: failed to allocate busdma tag\n", unit);
2106 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata,
2107 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap);
2109 printf("dc%d: failed to allocate DMA safe memory\n", unit);
2113 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata,
2114 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr,
2117 printf("dc%d: cannot get address of the descriptors\n", unit);
2123 * Allocate a busdma tag and DMA safe memory for the multicast
2126 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
2127 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1,
2128 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag);
2130 printf("dc%d: failed to allocate busdma tag\n", unit);
2134 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
2135 BUS_DMA_NOWAIT, &sc->dc_smap);
2137 printf("dc%d: failed to allocate DMA safe memory\n", unit);
2141 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
2142 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
2144 printf("dc%d: cannot get address of the descriptors\n", unit);
2149 /* Allocate a busdma tag for mbufs. */
2150 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
2151 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES,
2152 0, NULL, NULL, &sc->dc_mtag);
2154 printf("dc%d: failed to allocate busdma tag\n", unit);
2159 /* Create the TX/RX busdma maps. */
2160 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2161 error = bus_dmamap_create(sc->dc_mtag, 0,
2162 &sc->dc_cdata.dc_tx_map[i]);
2164 printf("dc%d: failed to init TX ring\n", unit);
2169 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2170 error = bus_dmamap_create(sc->dc_mtag, 0,
2171 &sc->dc_cdata.dc_rx_map[i]);
2173 printf("dc%d: failed to init RX ring\n", unit);
2178 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap);
2180 printf("dc%d: failed to init RX ring\n", unit);
2185 ifp = &sc->arpcom.ac_if;
2187 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2188 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */
2189 ifp->if_mtu = ETHERMTU;
2190 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2192 ifp->if_flags |= IFF_NEEDSGIANT;
2193 ifp->if_ioctl = dc_ioctl;
2194 ifp->if_start = dc_start;
2195 ifp->if_watchdog = dc_watchdog;
2196 ifp->if_init = dc_init;
2197 ifp->if_baudrate = 10000000;
2198 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2199 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2200 IFQ_SET_READY(&ifp->if_snd);
2203 * Do MII setup. If this is a 21143, check for a PHY on the
2204 * MII bus after applying any necessary fixups to twiddle the
2205 * GPIO bits. If we don't end up finding a PHY, restore the
2206 * old selection (SIA only or SIA/SYM) and attach the dcphy
2209 if (DC_IS_INTEL(sc)) {
2210 dc_apply_fixup(sc, IFM_AUTO);
2212 sc->dc_pmode = DC_PMODE_MII;
2216 * Setup General Purpose port mode and data so the tulip can talk
2217 * to the MII. This needs to be done before mii_phy_probe so that
2218 * we can actually see them.
2220 if (DC_IS_XIRCOM(sc)) {
2221 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2222 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2224 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2225 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2229 error = mii_phy_probe(dev, &sc->dc_miibus,
2230 dc_ifmedia_upd, dc_ifmedia_sts);
2232 if (error && DC_IS_INTEL(sc)) {
2234 if (sc->dc_pmode != DC_PMODE_SIA)
2235 sc->dc_pmode = DC_PMODE_SYM;
2236 sc->dc_flags |= DC_21143_NWAY;
2237 mii_phy_probe(dev, &sc->dc_miibus,
2238 dc_ifmedia_upd, dc_ifmedia_sts);
2240 * For non-MII cards, we need to have the 21143
2241 * drive the LEDs. Except there are some systems
2242 * like the NEC VersaPro NoteBook PC which have no
2243 * LEDs, and twiddling these bits has adverse effects
2244 * on them. (I.e. you suddenly can't get a link.)
2246 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2247 sc->dc_flags |= DC_TULIP_LEDS;
2252 printf("dc%d: MII without any PHY!\n", sc->dc_unit);
2256 if (DC_IS_ADMTEK(sc)) {
2258 * Set automatic TX underrun recovery for the ADMtek chips
2260 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2264 * Tell the upper layer(s) we support long frames.
2266 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2267 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2268 #ifdef DEVICE_POLLING
2269 ifp->if_capabilities |= IFCAP_POLLING;
2271 ifp->if_capenable = ifp->if_capabilities;
2273 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0);
2276 sc->dc_srm_media = 0;
2278 /* Remember the SRM console media setting */
2279 if (DC_IS_INTEL(sc)) {
2280 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2281 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2282 switch ((command >> 8) & 0xff) {
2284 sc->dc_srm_media = IFM_10_T;
2287 sc->dc_srm_media = IFM_10_T | IFM_FDX;
2290 sc->dc_srm_media = IFM_100_TX;
2293 sc->dc_srm_media = IFM_100_TX | IFM_FDX;
2296 if (sc->dc_srm_media)
2297 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER;
2302 * Call MI attach routine.
2304 ether_ifattach(ifp, eaddr);
2306 /* Hook interrupt last to avoid having to lock softc */
2307 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET |
2308 (IS_MPSAFE ? INTR_MPSAFE : 0),
2309 dc_intr, sc, &sc->dc_intrhand);
2312 printf("dc%d: couldn't set up irq\n", unit);
2313 ether_ifdetach(ifp);
2324 * Shutdown hardware and free up resources. This can be called any
2325 * time after the mutex has been initialized. It is called in both
2326 * the error case in attach and the normal detach case so it needs
2327 * to be careful about only freeing resources that have actually been
2331 dc_detach(device_t dev)
2333 struct dc_softc *sc;
2335 struct dc_mediainfo *m;
2338 sc = device_get_softc(dev);
2339 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2342 ifp = &sc->arpcom.ac_if;
2344 /* These should only be active if attach succeeded */
2345 if (device_is_attached(dev)) {
2347 ether_ifdetach(ifp);
2350 device_delete_child(dev, sc->dc_miibus);
2351 bus_generic_detach(dev);
2353 if (sc->dc_intrhand)
2354 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2356 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2358 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2360 if (sc->dc_cdata.dc_sbuf != NULL)
2361 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap);
2362 if (sc->dc_ldata != NULL)
2363 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap);
2364 for (i = 0; i < DC_TX_LIST_CNT; i++)
2365 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]);
2366 for (i = 0; i < DC_RX_LIST_CNT; i++)
2367 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
2368 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap);
2370 bus_dma_tag_destroy(sc->dc_stag);
2372 bus_dma_tag_destroy(sc->dc_mtag);
2374 bus_dma_tag_destroy(sc->dc_ltag);
2376 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2378 while (sc->dc_mi != NULL) {
2379 m = sc->dc_mi->dc_next;
2380 free(sc->dc_mi, M_DEVBUF);
2383 free(sc->dc_srom, M_DEVBUF);
2386 mtx_destroy(&sc->dc_mtx);
2392 * Initialize the transmit descriptors.
2395 dc_list_tx_init(struct dc_softc *sc)
2397 struct dc_chain_data *cd;
2398 struct dc_list_data *ld;
2403 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2404 if (i == DC_TX_LIST_CNT - 1)
2408 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2409 cd->dc_tx_chain[i] = NULL;
2410 ld->dc_tx_list[i].dc_data = 0;
2411 ld->dc_tx_list[i].dc_ctl = 0;
2414 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2415 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2416 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2422 * Initialize the RX descriptors and allocate mbufs for them. Note that
2423 * we arrange the descriptors in a closed ring, so that the last descriptor
2424 * points back to the first.
2427 dc_list_rx_init(struct dc_softc *sc)
2429 struct dc_chain_data *cd;
2430 struct dc_list_data *ld;
2436 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2437 if (dc_newbuf(sc, i, 1) != 0)
2439 if (i == DC_RX_LIST_CNT - 1)
2443 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2447 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2453 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
2455 bus_dma_segment_t *segs;
2460 struct dc_softc *sc;
2464 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur];
2466 sc->dc_cdata.dc_rx_err = error;
2470 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
2471 sc->dc_cdata.dc_rx_err = 0;
2472 c->dc_data = htole32(segs->ds_addr);
2476 * Initialize an RX descriptor and attach an MBUF cluster.
2479 dc_newbuf(struct dc_softc *sc, int i, int alloc)
2486 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2490 m_new = sc->dc_cdata.dc_rx_chain[i];
2491 m_new->m_data = m_new->m_ext.ext_buf;
2493 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2494 m_adj(m_new, sizeof(u_int64_t));
2497 * If this is a PNIC chip, zero the buffer. This is part
2498 * of the workaround for the receive bug in the 82c168 and
2501 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2502 bzero(mtod(m_new, char *), m_new->m_len);
2504 /* No need to remap the mbuf if we're reusing it. */
2506 sc->dc_cdata.dc_rx_cur = i;
2507 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap,
2508 m_new, dc_dma_map_rxbuf, sc, 0);
2513 if (sc->dc_cdata.dc_rx_err != 0) {
2515 return (sc->dc_cdata.dc_rx_err);
2517 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
2518 tmp = sc->dc_cdata.dc_rx_map[i];
2519 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2520 sc->dc_sparemap = tmp;
2521 sc->dc_cdata.dc_rx_chain[i] = m_new;
2524 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2525 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2526 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2527 BUS_DMASYNC_PREREAD);
2528 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2529 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2535 * The PNIC chip has a terrible bug in it that manifests itself during
2536 * periods of heavy activity. The exact mode of failure if difficult to
2537 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2538 * will happen on slow machines. The bug is that sometimes instead of
2539 * uploading one complete frame during reception, it uploads what looks
2540 * like the entire contents of its FIFO memory. The frame we want is at
2541 * the end of the whole mess, but we never know exactly how much data has
2542 * been uploaded, so salvaging the frame is hard.
2544 * There is only one way to do it reliably, and it's disgusting.
2545 * Here's what we know:
2547 * - We know there will always be somewhere between one and three extra
2548 * descriptors uploaded.
2550 * - We know the desired received frame will always be at the end of the
2551 * total data upload.
2553 * - We know the size of the desired received frame because it will be
2554 * provided in the length field of the status word in the last descriptor.
2556 * Here's what we do:
2558 * - When we allocate buffers for the receive ring, we bzero() them.
2559 * This means that we know that the buffer contents should be all
2560 * zeros, except for data uploaded by the chip.
2562 * - We also force the PNIC chip to upload frames that include the
2563 * ethernet CRC at the end.
2565 * - We gather all of the bogus frame data into a single buffer.
2567 * - We then position a pointer at the end of this buffer and scan
2568 * backwards until we encounter the first non-zero byte of data.
2569 * This is the end of the received frame. We know we will encounter
2570 * some data at the end of the frame because the CRC will always be
2571 * there, so even if the sender transmits a packet of all zeros,
2572 * we won't be fooled.
2574 * - We know the size of the actual received frame, so we subtract
2575 * that value from the current pointer location. This brings us
2576 * to the start of the actual received packet.
2578 * - We copy this into an mbuf and pass it on, along with the actual
2581 * The performance hit is tremendous, but it beats dropping frames all
2585 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2587 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2589 struct dc_desc *cur_rx;
2590 struct dc_desc *c = NULL;
2591 struct mbuf *m = NULL;
2594 u_int32_t rxstat = 0;
2596 i = sc->dc_pnic_rx_bug_save;
2597 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2598 ptr = sc->dc_pnic_rx_buf;
2599 bzero(ptr, DC_RXLEN * 5);
2601 /* Copy all the bytes from the bogus buffers. */
2603 c = &sc->dc_ldata->dc_rx_list[i];
2604 rxstat = le32toh(c->dc_status);
2605 m = sc->dc_cdata.dc_rx_chain[i];
2606 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2608 /* If this is the last buffer, break out. */
2609 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2611 dc_newbuf(sc, i, 0);
2612 DC_INC(i, DC_RX_LIST_CNT);
2615 /* Find the length of the actual receive frame. */
2616 total_len = DC_RXBYTES(rxstat);
2618 /* Scan backwards until we hit a non-zero byte. */
2619 while (*ptr == 0x00)
2623 if ((uintptr_t)(ptr) & 0x3)
2626 /* Now find the start of the frame. */
2628 if (ptr < sc->dc_pnic_rx_buf)
2629 ptr = sc->dc_pnic_rx_buf;
2632 * Now copy the salvaged frame to the last mbuf and fake up
2633 * the status word to make it look like a successful
2636 dc_newbuf(sc, i, 0);
2637 bcopy(ptr, mtod(m, char *), total_len);
2638 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2642 * This routine searches the RX ring for dirty descriptors in the
2643 * event that the rxeof routine falls out of sync with the chip's
2644 * current descriptor pointer. This may happen sometimes as a result
2645 * of a "no RX buffer available" condition that happens when the chip
2646 * consumes all of the RX buffers before the driver has a chance to
2647 * process the RX ring. This routine may need to be called more than
2648 * once to bring the driver back in sync with the chip, however we
2649 * should still be getting RX DONE interrupts to drive the search
2650 * for new packets in the RX ring, so we should catch up eventually.
2653 dc_rx_resync(struct dc_softc *sc)
2655 struct dc_desc *cur_rx;
2658 pos = sc->dc_cdata.dc_rx_prod;
2660 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2661 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2662 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2664 DC_INC(pos, DC_RX_LIST_CNT);
2667 /* If the ring really is empty, then just return. */
2668 if (i == DC_RX_LIST_CNT)
2671 /* We've fallen behing the chip: catch it. */
2672 sc->dc_cdata.dc_rx_prod = pos;
2678 * A frame has been uploaded: pass the resulting mbuf chain up to
2679 * the higher level protocols.
2682 dc_rxeof(struct dc_softc *sc)
2686 struct dc_desc *cur_rx;
2687 int i, total_len = 0;
2692 ifp = &sc->arpcom.ac_if;
2693 i = sc->dc_cdata.dc_rx_prod;
2695 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2696 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) &
2698 #ifdef DEVICE_POLLING
2699 if (ifp->if_flags & IFF_POLLING) {
2700 if (sc->rxcycles <= 0)
2705 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2706 rxstat = le32toh(cur_rx->dc_status);
2707 m = sc->dc_cdata.dc_rx_chain[i];
2708 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2709 BUS_DMASYNC_POSTREAD);
2710 total_len = DC_RXBYTES(rxstat);
2712 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2713 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2714 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2715 sc->dc_pnic_rx_bug_save = i;
2716 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2717 DC_INC(i, DC_RX_LIST_CNT);
2720 dc_pnic_rx_bug_war(sc, i);
2721 rxstat = le32toh(cur_rx->dc_status);
2722 total_len = DC_RXBYTES(rxstat);
2727 * If an error occurs, update stats, clear the
2728 * status word and leave the mbuf cluster in place:
2729 * it should simply get re-used next time this descriptor
2730 * comes up in the ring. However, don't report long
2731 * frames as errors since they could be vlans.
2733 if ((rxstat & DC_RXSTAT_RXERR)) {
2734 if (!(rxstat & DC_RXSTAT_GIANT) ||
2735 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2736 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2737 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2739 if (rxstat & DC_RXSTAT_COLLSEEN)
2740 ifp->if_collisions++;
2741 dc_newbuf(sc, i, 0);
2742 if (rxstat & DC_RXSTAT_CRCERR) {
2743 DC_INC(i, DC_RX_LIST_CNT);
2752 /* No errors; receive the packet. */
2753 total_len -= ETHER_CRC_LEN;
2756 * On the x86 we do not have alignment problems, so try to
2757 * allocate a new buffer for the receive ring, and pass up
2758 * the one where the packet is already, saving the expensive
2759 * copy done in m_devget().
2760 * If we are on an architecture with alignment problems, or
2761 * if the allocation fails, then use m_devget and leave the
2762 * existing buffer in the receive ring.
2764 if (dc_quick && dc_newbuf(sc, i, 1) == 0) {
2765 m->m_pkthdr.rcvif = ifp;
2766 m->m_pkthdr.len = m->m_len = total_len;
2767 DC_INC(i, DC_RX_LIST_CNT);
2773 m0 = m_devget(mtod(m, char *), total_len,
2774 ETHER_ALIGN, ifp, NULL);
2775 dc_newbuf(sc, i, 0);
2776 DC_INC(i, DC_RX_LIST_CNT);
2786 (*ifp->if_input)(ifp, m);
2790 sc->dc_cdata.dc_rx_prod = i;
2794 * A frame was downloaded to the chip. It's safe for us to clean up
2799 dc_txeof(struct dc_softc *sc)
2801 struct dc_desc *cur_tx = NULL;
2804 u_int32_t ctl, txstat;
2806 ifp = &sc->arpcom.ac_if;
2809 * Go through our tx list and free mbufs for those
2810 * frames that have been transmitted.
2812 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2813 idx = sc->dc_cdata.dc_tx_cons;
2814 while (idx != sc->dc_cdata.dc_tx_prod) {
2816 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2817 txstat = le32toh(cur_tx->dc_status);
2818 ctl = le32toh(cur_tx->dc_ctl);
2820 if (txstat & DC_TXSTAT_OWN)
2823 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) {
2824 if (ctl & DC_TXCTL_SETUP) {
2826 * Yes, the PNIC is so brain damaged
2827 * that it will sometimes generate a TX
2828 * underrun error while DMAing the RX
2829 * filter setup frame. If we detect this,
2830 * we have to send the setup frame again,
2831 * or else the filter won't be programmed
2834 if (DC_IS_PNIC(sc)) {
2835 if (txstat & DC_TXSTAT_ERRSUM)
2838 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2840 sc->dc_cdata.dc_tx_cnt--;
2841 DC_INC(idx, DC_TX_LIST_CNT);
2845 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2847 * XXX: Why does my Xircom taunt me so?
2848 * For some reason it likes setting the CARRLOST flag
2849 * even when the carrier is there. wtf?!?
2850 * Who knows, but Conexant chips have the
2851 * same problem. Maybe they took lessons
2854 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2855 sc->dc_pmode == DC_PMODE_MII &&
2856 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2857 DC_TXSTAT_NOCARRIER)))
2858 txstat &= ~DC_TXSTAT_ERRSUM;
2860 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2861 sc->dc_pmode == DC_PMODE_MII &&
2862 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2863 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
2864 txstat &= ~DC_TXSTAT_ERRSUM;
2867 if (txstat & DC_TXSTAT_ERRSUM) {
2869 if (txstat & DC_TXSTAT_EXCESSCOLL)
2870 ifp->if_collisions++;
2871 if (txstat & DC_TXSTAT_LATECOLL)
2872 ifp->if_collisions++;
2873 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2879 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2882 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2883 bus_dmamap_sync(sc->dc_mtag,
2884 sc->dc_cdata.dc_tx_map[idx],
2885 BUS_DMASYNC_POSTWRITE);
2886 bus_dmamap_unload(sc->dc_mtag,
2887 sc->dc_cdata.dc_tx_map[idx]);
2888 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2889 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2892 sc->dc_cdata.dc_tx_cnt--;
2893 DC_INC(idx, DC_TX_LIST_CNT);
2896 if (idx != sc->dc_cdata.dc_tx_cons) {
2897 /* Some buffers have been freed. */
2898 sc->dc_cdata.dc_tx_cons = idx;
2899 ifp->if_flags &= ~IFF_OACTIVE;
2901 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2907 struct dc_softc *sc;
2908 struct mii_data *mii;
2914 ifp = &sc->arpcom.ac_if;
2915 mii = device_get_softc(sc->dc_miibus);
2917 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2918 if (sc->dc_flags & DC_21143_NWAY) {
2919 r = CSR_READ_4(sc, DC_10BTSTAT);
2920 if (IFM_SUBTYPE(mii->mii_media_active) ==
2921 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2925 if (IFM_SUBTYPE(mii->mii_media_active) ==
2926 IFM_10_T && (r & DC_TSTAT_LS10)) {
2930 if (sc->dc_link == 0)
2933 r = CSR_READ_4(sc, DC_ISR);
2934 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2935 sc->dc_cdata.dc_tx_cnt == 0) {
2937 if (!(mii->mii_media_status & IFM_ACTIVE))
2945 * When the init routine completes, we expect to be able to send
2946 * packets right away, and in fact the network code will send a
2947 * gratuitous ARP the moment the init routine marks the interface
2948 * as running. However, even though the MAC may have been initialized,
2949 * there may be a delay of a few seconds before the PHY completes
2950 * autonegotiation and the link is brought up. Any transmissions
2951 * made during that delay will be lost. Dealing with this is tricky:
2952 * we can't just pause in the init routine while waiting for the
2953 * PHY to come ready since that would bring the whole system to
2954 * a screeching halt for several seconds.
2956 * What we do here is prevent the TX start routine from sending
2957 * any packets until a link has been established. After the
2958 * interface has been initialized, the tick routine will poll
2959 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2960 * that time, packets will stay in the send queue, and once the
2961 * link comes up, they will be flushed out to the wire.
2963 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
2964 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2966 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2970 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2971 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
2973 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
2979 * A transmit underrun has occurred. Back off the transmit threshold,
2980 * or switch to store and forward mode if we have to.
2983 dc_tx_underrun(struct dc_softc *sc)
2988 if (DC_IS_DAVICOM(sc))
2991 if (DC_IS_INTEL(sc)) {
2993 * The real 21143 requires that the transmitter be idle
2994 * in order to change the transmit threshold or store
2995 * and forward state.
2997 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2999 for (i = 0; i < DC_TIMEOUT; i++) {
3000 isr = CSR_READ_4(sc, DC_ISR);
3001 if (isr & DC_ISR_TX_IDLE)
3005 if (i == DC_TIMEOUT) {
3006 printf("dc%d: failed to force tx to idle state\n",
3012 printf("dc%d: TX underrun -- ", sc->dc_unit);
3013 sc->dc_txthresh += DC_TXTHRESH_INC;
3014 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3015 printf("using store and forward mode\n");
3016 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3018 printf("increasing TX threshold\n");
3019 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3020 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3023 if (DC_IS_INTEL(sc))
3024 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3027 #ifdef DEVICE_POLLING
3028 static poll_handler_t dc_poll;
3031 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3033 struct dc_softc *sc = ifp->if_softc;
3035 if (!(ifp->if_capenable & IFCAP_POLLING)) {
3036 ether_poll_deregister(ifp);
3037 cmd = POLL_DEREGISTER;
3039 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
3040 /* Re-enable interrupts. */
3041 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3045 sc->rxcycles = count;
3048 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE))
3051 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3054 status = CSR_READ_4(sc, DC_ISR);
3055 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3056 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3062 /* ack what we have */
3063 CSR_WRITE_4(sc, DC_ISR, status);
3065 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3066 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3067 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3069 if (dc_rx_resync(sc))
3072 /* restart transmit unit if necessary */
3073 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3074 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3076 if (status & DC_ISR_TX_UNDERRUN)
3079 if (status & DC_ISR_BUS_ERR) {
3080 printf("dc_poll: dc%d bus error\n", sc->dc_unit);
3087 #endif /* DEVICE_POLLING */
3092 struct dc_softc *sc;
3101 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3105 ifp = &sc->arpcom.ac_if;
3106 #ifdef DEVICE_POLLING
3107 if (ifp->if_flags & IFF_POLLING)
3109 if ((ifp->if_capenable & IFCAP_POLLING) &&
3110 ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
3111 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3116 /* Suppress unwanted interrupts */
3117 if (!(ifp->if_flags & IFF_UP)) {
3118 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3124 /* Disable interrupts. */
3125 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3127 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS)
3128 && status != 0xFFFFFFFF) {
3130 CSR_WRITE_4(sc, DC_ISR, status);
3132 if (status & DC_ISR_RX_OK) {
3134 curpkts = ifp->if_ipackets;
3136 if (curpkts == ifp->if_ipackets) {
3137 while (dc_rx_resync(sc))
3142 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3145 if (status & DC_ISR_TX_IDLE) {
3147 if (sc->dc_cdata.dc_tx_cnt) {
3148 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3149 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3153 if (status & DC_ISR_TX_UNDERRUN)
3156 if ((status & DC_ISR_RX_WATDOGTIMEO)
3157 || (status & DC_ISR_RX_NOBUF)) {
3159 curpkts = ifp->if_ipackets;
3161 if (curpkts == ifp->if_ipackets) {
3162 while (dc_rx_resync(sc))
3167 if (status & DC_ISR_BUS_ERR) {
3173 /* Re-enable interrupts. */
3174 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3176 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3179 #ifdef DEVICE_POLLING
3187 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error)
3189 bus_dma_segment_t *segs;
3194 struct dc_softc *sc;
3196 int cur, first, frag, i;
3200 sc->dc_cdata.dc_tx_err = error;
3204 first = cur = frag = sc->dc_cdata.dc_tx_prod;
3205 for (i = 0; i < nseg; i++) {
3206 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3207 (frag == (DC_TX_LIST_CNT - 1)) &&
3208 (first != sc->dc_cdata.dc_tx_first)) {
3209 bus_dmamap_unload(sc->dc_mtag,
3210 sc->dc_cdata.dc_tx_map[first]);
3211 sc->dc_cdata.dc_tx_err = ENOBUFS;
3215 f = &sc->dc_ldata->dc_tx_list[frag];
3216 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3219 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3221 f->dc_status = htole32(DC_TXSTAT_OWN);
3222 f->dc_data = htole32(segs[i].ds_addr);
3224 DC_INC(frag, DC_TX_LIST_CNT);
3227 sc->dc_cdata.dc_tx_err = 0;
3228 sc->dc_cdata.dc_tx_prod = frag;
3229 sc->dc_cdata.dc_tx_cnt += nseg;
3230 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3231 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping;
3232 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3233 sc->dc_ldata->dc_tx_list[first].dc_ctl |=
3234 htole32(DC_TXCTL_FINT);
3235 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3236 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3237 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3238 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3239 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3243 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3244 * pointers to the fragment pointers.
3247 dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3250 int error, idx, chainlen = 0;
3253 * If there's no way we can send any packets, return now.
3255 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6)
3259 * Count the number of frags in this chain to see if
3260 * we need to m_defrag. Since the descriptor list is shared
3261 * by all packets, we'll m_defrag long chains so that they
3262 * do not use up the entire list, even if they would fit.
3264 for (m = *m_head; m != NULL; m = m->m_next)
3267 if ((chainlen > DC_TX_LIST_CNT / 4) ||
3268 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) {
3269 m = m_defrag(*m_head, M_DONTWAIT);
3276 * Start packing the mbufs in this chain into
3277 * the fragment pointers. Stop when we run out
3278 * of fragments or hit the end of the mbuf chain.
3280 idx = sc->dc_cdata.dc_tx_prod;
3281 sc->dc_cdata.dc_tx_mapping = *m_head;
3282 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3283 *m_head, dc_dma_map_txbuf, sc, 0);
3286 if (sc->dc_cdata.dc_tx_err != 0)
3287 return (sc->dc_cdata.dc_tx_err);
3288 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3289 BUS_DMASYNC_PREWRITE);
3290 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
3291 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3296 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3297 * to the mbuf data regions directly in the transmit lists. We also save a
3298 * copy of the pointers since the transmit list fragment pointers are
3299 * physical addresses.
3303 dc_start(struct ifnet *ifp)
3305 struct dc_softc *sc;
3306 struct mbuf *m_head = NULL, *m;
3307 unsigned int queued = 0;
3314 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) {
3319 if (ifp->if_flags & IFF_OACTIVE) {
3324 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3326 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3327 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3331 if (sc->dc_flags & DC_TX_COALESCE &&
3332 (m_head->m_next != NULL ||
3333 sc->dc_flags & DC_TX_ALIGN)) {
3334 m = m_defrag(m_head, M_DONTWAIT);
3336 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3337 ifp->if_flags |= IFF_OACTIVE;
3344 if (dc_encap(sc, &m_head)) {
3345 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3346 ifp->if_flags |= IFF_OACTIVE;
3349 idx = sc->dc_cdata.dc_tx_prod;
3353 * If there's a BPF listener, bounce a copy of this frame
3356 BPF_MTAP(ifp, m_head);
3358 if (sc->dc_flags & DC_TX_ONE) {
3359 ifp->if_flags |= IFF_OACTIVE;
3366 if (!(sc->dc_flags & DC_TX_POLL))
3367 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3370 * Set a timeout in case the chip goes out to lunch.
3381 struct dc_softc *sc = xsc;
3382 struct ifnet *ifp = &sc->arpcom.ac_if;
3383 struct mii_data *mii;
3387 mii = device_get_softc(sc->dc_miibus);
3390 * Cancel pending I/O and free all RX/TX buffers.
3396 * Set cache alignment and burst length.
3398 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3399 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3401 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3403 * Evenly share the bus between receive and transmit process.
3405 if (DC_IS_INTEL(sc))
3406 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3407 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3408 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3410 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3412 if (sc->dc_flags & DC_TX_POLL)
3413 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3414 switch(sc->dc_cachesize) {
3416 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3419 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3422 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3426 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3430 if (sc->dc_flags & DC_TX_STORENFWD)
3431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3433 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3436 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3437 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3442 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3444 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3446 * The app notes for the 98713 and 98715A say that
3447 * in order to have the chips operate properly, a magic
3448 * number must be written to CSR16. Macronix does not
3449 * document the meaning of these bits so there's no way
3450 * to know exactly what they do. The 98713 has a magic
3451 * number all its own; the rest all use a different one.
3453 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3454 if (sc->dc_type == DC_TYPE_98713)
3455 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3457 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3460 if (DC_IS_XIRCOM(sc)) {
3462 * setup General Purpose Port mode and data so the tulip
3463 * can talk to the MII.
3465 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3466 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3468 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3469 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3473 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3474 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3476 /* Init circular RX list. */
3477 if (dc_list_rx_init(sc) == ENOBUFS) {
3478 printf("dc%d: initialization failed: no "
3479 "memory for rx buffers\n", sc->dc_unit);
3486 * Init TX descriptors.
3488 dc_list_tx_init(sc);
3491 * Load the address of the RX list.
3493 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3494 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3497 * Enable interrupts.
3499 #ifdef DEVICE_POLLING
3501 * ... but only if we are not polling, and make sure they are off in
3502 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3505 if (ifp->if_flags & IFF_POLLING)
3506 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3509 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3510 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3512 /* Enable transmitter. */
3513 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3516 * If this is an Intel 21143 and we're not using the
3517 * MII port, program the LED control pins so we get
3518 * link and activity indications.
3520 if (sc->dc_flags & DC_TULIP_LEDS) {
3521 CSR_WRITE_4(sc, DC_WATCHDOG,
3522 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3523 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3527 * Load the RX/multicast filter. We do this sort of late
3528 * because the filter programming scheme on the 21143 and
3529 * some clones requires DMAing a setup frame via the TX
3530 * engine, and we need the transmitter enabled for that.
3534 /* Enable receiver. */
3535 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3536 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3539 dc_setcfg(sc, sc->dc_if_media);
3541 ifp->if_flags |= IFF_RUNNING;
3542 ifp->if_flags &= ~IFF_OACTIVE;
3544 /* Don't start the ticker if this is a homePNA link. */
3545 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3548 if (sc->dc_flags & DC_21143_NWAY)
3549 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3551 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3555 if(sc->dc_srm_media) {
3558 ifr.ifr_media = sc->dc_srm_media;
3559 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3560 sc->dc_srm_media = 0;
3567 * Set media options.
3570 dc_ifmedia_upd(struct ifnet *ifp)
3572 struct dc_softc *sc;
3573 struct mii_data *mii;
3574 struct ifmedia *ifm;
3577 mii = device_get_softc(sc->dc_miibus);
3579 ifm = &mii->mii_media;
3581 if (DC_IS_DAVICOM(sc) &&
3582 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3583 dc_setcfg(sc, ifm->ifm_media);
3591 * Report current media status.
3594 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3596 struct dc_softc *sc;
3597 struct mii_data *mii;
3598 struct ifmedia *ifm;
3601 mii = device_get_softc(sc->dc_miibus);
3603 ifm = &mii->mii_media;
3604 if (DC_IS_DAVICOM(sc)) {
3605 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3606 ifmr->ifm_active = ifm->ifm_media;
3607 ifmr->ifm_status = 0;
3611 ifmr->ifm_active = mii->mii_media_active;
3612 ifmr->ifm_status = mii->mii_media_status;
3616 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3618 struct dc_softc *sc = ifp->if_softc;
3619 struct ifreq *ifr = (struct ifreq *)data;
3620 struct mii_data *mii;
3627 if (ifp->if_flags & IFF_UP) {
3628 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3629 (IFF_PROMISC | IFF_ALLMULTI);
3631 if (ifp->if_flags & IFF_RUNNING) {
3635 sc->dc_txthresh = 0;
3639 if (ifp->if_flags & IFF_RUNNING)
3642 sc->dc_if_flags = ifp->if_flags;
3652 mii = device_get_softc(sc->dc_miibus);
3653 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3655 if (sc->dc_srm_media)
3656 sc->dc_srm_media = 0;
3660 ifp->if_capenable &= ~IFCAP_POLLING;
3661 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING;
3664 error = ether_ioctl(ifp, command, data);
3674 dc_watchdog(struct ifnet *ifp)
3676 struct dc_softc *sc;
3683 printf("dc%d: watchdog timeout\n", sc->dc_unit);
3689 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3696 * Stop the adapter and free any mbufs allocated to the
3700 dc_stop(struct dc_softc *sc)
3703 struct dc_list_data *ld;
3704 struct dc_chain_data *cd;
3710 ifp = &sc->arpcom.ac_if;
3715 callout_stop(&sc->dc_stat_ch);
3717 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3718 #ifdef DEVICE_POLLING
3719 ether_poll_deregister(ifp);
3722 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
3723 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3724 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3725 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3729 * Free data in the RX lists.
3731 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3732 if (cd->dc_rx_chain[i] != NULL) {
3733 m_freem(cd->dc_rx_chain[i]);
3734 cd->dc_rx_chain[i] = NULL;
3737 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list));
3740 * Free the TX list buffers.
3742 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3743 if (cd->dc_tx_chain[i] != NULL) {
3744 ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
3745 if ((ctl & DC_TXCTL_SETUP) ||
3746 !(ctl & DC_TXCTL_LASTFRAG)) {
3747 cd->dc_tx_chain[i] = NULL;
3750 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]);
3751 m_freem(cd->dc_tx_chain[i]);
3752 cd->dc_tx_chain[i] = NULL;
3755 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list));
3761 * Device suspend routine. Stop the interface and save some PCI
3762 * settings in case the BIOS doesn't restore them properly on
3766 dc_suspend(device_t dev)
3768 struct dc_softc *sc;
3773 sc = device_get_softc(dev);
3782 * Device resume routine. Restore some PCI settings in case the BIOS
3783 * doesn't, re-enable busmastering, and restart the interface if
3787 dc_resume(device_t dev)
3789 struct dc_softc *sc;
3795 sc = device_get_softc(dev);
3796 ifp = &sc->arpcom.ac_if;
3798 /* reinitialize interface if necessary */
3799 if (ifp->if_flags & IFF_UP)
3809 * Stop all chip I/O so that the kernel's probe routines don't
3810 * get confused by errant DMAs when rebooting.
3813 dc_shutdown(device_t dev)
3815 struct dc_softc *sc;
3817 sc = device_get_softc(dev);
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