2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/sockio.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/module.h>
62 #include <sys/socket.h>
65 #include <net/if_arp.h>
66 #include <net/ethernet.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
72 #include <vm/vm.h> /* for vtophys */
73 #include <vm/pmap.h> /* for vtophys */
74 #include <machine/bus.h>
75 #include <machine/resource.h>
79 #include <dev/mii/mii.h>
80 #include <dev/mii/miivar.h>
82 #include <dev/pci/pcireg.h>
83 #include <dev/pci/pcivar.h>
85 #define PCN_USEIOSPACE
87 #include <pci/if_pcnreg.h>
89 MODULE_DEPEND(pcn, pci, 1, 1, 1);
90 MODULE_DEPEND(pcn, ether, 1, 1, 1);
91 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
93 /* "controller miibus0" required. See GENERIC if you get errors here. */
94 #include "miibus_if.h"
97 * Various supported device vendors/types and their names.
99 static struct pcn_type pcn_devs[] = {
100 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
101 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
105 static struct pcn_chipid {
109 { Am79C960, "Am79C960" },
110 { Am79C961, "Am79C961" },
111 { Am79C961A, "Am79C961A" },
112 { Am79C965, "Am79C965" },
113 { Am79C970, "Am79C970" },
114 { Am79C970A, "Am79C970A" },
115 { Am79C971, "Am79C971" },
116 { Am79C972, "Am79C972" },
117 { Am79C973, "Am79C973" },
118 { Am79C978, "Am79C978" },
119 { Am79C975, "Am79C975" },
120 { Am79C976, "Am79C976" },
124 static char * pcn_chipid_name(u_int32_t);
125 static u_int32_t pcn_chip_id(device_t);
127 static u_int32_t pcn_csr_read(struct pcn_softc *, int);
128 static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
129 static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
130 static void pcn_csr_write(struct pcn_softc *, int, int);
131 static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
132 static void pcn_bcr_write(struct pcn_softc *, int, int);
134 static int pcn_probe(device_t);
135 static int pcn_attach(device_t);
136 static int pcn_detach(device_t);
138 static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
139 static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
140 static void pcn_rxeof(struct pcn_softc *);
141 static void pcn_txeof(struct pcn_softc *);
142 static void pcn_intr(void *);
143 static void pcn_tick(void *);
144 static void pcn_start(struct ifnet *);
145 static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
146 static void pcn_init(void *);
147 static void pcn_stop(struct pcn_softc *);
148 static void pcn_watchdog(struct ifnet *);
149 static void pcn_shutdown(device_t);
150 static int pcn_ifmedia_upd(struct ifnet *);
151 static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
153 static int pcn_miibus_readreg(device_t, int, int);
154 static int pcn_miibus_writereg(device_t, int, int, int);
155 static void pcn_miibus_statchg(device_t);
157 static void pcn_setfilt(struct ifnet *);
158 static void pcn_setmulti(struct pcn_softc *);
159 static void pcn_reset(struct pcn_softc *);
160 static int pcn_list_rx_init(struct pcn_softc *);
161 static int pcn_list_tx_init(struct pcn_softc *);
163 #ifdef PCN_USEIOSPACE
164 #define PCN_RES SYS_RES_IOPORT
165 #define PCN_RID PCN_PCI_LOIO
167 #define PCN_RES SYS_RES_MEMORY
168 #define PCN_RID PCN_PCI_LOMEM
171 static device_method_t pcn_methods[] = {
172 /* Device interface */
173 DEVMETHOD(device_probe, pcn_probe),
174 DEVMETHOD(device_attach, pcn_attach),
175 DEVMETHOD(device_detach, pcn_detach),
176 DEVMETHOD(device_shutdown, pcn_shutdown),
179 DEVMETHOD(bus_print_child, bus_generic_print_child),
180 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
183 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
184 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
185 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
190 static driver_t pcn_driver = {
193 sizeof(struct pcn_softc)
196 static devclass_t pcn_devclass;
198 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
199 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
201 #define PCN_CSR_SETBIT(sc, reg, x) \
202 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
204 #define PCN_CSR_CLRBIT(sc, reg, x) \
205 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
207 #define PCN_BCR_SETBIT(sc, reg, x) \
208 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
210 #define PCN_BCR_CLRBIT(sc, reg, x) \
211 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
214 pcn_csr_read(sc, reg)
215 struct pcn_softc *sc;
218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
219 return(CSR_READ_4(sc, PCN_IO32_RDP));
223 pcn_csr_read16(sc, reg)
224 struct pcn_softc *sc;
227 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
228 return(CSR_READ_2(sc, PCN_IO16_RDP));
232 pcn_csr_write(sc, reg, val)
233 struct pcn_softc *sc;
237 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
238 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
243 pcn_bcr_read(sc, reg)
244 struct pcn_softc *sc;
247 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
248 return(CSR_READ_4(sc, PCN_IO32_BDP));
252 pcn_bcr_read16(sc, reg)
253 struct pcn_softc *sc;
256 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
257 return(CSR_READ_2(sc, PCN_IO16_BDP));
261 pcn_bcr_write(sc, reg, val)
262 struct pcn_softc *sc;
266 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
267 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
272 pcn_miibus_readreg(dev, phy, reg)
276 struct pcn_softc *sc;
279 sc = device_get_softc(dev);
281 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
284 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
285 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
289 sc->pcn_phyaddr = phy;
295 pcn_miibus_writereg(dev, phy, reg, data)
299 struct pcn_softc *sc;
301 sc = device_get_softc(dev);
303 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
304 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
310 pcn_miibus_statchg(dev)
313 struct pcn_softc *sc;
314 struct mii_data *mii;
316 sc = device_get_softc(dev);
317 mii = device_get_softc(sc->pcn_miibus);
319 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
320 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
322 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
330 struct pcn_softc *sc;
333 struct ifmultiaddr *ifma;
335 u_int16_t hashes[4] = { 0, 0, 0, 0 };
337 ifp = &sc->arpcom.ac_if;
339 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
341 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
342 for (i = 0; i < 4; i++)
343 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
344 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
348 /* first, zot all the existing hash bits */
349 for (i = 0; i < 4; i++)
350 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
352 /* now program new ones */
353 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
354 if (ifma->ifma_addr->sa_family != AF_LINK)
356 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
357 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
358 hashes[h >> 4] |= 1 << (h & 0xF);
361 for (i = 0; i < 4; i++)
362 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
364 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
371 struct pcn_softc *sc;
374 * Issue a reset by reading from the RESET register.
375 * Note that we don't know if the chip is operating in
376 * 16-bit or 32-bit mode at this point, so we attempt
377 * to reset the chip both ways. If one fails, the other
380 CSR_READ_2(sc, PCN_IO16_RESET);
381 CSR_READ_4(sc, PCN_IO32_RESET);
383 /* Wait a little while for the chip to get its brains in order. */
386 /* Select 32-bit (DWIO) mode */
387 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
389 /* Select software style 3. */
390 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
396 pcn_chipid_name (u_int32_t id)
398 struct pcn_chipid *p = pcn_chipid;
409 pcn_chip_id (device_t dev)
411 struct pcn_softc *sc;
414 sc = device_get_softc(dev);
416 * Note: we can *NOT* put the chip into
417 * 32-bit mode yet. The lnc driver will only
418 * work in 16-bit mode, and once the chip
419 * goes into 32-bit mode, the only way to
420 * get it out again is with a hardware reset.
421 * So if pcn_probe() is called before the
422 * lnc driver's probe routine, the chip will
423 * be locked into 32-bit operation and the lnc
424 * driver will be unable to attach to it.
425 * Note II: if the chip happens to already
426 * be in 32-bit mode, we still need to check
427 * the chip ID, but first we have to detect
428 * 32-bit mode using only 16-bit operations.
429 * The safest way to do this is to read the
430 * PCI subsystem ID from BCR23/24 and compare
431 * that with the value read from PCI config
434 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
436 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
438 * Note III: the test for 0x10001000 is a hack to
439 * pacify VMware, who's pseudo-PCnet interface is
440 * broken. Reading the subsystem register from PCI
441 * config space yields 0x00000000 while reading the
442 * same value from I/O space yields 0x10001000. It's
443 * not supposed to be that way.
445 if (chip_id == pci_read_config(dev,
446 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
447 /* We're in 16-bit mode. */
448 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
450 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
452 /* We're in 32-bit mode. */
453 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
455 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
461 static struct pcn_type *
462 pcn_match (u_int16_t vid, u_int16_t did)
467 while(t->pcn_name != NULL) {
468 if ((vid == t->pcn_vid) && (did == t->pcn_did))
476 * Probe for an AMD chip. Check the PCI vendor and device
477 * IDs against our list and return a device name if we find a match.
484 struct pcn_softc *sc;
488 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
491 sc = device_get_softc(dev);
494 * Temporarily map the I/O space so we can read the chip ID register.
497 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
498 if (sc->pcn_res == NULL) {
499 device_printf(dev, "couldn't map ports/memory\n");
502 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
503 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
505 chip_id = pcn_chip_id(dev);
507 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
509 switch((chip_id >> 12) & PART_MASK) {
520 device_set_desc(dev, t->pcn_name);
521 return(BUS_PROBE_DEFAULT);
525 * Attach the interface. Allocate softc structures, do ifmedia
526 * setup and ethernet/BPF attach.
533 struct pcn_softc *sc;
535 int unit, error = 0, rid;
537 sc = device_get_softc(dev);
538 unit = device_get_unit(dev);
540 /* Initialize our mutex. */
541 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
542 MTX_DEF | MTX_RECURSE);
544 * Map control/status registers.
546 pci_enable_busmaster(dev);
548 /* Retrieve the chip ID */
549 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
550 device_printf(dev, "Chip ID %04x (%s)\n",
551 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
554 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
556 if (sc->pcn_res == NULL) {
557 printf("pcn%d: couldn't map ports/memory\n", unit);
562 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
563 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
565 /* Allocate interrupt */
567 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
568 RF_SHAREABLE | RF_ACTIVE);
570 if (sc->pcn_irq == NULL) {
571 printf("pcn%d: couldn't map interrupt\n", unit);
576 /* Reset the adapter. */
580 * Get station address from the EEPROM.
582 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
583 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
584 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
587 callout_handle_init(&sc->pcn_stat_ch);
589 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
590 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
592 if (sc->pcn_ldata == NULL) {
593 printf("pcn%d: no memory for list buffers!\n", unit);
597 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
599 ifp = &sc->arpcom.ac_if;
601 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
602 ifp->if_mtu = ETHERMTU;
603 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
605 ifp->if_ioctl = pcn_ioctl;
606 ifp->if_start = pcn_start;
607 ifp->if_watchdog = pcn_watchdog;
608 ifp->if_init = pcn_init;
609 ifp->if_baudrate = 10000000;
610 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
615 if (mii_phy_probe(dev, &sc->pcn_miibus,
616 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
617 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
623 * Call MI attach routine.
625 ether_ifattach(ifp, (u_int8_t *) eaddr);
627 /* Hook interrupt last to avoid having to lock softc */
628 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET,
629 pcn_intr, sc, &sc->pcn_intrhand);
632 printf("pcn%d: couldn't set up irq\n", unit);
645 * Shutdown hardware and free up resources. This can be called any
646 * time after the mutex has been initialized. It is called in both
647 * the error case in attach and the normal detach case so it needs
648 * to be careful about only freeing resources that have actually been
655 struct pcn_softc *sc;
658 sc = device_get_softc(dev);
659 ifp = &sc->arpcom.ac_if;
661 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
664 /* These should only be active if attach succeeded */
665 if (device_is_attached(dev)) {
671 device_delete_child(dev, sc->pcn_miibus);
672 bus_generic_detach(dev);
674 if (sc->pcn_intrhand)
675 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
677 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
679 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
682 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
687 mtx_destroy(&sc->pcn_mtx);
693 * Initialize the transmit descriptors.
697 struct pcn_softc *sc;
699 struct pcn_list_data *ld;
700 struct pcn_ring_data *cd;
706 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
707 cd->pcn_tx_chain[i] = NULL;
708 ld->pcn_tx_list[i].pcn_tbaddr = 0;
709 ld->pcn_tx_list[i].pcn_txctl = 0;
710 ld->pcn_tx_list[i].pcn_txstat = 0;
713 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
720 * Initialize the RX descriptors and allocate mbufs for them.
724 struct pcn_softc *sc;
726 struct pcn_ring_data *cd;
731 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
732 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
742 * Initialize an RX descriptor and attach an MBUF cluster.
745 pcn_newbuf(sc, idx, m)
746 struct pcn_softc *sc;
750 struct mbuf *m_new = NULL;
751 struct pcn_rx_desc *c;
753 c = &sc->pcn_ldata->pcn_rx_list[idx];
756 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
760 MCLGET(m_new, M_DONTWAIT);
761 if (!(m_new->m_flags & M_EXT)) {
765 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
768 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
769 m_new->m_data = m_new->m_ext.ext_buf;
772 m_adj(m_new, ETHER_ALIGN);
774 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
775 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
776 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
777 c->pcn_bufsz |= PCN_RXLEN_MBO;
778 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
784 * A frame has been uploaded: pass the resulting mbuf chain up to
785 * the higher level protocols.
789 struct pcn_softc *sc;
793 struct pcn_rx_desc *cur_rx;
798 ifp = &sc->arpcom.ac_if;
799 i = sc->pcn_cdata.pcn_rx_prod;
801 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
802 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
803 m = sc->pcn_cdata.pcn_rx_chain[i];
804 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
807 * If an error occurs, update stats, clear the
808 * status word and leave the mbuf cluster in place:
809 * it should simply get re-used next time this descriptor
810 * comes up in the ring.
812 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
814 pcn_newbuf(sc, i, m);
815 PCN_INC(i, PCN_RX_LIST_CNT);
819 if (pcn_newbuf(sc, i, NULL)) {
820 /* Ran out of mbufs; recycle this one. */
821 pcn_newbuf(sc, i, m);
823 PCN_INC(i, PCN_RX_LIST_CNT);
827 PCN_INC(i, PCN_RX_LIST_CNT);
829 /* No errors; receive the packet. */
831 m->m_len = m->m_pkthdr.len =
832 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
833 m->m_pkthdr.rcvif = ifp;
836 (*ifp->if_input)(ifp, m);
840 sc->pcn_cdata.pcn_rx_prod = i;
846 * A frame was downloaded to the chip. It's safe for us to clean up
852 struct pcn_softc *sc;
854 struct pcn_tx_desc *cur_tx = NULL;
858 ifp = &sc->arpcom.ac_if;
861 * Go through our tx list and free mbufs for those
862 * frames that have been transmitted.
864 idx = sc->pcn_cdata.pcn_tx_cons;
865 while (idx != sc->pcn_cdata.pcn_tx_prod) {
866 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
868 if (!PCN_OWN_TXDESC(cur_tx))
871 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
872 sc->pcn_cdata.pcn_tx_cnt--;
873 PCN_INC(idx, PCN_TX_LIST_CNT);
877 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
879 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
880 ifp->if_collisions++;
881 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
882 ifp->if_collisions++;
885 ifp->if_collisions +=
886 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
889 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
890 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
891 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
894 sc->pcn_cdata.pcn_tx_cnt--;
895 PCN_INC(idx, PCN_TX_LIST_CNT);
898 if (idx != sc->pcn_cdata.pcn_tx_cons) {
899 /* Some buffers have been freed. */
900 sc->pcn_cdata.pcn_tx_cons = idx;
901 ifp->if_flags &= ~IFF_OACTIVE;
903 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
912 struct pcn_softc *sc;
913 struct mii_data *mii;
917 ifp = &sc->arpcom.ac_if;
920 mii = device_get_softc(sc->pcn_miibus);
924 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
927 /* link just came up, restart */
928 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
929 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
931 if (ifp->if_snd.ifq_head != NULL)
935 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
946 struct pcn_softc *sc;
951 ifp = &sc->arpcom.ac_if;
953 /* Suppress unwanted interrupts */
954 if (!(ifp->if_flags & IFF_UP)) {
961 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
963 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
964 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
966 if (status & PCN_CSR_RINT)
969 if (status & PCN_CSR_TINT)
972 if (status & PCN_CSR_ERR) {
978 if (ifp->if_snd.ifq_head != NULL)
986 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
987 * pointers to the fragment pointers.
990 pcn_encap(sc, m_head, txidx)
991 struct pcn_softc *sc;
995 struct pcn_tx_desc *f = NULL;
997 int frag, cur, cnt = 0;
1000 * Start packing the mbufs in this chain into
1001 * the fragment pointers. Stop when we run out
1002 * of fragments or hit the end of the mbuf chain.
1005 cur = frag = *txidx;
1007 for (m = m_head; m != NULL; m = m->m_next) {
1011 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1013 f = &sc->pcn_ldata->pcn_tx_list[frag];
1014 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1015 f->pcn_txctl |= PCN_TXCTL_MBO;
1016 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1018 f->pcn_txctl |= PCN_TXCTL_STP;
1020 f->pcn_txctl |= PCN_TXCTL_OWN;
1022 PCN_INC(frag, PCN_TX_LIST_CNT);
1029 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1030 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1031 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1032 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1033 sc->pcn_cdata.pcn_tx_cnt += cnt;
1040 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1041 * to the mbuf data regions directly in the transmit lists. We also save a
1042 * copy of the pointers since the transmit list fragment pointers are
1043 * physical addresses.
1049 struct pcn_softc *sc;
1050 struct mbuf *m_head = NULL;
1057 if (!sc->pcn_link) {
1062 idx = sc->pcn_cdata.pcn_tx_prod;
1064 if (ifp->if_flags & IFF_OACTIVE) {
1069 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1070 IF_DEQUEUE(&ifp->if_snd, m_head);
1074 if (pcn_encap(sc, m_head, &idx)) {
1075 IF_PREPEND(&ifp->if_snd, m_head);
1076 ifp->if_flags |= IFF_OACTIVE;
1081 * If there's a BPF listener, bounce a copy of this frame
1084 BPF_MTAP(ifp, m_head);
1089 sc->pcn_cdata.pcn_tx_prod = idx;
1090 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1093 * Set a timeout in case the chip goes out to lunch.
1106 struct pcn_softc *sc;
1110 /* If we want promiscuous mode, set the allframes bit. */
1111 if (ifp->if_flags & IFF_PROMISC) {
1112 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1114 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1117 /* Set the capture broadcast bit to capture broadcast frames. */
1118 if (ifp->if_flags & IFF_BROADCAST) {
1119 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1121 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1131 struct pcn_softc *sc = xsc;
1132 struct ifnet *ifp = &sc->arpcom.ac_if;
1133 struct mii_data *mii = NULL;
1138 * Cancel pending I/O and free all RX/TX buffers.
1143 mii = device_get_softc(sc->pcn_miibus);
1145 /* Set MAC address */
1146 pcn_csr_write(sc, PCN_CSR_PAR0,
1147 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1148 pcn_csr_write(sc, PCN_CSR_PAR1,
1149 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1150 pcn_csr_write(sc, PCN_CSR_PAR2,
1151 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1153 /* Init circular RX list. */
1154 if (pcn_list_rx_init(sc) == ENOBUFS) {
1155 printf("pcn%d: initialization failed: no "
1156 "memory for rx buffers\n", sc->pcn_unit);
1163 * Init tx descriptors.
1165 pcn_list_tx_init(sc);
1167 /* Set up the mode register. */
1168 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1170 /* Set up RX filter. */
1174 * Load the multicast filter.
1179 * Load the addresses of the RX and TX lists.
1181 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1182 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1183 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1184 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1185 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1186 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1187 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1188 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1190 /* Set the RX and TX ring sizes. */
1191 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1192 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1194 /* We're not using the initialization block. */
1195 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1197 /* Enable fast suspend mode. */
1198 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1201 * Enable burst read and write. Also set the no underflow
1202 * bit. This will avoid transmit underruns in certain
1203 * conditions while still providing decent performance.
1205 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1206 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1208 /* Enable graceful recovery from underflow. */
1209 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1211 /* Enable auto-padding of short TX frames. */
1212 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1214 /* Disable MII autoneg (we handle this ourselves). */
1215 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1217 if (sc->pcn_type == Am79C978)
1218 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1219 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1221 /* Enable interrupts and start the controller running. */
1222 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1226 ifp->if_flags |= IFF_RUNNING;
1227 ifp->if_flags &= ~IFF_OACTIVE;
1229 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
1236 * Set media options.
1239 pcn_ifmedia_upd(ifp)
1242 struct pcn_softc *sc;
1243 struct mii_data *mii;
1246 mii = device_get_softc(sc->pcn_miibus);
1249 if (mii->mii_instance) {
1250 struct mii_softc *miisc;
1251 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1252 mii_phy_reset(miisc);
1260 * Report current media status.
1263 pcn_ifmedia_sts(ifp, ifmr)
1265 struct ifmediareq *ifmr;
1267 struct pcn_softc *sc;
1268 struct mii_data *mii;
1272 mii = device_get_softc(sc->pcn_miibus);
1274 ifmr->ifm_active = mii->mii_media_active;
1275 ifmr->ifm_status = mii->mii_media_status;
1281 pcn_ioctl(ifp, command, data)
1286 struct pcn_softc *sc = ifp->if_softc;
1287 struct ifreq *ifr = (struct ifreq *) data;
1288 struct mii_data *mii = NULL;
1295 if (ifp->if_flags & IFF_UP) {
1296 if (ifp->if_flags & IFF_RUNNING &&
1297 ifp->if_flags & IFF_PROMISC &&
1298 !(sc->pcn_if_flags & IFF_PROMISC)) {
1299 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1302 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1304 pcn_csr_write(sc, PCN_CSR_CSR,
1305 PCN_CSR_INTEN|PCN_CSR_START);
1306 } else if (ifp->if_flags & IFF_RUNNING &&
1307 !(ifp->if_flags & IFF_PROMISC) &&
1308 sc->pcn_if_flags & IFF_PROMISC) {
1309 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1312 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1314 pcn_csr_write(sc, PCN_CSR_CSR,
1315 PCN_CSR_INTEN|PCN_CSR_START);
1316 } else if (!(ifp->if_flags & IFF_RUNNING))
1319 if (ifp->if_flags & IFF_RUNNING)
1322 sc->pcn_if_flags = ifp->if_flags;
1332 mii = device_get_softc(sc->pcn_miibus);
1333 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1336 error = ether_ioctl(ifp, command, data);
1349 struct pcn_softc *sc;
1356 printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
1362 if (ifp->if_snd.ifq_head != NULL)
1371 * Stop the adapter and free any mbufs allocated to the
1376 struct pcn_softc *sc;
1381 ifp = &sc->arpcom.ac_if;
1385 untimeout(pcn_tick, sc, sc->pcn_stat_ch);
1387 /* Turn off interrupts */
1388 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1390 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1394 * Free data in the RX lists.
1396 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1397 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1398 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1399 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1402 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1403 sizeof(sc->pcn_ldata->pcn_rx_list));
1406 * Free the TX list buffers.
1408 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1409 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1410 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1411 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1415 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1416 sizeof(sc->pcn_ldata->pcn_tx_list));
1418 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1425 * Stop all chip I/O so that the kernel's probe routines don't
1426 * get confused by errant DMAs when rebooting.
1432 struct pcn_softc *sc;
1434 sc = device_get_softc(dev);