2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/sockio.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/module.h>
62 #include <sys/socket.h>
65 #include <net/if_arp.h>
66 #include <net/ethernet.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
72 #include <vm/vm.h> /* for vtophys */
73 #include <vm/pmap.h> /* for vtophys */
74 #include <machine/bus_pio.h>
75 #include <machine/bus_memio.h>
76 #include <machine/bus.h>
77 #include <machine/resource.h>
81 #include <dev/mii/mii.h>
82 #include <dev/mii/miivar.h>
84 #include <dev/pci/pcireg.h>
85 #include <dev/pci/pcivar.h>
87 #define PCN_USEIOSPACE
89 #include <pci/if_pcnreg.h>
91 MODULE_DEPEND(pcn, pci, 1, 1, 1);
92 MODULE_DEPEND(pcn, ether, 1, 1, 1);
93 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
95 /* "controller miibus0" required. See GENERIC if you get errors here. */
96 #include "miibus_if.h"
99 * Various supported device vendors/types and their names.
101 static struct pcn_type pcn_devs[] = {
102 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
103 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
107 static struct pcn_chipid {
111 { Am79C960, "Am79C960" },
112 { Am79C961, "Am79C961" },
113 { Am79C961A, "Am79C961A" },
114 { Am79C965, "Am79C965" },
115 { Am79C970, "Am79C970" },
116 { Am79C970A, "Am79C970A" },
117 { Am79C971, "Am79C971" },
118 { Am79C972, "Am79C972" },
119 { Am79C973, "Am79C973" },
120 { Am79C978, "Am79C978" },
121 { Am79C975, "Am79C975" },
122 { Am79C976, "Am79C976" },
126 static char * pcn_chipid_name(u_int32_t);
127 static u_int32_t pcn_chip_id(device_t);
129 static u_int32_t pcn_csr_read(struct pcn_softc *, int);
130 static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
131 static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
132 static void pcn_csr_write(struct pcn_softc *, int, int);
133 static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
134 static void pcn_bcr_write(struct pcn_softc *, int, int);
136 static int pcn_probe(device_t);
137 static int pcn_attach(device_t);
138 static int pcn_detach(device_t);
140 static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
141 static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
142 static void pcn_rxeof(struct pcn_softc *);
143 static void pcn_txeof(struct pcn_softc *);
144 static void pcn_intr(void *);
145 static void pcn_tick(void *);
146 static void pcn_start(struct ifnet *);
147 static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
148 static void pcn_init(void *);
149 static void pcn_stop(struct pcn_softc *);
150 static void pcn_watchdog(struct ifnet *);
151 static void pcn_shutdown(device_t);
152 static int pcn_ifmedia_upd(struct ifnet *);
153 static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
155 static int pcn_miibus_readreg(device_t, int, int);
156 static int pcn_miibus_writereg(device_t, int, int, int);
157 static void pcn_miibus_statchg(device_t);
159 static void pcn_setfilt(struct ifnet *);
160 static void pcn_setmulti(struct pcn_softc *);
161 static void pcn_reset(struct pcn_softc *);
162 static int pcn_list_rx_init(struct pcn_softc *);
163 static int pcn_list_tx_init(struct pcn_softc *);
165 #ifdef PCN_USEIOSPACE
166 #define PCN_RES SYS_RES_IOPORT
167 #define PCN_RID PCN_PCI_LOIO
169 #define PCN_RES SYS_RES_MEMORY
170 #define PCN_RID PCN_PCI_LOMEM
173 static device_method_t pcn_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, pcn_probe),
176 DEVMETHOD(device_attach, pcn_attach),
177 DEVMETHOD(device_detach, pcn_detach),
178 DEVMETHOD(device_shutdown, pcn_shutdown),
181 DEVMETHOD(bus_print_child, bus_generic_print_child),
182 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
185 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
186 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
187 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
192 static driver_t pcn_driver = {
195 sizeof(struct pcn_softc)
198 static devclass_t pcn_devclass;
200 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
201 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
203 #define PCN_CSR_SETBIT(sc, reg, x) \
204 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
206 #define PCN_CSR_CLRBIT(sc, reg, x) \
207 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
209 #define PCN_BCR_SETBIT(sc, reg, x) \
210 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
212 #define PCN_BCR_CLRBIT(sc, reg, x) \
213 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
216 pcn_csr_read(sc, reg)
217 struct pcn_softc *sc;
220 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
221 return(CSR_READ_4(sc, PCN_IO32_RDP));
225 pcn_csr_read16(sc, reg)
226 struct pcn_softc *sc;
229 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
230 return(CSR_READ_2(sc, PCN_IO16_RDP));
234 pcn_csr_write(sc, reg, val)
235 struct pcn_softc *sc;
239 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
240 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
245 pcn_bcr_read(sc, reg)
246 struct pcn_softc *sc;
249 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
250 return(CSR_READ_4(sc, PCN_IO32_BDP));
254 pcn_bcr_read16(sc, reg)
255 struct pcn_softc *sc;
258 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
259 return(CSR_READ_2(sc, PCN_IO16_BDP));
263 pcn_bcr_write(sc, reg, val)
264 struct pcn_softc *sc;
268 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
269 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
274 pcn_miibus_readreg(dev, phy, reg)
278 struct pcn_softc *sc;
281 sc = device_get_softc(dev);
283 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
286 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
287 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
291 sc->pcn_phyaddr = phy;
297 pcn_miibus_writereg(dev, phy, reg, data)
301 struct pcn_softc *sc;
303 sc = device_get_softc(dev);
305 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
306 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
312 pcn_miibus_statchg(dev)
315 struct pcn_softc *sc;
316 struct mii_data *mii;
318 sc = device_get_softc(dev);
319 mii = device_get_softc(sc->pcn_miibus);
321 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
322 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
324 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
332 struct pcn_softc *sc;
335 struct ifmultiaddr *ifma;
337 u_int16_t hashes[4] = { 0, 0, 0, 0 };
339 ifp = &sc->arpcom.ac_if;
341 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
343 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
344 for (i = 0; i < 4; i++)
345 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
346 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
350 /* first, zot all the existing hash bits */
351 for (i = 0; i < 4; i++)
352 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
354 /* now program new ones */
355 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
356 if (ifma->ifma_addr->sa_family != AF_LINK)
358 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
359 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
360 hashes[h >> 4] |= 1 << (h & 0xF);
363 for (i = 0; i < 4; i++)
364 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
366 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
373 struct pcn_softc *sc;
376 * Issue a reset by reading from the RESET register.
377 * Note that we don't know if the chip is operating in
378 * 16-bit or 32-bit mode at this point, so we attempt
379 * to reset the chip both ways. If one fails, the other
382 CSR_READ_2(sc, PCN_IO16_RESET);
383 CSR_READ_4(sc, PCN_IO32_RESET);
385 /* Wait a little while for the chip to get its brains in order. */
388 /* Select 32-bit (DWIO) mode */
389 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
391 /* Select software style 3. */
392 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
398 pcn_chipid_name (u_int32_t id)
400 struct pcn_chipid *p = pcn_chipid;
411 pcn_chip_id (device_t dev)
413 struct pcn_softc *sc;
416 sc = device_get_softc(dev);
418 * Note: we can *NOT* put the chip into
419 * 32-bit mode yet. The lnc driver will only
420 * work in 16-bit mode, and once the chip
421 * goes into 32-bit mode, the only way to
422 * get it out again is with a hardware reset.
423 * So if pcn_probe() is called before the
424 * lnc driver's probe routine, the chip will
425 * be locked into 32-bit operation and the lnc
426 * driver will be unable to attach to it.
427 * Note II: if the chip happens to already
428 * be in 32-bit mode, we still need to check
429 * the chip ID, but first we have to detect
430 * 32-bit mode using only 16-bit operations.
431 * The safest way to do this is to read the
432 * PCI subsystem ID from BCR23/24 and compare
433 * that with the value read from PCI config
436 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
438 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
440 * Note III: the test for 0x10001000 is a hack to
441 * pacify VMware, who's pseudo-PCnet interface is
442 * broken. Reading the subsystem register from PCI
443 * config space yields 0x00000000 while reading the
444 * same value from I/O space yields 0x10001000. It's
445 * not supposed to be that way.
447 if (chip_id == pci_read_config(dev,
448 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
449 /* We're in 16-bit mode. */
450 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
452 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
454 /* We're in 32-bit mode. */
455 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
457 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
463 static struct pcn_type *
464 pcn_match (u_int16_t vid, u_int16_t did)
469 while(t->pcn_name != NULL) {
470 if ((vid == t->pcn_vid) && (did == t->pcn_did))
478 * Probe for an AMD chip. Check the PCI vendor and device
479 * IDs against our list and return a device name if we find a match.
486 struct pcn_softc *sc;
490 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
493 sc = device_get_softc(dev);
496 * Temporarily map the I/O space so we can read the chip ID register.
499 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
500 if (sc->pcn_res == NULL) {
501 device_printf(dev, "couldn't map ports/memory\n");
504 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
505 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
507 chip_id = pcn_chip_id(dev);
509 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
511 switch((chip_id >> 12) & PART_MASK) {
522 device_set_desc(dev, t->pcn_name);
523 return(BUS_PROBE_DEFAULT);
527 * Attach the interface. Allocate softc structures, do ifmedia
528 * setup and ethernet/BPF attach.
535 struct pcn_softc *sc;
537 int unit, error = 0, rid;
539 sc = device_get_softc(dev);
540 unit = device_get_unit(dev);
542 /* Initialize our mutex. */
543 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
544 MTX_DEF | MTX_RECURSE);
546 * Map control/status registers.
548 pci_enable_busmaster(dev);
550 /* Retrieve the chip ID */
551 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
552 device_printf(dev, "Chip ID %04x (%s)\n",
553 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
556 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
558 if (sc->pcn_res == NULL) {
559 printf("pcn%d: couldn't map ports/memory\n", unit);
564 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
565 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
567 /* Allocate interrupt */
569 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
570 RF_SHAREABLE | RF_ACTIVE);
572 if (sc->pcn_irq == NULL) {
573 printf("pcn%d: couldn't map interrupt\n", unit);
578 /* Reset the adapter. */
582 * Get station address from the EEPROM.
584 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
585 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
586 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
589 callout_handle_init(&sc->pcn_stat_ch);
591 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
592 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
594 if (sc->pcn_ldata == NULL) {
595 printf("pcn%d: no memory for list buffers!\n", unit);
599 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
601 ifp = &sc->arpcom.ac_if;
603 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
604 ifp->if_mtu = ETHERMTU;
605 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
607 ifp->if_ioctl = pcn_ioctl;
608 ifp->if_start = pcn_start;
609 ifp->if_watchdog = pcn_watchdog;
610 ifp->if_init = pcn_init;
611 ifp->if_baudrate = 10000000;
612 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
617 if (mii_phy_probe(dev, &sc->pcn_miibus,
618 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
619 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
625 * Call MI attach routine.
627 ether_ifattach(ifp, (u_int8_t *) eaddr);
629 /* Hook interrupt last to avoid having to lock softc */
630 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET,
631 pcn_intr, sc, &sc->pcn_intrhand);
634 printf("pcn%d: couldn't set up irq\n", unit);
647 * Shutdown hardware and free up resources. This can be called any
648 * time after the mutex has been initialized. It is called in both
649 * the error case in attach and the normal detach case so it needs
650 * to be careful about only freeing resources that have actually been
657 struct pcn_softc *sc;
660 sc = device_get_softc(dev);
661 ifp = &sc->arpcom.ac_if;
663 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
666 /* These should only be active if attach succeeded */
667 if (device_is_attached(dev)) {
673 device_delete_child(dev, sc->pcn_miibus);
674 bus_generic_detach(dev);
676 if (sc->pcn_intrhand)
677 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
679 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
681 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
684 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
689 mtx_destroy(&sc->pcn_mtx);
695 * Initialize the transmit descriptors.
699 struct pcn_softc *sc;
701 struct pcn_list_data *ld;
702 struct pcn_ring_data *cd;
708 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
709 cd->pcn_tx_chain[i] = NULL;
710 ld->pcn_tx_list[i].pcn_tbaddr = 0;
711 ld->pcn_tx_list[i].pcn_txctl = 0;
712 ld->pcn_tx_list[i].pcn_txstat = 0;
715 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
722 * Initialize the RX descriptors and allocate mbufs for them.
726 struct pcn_softc *sc;
728 struct pcn_ring_data *cd;
733 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
734 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
744 * Initialize an RX descriptor and attach an MBUF cluster.
747 pcn_newbuf(sc, idx, m)
748 struct pcn_softc *sc;
752 struct mbuf *m_new = NULL;
753 struct pcn_rx_desc *c;
755 c = &sc->pcn_ldata->pcn_rx_list[idx];
758 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
762 MCLGET(m_new, M_DONTWAIT);
763 if (!(m_new->m_flags & M_EXT)) {
767 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
770 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
771 m_new->m_data = m_new->m_ext.ext_buf;
774 m_adj(m_new, ETHER_ALIGN);
776 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
777 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
778 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
779 c->pcn_bufsz |= PCN_RXLEN_MBO;
780 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
786 * A frame has been uploaded: pass the resulting mbuf chain up to
787 * the higher level protocols.
791 struct pcn_softc *sc;
795 struct pcn_rx_desc *cur_rx;
800 ifp = &sc->arpcom.ac_if;
801 i = sc->pcn_cdata.pcn_rx_prod;
803 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
804 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
805 m = sc->pcn_cdata.pcn_rx_chain[i];
806 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
809 * If an error occurs, update stats, clear the
810 * status word and leave the mbuf cluster in place:
811 * it should simply get re-used next time this descriptor
812 * comes up in the ring.
814 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
816 pcn_newbuf(sc, i, m);
817 PCN_INC(i, PCN_RX_LIST_CNT);
821 if (pcn_newbuf(sc, i, NULL)) {
822 /* Ran out of mbufs; recycle this one. */
823 pcn_newbuf(sc, i, m);
825 PCN_INC(i, PCN_RX_LIST_CNT);
829 PCN_INC(i, PCN_RX_LIST_CNT);
831 /* No errors; receive the packet. */
833 m->m_len = m->m_pkthdr.len =
834 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
835 m->m_pkthdr.rcvif = ifp;
838 (*ifp->if_input)(ifp, m);
842 sc->pcn_cdata.pcn_rx_prod = i;
848 * A frame was downloaded to the chip. It's safe for us to clean up
854 struct pcn_softc *sc;
856 struct pcn_tx_desc *cur_tx = NULL;
860 ifp = &sc->arpcom.ac_if;
863 * Go through our tx list and free mbufs for those
864 * frames that have been transmitted.
866 idx = sc->pcn_cdata.pcn_tx_cons;
867 while (idx != sc->pcn_cdata.pcn_tx_prod) {
868 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
870 if (!PCN_OWN_TXDESC(cur_tx))
873 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
874 sc->pcn_cdata.pcn_tx_cnt--;
875 PCN_INC(idx, PCN_TX_LIST_CNT);
879 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
881 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
882 ifp->if_collisions++;
883 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
884 ifp->if_collisions++;
887 ifp->if_collisions +=
888 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
891 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
892 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
893 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
896 sc->pcn_cdata.pcn_tx_cnt--;
897 PCN_INC(idx, PCN_TX_LIST_CNT);
900 if (idx != sc->pcn_cdata.pcn_tx_cons) {
901 /* Some buffers have been freed. */
902 sc->pcn_cdata.pcn_tx_cons = idx;
903 ifp->if_flags &= ~IFF_OACTIVE;
905 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
914 struct pcn_softc *sc;
915 struct mii_data *mii;
919 ifp = &sc->arpcom.ac_if;
922 mii = device_get_softc(sc->pcn_miibus);
926 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
929 /* link just came up, restart */
930 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
931 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
933 if (ifp->if_snd.ifq_head != NULL)
937 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
948 struct pcn_softc *sc;
953 ifp = &sc->arpcom.ac_if;
955 /* Suppress unwanted interrupts */
956 if (!(ifp->if_flags & IFF_UP)) {
963 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
965 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
966 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
968 if (status & PCN_CSR_RINT)
971 if (status & PCN_CSR_TINT)
974 if (status & PCN_CSR_ERR) {
980 if (ifp->if_snd.ifq_head != NULL)
988 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
989 * pointers to the fragment pointers.
992 pcn_encap(sc, m_head, txidx)
993 struct pcn_softc *sc;
997 struct pcn_tx_desc *f = NULL;
999 int frag, cur, cnt = 0;
1002 * Start packing the mbufs in this chain into
1003 * the fragment pointers. Stop when we run out
1004 * of fragments or hit the end of the mbuf chain.
1007 cur = frag = *txidx;
1009 for (m = m_head; m != NULL; m = m->m_next) {
1013 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1015 f = &sc->pcn_ldata->pcn_tx_list[frag];
1016 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1017 f->pcn_txctl |= PCN_TXCTL_MBO;
1018 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1020 f->pcn_txctl |= PCN_TXCTL_STP;
1022 f->pcn_txctl |= PCN_TXCTL_OWN;
1024 PCN_INC(frag, PCN_TX_LIST_CNT);
1031 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1032 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1033 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1034 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1035 sc->pcn_cdata.pcn_tx_cnt += cnt;
1042 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1043 * to the mbuf data regions directly in the transmit lists. We also save a
1044 * copy of the pointers since the transmit list fragment pointers are
1045 * physical addresses.
1051 struct pcn_softc *sc;
1052 struct mbuf *m_head = NULL;
1059 if (!sc->pcn_link) {
1064 idx = sc->pcn_cdata.pcn_tx_prod;
1066 if (ifp->if_flags & IFF_OACTIVE) {
1071 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1072 IF_DEQUEUE(&ifp->if_snd, m_head);
1076 if (pcn_encap(sc, m_head, &idx)) {
1077 IF_PREPEND(&ifp->if_snd, m_head);
1078 ifp->if_flags |= IFF_OACTIVE;
1083 * If there's a BPF listener, bounce a copy of this frame
1086 BPF_MTAP(ifp, m_head);
1091 sc->pcn_cdata.pcn_tx_prod = idx;
1092 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1095 * Set a timeout in case the chip goes out to lunch.
1108 struct pcn_softc *sc;
1112 /* If we want promiscuous mode, set the allframes bit. */
1113 if (ifp->if_flags & IFF_PROMISC) {
1114 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1116 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1119 /* Set the capture broadcast bit to capture broadcast frames. */
1120 if (ifp->if_flags & IFF_BROADCAST) {
1121 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1123 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1133 struct pcn_softc *sc = xsc;
1134 struct ifnet *ifp = &sc->arpcom.ac_if;
1135 struct mii_data *mii = NULL;
1140 * Cancel pending I/O and free all RX/TX buffers.
1145 mii = device_get_softc(sc->pcn_miibus);
1147 /* Set MAC address */
1148 pcn_csr_write(sc, PCN_CSR_PAR0,
1149 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1150 pcn_csr_write(sc, PCN_CSR_PAR1,
1151 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1152 pcn_csr_write(sc, PCN_CSR_PAR2,
1153 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1155 /* Init circular RX list. */
1156 if (pcn_list_rx_init(sc) == ENOBUFS) {
1157 printf("pcn%d: initialization failed: no "
1158 "memory for rx buffers\n", sc->pcn_unit);
1165 * Init tx descriptors.
1167 pcn_list_tx_init(sc);
1169 /* Set up the mode register. */
1170 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1172 /* Set up RX filter. */
1176 * Load the multicast filter.
1181 * Load the addresses of the RX and TX lists.
1183 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1184 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1185 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1186 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1187 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1188 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1189 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1190 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1192 /* Set the RX and TX ring sizes. */
1193 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1194 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1196 /* We're not using the initialization block. */
1197 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1199 /* Enable fast suspend mode. */
1200 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1203 * Enable burst read and write. Also set the no underflow
1204 * bit. This will avoid transmit underruns in certain
1205 * conditions while still providing decent performance.
1207 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1208 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1210 /* Enable graceful recovery from underflow. */
1211 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1213 /* Enable auto-padding of short TX frames. */
1214 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1216 /* Disable MII autoneg (we handle this ourselves). */
1217 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1219 if (sc->pcn_type == Am79C978)
1220 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1221 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1223 /* Enable interrupts and start the controller running. */
1224 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1228 ifp->if_flags |= IFF_RUNNING;
1229 ifp->if_flags &= ~IFF_OACTIVE;
1231 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
1238 * Set media options.
1241 pcn_ifmedia_upd(ifp)
1244 struct pcn_softc *sc;
1245 struct mii_data *mii;
1248 mii = device_get_softc(sc->pcn_miibus);
1251 if (mii->mii_instance) {
1252 struct mii_softc *miisc;
1253 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1254 mii_phy_reset(miisc);
1262 * Report current media status.
1265 pcn_ifmedia_sts(ifp, ifmr)
1267 struct ifmediareq *ifmr;
1269 struct pcn_softc *sc;
1270 struct mii_data *mii;
1274 mii = device_get_softc(sc->pcn_miibus);
1276 ifmr->ifm_active = mii->mii_media_active;
1277 ifmr->ifm_status = mii->mii_media_status;
1283 pcn_ioctl(ifp, command, data)
1288 struct pcn_softc *sc = ifp->if_softc;
1289 struct ifreq *ifr = (struct ifreq *) data;
1290 struct mii_data *mii = NULL;
1297 if (ifp->if_flags & IFF_UP) {
1298 if (ifp->if_flags & IFF_RUNNING &&
1299 ifp->if_flags & IFF_PROMISC &&
1300 !(sc->pcn_if_flags & IFF_PROMISC)) {
1301 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1304 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1306 pcn_csr_write(sc, PCN_CSR_CSR,
1307 PCN_CSR_INTEN|PCN_CSR_START);
1308 } else if (ifp->if_flags & IFF_RUNNING &&
1309 !(ifp->if_flags & IFF_PROMISC) &&
1310 sc->pcn_if_flags & IFF_PROMISC) {
1311 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1314 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1316 pcn_csr_write(sc, PCN_CSR_CSR,
1317 PCN_CSR_INTEN|PCN_CSR_START);
1318 } else if (!(ifp->if_flags & IFF_RUNNING))
1321 if (ifp->if_flags & IFF_RUNNING)
1324 sc->pcn_if_flags = ifp->if_flags;
1334 mii = device_get_softc(sc->pcn_miibus);
1335 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1338 error = ether_ioctl(ifp, command, data);
1351 struct pcn_softc *sc;
1358 printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
1364 if (ifp->if_snd.ifq_head != NULL)
1373 * Stop the adapter and free any mbufs allocated to the
1378 struct pcn_softc *sc;
1383 ifp = &sc->arpcom.ac_if;
1387 untimeout(pcn_tick, sc, sc->pcn_stat_ch);
1389 /* Turn off interrupts */
1390 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1392 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1396 * Free data in the RX lists.
1398 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1399 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1400 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1401 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1404 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1405 sizeof(sc->pcn_ldata->pcn_rx_list));
1408 * Free the TX list buffers.
1410 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1411 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1412 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1413 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1417 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1418 sizeof(sc->pcn_ldata->pcn_tx_list));
1420 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1427 * Stop all chip I/O so that the kernel's probe routines don't
1428 * get confused by errant DMAs when rebooting.
1434 struct pcn_softc *sc;
1436 sc = device_get_softc(dev);