2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/sockio.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/module.h>
62 #include <sys/socket.h>
65 #include <net/if_arp.h>
66 #include <net/ethernet.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
73 #include <vm/vm.h> /* for vtophys */
74 #include <vm/pmap.h> /* for vtophys */
75 #include <machine/bus.h>
76 #include <machine/resource.h>
80 #include <dev/mii/mii.h>
81 #include <dev/mii/miivar.h>
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
86 #define PCN_USEIOSPACE
88 #include <pci/if_pcnreg.h>
90 MODULE_DEPEND(pcn, pci, 1, 1, 1);
91 MODULE_DEPEND(pcn, ether, 1, 1, 1);
92 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
94 /* "controller miibus0" required. See GENERIC if you get errors here. */
95 #include "miibus_if.h"
98 * Various supported device vendors/types and their names.
100 static struct pcn_type pcn_devs[] = {
101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
106 static struct pcn_chipid {
110 { Am79C960, "Am79C960" },
111 { Am79C961, "Am79C961" },
112 { Am79C961A, "Am79C961A" },
113 { Am79C965, "Am79C965" },
114 { Am79C970, "Am79C970" },
115 { Am79C970A, "Am79C970A" },
116 { Am79C971, "Am79C971" },
117 { Am79C972, "Am79C972" },
118 { Am79C973, "Am79C973" },
119 { Am79C978, "Am79C978" },
120 { Am79C975, "Am79C975" },
121 { Am79C976, "Am79C976" },
125 static char * pcn_chipid_name(u_int32_t);
126 static u_int32_t pcn_chip_id(device_t);
128 static u_int32_t pcn_csr_read(struct pcn_softc *, int);
129 static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
130 static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
131 static void pcn_csr_write(struct pcn_softc *, int, int);
132 static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
133 static void pcn_bcr_write(struct pcn_softc *, int, int);
135 static int pcn_probe(device_t);
136 static int pcn_attach(device_t);
137 static int pcn_detach(device_t);
139 static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
140 static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
141 static void pcn_rxeof(struct pcn_softc *);
142 static void pcn_txeof(struct pcn_softc *);
143 static void pcn_intr(void *);
144 static void pcn_tick(void *);
145 static void pcn_start(struct ifnet *);
146 static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
147 static void pcn_init(void *);
148 static void pcn_stop(struct pcn_softc *);
149 static void pcn_watchdog(struct ifnet *);
150 static void pcn_shutdown(device_t);
151 static int pcn_ifmedia_upd(struct ifnet *);
152 static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
154 static int pcn_miibus_readreg(device_t, int, int);
155 static int pcn_miibus_writereg(device_t, int, int, int);
156 static void pcn_miibus_statchg(device_t);
158 static void pcn_setfilt(struct ifnet *);
159 static void pcn_setmulti(struct pcn_softc *);
160 static void pcn_reset(struct pcn_softc *);
161 static int pcn_list_rx_init(struct pcn_softc *);
162 static int pcn_list_tx_init(struct pcn_softc *);
164 #ifdef PCN_USEIOSPACE
165 #define PCN_RES SYS_RES_IOPORT
166 #define PCN_RID PCN_PCI_LOIO
168 #define PCN_RES SYS_RES_MEMORY
169 #define PCN_RID PCN_PCI_LOMEM
172 static device_method_t pcn_methods[] = {
173 /* Device interface */
174 DEVMETHOD(device_probe, pcn_probe),
175 DEVMETHOD(device_attach, pcn_attach),
176 DEVMETHOD(device_detach, pcn_detach),
177 DEVMETHOD(device_shutdown, pcn_shutdown),
180 DEVMETHOD(bus_print_child, bus_generic_print_child),
181 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
184 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
185 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
186 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
191 static driver_t pcn_driver = {
194 sizeof(struct pcn_softc)
197 static devclass_t pcn_devclass;
199 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
200 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
202 #define PCN_CSR_SETBIT(sc, reg, x) \
203 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
205 #define PCN_CSR_CLRBIT(sc, reg, x) \
206 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
208 #define PCN_BCR_SETBIT(sc, reg, x) \
209 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
211 #define PCN_BCR_CLRBIT(sc, reg, x) \
212 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
215 pcn_csr_read(sc, reg)
216 struct pcn_softc *sc;
219 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
220 return(CSR_READ_4(sc, PCN_IO32_RDP));
224 pcn_csr_read16(sc, reg)
225 struct pcn_softc *sc;
228 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
229 return(CSR_READ_2(sc, PCN_IO16_RDP));
233 pcn_csr_write(sc, reg, val)
234 struct pcn_softc *sc;
238 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
239 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
244 pcn_bcr_read(sc, reg)
245 struct pcn_softc *sc;
248 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
249 return(CSR_READ_4(sc, PCN_IO32_BDP));
253 pcn_bcr_read16(sc, reg)
254 struct pcn_softc *sc;
257 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
258 return(CSR_READ_2(sc, PCN_IO16_BDP));
262 pcn_bcr_write(sc, reg, val)
263 struct pcn_softc *sc;
267 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
268 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
273 pcn_miibus_readreg(dev, phy, reg)
277 struct pcn_softc *sc;
280 sc = device_get_softc(dev);
282 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
285 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
286 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
290 sc->pcn_phyaddr = phy;
296 pcn_miibus_writereg(dev, phy, reg, data)
300 struct pcn_softc *sc;
302 sc = device_get_softc(dev);
304 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
305 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
311 pcn_miibus_statchg(dev)
314 struct pcn_softc *sc;
315 struct mii_data *mii;
317 sc = device_get_softc(dev);
318 mii = device_get_softc(sc->pcn_miibus);
320 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
321 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
323 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
331 struct pcn_softc *sc;
334 struct ifmultiaddr *ifma;
336 u_int16_t hashes[4] = { 0, 0, 0, 0 };
340 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
342 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
343 for (i = 0; i < 4; i++)
344 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
345 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
349 /* first, zot all the existing hash bits */
350 for (i = 0; i < 4; i++)
351 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
353 /* now program new ones */
355 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
356 if (ifma->ifma_addr->sa_family != AF_LINK)
358 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
359 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
360 hashes[h >> 4] |= 1 << (h & 0xF);
364 for (i = 0; i < 4; i++)
365 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
367 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
374 struct pcn_softc *sc;
377 * Issue a reset by reading from the RESET register.
378 * Note that we don't know if the chip is operating in
379 * 16-bit or 32-bit mode at this point, so we attempt
380 * to reset the chip both ways. If one fails, the other
383 CSR_READ_2(sc, PCN_IO16_RESET);
384 CSR_READ_4(sc, PCN_IO32_RESET);
386 /* Wait a little while for the chip to get its brains in order. */
389 /* Select 32-bit (DWIO) mode */
390 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
392 /* Select software style 3. */
393 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
399 pcn_chipid_name (u_int32_t id)
401 struct pcn_chipid *p = pcn_chipid;
412 pcn_chip_id (device_t dev)
414 struct pcn_softc *sc;
417 sc = device_get_softc(dev);
419 * Note: we can *NOT* put the chip into
420 * 32-bit mode yet. The lnc driver will only
421 * work in 16-bit mode, and once the chip
422 * goes into 32-bit mode, the only way to
423 * get it out again is with a hardware reset.
424 * So if pcn_probe() is called before the
425 * lnc driver's probe routine, the chip will
426 * be locked into 32-bit operation and the lnc
427 * driver will be unable to attach to it.
428 * Note II: if the chip happens to already
429 * be in 32-bit mode, we still need to check
430 * the chip ID, but first we have to detect
431 * 32-bit mode using only 16-bit operations.
432 * The safest way to do this is to read the
433 * PCI subsystem ID from BCR23/24 and compare
434 * that with the value read from PCI config
437 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
439 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
441 * Note III: the test for 0x10001000 is a hack to
442 * pacify VMware, who's pseudo-PCnet interface is
443 * broken. Reading the subsystem register from PCI
444 * config space yields 0x00000000 while reading the
445 * same value from I/O space yields 0x10001000. It's
446 * not supposed to be that way.
448 if (chip_id == pci_read_config(dev,
449 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
450 /* We're in 16-bit mode. */
451 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
453 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
455 /* We're in 32-bit mode. */
456 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
458 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
464 static struct pcn_type *
465 pcn_match (u_int16_t vid, u_int16_t did)
470 while(t->pcn_name != NULL) {
471 if ((vid == t->pcn_vid) && (did == t->pcn_did))
479 * Probe for an AMD chip. Check the PCI vendor and device
480 * IDs against our list and return a device name if we find a match.
487 struct pcn_softc *sc;
491 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
494 sc = device_get_softc(dev);
497 * Temporarily map the I/O space so we can read the chip ID register.
500 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
501 if (sc->pcn_res == NULL) {
502 device_printf(dev, "couldn't map ports/memory\n");
505 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
506 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
508 chip_id = pcn_chip_id(dev);
510 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
512 switch((chip_id >> 12) & PART_MASK) {
523 device_set_desc(dev, t->pcn_name);
524 return(BUS_PROBE_DEFAULT);
528 * Attach the interface. Allocate softc structures, do ifmedia
529 * setup and ethernet/BPF attach.
536 struct pcn_softc *sc;
538 int unit, error = 0, rid;
540 sc = device_get_softc(dev);
541 unit = device_get_unit(dev);
543 /* Initialize our mutex. */
544 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
545 MTX_DEF | MTX_RECURSE);
547 * Map control/status registers.
549 pci_enable_busmaster(dev);
551 /* Retrieve the chip ID */
552 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
553 device_printf(dev, "Chip ID %04x (%s)\n",
554 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
557 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
559 if (sc->pcn_res == NULL) {
560 printf("pcn%d: couldn't map ports/memory\n", unit);
565 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
566 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
568 /* Allocate interrupt */
570 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
571 RF_SHAREABLE | RF_ACTIVE);
573 if (sc->pcn_irq == NULL) {
574 printf("pcn%d: couldn't map interrupt\n", unit);
579 /* Reset the adapter. */
583 * Get station address from the EEPROM.
585 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
586 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
589 callout_handle_init(&sc->pcn_stat_ch);
591 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
592 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
594 if (sc->pcn_ldata == NULL) {
595 printf("pcn%d: no memory for list buffers!\n", unit);
599 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
601 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER);
603 printf("pcn%d: can not if_alloc()\n", unit);
608 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
609 ifp->if_mtu = ETHERMTU;
610 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
612 ifp->if_ioctl = pcn_ioctl;
613 ifp->if_start = pcn_start;
614 ifp->if_watchdog = pcn_watchdog;
615 ifp->if_init = pcn_init;
616 ifp->if_baudrate = 10000000;
617 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
622 if (mii_phy_probe(dev, &sc->pcn_miibus,
623 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
624 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
631 * Call MI attach routine.
633 ether_ifattach(ifp, (u_int8_t *) eaddr);
635 /* Hook interrupt last to avoid having to lock softc */
636 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET,
637 pcn_intr, sc, &sc->pcn_intrhand);
640 printf("pcn%d: couldn't set up irq\n", unit);
653 * Shutdown hardware and free up resources. This can be called any
654 * time after the mutex has been initialized. It is called in both
655 * the error case in attach and the normal detach case so it needs
656 * to be careful about only freeing resources that have actually been
663 struct pcn_softc *sc;
666 sc = device_get_softc(dev);
669 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
672 /* These should only be active if attach succeeded */
673 if (device_is_attached(dev)) {
680 device_delete_child(dev, sc->pcn_miibus);
681 bus_generic_detach(dev);
683 if (sc->pcn_intrhand)
684 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
686 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
688 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
691 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
696 mtx_destroy(&sc->pcn_mtx);
702 * Initialize the transmit descriptors.
706 struct pcn_softc *sc;
708 struct pcn_list_data *ld;
709 struct pcn_ring_data *cd;
715 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
716 cd->pcn_tx_chain[i] = NULL;
717 ld->pcn_tx_list[i].pcn_tbaddr = 0;
718 ld->pcn_tx_list[i].pcn_txctl = 0;
719 ld->pcn_tx_list[i].pcn_txstat = 0;
722 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
729 * Initialize the RX descriptors and allocate mbufs for them.
733 struct pcn_softc *sc;
735 struct pcn_ring_data *cd;
740 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
741 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
751 * Initialize an RX descriptor and attach an MBUF cluster.
754 pcn_newbuf(sc, idx, m)
755 struct pcn_softc *sc;
759 struct mbuf *m_new = NULL;
760 struct pcn_rx_desc *c;
762 c = &sc->pcn_ldata->pcn_rx_list[idx];
765 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
769 MCLGET(m_new, M_DONTWAIT);
770 if (!(m_new->m_flags & M_EXT)) {
774 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
777 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
778 m_new->m_data = m_new->m_ext.ext_buf;
781 m_adj(m_new, ETHER_ALIGN);
783 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
784 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
785 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
786 c->pcn_bufsz |= PCN_RXLEN_MBO;
787 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
793 * A frame has been uploaded: pass the resulting mbuf chain up to
794 * the higher level protocols.
798 struct pcn_softc *sc;
802 struct pcn_rx_desc *cur_rx;
808 i = sc->pcn_cdata.pcn_rx_prod;
810 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
811 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
812 m = sc->pcn_cdata.pcn_rx_chain[i];
813 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
816 * If an error occurs, update stats, clear the
817 * status word and leave the mbuf cluster in place:
818 * it should simply get re-used next time this descriptor
819 * comes up in the ring.
821 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
823 pcn_newbuf(sc, i, m);
824 PCN_INC(i, PCN_RX_LIST_CNT);
828 if (pcn_newbuf(sc, i, NULL)) {
829 /* Ran out of mbufs; recycle this one. */
830 pcn_newbuf(sc, i, m);
832 PCN_INC(i, PCN_RX_LIST_CNT);
836 PCN_INC(i, PCN_RX_LIST_CNT);
838 /* No errors; receive the packet. */
840 m->m_len = m->m_pkthdr.len =
841 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
842 m->m_pkthdr.rcvif = ifp;
845 (*ifp->if_input)(ifp, m);
849 sc->pcn_cdata.pcn_rx_prod = i;
855 * A frame was downloaded to the chip. It's safe for us to clean up
861 struct pcn_softc *sc;
863 struct pcn_tx_desc *cur_tx = NULL;
870 * Go through our tx list and free mbufs for those
871 * frames that have been transmitted.
873 idx = sc->pcn_cdata.pcn_tx_cons;
874 while (idx != sc->pcn_cdata.pcn_tx_prod) {
875 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
877 if (!PCN_OWN_TXDESC(cur_tx))
880 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
881 sc->pcn_cdata.pcn_tx_cnt--;
882 PCN_INC(idx, PCN_TX_LIST_CNT);
886 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
888 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
889 ifp->if_collisions++;
890 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
891 ifp->if_collisions++;
894 ifp->if_collisions +=
895 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
898 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
899 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
900 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
903 sc->pcn_cdata.pcn_tx_cnt--;
904 PCN_INC(idx, PCN_TX_LIST_CNT);
907 if (idx != sc->pcn_cdata.pcn_tx_cons) {
908 /* Some buffers have been freed. */
909 sc->pcn_cdata.pcn_tx_cons = idx;
910 ifp->if_flags &= ~IFF_OACTIVE;
912 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
921 struct pcn_softc *sc;
922 struct mii_data *mii;
929 mii = device_get_softc(sc->pcn_miibus);
933 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
936 /* link just came up, restart */
937 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
938 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
940 if (ifp->if_snd.ifq_head != NULL)
944 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
955 struct pcn_softc *sc;
962 /* Suppress unwanted interrupts */
963 if (!(ifp->if_flags & IFF_UP)) {
970 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
972 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
973 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
975 if (status & PCN_CSR_RINT)
978 if (status & PCN_CSR_TINT)
981 if (status & PCN_CSR_ERR) {
987 if (ifp->if_snd.ifq_head != NULL)
995 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
996 * pointers to the fragment pointers.
999 pcn_encap(sc, m_head, txidx)
1000 struct pcn_softc *sc;
1001 struct mbuf *m_head;
1004 struct pcn_tx_desc *f = NULL;
1006 int frag, cur, cnt = 0;
1009 * Start packing the mbufs in this chain into
1010 * the fragment pointers. Stop when we run out
1011 * of fragments or hit the end of the mbuf chain.
1014 cur = frag = *txidx;
1016 for (m = m_head; m != NULL; m = m->m_next) {
1020 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1022 f = &sc->pcn_ldata->pcn_tx_list[frag];
1023 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1024 f->pcn_txctl |= PCN_TXCTL_MBO;
1025 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1027 f->pcn_txctl |= PCN_TXCTL_STP;
1029 f->pcn_txctl |= PCN_TXCTL_OWN;
1031 PCN_INC(frag, PCN_TX_LIST_CNT);
1038 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1039 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1040 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1041 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1042 sc->pcn_cdata.pcn_tx_cnt += cnt;
1049 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1050 * to the mbuf data regions directly in the transmit lists. We also save a
1051 * copy of the pointers since the transmit list fragment pointers are
1052 * physical addresses.
1058 struct pcn_softc *sc;
1059 struct mbuf *m_head = NULL;
1066 if (!sc->pcn_link) {
1071 idx = sc->pcn_cdata.pcn_tx_prod;
1073 if (ifp->if_flags & IFF_OACTIVE) {
1078 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1079 IF_DEQUEUE(&ifp->if_snd, m_head);
1083 if (pcn_encap(sc, m_head, &idx)) {
1084 IF_PREPEND(&ifp->if_snd, m_head);
1085 ifp->if_flags |= IFF_OACTIVE;
1090 * If there's a BPF listener, bounce a copy of this frame
1093 BPF_MTAP(ifp, m_head);
1098 sc->pcn_cdata.pcn_tx_prod = idx;
1099 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1102 * Set a timeout in case the chip goes out to lunch.
1115 struct pcn_softc *sc;
1119 /* If we want promiscuous mode, set the allframes bit. */
1120 if (ifp->if_flags & IFF_PROMISC) {
1121 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1123 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1126 /* Set the capture broadcast bit to capture broadcast frames. */
1127 if (ifp->if_flags & IFF_BROADCAST) {
1128 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1130 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1140 struct pcn_softc *sc = xsc;
1141 struct ifnet *ifp = sc->pcn_ifp;
1142 struct mii_data *mii = NULL;
1147 * Cancel pending I/O and free all RX/TX buffers.
1152 mii = device_get_softc(sc->pcn_miibus);
1154 /* Set MAC address */
1155 pcn_csr_write(sc, PCN_CSR_PAR0,
1156 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[0]);
1157 pcn_csr_write(sc, PCN_CSR_PAR1,
1158 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[1]);
1159 pcn_csr_write(sc, PCN_CSR_PAR2,
1160 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[2]);
1162 /* Init circular RX list. */
1163 if (pcn_list_rx_init(sc) == ENOBUFS) {
1164 printf("pcn%d: initialization failed: no "
1165 "memory for rx buffers\n", sc->pcn_unit);
1172 * Init tx descriptors.
1174 pcn_list_tx_init(sc);
1176 /* Set up the mode register. */
1177 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1179 /* Set up RX filter. */
1183 * Load the multicast filter.
1188 * Load the addresses of the RX and TX lists.
1190 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1191 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1192 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1193 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1194 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1195 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1196 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1197 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1199 /* Set the RX and TX ring sizes. */
1200 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1201 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1203 /* We're not using the initialization block. */
1204 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1206 /* Enable fast suspend mode. */
1207 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1210 * Enable burst read and write. Also set the no underflow
1211 * bit. This will avoid transmit underruns in certain
1212 * conditions while still providing decent performance.
1214 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1215 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1217 /* Enable graceful recovery from underflow. */
1218 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1220 /* Enable auto-padding of short TX frames. */
1221 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1223 /* Disable MII autoneg (we handle this ourselves). */
1224 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1226 if (sc->pcn_type == Am79C978)
1227 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1228 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1230 /* Enable interrupts and start the controller running. */
1231 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1235 ifp->if_flags |= IFF_RUNNING;
1236 ifp->if_flags &= ~IFF_OACTIVE;
1238 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
1245 * Set media options.
1248 pcn_ifmedia_upd(ifp)
1251 struct pcn_softc *sc;
1252 struct mii_data *mii;
1255 mii = device_get_softc(sc->pcn_miibus);
1258 if (mii->mii_instance) {
1259 struct mii_softc *miisc;
1260 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1261 mii_phy_reset(miisc);
1269 * Report current media status.
1272 pcn_ifmedia_sts(ifp, ifmr)
1274 struct ifmediareq *ifmr;
1276 struct pcn_softc *sc;
1277 struct mii_data *mii;
1281 mii = device_get_softc(sc->pcn_miibus);
1283 ifmr->ifm_active = mii->mii_media_active;
1284 ifmr->ifm_status = mii->mii_media_status;
1290 pcn_ioctl(ifp, command, data)
1295 struct pcn_softc *sc = ifp->if_softc;
1296 struct ifreq *ifr = (struct ifreq *) data;
1297 struct mii_data *mii = NULL;
1304 if (ifp->if_flags & IFF_UP) {
1305 if (ifp->if_flags & IFF_RUNNING &&
1306 ifp->if_flags & IFF_PROMISC &&
1307 !(sc->pcn_if_flags & IFF_PROMISC)) {
1308 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1311 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1313 pcn_csr_write(sc, PCN_CSR_CSR,
1314 PCN_CSR_INTEN|PCN_CSR_START);
1315 } else if (ifp->if_flags & IFF_RUNNING &&
1316 !(ifp->if_flags & IFF_PROMISC) &&
1317 sc->pcn_if_flags & IFF_PROMISC) {
1318 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1321 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1323 pcn_csr_write(sc, PCN_CSR_CSR,
1324 PCN_CSR_INTEN|PCN_CSR_START);
1325 } else if (!(ifp->if_flags & IFF_RUNNING))
1328 if (ifp->if_flags & IFF_RUNNING)
1331 sc->pcn_if_flags = ifp->if_flags;
1341 mii = device_get_softc(sc->pcn_miibus);
1342 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1345 error = ether_ioctl(ifp, command, data);
1358 struct pcn_softc *sc;
1365 printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
1371 if (ifp->if_snd.ifq_head != NULL)
1380 * Stop the adapter and free any mbufs allocated to the
1385 struct pcn_softc *sc;
1394 untimeout(pcn_tick, sc, sc->pcn_stat_ch);
1396 /* Turn off interrupts */
1397 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1399 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1403 * Free data in the RX lists.
1405 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1406 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1407 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1408 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1411 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1412 sizeof(sc->pcn_ldata->pcn_rx_list));
1415 * Free the TX list buffers.
1417 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1418 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1419 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1420 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1424 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1425 sizeof(sc->pcn_ldata->pcn_tx_list));
1427 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1434 * Stop all chip I/O so that the kernel's probe routines don't
1435 * get confused by errant DMAs when rebooting.
1441 struct pcn_softc *sc;
1443 sc = device_get_softc(dev);