2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available
39 * from http://www.amd.com.
41 * The AMD PCnet/PCI controllers are more advanced and functional
42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
43 * backwards compatibility with the LANCE and thus can be made
44 * to work with older LANCE drivers. This is in fact how the
45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
46 * is that the PCnet/PCI devices offer several performance enhancements
47 * which can't be exploited in LANCE compatibility mode. Chief among
48 * these enhancements is the ability to perform PCI DMA operations
49 * using 32-bit addressing (which eliminates the need for ISA
50 * bounce-buffering), and special receive buffer alignment (which
51 * allows the receive handler to pass packets to the upper protocol
52 * layers without copying on both the x86 and alpha platforms).
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/sockio.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/module.h>
62 #include <sys/socket.h>
65 #include <net/if_arp.h>
66 #include <net/ethernet.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
73 #include <vm/vm.h> /* for vtophys */
74 #include <vm/pmap.h> /* for vtophys */
75 #include <machine/bus.h>
76 #include <machine/resource.h>
80 #include <dev/mii/mii.h>
81 #include <dev/mii/miivar.h>
83 #include <dev/pci/pcireg.h>
84 #include <dev/pci/pcivar.h>
86 #define PCN_USEIOSPACE
88 #include <pci/if_pcnreg.h>
90 MODULE_DEPEND(pcn, pci, 1, 1, 1);
91 MODULE_DEPEND(pcn, ether, 1, 1, 1);
92 MODULE_DEPEND(pcn, miibus, 1, 1, 1);
94 /* "controller miibus0" required. See GENERIC if you get errors here. */
95 #include "miibus_if.h"
98 * Various supported device vendors/types and their names.
100 static struct pcn_type pcn_devs[] = {
101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
106 static struct pcn_chipid {
110 { Am79C960, "Am79C960" },
111 { Am79C961, "Am79C961" },
112 { Am79C961A, "Am79C961A" },
113 { Am79C965, "Am79C965" },
114 { Am79C970, "Am79C970" },
115 { Am79C970A, "Am79C970A" },
116 { Am79C971, "Am79C971" },
117 { Am79C972, "Am79C972" },
118 { Am79C973, "Am79C973" },
119 { Am79C978, "Am79C978" },
120 { Am79C975, "Am79C975" },
121 { Am79C976, "Am79C976" },
125 static char * pcn_chipid_name(u_int32_t);
126 static u_int32_t pcn_chip_id(device_t);
128 static u_int32_t pcn_csr_read(struct pcn_softc *, int);
129 static u_int16_t pcn_csr_read16(struct pcn_softc *, int);
130 static u_int16_t pcn_bcr_read16(struct pcn_softc *, int);
131 static void pcn_csr_write(struct pcn_softc *, int, int);
132 static u_int32_t pcn_bcr_read(struct pcn_softc *, int);
133 static void pcn_bcr_write(struct pcn_softc *, int, int);
135 static int pcn_probe(device_t);
136 static int pcn_attach(device_t);
137 static int pcn_detach(device_t);
139 static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *);
140 static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *);
141 static void pcn_rxeof(struct pcn_softc *);
142 static void pcn_txeof(struct pcn_softc *);
143 static void pcn_intr(void *);
144 static void pcn_tick(void *);
145 static void pcn_start(struct ifnet *);
146 static int pcn_ioctl(struct ifnet *, u_long, caddr_t);
147 static void pcn_init(void *);
148 static void pcn_stop(struct pcn_softc *);
149 static void pcn_watchdog(struct ifnet *);
150 static void pcn_shutdown(device_t);
151 static int pcn_ifmedia_upd(struct ifnet *);
152 static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *);
154 static int pcn_miibus_readreg(device_t, int, int);
155 static int pcn_miibus_writereg(device_t, int, int, int);
156 static void pcn_miibus_statchg(device_t);
158 static void pcn_setfilt(struct ifnet *);
159 static void pcn_setmulti(struct pcn_softc *);
160 static void pcn_reset(struct pcn_softc *);
161 static int pcn_list_rx_init(struct pcn_softc *);
162 static int pcn_list_tx_init(struct pcn_softc *);
164 #ifdef PCN_USEIOSPACE
165 #define PCN_RES SYS_RES_IOPORT
166 #define PCN_RID PCN_PCI_LOIO
168 #define PCN_RES SYS_RES_MEMORY
169 #define PCN_RID PCN_PCI_LOMEM
172 static device_method_t pcn_methods[] = {
173 /* Device interface */
174 DEVMETHOD(device_probe, pcn_probe),
175 DEVMETHOD(device_attach, pcn_attach),
176 DEVMETHOD(device_detach, pcn_detach),
177 DEVMETHOD(device_shutdown, pcn_shutdown),
180 DEVMETHOD(bus_print_child, bus_generic_print_child),
181 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
184 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
185 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
186 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
191 static driver_t pcn_driver = {
194 sizeof(struct pcn_softc)
197 static devclass_t pcn_devclass;
199 DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0);
200 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
202 #define PCN_CSR_SETBIT(sc, reg, x) \
203 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
205 #define PCN_CSR_CLRBIT(sc, reg, x) \
206 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
208 #define PCN_BCR_SETBIT(sc, reg, x) \
209 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
211 #define PCN_BCR_CLRBIT(sc, reg, x) \
212 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
215 pcn_csr_read(sc, reg)
216 struct pcn_softc *sc;
219 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
220 return(CSR_READ_4(sc, PCN_IO32_RDP));
224 pcn_csr_read16(sc, reg)
225 struct pcn_softc *sc;
228 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
229 return(CSR_READ_2(sc, PCN_IO16_RDP));
233 pcn_csr_write(sc, reg, val)
234 struct pcn_softc *sc;
238 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
239 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
244 pcn_bcr_read(sc, reg)
245 struct pcn_softc *sc;
248 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
249 return(CSR_READ_4(sc, PCN_IO32_BDP));
253 pcn_bcr_read16(sc, reg)
254 struct pcn_softc *sc;
257 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
258 return(CSR_READ_2(sc, PCN_IO16_BDP));
262 pcn_bcr_write(sc, reg, val)
263 struct pcn_softc *sc;
267 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
268 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
273 pcn_miibus_readreg(dev, phy, reg)
277 struct pcn_softc *sc;
280 sc = device_get_softc(dev);
282 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
285 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
286 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
290 sc->pcn_phyaddr = phy;
296 pcn_miibus_writereg(dev, phy, reg, data)
300 struct pcn_softc *sc;
302 sc = device_get_softc(dev);
304 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
305 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
311 pcn_miibus_statchg(dev)
314 struct pcn_softc *sc;
315 struct mii_data *mii;
317 sc = device_get_softc(dev);
318 mii = device_get_softc(sc->pcn_miibus);
320 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
321 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
323 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
331 struct pcn_softc *sc;
334 struct ifmultiaddr *ifma;
336 u_int16_t hashes[4] = { 0, 0, 0, 0 };
340 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
342 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
343 for (i = 0; i < 4; i++)
344 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
345 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
349 /* first, zot all the existing hash bits */
350 for (i = 0; i < 4; i++)
351 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
353 /* now program new ones */
354 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
355 if (ifma->ifma_addr->sa_family != AF_LINK)
357 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
358 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
359 hashes[h >> 4] |= 1 << (h & 0xF);
362 for (i = 0; i < 4; i++)
363 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
365 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
372 struct pcn_softc *sc;
375 * Issue a reset by reading from the RESET register.
376 * Note that we don't know if the chip is operating in
377 * 16-bit or 32-bit mode at this point, so we attempt
378 * to reset the chip both ways. If one fails, the other
381 CSR_READ_2(sc, PCN_IO16_RESET);
382 CSR_READ_4(sc, PCN_IO32_RESET);
384 /* Wait a little while for the chip to get its brains in order. */
387 /* Select 32-bit (DWIO) mode */
388 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
390 /* Select software style 3. */
391 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
397 pcn_chipid_name (u_int32_t id)
399 struct pcn_chipid *p = pcn_chipid;
410 pcn_chip_id (device_t dev)
412 struct pcn_softc *sc;
415 sc = device_get_softc(dev);
417 * Note: we can *NOT* put the chip into
418 * 32-bit mode yet. The lnc driver will only
419 * work in 16-bit mode, and once the chip
420 * goes into 32-bit mode, the only way to
421 * get it out again is with a hardware reset.
422 * So if pcn_probe() is called before the
423 * lnc driver's probe routine, the chip will
424 * be locked into 32-bit operation and the lnc
425 * driver will be unable to attach to it.
426 * Note II: if the chip happens to already
427 * be in 32-bit mode, we still need to check
428 * the chip ID, but first we have to detect
429 * 32-bit mode using only 16-bit operations.
430 * The safest way to do this is to read the
431 * PCI subsystem ID from BCR23/24 and compare
432 * that with the value read from PCI config
435 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
437 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
439 * Note III: the test for 0x10001000 is a hack to
440 * pacify VMware, who's pseudo-PCnet interface is
441 * broken. Reading the subsystem register from PCI
442 * config space yields 0x00000000 while reading the
443 * same value from I/O space yields 0x10001000. It's
444 * not supposed to be that way.
446 if (chip_id == pci_read_config(dev,
447 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
448 /* We're in 16-bit mode. */
449 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
451 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
453 /* We're in 32-bit mode. */
454 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
456 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
462 static struct pcn_type *
463 pcn_match (u_int16_t vid, u_int16_t did)
468 while(t->pcn_name != NULL) {
469 if ((vid == t->pcn_vid) && (did == t->pcn_did))
477 * Probe for an AMD chip. Check the PCI vendor and device
478 * IDs against our list and return a device name if we find a match.
485 struct pcn_softc *sc;
489 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev));
492 sc = device_get_softc(dev);
495 * Temporarily map the I/O space so we can read the chip ID register.
498 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
499 if (sc->pcn_res == NULL) {
500 device_printf(dev, "couldn't map ports/memory\n");
503 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
504 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
506 chip_id = pcn_chip_id(dev);
508 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
510 switch((chip_id >> 12) & PART_MASK) {
521 device_set_desc(dev, t->pcn_name);
522 return(BUS_PROBE_DEFAULT);
526 * Attach the interface. Allocate softc structures, do ifmedia
527 * setup and ethernet/BPF attach.
534 struct pcn_softc *sc;
536 int unit, error = 0, rid;
538 sc = device_get_softc(dev);
539 unit = device_get_unit(dev);
541 /* Initialize our mutex. */
542 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
543 MTX_DEF | MTX_RECURSE);
545 * Map control/status registers.
547 pci_enable_busmaster(dev);
549 /* Retrieve the chip ID */
550 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK;
551 device_printf(dev, "Chip ID %04x (%s)\n",
552 sc->pcn_type, pcn_chipid_name(sc->pcn_type));
555 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
557 if (sc->pcn_res == NULL) {
558 printf("pcn%d: couldn't map ports/memory\n", unit);
563 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
564 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
566 /* Allocate interrupt */
568 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
569 RF_SHAREABLE | RF_ACTIVE);
571 if (sc->pcn_irq == NULL) {
572 printf("pcn%d: couldn't map interrupt\n", unit);
577 /* Reset the adapter. */
581 * Get station address from the EEPROM.
583 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00);
584 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01);
587 callout_handle_init(&sc->pcn_stat_ch);
589 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
590 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
592 if (sc->pcn_ldata == NULL) {
593 printf("pcn%d: no memory for list buffers!\n", unit);
597 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
599 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER);
601 printf("pcn%d: can not if_alloc()\n", unit);
606 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
607 ifp->if_mtu = ETHERMTU;
608 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
610 ifp->if_ioctl = pcn_ioctl;
611 ifp->if_start = pcn_start;
612 ifp->if_watchdog = pcn_watchdog;
613 ifp->if_init = pcn_init;
614 ifp->if_baudrate = 10000000;
615 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1;
620 if (mii_phy_probe(dev, &sc->pcn_miibus,
621 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
622 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
629 * Call MI attach routine.
631 ether_ifattach(ifp, (u_int8_t *) eaddr);
633 /* Hook interrupt last to avoid having to lock softc */
634 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET,
635 pcn_intr, sc, &sc->pcn_intrhand);
638 printf("pcn%d: couldn't set up irq\n", unit);
651 * Shutdown hardware and free up resources. This can be called any
652 * time after the mutex has been initialized. It is called in both
653 * the error case in attach and the normal detach case so it needs
654 * to be careful about only freeing resources that have actually been
661 struct pcn_softc *sc;
664 sc = device_get_softc(dev);
667 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized"));
670 /* These should only be active if attach succeeded */
671 if (device_is_attached(dev)) {
678 device_delete_child(dev, sc->pcn_miibus);
679 bus_generic_detach(dev);
681 if (sc->pcn_intrhand)
682 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
686 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
689 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
694 mtx_destroy(&sc->pcn_mtx);
700 * Initialize the transmit descriptors.
704 struct pcn_softc *sc;
706 struct pcn_list_data *ld;
707 struct pcn_ring_data *cd;
713 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
714 cd->pcn_tx_chain[i] = NULL;
715 ld->pcn_tx_list[i].pcn_tbaddr = 0;
716 ld->pcn_tx_list[i].pcn_txctl = 0;
717 ld->pcn_tx_list[i].pcn_txstat = 0;
720 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
727 * Initialize the RX descriptors and allocate mbufs for them.
731 struct pcn_softc *sc;
733 struct pcn_ring_data *cd;
738 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
739 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
749 * Initialize an RX descriptor and attach an MBUF cluster.
752 pcn_newbuf(sc, idx, m)
753 struct pcn_softc *sc;
757 struct mbuf *m_new = NULL;
758 struct pcn_rx_desc *c;
760 c = &sc->pcn_ldata->pcn_rx_list[idx];
763 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
767 MCLGET(m_new, M_DONTWAIT);
768 if (!(m_new->m_flags & M_EXT)) {
772 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
775 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
776 m_new->m_data = m_new->m_ext.ext_buf;
779 m_adj(m_new, ETHER_ALIGN);
781 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
782 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
783 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
784 c->pcn_bufsz |= PCN_RXLEN_MBO;
785 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
791 * A frame has been uploaded: pass the resulting mbuf chain up to
792 * the higher level protocols.
796 struct pcn_softc *sc;
800 struct pcn_rx_desc *cur_rx;
806 i = sc->pcn_cdata.pcn_rx_prod;
808 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
809 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
810 m = sc->pcn_cdata.pcn_rx_chain[i];
811 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
814 * If an error occurs, update stats, clear the
815 * status word and leave the mbuf cluster in place:
816 * it should simply get re-used next time this descriptor
817 * comes up in the ring.
819 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
821 pcn_newbuf(sc, i, m);
822 PCN_INC(i, PCN_RX_LIST_CNT);
826 if (pcn_newbuf(sc, i, NULL)) {
827 /* Ran out of mbufs; recycle this one. */
828 pcn_newbuf(sc, i, m);
830 PCN_INC(i, PCN_RX_LIST_CNT);
834 PCN_INC(i, PCN_RX_LIST_CNT);
836 /* No errors; receive the packet. */
838 m->m_len = m->m_pkthdr.len =
839 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
840 m->m_pkthdr.rcvif = ifp;
843 (*ifp->if_input)(ifp, m);
847 sc->pcn_cdata.pcn_rx_prod = i;
853 * A frame was downloaded to the chip. It's safe for us to clean up
859 struct pcn_softc *sc;
861 struct pcn_tx_desc *cur_tx = NULL;
868 * Go through our tx list and free mbufs for those
869 * frames that have been transmitted.
871 idx = sc->pcn_cdata.pcn_tx_cons;
872 while (idx != sc->pcn_cdata.pcn_tx_prod) {
873 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
875 if (!PCN_OWN_TXDESC(cur_tx))
878 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
879 sc->pcn_cdata.pcn_tx_cnt--;
880 PCN_INC(idx, PCN_TX_LIST_CNT);
884 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
886 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
887 ifp->if_collisions++;
888 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
889 ifp->if_collisions++;
892 ifp->if_collisions +=
893 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
896 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
897 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
898 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
901 sc->pcn_cdata.pcn_tx_cnt--;
902 PCN_INC(idx, PCN_TX_LIST_CNT);
905 if (idx != sc->pcn_cdata.pcn_tx_cons) {
906 /* Some buffers have been freed. */
907 sc->pcn_cdata.pcn_tx_cons = idx;
908 ifp->if_flags &= ~IFF_OACTIVE;
910 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
919 struct pcn_softc *sc;
920 struct mii_data *mii;
927 mii = device_get_softc(sc->pcn_miibus);
931 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
934 /* link just came up, restart */
935 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE &&
936 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
938 if (ifp->if_snd.ifq_head != NULL)
942 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
953 struct pcn_softc *sc;
960 /* Suppress unwanted interrupts */
961 if (!(ifp->if_flags & IFF_UP)) {
968 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
970 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
971 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
973 if (status & PCN_CSR_RINT)
976 if (status & PCN_CSR_TINT)
979 if (status & PCN_CSR_ERR) {
985 if (ifp->if_snd.ifq_head != NULL)
993 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
994 * pointers to the fragment pointers.
997 pcn_encap(sc, m_head, txidx)
998 struct pcn_softc *sc;
1002 struct pcn_tx_desc *f = NULL;
1004 int frag, cur, cnt = 0;
1007 * Start packing the mbufs in this chain into
1008 * the fragment pointers. Stop when we run out
1009 * of fragments or hit the end of the mbuf chain.
1012 cur = frag = *txidx;
1014 for (m = m_head; m != NULL; m = m->m_next) {
1018 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
1020 f = &sc->pcn_ldata->pcn_tx_list[frag];
1021 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
1022 f->pcn_txctl |= PCN_TXCTL_MBO;
1023 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
1025 f->pcn_txctl |= PCN_TXCTL_STP;
1027 f->pcn_txctl |= PCN_TXCTL_OWN;
1029 PCN_INC(frag, PCN_TX_LIST_CNT);
1036 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1037 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1038 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1039 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1040 sc->pcn_cdata.pcn_tx_cnt += cnt;
1047 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1048 * to the mbuf data regions directly in the transmit lists. We also save a
1049 * copy of the pointers since the transmit list fragment pointers are
1050 * physical addresses.
1056 struct pcn_softc *sc;
1057 struct mbuf *m_head = NULL;
1064 if (!sc->pcn_link) {
1069 idx = sc->pcn_cdata.pcn_tx_prod;
1071 if (ifp->if_flags & IFF_OACTIVE) {
1076 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1077 IF_DEQUEUE(&ifp->if_snd, m_head);
1081 if (pcn_encap(sc, m_head, &idx)) {
1082 IF_PREPEND(&ifp->if_snd, m_head);
1083 ifp->if_flags |= IFF_OACTIVE;
1088 * If there's a BPF listener, bounce a copy of this frame
1091 BPF_MTAP(ifp, m_head);
1096 sc->pcn_cdata.pcn_tx_prod = idx;
1097 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1100 * Set a timeout in case the chip goes out to lunch.
1113 struct pcn_softc *sc;
1117 /* If we want promiscuous mode, set the allframes bit. */
1118 if (ifp->if_flags & IFF_PROMISC) {
1119 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1121 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1124 /* Set the capture broadcast bit to capture broadcast frames. */
1125 if (ifp->if_flags & IFF_BROADCAST) {
1126 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1128 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1138 struct pcn_softc *sc = xsc;
1139 struct ifnet *ifp = sc->pcn_ifp;
1140 struct mii_data *mii = NULL;
1145 * Cancel pending I/O and free all RX/TX buffers.
1150 mii = device_get_softc(sc->pcn_miibus);
1152 /* Set MAC address */
1153 pcn_csr_write(sc, PCN_CSR_PAR0,
1154 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[0]);
1155 pcn_csr_write(sc, PCN_CSR_PAR1,
1156 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[1]);
1157 pcn_csr_write(sc, PCN_CSR_PAR2,
1158 ((u_int16_t *)IFP2ENADDR(sc->pcn_ifp))[2]);
1160 /* Init circular RX list. */
1161 if (pcn_list_rx_init(sc) == ENOBUFS) {
1162 printf("pcn%d: initialization failed: no "
1163 "memory for rx buffers\n", sc->pcn_unit);
1170 * Init tx descriptors.
1172 pcn_list_tx_init(sc);
1174 /* Set up the mode register. */
1175 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1177 /* Set up RX filter. */
1181 * Load the multicast filter.
1186 * Load the addresses of the RX and TX lists.
1188 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1189 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1190 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1191 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1192 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1193 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1194 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1195 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1197 /* Set the RX and TX ring sizes. */
1198 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1199 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1201 /* We're not using the initialization block. */
1202 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1204 /* Enable fast suspend mode. */
1205 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1208 * Enable burst read and write. Also set the no underflow
1209 * bit. This will avoid transmit underruns in certain
1210 * conditions while still providing decent performance.
1212 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1213 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1215 /* Enable graceful recovery from underflow. */
1216 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1218 /* Enable auto-padding of short TX frames. */
1219 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1221 /* Disable MII autoneg (we handle this ourselves). */
1222 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1224 if (sc->pcn_type == Am79C978)
1225 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1226 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1228 /* Enable interrupts and start the controller running. */
1229 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1233 ifp->if_flags |= IFF_RUNNING;
1234 ifp->if_flags &= ~IFF_OACTIVE;
1236 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz);
1243 * Set media options.
1246 pcn_ifmedia_upd(ifp)
1249 struct pcn_softc *sc;
1250 struct mii_data *mii;
1253 mii = device_get_softc(sc->pcn_miibus);
1256 if (mii->mii_instance) {
1257 struct mii_softc *miisc;
1258 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1259 mii_phy_reset(miisc);
1267 * Report current media status.
1270 pcn_ifmedia_sts(ifp, ifmr)
1272 struct ifmediareq *ifmr;
1274 struct pcn_softc *sc;
1275 struct mii_data *mii;
1279 mii = device_get_softc(sc->pcn_miibus);
1281 ifmr->ifm_active = mii->mii_media_active;
1282 ifmr->ifm_status = mii->mii_media_status;
1288 pcn_ioctl(ifp, command, data)
1293 struct pcn_softc *sc = ifp->if_softc;
1294 struct ifreq *ifr = (struct ifreq *) data;
1295 struct mii_data *mii = NULL;
1302 if (ifp->if_flags & IFF_UP) {
1303 if (ifp->if_flags & IFF_RUNNING &&
1304 ifp->if_flags & IFF_PROMISC &&
1305 !(sc->pcn_if_flags & IFF_PROMISC)) {
1306 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1309 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1311 pcn_csr_write(sc, PCN_CSR_CSR,
1312 PCN_CSR_INTEN|PCN_CSR_START);
1313 } else if (ifp->if_flags & IFF_RUNNING &&
1314 !(ifp->if_flags & IFF_PROMISC) &&
1315 sc->pcn_if_flags & IFF_PROMISC) {
1316 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1319 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1321 pcn_csr_write(sc, PCN_CSR_CSR,
1322 PCN_CSR_INTEN|PCN_CSR_START);
1323 } else if (!(ifp->if_flags & IFF_RUNNING))
1326 if (ifp->if_flags & IFF_RUNNING)
1329 sc->pcn_if_flags = ifp->if_flags;
1339 mii = device_get_softc(sc->pcn_miibus);
1340 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1343 error = ether_ioctl(ifp, command, data);
1356 struct pcn_softc *sc;
1363 printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
1369 if (ifp->if_snd.ifq_head != NULL)
1378 * Stop the adapter and free any mbufs allocated to the
1383 struct pcn_softc *sc;
1392 untimeout(pcn_tick, sc, sc->pcn_stat_ch);
1394 /* Turn off interrupts */
1395 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN);
1397 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1401 * Free data in the RX lists.
1403 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1404 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1405 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1406 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1409 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1410 sizeof(sc->pcn_ldata->pcn_rx_list));
1413 * Free the TX list buffers.
1415 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1416 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1417 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1418 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1422 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1423 sizeof(sc->pcn_ldata->pcn_tx_list));
1425 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1432 * Stop all chip I/O so that the kernel's probe routines don't
1433 * get confused by errant DMAs when rebooting.
1439 struct pcn_softc *sc;
1441 sc = device_get_softc(dev);