sys/pci/if_rl.c

   1 /*-
   2  * Copyright (c) 1997, 1998
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * RealTek 8129/8139 PCI NIC driver
  38  *
  39  * Supports several extremely cheap PCI 10/100 adapters based on
  40  * the RealTek chipset. Datasheets can be obtained from
  41  * www.realtek.com.tw.
  42  *
  43  * Written by Bill Paul <wpaul@ctr.columbia.edu>
  44  * Electrical Engineering Department
  45  * Columbia University, New York City
  46  */
  47 /*
  48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
  49  * probably the worst PCI ethernet controller ever made, with the possible
  50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
  51  * DMA, but it has a terrible interface that nullifies any performance
  52  * gains that bus-master DMA usually offers.
  53  *
  54  * For transmission, the chip offers a series of four TX descriptor
  55  * registers. Each transmit frame must be in a contiguous buffer, aligned
  56  * on a longword (32-bit) boundary. This means we almost always have to
  57  * do mbuf copies in order to transmit a frame, except in the unlikely
  58  * case where a) the packet fits into a single mbuf, and b) the packet
  59  * is 32-bit aligned within the mbuf's data area. The presence of only
  60  * four descriptor registers means that we can never have more than four
  61  * packets queued for transmission at any one time.
  62  *
  63  * Reception is not much better. The driver has to allocate a single large
  64  * buffer area (up to 64K in size) into which the chip will DMA received
  65  * frames. Because we don't know where within this region received packets
  66  * will begin or end, we have no choice but to copy data from the buffer
  67  * area into mbufs in order to pass the packets up to the higher protocol
  68  * levels.
  69  *
  70  * It's impossible given this rotten design to really achieve decent
  71  * performance at 100Mbps, unless you happen to have a 400Mhz PII or
  72  * some equally overmuscled CPU to drive it.
  73  *
  74  * On the bright side, the 8139 does have a built-in PHY, although
  75  * rather than using an MDIO serial interface like most other NICs, the
  76  * PHY registers are directly accessible through the 8139's register
  77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
  78  * filter.
  79  *
  80  * The 8129 chip is an older version of the 8139 that uses an external PHY
  81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
  82  * the 8139 lets you directly access the on-board PHY registers. We need
  83  * to select which interface to use depending on the chip type.
  84  */
  85
  86 #ifdef HAVE_KERNEL_OPTION_HEADERS
  87 #include "opt_device_polling.h"
  88 #endif
  89
  90 #include <sys/param.h>
  91 #include <sys/endian.h>
  92 #include <sys/systm.h>
  93 #include <sys/sockio.h>
  94 #include <sys/mbuf.h>
  95 #include <sys/malloc.h>
  96 #include <sys/kernel.h>
  97 #include <sys/module.h>
  98 #include <sys/socket.h>
  99 #include <sys/sysctl.h>
 100
 101 #include <net/if.h>
 102 #include <net/if_arp.h>
 103 #include <net/ethernet.h>
 104 #include <net/if_dl.h>
 105 #include <net/if_media.h>
 106 #include <net/if_types.h>
 107
 108 #include <net/bpf.h>
 109
 110 #include <machine/bus.h>
 111 #include <machine/resource.h>
 112 #include <sys/bus.h>
 113 #include <sys/rman.h>
 114
 115 #include <dev/mii/mii.h>
 116 #include <dev/mii/miivar.h>
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 MODULE_DEPEND(rl, pci, 1, 1, 1);
 122 MODULE_DEPEND(rl, ether, 1, 1, 1);
 123 MODULE_DEPEND(rl, miibus, 1, 1, 1);
 124
 125 /* "device miibus" required.  See GENERIC if you get errors here. */
 126 #include "miibus_if.h"
 127
 128 /*
 129  * Default to using PIO access for this driver. On SMP systems,
 130  * there appear to be problems with memory mapped mode: it looks like
 131  * doing too many memory mapped access back to back in rapid succession
 132  * can hang the bus. I'm inclined to blame this on crummy design/construction
 133  * on the part of RealTek. Memory mapped mode does appear to work on
 134  * uniprocessor systems though.
 135  */
 136 #define RL_USEIOSPACE
 137
 138 #include <pci/if_rlreg.h>
 139
 140 /*
 141  * Various supported device vendors/types and their names.
 142  */
 143 static struct rl_type rl_devs[] = {
 144         { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
 145                 "RealTek 8129 10/100BaseTX" },
 146         { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
 147                 "RealTek 8139 10/100BaseTX" },
 148         { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
 149                 "RealTek 8139 10/100BaseTX" },
 150         { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
 151                 "RealTek 8139 10/100BaseTX CardBus" },
 152         { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
 153                 "RealTek 8100 10/100BaseTX" },
 154         { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
 155                 "Accton MPX 5030/5038 10/100BaseTX" },
 156         { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
 157                 "Delta Electronics 8139 10/100BaseTX" },
 158         { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
 159                 "Addtron Technology 8139 10/100BaseTX" },
 160         { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
 161                 "D-Link DFE-530TX+ 10/100BaseTX" },
 162         { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
 163                 "D-Link DFE-690TXD 10/100BaseTX" },
 164         { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
 165                 "Nortel Networks 10/100BaseTX" },
 166         { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
 167                 "Corega FEther CB-TXD" },
 168         { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
 169                 "Corega FEtherII CB-TXD" },
 170         { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
 171                 "Peppercon AG ROL-F" },
 172         { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
 173                 "Planex FNW-3603-TX" },
 174         { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
 175                 "Planex FNW-3800-TX" },
 176         { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
 177                 "Compaq HNE-300" },
 178         { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
 179                 "LevelOne FPC-0106TX" },
 180         { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
 181                 "Edimax EP-4103DL CardBus" }
 182 };
 183
 184 static int rl_attach(device_t);
 185 static int rl_detach(device_t);
 186 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 187 static int rl_dma_alloc(struct rl_softc *);
 188 static void rl_dma_free(struct rl_softc *);
 189 static void rl_eeprom_putbyte(struct rl_softc *, int);
 190 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
 191 static int rl_encap(struct rl_softc *, struct mbuf **);
 192 static int rl_list_tx_init(struct rl_softc *);
 193 static int rl_list_rx_init(struct rl_softc *);
 194 static int rl_ifmedia_upd(struct ifnet *);
 195 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 196 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
 197 static void rl_intr(void *);
 198 static void rl_init(void *);
 199 static void rl_init_locked(struct rl_softc *sc);
 200 static void rl_mii_send(struct rl_softc *, uint32_t, int);
 201 static void rl_mii_sync(struct rl_softc *);
 202 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
 203 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
 204 static int rl_miibus_readreg(device_t, int, int);
 205 static void rl_miibus_statchg(device_t);
 206 static int rl_miibus_writereg(device_t, int, int, int);
 207 #ifdef DEVICE_POLLING
 208 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 209 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
 210 #endif
 211 static int rl_probe(device_t);
 212 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
 213 static void rl_reset(struct rl_softc *);
 214 static int rl_resume(device_t);
 215 static void rl_rxeof(struct rl_softc *);
 216 static void rl_setmulti(struct rl_softc *);
 217 static int rl_shutdown(device_t);
 218 static void rl_start(struct ifnet *);
 219 static void rl_start_locked(struct ifnet *);
 220 static void rl_stop(struct rl_softc *);
 221 static int rl_suspend(device_t);
 222 static void rl_tick(void *);
 223 static void rl_txeof(struct rl_softc *);
 224 static void rl_watchdog(struct rl_softc *);
 225
 226 #ifdef RL_USEIOSPACE
 227 #define RL_RES                  SYS_RES_IOPORT
 228 #define RL_RID                  RL_PCI_LOIO
 229 #else
 230 #define RL_RES                  SYS_RES_MEMORY
 231 #define RL_RID                  RL_PCI_LOMEM
 232 #endif
 233
 234 static device_method_t rl_methods[] = {
 235         /* Device interface */
 236         DEVMETHOD(device_probe,         rl_probe),
 237         DEVMETHOD(device_attach,        rl_attach),
 238         DEVMETHOD(device_detach,        rl_detach),
 239         DEVMETHOD(device_suspend,       rl_suspend),
 240         DEVMETHOD(device_resume,        rl_resume),
 241         DEVMETHOD(device_shutdown,      rl_shutdown),
 242
 243         /* bus interface */
 244         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 245         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 246
 247         /* MII interface */
 248         DEVMETHOD(miibus_readreg,       rl_miibus_readreg),
 249         DEVMETHOD(miibus_writereg,      rl_miibus_writereg),
 250         DEVMETHOD(miibus_statchg,       rl_miibus_statchg),
 251
 252         { 0, 0 }
 253 };
 254
 255 static driver_t rl_driver = {
 256         "rl",
 257         rl_methods,
 258         sizeof(struct rl_softc)
 259 };
 260
 261 static devclass_t rl_devclass;
 262
 263 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
 264 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
 265 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
 266
 267 #define EE_SET(x)                                       \
 268         CSR_WRITE_1(sc, RL_EECMD,                       \
 269                 CSR_READ_1(sc, RL_EECMD) | x)
 270
 271 #define EE_CLR(x)                                       \
 272         CSR_WRITE_1(sc, RL_EECMD,                       \
 273                 CSR_READ_1(sc, RL_EECMD) & ~x)
 274
 275 /*
 276  * Send a read command and address to the EEPROM, check for ACK.
 277  */
 278 static void
 279 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
 280 {
 281         register int            d, i;
 282
 283         d = addr | sc->rl_eecmd_read;
 284
 285         /*
 286          * Feed in each bit and strobe the clock.
 287          */
 288         for (i = 0x400; i; i >>= 1) {
 289                 if (d & i) {
 290                         EE_SET(RL_EE_DATAIN);
 291                 } else {
 292                         EE_CLR(RL_EE_DATAIN);
 293                 }
 294                 DELAY(100);
 295                 EE_SET(RL_EE_CLK);
 296                 DELAY(150);
 297                 EE_CLR(RL_EE_CLK);
 298                 DELAY(100);
 299         }
 300 }
 301
 302 /*
 303  * Read a word of data stored in the EEPROM at address 'addr.'
 304  */
 305 static void
 306 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
 307 {
 308         register int            i;
 309         uint16_t                word = 0;
 310
 311         /* Enter EEPROM access mode. */
 312         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 313
 314         /*
 315          * Send address of word we want to read.
 316          */
 317         rl_eeprom_putbyte(sc, addr);
 318
 319         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 320
 321         /*
 322          * Start reading bits from EEPROM.
 323          */
 324         for (i = 0x8000; i; i >>= 1) {
 325                 EE_SET(RL_EE_CLK);
 326                 DELAY(100);
 327                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
 328                         word |= i;
 329                 EE_CLR(RL_EE_CLK);
 330                 DELAY(100);
 331         }
 332
 333         /* Turn off EEPROM access mode. */
 334         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 335
 336         *dest = word;
 337 }
 338
 339 /*
 340  * Read a sequence of words from the EEPROM.
 341  */
 342 static void
 343 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
 344 {
 345         int                     i;
 346         uint16_t                word = 0, *ptr;
 347
 348         for (i = 0; i < cnt; i++) {
 349                 rl_eeprom_getword(sc, off + i, &word);
 350                 ptr = (uint16_t *)(dest + (i * 2));
 351                 if (swap)
 352                         *ptr = ntohs(word);
 353                 else
 354                         *ptr = word;
 355         }
 356 }
 357
 358 /*
 359  * MII access routines are provided for the 8129, which
 360  * doesn't have a built-in PHY. For the 8139, we fake things
 361  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
 362  * direct access PHY registers.
 363  */
 364 #define MII_SET(x)                                      \
 365         CSR_WRITE_1(sc, RL_MII,                         \
 366                 CSR_READ_1(sc, RL_MII) | (x))
 367
 368 #define MII_CLR(x)                                      \
 369         CSR_WRITE_1(sc, RL_MII,                         \
 370                 CSR_READ_1(sc, RL_MII) & ~(x))
 371
 372 /*
 373  * Sync the PHYs by setting data bit and strobing the clock 32 times.
 374  */
 375 static void
 376 rl_mii_sync(struct rl_softc *sc)
 377 {
 378         register int            i;
 379
 380         MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
 381
 382         for (i = 0; i < 32; i++) {
 383                 MII_SET(RL_MII_CLK);
 384                 DELAY(1);
 385                 MII_CLR(RL_MII_CLK);
 386                 DELAY(1);
 387         }
 388 }
 389
 390 /*
 391  * Clock a series of bits through the MII.
 392  */
 393 static void
 394 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
 395 {
 396         int                     i;
 397
 398         MII_CLR(RL_MII_CLK);
 399
 400         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
 401                 if (bits & i) {
 402                         MII_SET(RL_MII_DATAOUT);
 403                 } else {
 404                         MII_CLR(RL_MII_DATAOUT);
 405                 }
 406                 DELAY(1);
 407                 MII_CLR(RL_MII_CLK);
 408                 DELAY(1);
 409                 MII_SET(RL_MII_CLK);
 410         }
 411 }
 412
 413 /*
 414  * Read an PHY register through the MII.
 415  */
 416 static int
 417 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
 418 {
 419         int                     i, ack;
 420
 421         /* Set up frame for RX. */
 422         frame->mii_stdelim = RL_MII_STARTDELIM;
 423         frame->mii_opcode = RL_MII_READOP;
 424         frame->mii_turnaround = 0;
 425         frame->mii_data = 0;
 426
 427         CSR_WRITE_2(sc, RL_MII, 0);
 428
 429         /* Turn on data xmit. */
 430         MII_SET(RL_MII_DIR);
 431
 432         rl_mii_sync(sc);
 433
 434         /* Send command/address info. */
 435         rl_mii_send(sc, frame->mii_stdelim, 2);
 436         rl_mii_send(sc, frame->mii_opcode, 2);
 437         rl_mii_send(sc, frame->mii_phyaddr, 5);
 438         rl_mii_send(sc, frame->mii_regaddr, 5);
 439
 440         /* Idle bit */
 441         MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
 442         DELAY(1);
 443         MII_SET(RL_MII_CLK);
 444         DELAY(1);
 445
 446         /* Turn off xmit. */
 447         MII_CLR(RL_MII_DIR);
 448
 449         /* Check for ack */
 450         MII_CLR(RL_MII_CLK);
 451         DELAY(1);
 452         ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
 453         MII_SET(RL_MII_CLK);
 454         DELAY(1);
 455
 456         /*
 457          * Now try reading data bits. If the ack failed, we still
 458          * need to clock through 16 cycles to keep the PHY(s) in sync.
 459          */
 460         if (ack) {
 461                 for(i = 0; i < 16; i++) {
 462                         MII_CLR(RL_MII_CLK);
 463                         DELAY(1);
 464                         MII_SET(RL_MII_CLK);
 465                         DELAY(1);
 466                 }
 467                 goto fail;
 468         }
 469
 470         for (i = 0x8000; i; i >>= 1) {
 471                 MII_CLR(RL_MII_CLK);
 472                 DELAY(1);
 473                 if (!ack) {
 474                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
 475                                 frame->mii_data |= i;
 476                         DELAY(1);
 477                 }
 478                 MII_SET(RL_MII_CLK);
 479                 DELAY(1);
 480         }
 481
 482 fail:
 483         MII_CLR(RL_MII_CLK);
 484         DELAY(1);
 485         MII_SET(RL_MII_CLK);
 486         DELAY(1);
 487
 488         return (ack ? 1 : 0);
 489 }
 490
 491 /*
 492  * Write to a PHY register through the MII.
 493  */
 494 static int
 495 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
 496 {
 497
 498         /* Set up frame for TX. */
 499         frame->mii_stdelim = RL_MII_STARTDELIM;
 500         frame->mii_opcode = RL_MII_WRITEOP;
 501         frame->mii_turnaround = RL_MII_TURNAROUND;
 502
 503         /* Turn on data output. */
 504         MII_SET(RL_MII_DIR);
 505
 506         rl_mii_sync(sc);
 507
 508         rl_mii_send(sc, frame->mii_stdelim, 2);
 509         rl_mii_send(sc, frame->mii_opcode, 2);
 510         rl_mii_send(sc, frame->mii_phyaddr, 5);
 511         rl_mii_send(sc, frame->mii_regaddr, 5);
 512         rl_mii_send(sc, frame->mii_turnaround, 2);
 513         rl_mii_send(sc, frame->mii_data, 16);
 514
 515         /* Idle bit. */
 516         MII_SET(RL_MII_CLK);
 517         DELAY(1);
 518         MII_CLR(RL_MII_CLK);
 519         DELAY(1);
 520
 521         /* Turn off xmit. */
 522         MII_CLR(RL_MII_DIR);
 523
 524         return (0);
 525 }
 526
 527 static int
 528 rl_miibus_readreg(device_t dev, int phy, int reg)
 529 {
 530         struct rl_softc         *sc;
 531         struct rl_mii_frame     frame;
 532         uint16_t                rval = 0;
 533         uint16_t                rl8139_reg = 0;
 534
 535         sc = device_get_softc(dev);
 536
 537         if (sc->rl_type == RL_8139) {
 538                 /* Pretend the internal PHY is only at address 0 */
 539                 if (phy) {
 540                         return (0);
 541                 }
 542                 switch (reg) {
 543                 case MII_BMCR:
 544                         rl8139_reg = RL_BMCR;
 545                         break;
 546                 case MII_BMSR:
 547                         rl8139_reg = RL_BMSR;
 548                         break;
 549                 case MII_ANAR:
 550                         rl8139_reg = RL_ANAR;
 551                         break;
 552                 case MII_ANER:
 553                         rl8139_reg = RL_ANER;
 554                         break;
 555                 case MII_ANLPAR:
 556                         rl8139_reg = RL_LPAR;
 557                         break;
 558                 case MII_PHYIDR1:
 559                 case MII_PHYIDR2:
 560                         return (0);
 561                 /*
 562                  * Allow the rlphy driver to read the media status
 563                  * register. If we have a link partner which does not
 564                  * support NWAY, this is the register which will tell
 565                  * us the results of parallel detection.
 566                  */
 567                 case RL_MEDIASTAT:
 568                         rval = CSR_READ_1(sc, RL_MEDIASTAT);
 569                         return (rval);
 570                 default:
 571                         device_printf(sc->rl_dev, "bad phy register\n");
 572                         return (0);
 573                 }
 574                 rval = CSR_READ_2(sc, rl8139_reg);
 575                 return (rval);
 576         }
 577
 578         bzero((char *)&frame, sizeof(frame));
 579         frame.mii_phyaddr = phy;
 580         frame.mii_regaddr = reg;
 581         rl_mii_readreg(sc, &frame);
 582
 583         return (frame.mii_data);
 584 }
 585
 586 static int
 587 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
 588 {
 589         struct rl_softc         *sc;
 590         struct rl_mii_frame     frame;
 591         uint16_t                rl8139_reg = 0;
 592
 593         sc = device_get_softc(dev);
 594
 595         if (sc->rl_type == RL_8139) {
 596                 /* Pretend the internal PHY is only at address 0 */
 597                 if (phy) {
 598                         return (0);
 599                 }
 600                 switch (reg) {
 601                 case MII_BMCR:
 602                         rl8139_reg = RL_BMCR;
 603                         break;
 604                 case MII_BMSR:
 605                         rl8139_reg = RL_BMSR;
 606                         break;
 607                 case MII_ANAR:
 608                         rl8139_reg = RL_ANAR;
 609                         break;
 610                 case MII_ANER:
 611                         rl8139_reg = RL_ANER;
 612                         break;
 613                 case MII_ANLPAR:
 614                         rl8139_reg = RL_LPAR;
 615                         break;
 616                 case MII_PHYIDR1:
 617                 case MII_PHYIDR2:
 618                         return (0);
 619                         break;
 620                 default:
 621                         device_printf(sc->rl_dev, "bad phy register\n");
 622                         return (0);
 623                 }
 624                 CSR_WRITE_2(sc, rl8139_reg, data);
 625                 return (0);
 626         }
 627
 628         bzero((char *)&frame, sizeof(frame));
 629         frame.mii_phyaddr = phy;
 630         frame.mii_regaddr = reg;
 631         frame.mii_data = data;
 632         rl_mii_writereg(sc, &frame);
 633
 634         return (0);
 635 }
 636
 637 static void
 638 rl_miibus_statchg(device_t dev)
 639 {
 640         struct rl_softc         *sc;
 641         struct ifnet            *ifp;
 642         struct mii_data         *mii;
 643
 644         sc = device_get_softc(dev);
 645         mii = device_get_softc(sc->rl_miibus);
 646         ifp = sc->rl_ifp;
 647         if (mii == NULL || ifp == NULL ||
 648             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 649                 return;
 650
 651         sc->rl_flags &= ~RL_FLAG_LINK;
 652         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 653             (IFM_ACTIVE | IFM_AVALID)) {
 654                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 655                 case IFM_10_T:
 656                 case IFM_100_TX:
 657                         sc->rl_flags |= RL_FLAG_LINK;
 658                         break;
 659                 default:
 660                         break;
 661                 }
 662         }
 663         /*
 664          * RealTek controllers do not provide any interface to
 665          * Tx/Rx MACs for resolved speed, duplex and flow-control
 666          * parameters.
 667          */
 668 }
 669
 670 /*
 671  * Program the 64-bit multicast hash filter.
 672  */
 673 static void
 674 rl_setmulti(struct rl_softc *sc)
 675 {
 676         struct ifnet            *ifp = sc->rl_ifp;
 677         int                     h = 0;
 678         uint32_t                hashes[2] = { 0, 0 };
 679         struct ifmultiaddr      *ifma;
 680         uint32_t                rxfilt;
 681         int                     mcnt = 0;
 682
 683         RL_LOCK_ASSERT(sc);
 684
 685         rxfilt = CSR_READ_4(sc, RL_RXCFG);
 686
 687         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 688                 rxfilt |= RL_RXCFG_RX_MULTI;
 689                 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 690                 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
 691                 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
 692                 return;
 693         }
 694
 695         /* first, zot all the existing hash bits */
 696         CSR_WRITE_4(sc, RL_MAR0, 0);
 697         CSR_WRITE_4(sc, RL_MAR4, 0);
 698
 699         /* now program new ones */
 700         IF_ADDR_LOCK(ifp);
 701         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 702                 if (ifma->ifma_addr->sa_family != AF_LINK)
 703                         continue;
 704                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 705                     ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
 706                 if (h < 32)
 707                         hashes[0] |= (1 << h);
 708                 else
 709                         hashes[1] |= (1 << (h - 32));
 710                 mcnt++;
 711         }
 712         IF_ADDR_UNLOCK(ifp);
 713
 714         if (mcnt)
 715                 rxfilt |= RL_RXCFG_RX_MULTI;
 716         else
 717                 rxfilt &= ~RL_RXCFG_RX_MULTI;
 718
 719         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 720         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
 721         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
 722 }
 723
 724 static void
 725 rl_reset(struct rl_softc *sc)
 726 {
 727         register int            i;
 728
 729         RL_LOCK_ASSERT(sc);
 730
 731         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
 732
 733         for (i = 0; i < RL_TIMEOUT; i++) {
 734                 DELAY(10);
 735                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
 736                         break;
 737         }
 738         if (i == RL_TIMEOUT)
 739                 device_printf(sc->rl_dev, "reset never completed!\n");
 740 }
 741
 742 /*
 743  * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
 744  * IDs against our list and return a device name if we find a match.
 745  */
 746 static int
 747 rl_probe(device_t dev)
 748 {
 749         struct rl_type          *t;
 750         uint16_t                devid, revid, vendor;
 751         int                     i;
 752
 753         vendor = pci_get_vendor(dev);
 754         devid = pci_get_device(dev);
 755         revid = pci_get_revid(dev);
 756
 757         if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
 758                 if (revid == 0x20) {
 759                         /* 8139C+, let re(4) take care of this device. */
 760                         return (ENXIO);
 761                 }
 762         }
 763         t = rl_devs;
 764         for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
 765                 if (vendor == t->rl_vid && devid == t->rl_did) {
 766                         device_set_desc(dev, t->rl_name);
 767                         return (BUS_PROBE_DEFAULT);
 768                 }
 769         }
 770
 771         return (ENXIO);
 772 }
 773
 774 struct rl_dmamap_arg {
 775         bus_addr_t      rl_busaddr;
 776 };
 777
 778 static void
 779 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 780 {
 781         struct rl_dmamap_arg    *ctx;
 782
 783         if (error != 0)
 784                 return;
 785
 786         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 787
 788         ctx = (struct rl_dmamap_arg *)arg;
 789         ctx->rl_busaddr = segs[0].ds_addr;
 790 }
 791
 792 /*
 793  * Attach the interface. Allocate softc structures, do ifmedia
 794  * setup and ethernet/BPF attach.
 795  */
 796 static int
 797 rl_attach(device_t dev)
 798 {
 799         uint8_t                 eaddr[ETHER_ADDR_LEN];
 800         uint16_t                as[3];
 801         struct ifnet            *ifp;
 802         struct rl_softc         *sc;
 803         struct rl_type          *t;
 804         struct sysctl_ctx_list  *ctx;
 805         struct sysctl_oid_list  *children;
 806         int                     error = 0, i, rid;
 807         int                     unit;
 808         uint16_t                rl_did = 0;
 809         char                    tn[32];
 810
 811         sc = device_get_softc(dev);
 812         unit = device_get_unit(dev);
 813         sc->rl_dev = dev;
 814
 815         sc->rl_twister_enable = 0;
 816         snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
 817         TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
 818         ctx = device_get_sysctl_ctx(sc->rl_dev);
 819         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
 820         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
 821            &sc->rl_twister_enable, 0, "");
 822
 823         mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 824             MTX_DEF);
 825         callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
 826
 827         pci_enable_busmaster(dev);
 828
 829         /* Map control/status registers. */
 830         rid = RL_RID;
 831         sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
 832
 833         if (sc->rl_res == NULL) {
 834                 device_printf(dev, "couldn't map ports/memory\n");
 835                 error = ENXIO;
 836                 goto fail;
 837         }
 838
 839 #ifdef notdef
 840         /*
 841          * Detect the Realtek 8139B. For some reason, this chip is very
 842          * unstable when left to autoselect the media
 843          * The best workaround is to set the device to the required
 844          * media type or to set it to the 10 Meg speed.
 845          */
 846         if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
 847                 device_printf(dev,
 848 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
 849 #endif
 850
 851         sc->rl_btag = rman_get_bustag(sc->rl_res);
 852         sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
 853
 854         /* Allocate interrupt */
 855         rid = 0;
 856         sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 857             RF_SHAREABLE | RF_ACTIVE);
 858
 859         if (sc->rl_irq[0] == NULL) {
 860                 device_printf(dev, "couldn't map interrupt\n");
 861                 error = ENXIO;
 862                 goto fail;
 863         }
 864
 865         /*
 866          * Reset the adapter. Only take the lock here as it's needed in
 867          * order to call rl_reset().
 868          */
 869         RL_LOCK(sc);
 870         rl_reset(sc);
 871         RL_UNLOCK(sc);
 872
 873         sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
 874         rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
 875         if (rl_did != 0x8129)
 876                 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
 877
 878         /*
 879          * Get station address from the EEPROM.
 880          */
 881         rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
 882         for (i = 0; i < 3; i++) {
 883                 eaddr[(i * 2) + 0] = as[i] & 0xff;
 884                 eaddr[(i * 2) + 1] = as[i] >> 8;
 885         }
 886
 887         /*
 888          * Now read the exact device type from the EEPROM to find
 889          * out if it's an 8129 or 8139.
 890          */
 891         rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
 892
 893         t = rl_devs;
 894         sc->rl_type = 0;
 895         while(t->rl_name != NULL) {
 896                 if (rl_did == t->rl_did) {
 897                         sc->rl_type = t->rl_basetype;
 898                         break;
 899                 }
 900                 t++;
 901         }
 902
 903         if (sc->rl_type == 0) {
 904                 device_printf(dev, "unknown device ID: %x\n", rl_did);
 905                 error = ENXIO;
 906                 goto fail;
 907         }
 908
 909         if ((error = rl_dma_alloc(sc)) != 0)
 910                 goto fail;
 911
 912         ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
 913         if (ifp == NULL) {
 914                 device_printf(dev, "can not if_alloc()\n");
 915                 error = ENOSPC;
 916                 goto fail;
 917         }
 918
 919         /* Do MII setup */
 920         if (mii_phy_probe(dev, &sc->rl_miibus,
 921             rl_ifmedia_upd, rl_ifmedia_sts)) {
 922                 device_printf(dev, "MII without any phy!\n");
 923                 error = ENXIO;
 924                 goto fail;
 925         }
 926
 927         ifp->if_softc = sc;
 928         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 929         ifp->if_mtu = ETHERMTU;
 930         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 931         ifp->if_ioctl = rl_ioctl;
 932         ifp->if_start = rl_start;
 933         ifp->if_init = rl_init;
 934         ifp->if_capabilities = IFCAP_VLAN_MTU;
 935         ifp->if_capenable = ifp->if_capabilities;
 936 #ifdef DEVICE_POLLING
 937         ifp->if_capabilities |= IFCAP_POLLING;
 938 #endif
 939         IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
 940         ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
 941         IFQ_SET_READY(&ifp->if_snd);
 942
 943         /*
 944          * Call MI attach routine.
 945          */
 946         ether_ifattach(ifp, eaddr);
 947
 948         /* Hook interrupt last to avoid having to lock softc */
 949         error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
 950             NULL, rl_intr, sc, &sc->rl_intrhand[0]);
 951         if (error) {
 952                 device_printf(sc->rl_dev, "couldn't set up irq\n");
 953                 ether_ifdetach(ifp);
 954         }
 955
 956 fail:
 957         if (error)
 958                 rl_detach(dev);
 959
 960         return (error);
 961 }
 962
 963 /*
 964  * Shutdown hardware and free up resources. This can be called any
 965  * time after the mutex has been initialized. It is called in both
 966  * the error case in attach and the normal detach case so it needs
 967  * to be careful about only freeing resources that have actually been
 968  * allocated.
 969  */
 970 static int
 971 rl_detach(device_t dev)
 972 {
 973         struct rl_softc         *sc;
 974         struct ifnet            *ifp;
 975
 976         sc = device_get_softc(dev);
 977         ifp = sc->rl_ifp;
 978
 979         KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
 980
 981 #ifdef DEVICE_POLLING
 982         if (ifp->if_capenable & IFCAP_POLLING)
 983                 ether_poll_deregister(ifp);
 984 #endif
 985         /* These should only be active if attach succeeded */
 986         if (device_is_attached(dev)) {
 987                 RL_LOCK(sc);
 988                 rl_stop(sc);
 989                 RL_UNLOCK(sc);
 990                 callout_drain(&sc->rl_stat_callout);
 991                 ether_ifdetach(ifp);
 992         }
 993 #if 0
 994         sc->suspended = 1;
 995 #endif
 996         if (sc->rl_miibus)
 997                 device_delete_child(dev, sc->rl_miibus);
 998         bus_generic_detach(dev);
 999
1000         if (sc->rl_intrhand[0])
1001                 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1002         if (sc->rl_irq[0])
1003                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
1004         if (sc->rl_res)
1005                 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1006
1007         if (ifp)
1008                 if_free(ifp);
1009
1010         rl_dma_free(sc);
1011
1012         mtx_destroy(&sc->rl_mtx);
1013
1014         return (0);
1015 }
1016
1017 static int
1018 rl_dma_alloc(struct rl_softc *sc)
1019 {
1020         struct rl_dmamap_arg    ctx;
1021         int                     error, i;
1022
1023         /*
1024          * Allocate the parent bus DMA tag appropriate for PCI.
1025          */
1026         error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
1027             1, 0,                       /* alignment, boundary */
1028             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1029             BUS_SPACE_MAXADDR,          /* highaddr */
1030             NULL, NULL,                 /* filter, filterarg */
1031             BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
1032             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1033             0,                          /* flags */
1034             NULL, NULL,                 /* lockfunc, lockarg */
1035             &sc->rl_parent_tag);
1036         if (error) {
1037                 device_printf(sc->rl_dev,
1038                     "failed to create parent DMA tag.\n");
1039                 goto fail;
1040         }
1041         /* Create DMA tag for Rx memory block. */
1042         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
1043             RL_RX_8139_BUF_ALIGN, 0,    /* alignment, boundary */
1044             BUS_SPACE_MAXADDR,          /* lowaddr */
1045             BUS_SPACE_MAXADDR,          /* highaddr */
1046             NULL, NULL,                 /* filter, filterarg */
1047             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1,   /* maxsize,nsegments */
1048             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ,      /* maxsegsize */
1049             0,                          /* flags */
1050             NULL, NULL,                 /* lockfunc, lockarg */
1051             &sc->rl_cdata.rl_rx_tag);
1052         if (error) {
1053                 device_printf(sc->rl_dev,
1054                     "failed to create Rx memory block DMA tag.\n");
1055                 goto fail;
1056         }
1057         /* Create DMA tag for Tx buffer. */
1058         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
1059             RL_TX_8139_BUF_ALIGN, 0,    /* alignment, boundary */
1060             BUS_SPACE_MAXADDR,          /* lowaddr */
1061             BUS_SPACE_MAXADDR,          /* highaddr */
1062             NULL, NULL,                 /* filter, filterarg */
1063             MCLBYTES, 1,                /* maxsize, nsegments */
1064             MCLBYTES,                   /* maxsegsize */
1065             0,                          /* flags */
1066             NULL, NULL,                 /* lockfunc, lockarg */
1067             &sc->rl_cdata.rl_tx_tag);
1068         if (error) {
1069                 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
1070                 goto fail;
1071         }
1072
1073         /*
1074          * Allocate DMA'able memory and load DMA map for Rx memory block.
1075          */
1076         error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
1077             (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
1078             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
1079         if (error != 0) {
1080                 device_printf(sc->rl_dev,
1081                     "failed to allocate Rx DMA memory block.\n");
1082                 goto fail;
1083         }
1084         ctx.rl_busaddr = 0;
1085         error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
1086             sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
1087             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
1088             BUS_DMA_NOWAIT);
1089         if (error != 0 || ctx.rl_busaddr == 0) {
1090                 device_printf(sc->rl_dev,
1091                     "could not load Rx DMA memory block.\n");
1092                 goto fail;
1093         }
1094         sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
1095
1096         /* Create DMA maps for Tx buffers. */
1097         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1098                 sc->rl_cdata.rl_tx_chain[i] = NULL;
1099                 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1100                 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
1101                     &sc->rl_cdata.rl_tx_dmamap[i]);
1102                 if (error != 0) {
1103                         device_printf(sc->rl_dev,
1104                             "could not create Tx dmamap.\n");
1105                         goto fail;
1106                 }
1107         }
1108
1109         /* Leave a few bytes before the start of the RX ring buffer. */
1110         sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1111         sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1112
1113 fail:
1114         return (error);
1115 }
1116
1117 static void
1118 rl_dma_free(struct rl_softc *sc)
1119 {
1120         int                     i;
1121
1122         /* Rx memory block. */
1123         if (sc->rl_cdata.rl_rx_tag != NULL) {
1124                 if (sc->rl_cdata.rl_rx_dmamap != NULL)
1125                         bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1126                             sc->rl_cdata.rl_rx_dmamap);
1127                 if (sc->rl_cdata.rl_rx_dmamap != NULL &&
1128                     sc->rl_cdata.rl_rx_buf_ptr != NULL)
1129                         bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1130                             sc->rl_cdata.rl_rx_buf_ptr,
1131                             sc->rl_cdata.rl_rx_dmamap);
1132                 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1133                 sc->rl_cdata.rl_rx_buf = NULL;
1134                 sc->rl_cdata.rl_rx_dmamap = NULL;
1135                 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1136                 sc->rl_cdata.rl_tx_tag = NULL;
1137         }
1138
1139         /* Tx buffers. */
1140         if (sc->rl_cdata.rl_tx_tag != NULL) {
1141                 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1142                         if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1143                                 bus_dmamap_destroy(
1144                                     sc->rl_cdata.rl_tx_tag,
1145                                     sc->rl_cdata.rl_tx_dmamap[i]);
1146                                 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1147                         }
1148                 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1149                 sc->rl_cdata.rl_tx_tag = NULL;
1150                 }
1151         }
1152
1153         if (sc->rl_parent_tag != NULL) {
1154                 bus_dma_tag_destroy(sc->rl_parent_tag);
1155                 sc->rl_parent_tag = NULL;
1156         }
1157 }
1158
1159 /*
1160  * Initialize the transmit descriptors.
1161  */
1162 static int
1163 rl_list_tx_init(struct rl_softc *sc)
1164 {
1165         struct rl_chain_data    *cd;
1166         int                     i;
1167
1168         RL_LOCK_ASSERT(sc);
1169
1170         cd = &sc->rl_cdata;
1171         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1172                 cd->rl_tx_chain[i] = NULL;
1173                 CSR_WRITE_4(sc,
1174                     RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1175         }
1176
1177         sc->rl_cdata.cur_tx = 0;
1178         sc->rl_cdata.last_tx = 0;
1179
1180         return (0);
1181 }
1182
1183 static int
1184 rl_list_rx_init(struct rl_softc *sc)
1185 {
1186
1187         RL_LOCK_ASSERT(sc);
1188
1189         bzero(sc->rl_cdata.rl_rx_buf_ptr,
1190             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1191         bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1192             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1193
1194         return (0);
1195 }
1196
1197 /*
1198  * A frame has been uploaded: pass the resulting mbuf chain up to
1199  * the higher level protocols.
1200  *
1201  * You know there's something wrong with a PCI bus-master chip design
1202  * when you have to use m_devget().
1203  *
1204  * The receive operation is badly documented in the datasheet, so I'll
1205  * attempt to document it here. The driver provides a buffer area and
1206  * places its base address in the RX buffer start address register.
1207  * The chip then begins copying frames into the RX buffer. Each frame
1208  * is preceded by a 32-bit RX status word which specifies the length
1209  * of the frame and certain other status bits. Each frame (starting with
1210  * the status word) is also 32-bit aligned. The frame length is in the
1211  * first 16 bits of the status word; the lower 15 bits correspond with
1212  * the 'rx status register' mentioned in the datasheet.
1213  *
1214  * Note: to make the Alpha happy, the frame payload needs to be aligned
1215  * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1216  * as the offset argument to m_devget().
1217  */
1218 static void
1219 rl_rxeof(struct rl_softc *sc)
1220 {
1221         struct mbuf             *m;
1222         struct ifnet            *ifp = sc->rl_ifp;
1223         uint8_t                 *rxbufpos;
1224         int                     total_len = 0;
1225         int                     wrap = 0;
1226         uint32_t                rxstat;
1227         uint16_t                cur_rx;
1228         uint16_t                limit;
1229         uint16_t                max_bytes, rx_bytes = 0;
1230
1231         RL_LOCK_ASSERT(sc);
1232
1233         bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1234             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1235
1236         cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1237
1238         /* Do not try to read past this point. */
1239         limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1240
1241         if (limit < cur_rx)
1242                 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1243         else
1244                 max_bytes = limit - cur_rx;
1245
1246         while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1247 #ifdef DEVICE_POLLING
1248                 if (ifp->if_capenable & IFCAP_POLLING) {
1249                         if (sc->rxcycles <= 0)
1250                                 break;
1251                         sc->rxcycles--;
1252                 }
1253 #endif
1254                 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1255                 rxstat = le32toh(*(uint32_t *)rxbufpos);
1256
1257                 /*
1258                  * Here's a totally undocumented fact for you. When the
1259                  * RealTek chip is in the process of copying a packet into
1260                  * RAM for you, the length will be 0xfff0. If you spot a
1261                  * packet header with this value, you need to stop. The
1262                  * datasheet makes absolutely no mention of this and
1263                  * RealTek should be shot for this.
1264                  */
1265                 total_len = rxstat >> 16;
1266                 if (total_len == RL_RXSTAT_UNFINISHED)
1267                         break;
1268
1269                 if (!(rxstat & RL_RXSTAT_RXOK) ||
1270                     total_len < ETHER_MIN_LEN ||
1271                     total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1272                         ifp->if_ierrors++;
1273                         rl_init_locked(sc);
1274                         return;
1275                 }
1276
1277                 /* No errors; receive the packet. */
1278                 rx_bytes += total_len + 4;
1279
1280                 /*
1281                  * XXX The RealTek chip includes the CRC with every
1282                  * received frame, and there's no way to turn this
1283                  * behavior off (at least, I can't find anything in
1284                  * the manual that explains how to do it) so we have
1285                  * to trim off the CRC manually.
1286                  */
1287                 total_len -= ETHER_CRC_LEN;
1288
1289                 /*
1290                  * Avoid trying to read more bytes than we know
1291                  * the chip has prepared for us.
1292                  */
1293                 if (rx_bytes > max_bytes)
1294                         break;
1295
1296                 rxbufpos = sc->rl_cdata.rl_rx_buf +
1297                         ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1298                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1299                         rxbufpos = sc->rl_cdata.rl_rx_buf;
1300
1301                 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1302                 if (total_len > wrap) {
1303                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1304                             NULL);
1305                         if (m == NULL) {
1306                                 ifp->if_ierrors++;
1307                         } else {
1308                                 m_copyback(m, wrap, total_len - wrap,
1309                                         sc->rl_cdata.rl_rx_buf);
1310                         }
1311                         cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1312                 } else {
1313                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1314                             NULL);
1315                         if (m == NULL)
1316                                 ifp->if_ierrors++;
1317                         cur_rx += total_len + 4 + ETHER_CRC_LEN;
1318                 }
1319
1320                 /* Round up to 32-bit boundary. */
1321                 cur_rx = (cur_rx + 3) & ~3;
1322                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1323
1324                 if (m == NULL)
1325                         continue;
1326
1327                 ifp->if_ipackets++;
1328                 RL_UNLOCK(sc);
1329                 (*ifp->if_input)(ifp, m);
1330                 RL_LOCK(sc);
1331         }
1332
1333         /* No need to sync Rx memory block as we didn't modify it. */
1334 }
1335
1336 /*
1337  * A frame was downloaded to the chip. It's safe for us to clean up
1338  * the list buffers.
1339  */
1340 static void
1341 rl_txeof(struct rl_softc *sc)
1342 {
1343         struct ifnet            *ifp = sc->rl_ifp;
1344         uint32_t                txstat;
1345
1346         RL_LOCK_ASSERT(sc);
1347
1348         /*
1349          * Go through our tx list and free mbufs for those
1350          * frames that have been uploaded.
1351          */
1352         do {
1353                 if (RL_LAST_TXMBUF(sc) == NULL)
1354                         break;
1355                 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1356                 if (!(txstat & (RL_TXSTAT_TX_OK|
1357                     RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1358                         break;
1359
1360                 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1361
1362                 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1363                     BUS_DMASYNC_POSTWRITE);
1364                 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1365                 m_freem(RL_LAST_TXMBUF(sc));
1366                 RL_LAST_TXMBUF(sc) = NULL;
1367                 /*
1368                  * If there was a transmit underrun, bump the TX threshold.
1369                  * Make sure not to overflow the 63 * 32byte we can address
1370                  * with the 6 available bit.
1371                  */
1372                 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1373                     (sc->rl_txthresh < 2016))
1374                         sc->rl_txthresh += 32;
1375                 if (txstat & RL_TXSTAT_TX_OK)
1376                         ifp->if_opackets++;
1377                 else {
1378                         int                     oldthresh;
1379                         ifp->if_oerrors++;
1380                         if ((txstat & RL_TXSTAT_TXABRT) ||
1381                             (txstat & RL_TXSTAT_OUTOFWIN))
1382                                 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1383                         oldthresh = sc->rl_txthresh;
1384                         /* error recovery */
1385                         rl_init_locked(sc);
1386                         /* restore original threshold */
1387                         sc->rl_txthresh = oldthresh;
1388                         return;
1389                 }
1390                 RL_INC(sc->rl_cdata.last_tx);
1391                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1392         } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1393
1394         if (RL_LAST_TXMBUF(sc) == NULL)
1395                 sc->rl_watchdog_timer = 0;
1396 }
1397
1398 static void
1399 rl_twister_update(struct rl_softc *sc)
1400 {
1401         uint16_t linktest;
1402         /*
1403          * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
1404          * Linux driver.  Values undocumented otherwise.
1405          */
1406         static const uint32_t param[4][4] = {
1407                 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1408                 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1409                 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1410                 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1411         };
1412
1413         /*
1414          * Tune the so-called twister registers of the RTL8139.  These
1415          * are used to compensate for impedance mismatches.  The
1416          * method for tuning these registers is undocumented and the
1417          * following procedure is collected from public sources.
1418          */
1419         switch (sc->rl_twister)
1420         {
1421         case CHK_LINK:
1422                 /*
1423                  * If we have a sufficient link, then we can proceed in
1424                  * the state machine to the next stage.  If not, then
1425                  * disable further tuning after writing sane defaults.
1426                  */
1427                 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1428                         CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1429                         sc->rl_twister = FIND_ROW;
1430                 } else {
1431                         CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1432                         CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1433                         CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1434                         CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1435                         sc->rl_twister = DONE;
1436                 }
1437                 break;
1438         case FIND_ROW:
1439                 /*
1440                  * Read how long it took to see the echo to find the tuning
1441                  * row to use.
1442                  */
1443                 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1444                 if (linktest == RL_CSCFG_ROW3)
1445                         sc->rl_twist_row = 3;
1446                 else if (linktest == RL_CSCFG_ROW2)
1447                         sc->rl_twist_row = 2;
1448                 else if (linktest == RL_CSCFG_ROW1)
1449                         sc->rl_twist_row = 1;
1450                 else
1451                         sc->rl_twist_row = 0;
1452                 sc->rl_twist_col = 0;
1453                 sc->rl_twister = SET_PARAM;
1454                 break;
1455         case SET_PARAM:
1456                 if (sc->rl_twist_col == 0)
1457                         CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1458                 CSR_WRITE_4(sc, RL_PARA7C,
1459                     param[sc->rl_twist_row][sc->rl_twist_col]);
1460                 if (++sc->rl_twist_col == 4) {
1461                         if (sc->rl_twist_row == 3)
1462                                 sc->rl_twister = RECHK_LONG;
1463                         else
1464                                 sc->rl_twister = DONE;
1465                 }
1466                 break;
1467         case RECHK_LONG:
1468                 /*
1469                  * For long cables, we have to double check to make sure we
1470                  * don't mistune.
1471                  */
1472                 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1473                 if (linktest == RL_CSCFG_ROW3)
1474                         sc->rl_twister = DONE;
1475                 else {
1476                         CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
1477                         sc->rl_twister = RETUNE;
1478                 }
1479                 break;
1480         case RETUNE:
1481                 /* Retune for a shorter cable (try column 2) */
1482                 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1483                 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1484                 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1485                 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1486                 sc->rl_twist_row--;
1487                 sc->rl_twist_col = 0;
1488                 sc->rl_twister = SET_PARAM;
1489                 break;
1490
1491         case DONE:
1492                 break;
1493         }
1494
1495 }
1496
1497 static void
1498 rl_tick(void *xsc)
1499 {
1500         struct rl_softc         *sc = xsc;
1501         struct mii_data         *mii;
1502         int ticks;
1503
1504         RL_LOCK_ASSERT(sc);
1505         /*
1506          * If we're doing the twister cable calibration, then we need to defer
1507          * watchdog timeouts.  This is a no-op in normal operations, but
1508          * can falsely trigger when the cable calibration takes a while and
1509          * there was traffic ready to go when rl was started.
1510          *
1511          * We don't defer mii_tick since that updates the mii status, which
1512          * helps the twister process, at least according to similar patches
1513          * for the Linux driver I found online while doing the fixes.  Worst
1514          * case is a few extra mii reads during calibration.
1515          */
1516         mii = device_get_softc(sc->rl_miibus);
1517         mii_tick(mii);
1518         if (sc->rl_twister_enable) {
1519                 if (sc->rl_twister == DONE)
1520                         rl_watchdog(sc);
1521                 else
1522                         rl_twister_update(sc);
1523                 if (sc->rl_twister == DONE)
1524                         ticks = hz;
1525                 else
1526                         ticks = hz / 10;
1527         } else {
1528                 rl_watchdog(sc);
1529                 ticks = hz;
1530         }
1531
1532         callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
1533 }
1534
1535 #ifdef DEVICE_POLLING
1536 static void
1537 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1538 {
1539         struct rl_softc *sc = ifp->if_softc;
1540
1541         RL_LOCK(sc);
1542         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1543                 rl_poll_locked(ifp, cmd, count);
1544         RL_UNLOCK(sc);
1545 }
1546
1547 static void
1548 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1549 {
1550         struct rl_softc *sc = ifp->if_softc;
1551
1552         RL_LOCK_ASSERT(sc);
1553
1554         sc->rxcycles = count;
1555         rl_rxeof(sc);
1556         rl_txeof(sc);
1557
1558         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1559                 rl_start_locked(ifp);
1560
1561         if (cmd == POLL_AND_CHECK_STATUS) {
1562                 uint16_t        status;
1563
1564                 /* We should also check the status register. */
1565                 status = CSR_READ_2(sc, RL_ISR);
1566                 if (status == 0xffff)
1567                         return;
1568                 if (status != 0)
1569                         CSR_WRITE_2(sc, RL_ISR, status);
1570
1571                 /* XXX We should check behaviour on receiver stalls. */
1572
1573                 if (status & RL_ISR_SYSTEM_ERR)
1574                         rl_init_locked(sc);
1575         }
1576 }
1577 #endif /* DEVICE_POLLING */
1578
1579 static void
1580 rl_intr(void *arg)
1581 {
1582         struct rl_softc         *sc = arg;
1583         struct ifnet            *ifp = sc->rl_ifp;
1584         uint16_t                status;
1585
1586         RL_LOCK(sc);
1587
1588         if (sc->suspended)
1589                 goto done_locked;
1590
1591 #ifdef DEVICE_POLLING
1592         if  (ifp->if_capenable & IFCAP_POLLING)
1593                 goto done_locked;
1594 #endif
1595
1596         for (;;) {
1597                 status = CSR_READ_2(sc, RL_ISR);
1598                 /* If the card has gone away, the read returns 0xffff. */
1599                 if (status == 0xffff)
1600                         break;
1601                 if (status != 0)
1602                         CSR_WRITE_2(sc, RL_ISR, status);
1603                 if ((status & RL_INTRS) == 0)
1604                         break;
1605                 if (status & RL_ISR_RX_OK)
1606                         rl_rxeof(sc);
1607                 if (status & RL_ISR_RX_ERR)
1608                         rl_rxeof(sc);
1609                 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1610                         rl_txeof(sc);
1611                 if (status & RL_ISR_SYSTEM_ERR)
1612                         rl_init_locked(sc);
1613         }
1614
1615         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1616                 rl_start_locked(ifp);
1617
1618 done_locked:
1619         RL_UNLOCK(sc);
1620 }
1621
1622 /*
1623  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1624  * pointers to the fragment pointers.
1625  */
1626 static int
1627 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1628 {
1629         struct mbuf             *m;
1630         bus_dma_segment_t       txsegs[1];
1631         int                     error, nsegs, padlen;
1632
1633         RL_LOCK_ASSERT(sc);
1634
1635         m = *m_head;
1636         padlen = 0;
1637         /*
1638          * Hardware doesn't auto-pad, so we have to make sure
1639          * pad short frames out to the minimum frame length.
1640          */
1641         if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1642                 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1643         /*
1644          * The RealTek is brain damaged and wants longword-aligned
1645          * TX buffers, plus we can only have one fragment buffer
1646          * per packet. We have to copy pretty much all the time.
1647          */
1648         if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1649             (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1650                 m = m_defrag(*m_head, M_DONTWAIT);
1651                 if (m == NULL) {
1652                         m_freem(*m_head);
1653                         *m_head = NULL;
1654                         return (ENOMEM);
1655                 }
1656         }
1657         *m_head = m;
1658
1659         if (padlen > 0) {
1660                 /*
1661                  * Make security-conscious people happy: zero out the
1662                  * bytes in the pad area, since we don't know what
1663                  * this mbuf cluster buffer's previous user might
1664                  * have left in it.
1665                  */
1666                 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1667                 m->m_pkthdr.len += padlen;
1668                 m->m_len = m->m_pkthdr.len;
1669         }
1670
1671         error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1672             RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1673         if (error != 0)
1674                 return (error);
1675         if (nsegs == 0) {
1676                 m_freem(*m_head);
1677                 *m_head = NULL;
1678                 return (EIO);
1679         }
1680
1681         RL_CUR_TXMBUF(sc) = m;
1682         bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1683             BUS_DMASYNC_PREWRITE);
1684         CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1685
1686         return (0);
1687 }
1688
1689 /*
1690  * Main transmit routine.
1691  */
1692 static void
1693 rl_start(struct ifnet *ifp)
1694 {
1695         struct rl_softc         *sc = ifp->if_softc;
1696
1697         RL_LOCK(sc);
1698         rl_start_locked(ifp);
1699         RL_UNLOCK(sc);
1700 }
1701
1702 static void
1703 rl_start_locked(struct ifnet *ifp)
1704 {
1705         struct rl_softc         *sc = ifp->if_softc;
1706         struct mbuf             *m_head = NULL;
1707
1708         RL_LOCK_ASSERT(sc);
1709
1710         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1711             IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1712                 return;
1713
1714         while (RL_CUR_TXMBUF(sc) == NULL) {
1715
1716                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1717
1718                 if (m_head == NULL)
1719                         break;
1720
1721                 if (rl_encap(sc, &m_head)) {
1722                         if (m_head == NULL)
1723                                 break;
1724                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1725                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1726                         break;
1727                 }
1728
1729                 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1730                 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1731
1732                 /* Transmit the frame. */
1733                 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1734                     RL_TXTHRESH(sc->rl_txthresh) |
1735                     RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1736
1737                 RL_INC(sc->rl_cdata.cur_tx);
1738
1739                 /* Set a timeout in case the chip goes out to lunch. */
1740                 sc->rl_watchdog_timer = 5;
1741         }
1742
1743         /*
1744          * We broke out of the loop because all our TX slots are
1745          * full. Mark the NIC as busy until it drains some of the
1746          * packets from the queue.
1747          */
1748         if (RL_CUR_TXMBUF(sc) != NULL)
1749                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1750 }
1751
1752 static void
1753 rl_init(void *xsc)
1754 {
1755         struct rl_softc         *sc = xsc;
1756
1757         RL_LOCK(sc);
1758         rl_init_locked(sc);
1759         RL_UNLOCK(sc);
1760 }
1761
1762 static void
1763 rl_init_locked(struct rl_softc *sc)
1764 {
1765         struct ifnet            *ifp = sc->rl_ifp;
1766         struct mii_data         *mii;
1767         uint32_t                rxcfg = 0;
1768         uint32_t                eaddr[2];
1769
1770         RL_LOCK_ASSERT(sc);
1771
1772         mii = device_get_softc(sc->rl_miibus);
1773
1774         /*
1775          * Cancel pending I/O and free all RX/TX buffers.
1776          */
1777         rl_stop(sc);
1778
1779         rl_reset(sc);
1780         if (sc->rl_twister_enable) {
1781                 /*
1782                  * Reset twister register tuning state.  The twister
1783                  * registers and their tuning are undocumented, but
1784                  * are necessary to cope with bad links.  rl_twister =
1785                  * DONE here will disable this entirely.
1786                  */
1787                 sc->rl_twister = CHK_LINK;
1788         }
1789
1790         /*
1791          * Init our MAC address.  Even though the chipset
1792          * documentation doesn't mention it, we need to enter "Config
1793          * register write enable" mode to modify the ID registers.
1794          */
1795         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1796         bzero(eaddr, sizeof(eaddr));
1797         bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1798         CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1799         CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1800         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1801
1802         /* Init the RX memory block pointer register. */
1803         CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1804             RL_RX_8139_BUF_RESERVE);
1805         /* Init TX descriptors. */
1806         rl_list_tx_init(sc);
1807         /* Init Rx memory block. */
1808         rl_list_rx_init(sc);
1809
1810         /*
1811          * Enable transmit and receive.
1812          */
1813         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1814
1815         /*
1816          * Set the initial TX and RX configuration.
1817          */
1818         CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1819         CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1820
1821         /* Set the individual bit to receive frames for this host only. */
1822         rxcfg = CSR_READ_4(sc, RL_RXCFG);
1823         rxcfg |= RL_RXCFG_RX_INDIV;
1824
1825         /* If we want promiscuous mode, set the allframes bit. */
1826         if (ifp->if_flags & IFF_PROMISC) {
1827                 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1828                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1829         } else {
1830                 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1831                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1832         }
1833
1834         /* Set capture broadcast bit to capture broadcast frames. */
1835         if (ifp->if_flags & IFF_BROADCAST) {
1836                 rxcfg |= RL_RXCFG_RX_BROAD;
1837                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1838         } else {
1839                 rxcfg &= ~RL_RXCFG_RX_BROAD;
1840                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1841         }
1842
1843         /* Program the multicast filter, if necessary. */
1844         rl_setmulti(sc);
1845
1846 #ifdef DEVICE_POLLING
1847         /* Disable interrupts if we are polling. */
1848         if (ifp->if_capenable & IFCAP_POLLING)
1849                 CSR_WRITE_2(sc, RL_IMR, 0);
1850         else
1851 #endif
1852         /* Enable interrupts. */
1853         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1854
1855         /* Set initial TX threshold */
1856         sc->rl_txthresh = RL_TX_THRESH_INIT;
1857
1858         /* Start RX/TX process. */
1859         CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1860
1861         /* Enable receiver and transmitter. */
1862         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1863
1864         sc->rl_flags &= ~RL_FLAG_LINK;
1865         mii_mediachg(mii);
1866
1867         CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1868
1869         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1870         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1871
1872         callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1873 }
1874
1875 /*
1876  * Set media options.
1877  */
1878 static int
1879 rl_ifmedia_upd(struct ifnet *ifp)
1880 {
1881         struct rl_softc         *sc = ifp->if_softc;
1882         struct mii_data         *mii;
1883
1884         mii = device_get_softc(sc->rl_miibus);
1885
1886         RL_LOCK(sc);
1887         mii_mediachg(mii);
1888         RL_UNLOCK(sc);
1889
1890         return (0);
1891 }
1892
1893 /*
1894  * Report current media status.
1895  */
1896 static void
1897 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1898 {
1899         struct rl_softc         *sc = ifp->if_softc;
1900         struct mii_data         *mii;
1901
1902         mii = device_get_softc(sc->rl_miibus);
1903
1904         RL_LOCK(sc);
1905         mii_pollstat(mii);
1906         RL_UNLOCK(sc);
1907         ifmr->ifm_active = mii->mii_media_active;
1908         ifmr->ifm_status = mii->mii_media_status;
1909 }
1910
1911 static int
1912 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1913 {
1914         struct ifreq            *ifr = (struct ifreq *)data;
1915         struct mii_data         *mii;
1916         struct rl_softc         *sc = ifp->if_softc;
1917         int                     error = 0;
1918
1919         switch (command) {
1920         case SIOCSIFFLAGS:
1921                 RL_LOCK(sc);
1922                 if (ifp->if_flags & IFF_UP) {
1923                         rl_init_locked(sc);
1924                 } else {
1925                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1926                                 rl_stop(sc);
1927                 }
1928                 RL_UNLOCK(sc);
1929                 error = 0;
1930                 break;
1931         case SIOCADDMULTI:
1932         case SIOCDELMULTI:
1933                 RL_LOCK(sc);
1934                 rl_setmulti(sc);
1935                 RL_UNLOCK(sc);
1936                 error = 0;
1937                 break;
1938         case SIOCGIFMEDIA:
1939         case SIOCSIFMEDIA:
1940                 mii = device_get_softc(sc->rl_miibus);
1941                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1942                 break;
1943         case SIOCSIFCAP:
1944 #ifdef DEVICE_POLLING
1945                 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1946                     !(ifp->if_capenable & IFCAP_POLLING)) {
1947                         error = ether_poll_register(rl_poll, ifp);
1948                         if (error)
1949                                 return(error);
1950                         RL_LOCK(sc);
1951                         /* Disable interrupts */
1952                         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1953                         ifp->if_capenable |= IFCAP_POLLING;
1954                         RL_UNLOCK(sc);
1955                         return (error);
1956
1957                 }
1958                 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1959                     ifp->if_capenable & IFCAP_POLLING) {
1960                         error = ether_poll_deregister(ifp);
1961                         /* Enable interrupts. */
1962                         RL_LOCK(sc);
1963                         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1964                         ifp->if_capenable &= ~IFCAP_POLLING;
1965                         RL_UNLOCK(sc);
1966                         return (error);
1967                 }
1968 #endif /* DEVICE_POLLING */
1969                 break;
1970         default:
1971                 error = ether_ioctl(ifp, command, data);
1972                 break;
1973         }
1974
1975         return (error);
1976 }
1977
1978 static void
1979 rl_watchdog(struct rl_softc *sc)
1980 {
1981
1982         RL_LOCK_ASSERT(sc);
1983
1984         if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1985                 return;
1986
1987         device_printf(sc->rl_dev, "watchdog timeout\n");
1988         sc->rl_ifp->if_oerrors++;
1989
1990         rl_txeof(sc);
1991         rl_rxeof(sc);
1992         rl_init_locked(sc);
1993 }
1994
1995 /*
1996  * Stop the adapter and free any mbufs allocated to the
1997  * RX and TX lists.
1998  */
1999 static void
2000 rl_stop(struct rl_softc *sc)
2001 {
2002         register int            i;
2003         struct ifnet            *ifp = sc->rl_ifp;
2004
2005         RL_LOCK_ASSERT(sc);
2006
2007         sc->rl_watchdog_timer = 0;
2008         callout_stop(&sc->rl_stat_callout);
2009         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2010         sc->rl_flags &= ~RL_FLAG_LINK;
2011
2012         CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2013         CSR_WRITE_2(sc, RL_IMR, 0x0000);
2014         for (i = 0; i < RL_TIMEOUT; i++) {
2015                 DELAY(10);
2016                 if ((CSR_READ_1(sc, RL_COMMAND) &
2017                     (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
2018                         break;
2019         }
2020         if (i == RL_TIMEOUT)
2021                 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
2022
2023         /*
2024          * Free the TX list buffers.
2025          */
2026         for (i = 0; i < RL_TX_LIST_CNT; i++) {
2027                 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
2028                         if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
2029                                 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
2030                                     sc->rl_cdata.rl_tx_dmamap[i],
2031                                     BUS_DMASYNC_POSTWRITE);
2032                                 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
2033                                     sc->rl_cdata.rl_tx_dmamap[i]);
2034                                 m_freem(sc->rl_cdata.rl_tx_chain[i]);
2035                                 sc->rl_cdata.rl_tx_chain[i] = NULL;
2036                         }
2037                         CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
2038                             0x0000000);
2039                 }
2040         }
2041 }
2042
2043 /*
2044  * Device suspend routine.  Stop the interface and save some PCI
2045  * settings in case the BIOS doesn't restore them properly on
2046  * resume.
2047  */
2048 static int
2049 rl_suspend(device_t dev)
2050 {
2051         struct rl_softc         *sc;
2052
2053         sc = device_get_softc(dev);
2054
2055         RL_LOCK(sc);
2056         rl_stop(sc);
2057         sc->suspended = 1;
2058         RL_UNLOCK(sc);
2059
2060         return (0);
2061 }
2062
2063 /*
2064  * Device resume routine.  Restore some PCI settings in case the BIOS
2065  * doesn't, re-enable busmastering, and restart the interface if
2066  * appropriate.
2067  */
2068 static int
2069 rl_resume(device_t dev)
2070 {
2071         struct rl_softc         *sc;
2072         struct ifnet            *ifp;
2073
2074         sc = device_get_softc(dev);
2075         ifp = sc->rl_ifp;
2076
2077         RL_LOCK(sc);
2078
2079         /* reinitialize interface if necessary */
2080         if (ifp->if_flags & IFF_UP)
2081                 rl_init_locked(sc);
2082
2083         sc->suspended = 0;
2084
2085         RL_UNLOCK(sc);
2086
2087         return (0);
2088 }
2089
2090 /*
2091  * Stop all chip I/O so that the kernel's probe routines don't
2092  * get confused by errant DMAs when rebooting.
2093  */
2094 static int
2095 rl_shutdown(device_t dev)
2096 {
2097         struct rl_softc         *sc;
2098
2099         sc = device_get_softc(dev);
2100
2101         RL_LOCK(sc);
2102         rl_stop(sc);
2103         RL_UNLOCK(sc);
2104
2105         return (0);
2106 }