2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
86 #ifdef HAVE_KERNEL_OPTION_HEADERS
87 #include "opt_device_polling.h"
90 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/module.h>
98 #include <sys/socket.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
105 #include <net/if_types.h>
109 #include <machine/bus.h>
110 #include <machine/resource.h>
112 #include <sys/rman.h>
114 #include <dev/mii/mii.h>
115 #include <dev/mii/miivar.h>
117 #include <dev/pci/pcireg.h>
118 #include <dev/pci/pcivar.h>
120 MODULE_DEPEND(rl, pci, 1, 1, 1);
121 MODULE_DEPEND(rl, ether, 1, 1, 1);
122 MODULE_DEPEND(rl, miibus, 1, 1, 1);
124 /* "device miibus" required. See GENERIC if you get errors here. */
125 #include "miibus_if.h"
128 * Default to using PIO access for this driver. On SMP systems,
129 * there appear to be problems with memory mapped mode: it looks like
130 * doing too many memory mapped access back to back in rapid succession
131 * can hang the bus. I'm inclined to blame this on crummy design/construction
132 * on the part of RealTek. Memory mapped mode does appear to work on
133 * uniprocessor systems though.
135 #define RL_USEIOSPACE
137 #include <pci/if_rlreg.h>
140 * Various supported device vendors/types and their names.
142 static struct rl_type rl_devs[] = {
143 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
144 "RealTek 8129 10/100BaseTX" },
145 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
146 "RealTek 8139 10/100BaseTX" },
147 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
148 "RealTek 8139 10/100BaseTX CardBus" },
149 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
150 "RealTek 8100 10/100BaseTX" },
151 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
152 "Accton MPX 5030/5038 10/100BaseTX" },
153 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
154 "Delta Electronics 8139 10/100BaseTX" },
155 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
156 "Addtron Technolgy 8139 10/100BaseTX" },
157 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
158 "D-Link DFE-530TX+ 10/100BaseTX" },
159 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
160 "D-Link DFE-690TXD 10/100BaseTX" },
161 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
162 "Nortel Networks 10/100BaseTX" },
163 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
164 "Corega FEther CB-TXD" },
165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
166 "Corega FEtherII CB-TXD" },
167 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
168 "Peppercon AG ROL-F" },
169 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
170 "Planex FNW-3800-TX" },
171 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
173 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
174 "LevelOne FPC-0106TX" },
175 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
176 "Edimax EP-4103DL CardBus" },
180 static int rl_attach(device_t);
181 static int rl_detach(device_t);
182 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
183 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
184 static void rl_eeprom_putbyte(struct rl_softc *, int);
185 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
186 static int rl_encap(struct rl_softc *, struct mbuf * );
187 static int rl_list_tx_init(struct rl_softc *);
188 static int rl_ifmedia_upd(struct ifnet *);
189 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
190 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
191 static void rl_intr(void *);
192 static void rl_init(void *);
193 static void rl_init_locked(struct rl_softc *sc);
194 static void rl_mii_send(struct rl_softc *, uint32_t, int);
195 static void rl_mii_sync(struct rl_softc *);
196 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
197 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
198 static int rl_miibus_readreg(device_t, int, int);
199 static void rl_miibus_statchg(device_t);
200 static int rl_miibus_writereg(device_t, int, int, int);
201 #ifdef DEVICE_POLLING
202 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
203 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
205 static int rl_probe(device_t);
206 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
207 static void rl_reset(struct rl_softc *);
208 static int rl_resume(device_t);
209 static void rl_rxeof(struct rl_softc *);
210 static void rl_setmulti(struct rl_softc *);
211 static void rl_shutdown(device_t);
212 static void rl_start(struct ifnet *);
213 static void rl_start_locked(struct ifnet *);
214 static void rl_stop(struct rl_softc *);
215 static int rl_suspend(device_t);
216 static void rl_tick(void *);
217 static void rl_txeof(struct rl_softc *);
218 static void rl_watchdog(struct ifnet *);
221 #define RL_RES SYS_RES_IOPORT
222 #define RL_RID RL_PCI_LOIO
224 #define RL_RES SYS_RES_MEMORY
225 #define RL_RID RL_PCI_LOMEM
228 static device_method_t rl_methods[] = {
229 /* Device interface */
230 DEVMETHOD(device_probe, rl_probe),
231 DEVMETHOD(device_attach, rl_attach),
232 DEVMETHOD(device_detach, rl_detach),
233 DEVMETHOD(device_suspend, rl_suspend),
234 DEVMETHOD(device_resume, rl_resume),
235 DEVMETHOD(device_shutdown, rl_shutdown),
238 DEVMETHOD(bus_print_child, bus_generic_print_child),
239 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
242 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
243 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
244 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
249 static driver_t rl_driver = {
252 sizeof(struct rl_softc)
255 static devclass_t rl_devclass;
257 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
258 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
259 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
262 CSR_WRITE_1(sc, RL_EECMD, \
263 CSR_READ_1(sc, RL_EECMD) | x)
266 CSR_WRITE_1(sc, RL_EECMD, \
267 CSR_READ_1(sc, RL_EECMD) & ~x)
270 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
272 struct rl_softc *sc = arg;
274 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
278 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
280 struct rl_softc *sc = arg;
282 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
286 * Send a read command and address to the EEPROM, check for ACK.
289 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
293 d = addr | sc->rl_eecmd_read;
296 * Feed in each bit and strobe the clock.
298 for (i = 0x400; i; i >>= 1) {
300 EE_SET(RL_EE_DATAIN);
302 EE_CLR(RL_EE_DATAIN);
313 * Read a word of data stored in the EEPROM at address 'addr.'
316 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
321 /* Enter EEPROM access mode. */
322 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
325 * Send address of word we want to read.
327 rl_eeprom_putbyte(sc, addr);
329 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
332 * Start reading bits from EEPROM.
334 for (i = 0x8000; i; i >>= 1) {
337 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
343 /* Turn off EEPROM access mode. */
344 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
350 * Read a sequence of words from the EEPROM.
353 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
356 uint16_t word = 0, *ptr;
358 for (i = 0; i < cnt; i++) {
359 rl_eeprom_getword(sc, off + i, &word);
360 ptr = (uint16_t *)(dest + (i * 2));
369 * MII access routines are provided for the 8129, which
370 * doesn't have a built-in PHY. For the 8139, we fake things
371 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
372 * direct access PHY registers.
375 CSR_WRITE_1(sc, RL_MII, \
376 CSR_READ_1(sc, RL_MII) | (x))
379 CSR_WRITE_1(sc, RL_MII, \
380 CSR_READ_1(sc, RL_MII) & ~(x))
383 * Sync the PHYs by setting data bit and strobing the clock 32 times.
386 rl_mii_sync(struct rl_softc *sc)
390 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
392 for (i = 0; i < 32; i++) {
401 * Clock a series of bits through the MII.
404 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
410 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
412 MII_SET(RL_MII_DATAOUT);
414 MII_CLR(RL_MII_DATAOUT);
424 * Read an PHY register through the MII.
427 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
431 /* Set up frame for RX. */
432 frame->mii_stdelim = RL_MII_STARTDELIM;
433 frame->mii_opcode = RL_MII_READOP;
434 frame->mii_turnaround = 0;
437 CSR_WRITE_2(sc, RL_MII, 0);
439 /* Turn on data xmit. */
444 /* Send command/address info. */
445 rl_mii_send(sc, frame->mii_stdelim, 2);
446 rl_mii_send(sc, frame->mii_opcode, 2);
447 rl_mii_send(sc, frame->mii_phyaddr, 5);
448 rl_mii_send(sc, frame->mii_regaddr, 5);
451 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
462 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
467 * Now try reading data bits. If the ack failed, we still
468 * need to clock through 16 cycles to keep the PHY(s) in sync.
471 for(i = 0; i < 16; i++) {
480 for (i = 0x8000; i; i >>= 1) {
484 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
485 frame->mii_data |= i;
498 return (ack ? 1 : 0);
502 * Write to a PHY register through the MII.
505 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
508 /* Set up frame for TX. */
509 frame->mii_stdelim = RL_MII_STARTDELIM;
510 frame->mii_opcode = RL_MII_WRITEOP;
511 frame->mii_turnaround = RL_MII_TURNAROUND;
513 /* Turn on data output. */
518 rl_mii_send(sc, frame->mii_stdelim, 2);
519 rl_mii_send(sc, frame->mii_opcode, 2);
520 rl_mii_send(sc, frame->mii_phyaddr, 5);
521 rl_mii_send(sc, frame->mii_regaddr, 5);
522 rl_mii_send(sc, frame->mii_turnaround, 2);
523 rl_mii_send(sc, frame->mii_data, 16);
538 rl_miibus_readreg(device_t dev, int phy, int reg)
541 struct rl_mii_frame frame;
543 uint16_t rl8139_reg = 0;
545 sc = device_get_softc(dev);
547 if (sc->rl_type == RL_8139) {
548 /* Pretend the internal PHY is only at address 0 */
554 rl8139_reg = RL_BMCR;
557 rl8139_reg = RL_BMSR;
560 rl8139_reg = RL_ANAR;
563 rl8139_reg = RL_ANER;
566 rl8139_reg = RL_LPAR;
572 * Allow the rlphy driver to read the media status
573 * register. If we have a link partner which does not
574 * support NWAY, this is the register which will tell
575 * us the results of parallel detection.
578 rval = CSR_READ_1(sc, RL_MEDIASTAT);
581 if_printf(sc->rl_ifp, "bad phy register\n");
584 rval = CSR_READ_2(sc, rl8139_reg);
588 bzero((char *)&frame, sizeof(frame));
589 frame.mii_phyaddr = phy;
590 frame.mii_regaddr = reg;
591 rl_mii_readreg(sc, &frame);
593 return (frame.mii_data);
597 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
600 struct rl_mii_frame frame;
601 uint16_t rl8139_reg = 0;
603 sc = device_get_softc(dev);
605 if (sc->rl_type == RL_8139) {
606 /* Pretend the internal PHY is only at address 0 */
612 rl8139_reg = RL_BMCR;
615 rl8139_reg = RL_BMSR;
618 rl8139_reg = RL_ANAR;
621 rl8139_reg = RL_ANER;
624 rl8139_reg = RL_LPAR;
631 if_printf(sc->rl_ifp, "bad phy register\n");
634 CSR_WRITE_2(sc, rl8139_reg, data);
638 bzero((char *)&frame, sizeof(frame));
639 frame.mii_phyaddr = phy;
640 frame.mii_regaddr = reg;
641 frame.mii_data = data;
642 rl_mii_writereg(sc, &frame);
648 rl_miibus_statchg(device_t dev)
653 * Program the 64-bit multicast hash filter.
656 rl_setmulti(struct rl_softc *sc)
658 struct ifnet *ifp = sc->rl_ifp;
660 uint32_t hashes[2] = { 0, 0 };
661 struct ifmultiaddr *ifma;
667 rxfilt = CSR_READ_4(sc, RL_RXCFG);
669 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
670 rxfilt |= RL_RXCFG_RX_MULTI;
671 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
672 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
673 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
677 /* first, zot all the existing hash bits */
678 CSR_WRITE_4(sc, RL_MAR0, 0);
679 CSR_WRITE_4(sc, RL_MAR4, 0);
681 /* now program new ones */
683 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
684 if (ifma->ifma_addr->sa_family != AF_LINK)
686 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
687 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
689 hashes[0] |= (1 << h);
691 hashes[1] |= (1 << (h - 32));
697 rxfilt |= RL_RXCFG_RX_MULTI;
699 rxfilt &= ~RL_RXCFG_RX_MULTI;
701 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
702 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
703 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
707 rl_reset(struct rl_softc *sc)
713 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
715 for (i = 0; i < RL_TIMEOUT; i++) {
717 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
721 if_printf(sc->rl_ifp, "reset never completed!\n");
725 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
726 * IDs against our list and return a device name if we find a match.
729 rl_probe(device_t dev)
732 struct rl_type *t = rl_devs;
736 sc = device_get_softc(dev);
738 while (t->rl_name != NULL) {
739 if ((pci_get_vendor(dev) == t->rl_vid) &&
740 (pci_get_device(dev) == t->rl_did)) {
742 * Temporarily map the I/O space
743 * so we can read the chip ID register.
746 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
748 if (sc->rl_res == NULL) {
750 "couldn't map ports/memory\n");
753 sc->rl_btag = rman_get_bustag(sc->rl_res);
754 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
756 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
757 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
759 /* Don't attach to 8139C+ or 8169/8110 chips. */
760 if (hwrev == RL_HWREV_8139CPLUS ||
761 (hwrev == RL_HWREV_8169 &&
762 t->rl_did == RT_DEVICEID_8169) ||
763 hwrev == RL_HWREV_8169S ||
764 hwrev == RL_HWREV_8110S) {
769 device_set_desc(dev, t->rl_name);
770 return (BUS_PROBE_DEFAULT);
779 * Attach the interface. Allocate softc structures, do ifmedia
780 * setup and ethernet/BPF attach.
783 rl_attach(device_t dev)
785 uint8_t eaddr[ETHER_ADDR_LEN];
790 int error = 0, i, rid;
794 sc = device_get_softc(dev);
795 unit = device_get_unit(dev);
797 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
799 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
801 pci_enable_busmaster(dev);
803 /* Map control/status registers. */
805 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
807 if (sc->rl_res == NULL) {
808 device_printf(dev, "couldn't map ports/memory\n");
815 * Detect the Realtek 8139B. For some reason, this chip is very
816 * unstable when left to autoselect the media
817 * The best workaround is to set the device to the required
818 * media type or to set it to the 10 Meg speed.
820 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
822 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
825 sc->rl_btag = rman_get_bustag(sc->rl_res);
826 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
828 /* Allocate interrupt */
830 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
831 RF_SHAREABLE | RF_ACTIVE);
833 if (sc->rl_irq == NULL) {
834 device_printf(dev, "couldn't map interrupt\n");
840 * Reset the adapter. Only take the lock here as it's needed in
841 * order to call rl_reset().
847 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
848 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
849 if (rl_did != 0x8129)
850 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
853 * Get station address from the EEPROM.
855 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
856 for (i = 0; i < 3; i++) {
857 eaddr[(i * 2) + 0] = as[i] & 0xff;
858 eaddr[(i * 2) + 1] = as[i] >> 8;
862 * Now read the exact device type from the EEPROM to find
863 * out if it's an 8129 or 8139.
865 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
869 while(t->rl_name != NULL) {
870 if (rl_did == t->rl_did) {
871 sc->rl_type = t->rl_basetype;
877 if (sc->rl_type == 0) {
878 device_printf(dev, "unknown device ID: %x\n", rl_did);
884 * Allocate the parent bus DMA tag appropriate for PCI.
886 #define RL_NSEG_NEW 32
887 error = bus_dma_tag_create(NULL, /* parent */
888 1, 0, /* alignment, boundary */
889 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
890 BUS_SPACE_MAXADDR, /* highaddr */
891 NULL, NULL, /* filter, filterarg */
892 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
893 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
894 BUS_DMA_ALLOCNOW, /* flags */
895 NULL, NULL, /* lockfunc, lockarg */
901 * Now allocate a tag for the DMA descriptor lists.
902 * All of our lists are allocated as a contiguous block
905 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
906 1, 0, /* alignment, boundary */
907 BUS_SPACE_MAXADDR, /* lowaddr */
908 BUS_SPACE_MAXADDR, /* highaddr */
909 NULL, NULL, /* filter, filterarg */
910 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
911 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
912 BUS_DMA_ALLOCNOW, /* flags */
913 NULL, NULL, /* lockfunc, lockarg */
919 * Now allocate a chunk of DMA-able memory based on the
920 * tag we just created.
922 error = bus_dmamem_alloc(sc->rl_tag,
923 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
924 &sc->rl_cdata.rl_rx_dmamap);
926 device_printf(dev, "no memory for list buffers!\n");
927 bus_dma_tag_destroy(sc->rl_tag);
932 /* Leave a few bytes before the start of the RX ring buffer. */
933 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
934 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
936 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
938 device_printf(dev, "can not if_alloc()\n");
944 if (mii_phy_probe(dev, &sc->rl_miibus,
945 rl_ifmedia_upd, rl_ifmedia_sts)) {
946 device_printf(dev, "MII without any phy!\n");
952 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
953 ifp->if_mtu = ETHERMTU;
954 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
955 ifp->if_ioctl = rl_ioctl;
956 ifp->if_start = rl_start;
957 ifp->if_watchdog = rl_watchdog;
958 ifp->if_init = rl_init;
959 ifp->if_baudrate = 10000000;
960 ifp->if_capabilities = IFCAP_VLAN_MTU;
961 ifp->if_capenable = ifp->if_capabilities;
962 #ifdef DEVICE_POLLING
963 ifp->if_capabilities |= IFCAP_POLLING;
965 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
966 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
967 IFQ_SET_READY(&ifp->if_snd);
970 * Call MI attach routine.
972 ether_ifattach(ifp, eaddr);
974 /* Hook interrupt last to avoid having to lock softc */
975 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
976 rl_intr, sc, &sc->rl_intrhand);
978 if_printf(ifp, "couldn't set up irq\n");
990 * Shutdown hardware and free up resources. This can be called any
991 * time after the mutex has been initialized. It is called in both
992 * the error case in attach and the normal detach case so it needs
993 * to be careful about only freeing resources that have actually been
997 rl_detach(device_t dev)
1002 sc = device_get_softc(dev);
1005 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1007 #ifdef DEVICE_POLLING
1008 if (ifp->if_capenable & IFCAP_POLLING)
1009 ether_poll_deregister(ifp);
1011 /* These should only be active if attach succeeded */
1012 if (device_is_attached(dev)) {
1016 callout_drain(&sc->rl_stat_callout);
1017 ether_ifdetach(ifp);
1023 device_delete_child(dev, sc->rl_miibus);
1024 bus_generic_detach(dev);
1026 if (sc->rl_intrhand)
1027 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1029 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1031 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1037 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1038 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1039 sc->rl_cdata.rl_rx_dmamap);
1040 bus_dma_tag_destroy(sc->rl_tag);
1042 if (sc->rl_parent_tag)
1043 bus_dma_tag_destroy(sc->rl_parent_tag);
1045 mtx_destroy(&sc->rl_mtx);
1051 * Initialize the transmit descriptors.
1054 rl_list_tx_init(struct rl_softc *sc)
1056 struct rl_chain_data *cd;
1062 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1063 cd->rl_tx_chain[i] = NULL;
1065 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1068 sc->rl_cdata.cur_tx = 0;
1069 sc->rl_cdata.last_tx = 0;
1075 * A frame has been uploaded: pass the resulting mbuf chain up to
1076 * the higher level protocols.
1078 * You know there's something wrong with a PCI bus-master chip design
1079 * when you have to use m_devget().
1081 * The receive operation is badly documented in the datasheet, so I'll
1082 * attempt to document it here. The driver provides a buffer area and
1083 * places its base address in the RX buffer start address register.
1084 * The chip then begins copying frames into the RX buffer. Each frame
1085 * is preceded by a 32-bit RX status word which specifies the length
1086 * of the frame and certain other status bits. Each frame (starting with
1087 * the status word) is also 32-bit aligned. The frame length is in the
1088 * first 16 bits of the status word; the lower 15 bits correspond with
1089 * the 'rx status register' mentioned in the datasheet.
1091 * Note: to make the Alpha happy, the frame payload needs to be aligned
1092 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1093 * as the offset argument to m_devget().
1096 rl_rxeof(struct rl_softc *sc)
1099 struct ifnet *ifp = sc->rl_ifp;
1106 uint16_t max_bytes, rx_bytes = 0;
1110 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1111 BUS_DMASYNC_POSTREAD);
1113 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1115 /* Do not try to read past this point. */
1116 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1119 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1121 max_bytes = limit - cur_rx;
1123 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1124 #ifdef DEVICE_POLLING
1125 if (ifp->if_capenable & IFCAP_POLLING) {
1126 if (sc->rxcycles <= 0)
1131 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1132 rxstat = le32toh(*(uint32_t *)rxbufpos);
1135 * Here's a totally undocumented fact for you. When the
1136 * RealTek chip is in the process of copying a packet into
1137 * RAM for you, the length will be 0xfff0. If you spot a
1138 * packet header with this value, you need to stop. The
1139 * datasheet makes absolutely no mention of this and
1140 * RealTek should be shot for this.
1142 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1145 if (!(rxstat & RL_RXSTAT_RXOK)) {
1151 /* No errors; receive the packet. */
1152 total_len = rxstat >> 16;
1153 rx_bytes += total_len + 4;
1156 * XXX The RealTek chip includes the CRC with every
1157 * received frame, and there's no way to turn this
1158 * behavior off (at least, I can't find anything in
1159 * the manual that explains how to do it) so we have
1160 * to trim off the CRC manually.
1162 total_len -= ETHER_CRC_LEN;
1165 * Avoid trying to read more bytes than we know
1166 * the chip has prepared for us.
1168 if (rx_bytes > max_bytes)
1171 rxbufpos = sc->rl_cdata.rl_rx_buf +
1172 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1173 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1174 rxbufpos = sc->rl_cdata.rl_rx_buf;
1176 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1177 if (total_len > wrap) {
1178 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1183 m_copyback(m, wrap, total_len - wrap,
1184 sc->rl_cdata.rl_rx_buf);
1186 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1188 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1192 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1195 /* Round up to 32-bit boundary. */
1196 cur_rx = (cur_rx + 3) & ~3;
1197 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1204 (*ifp->if_input)(ifp, m);
1210 * A frame was downloaded to the chip. It's safe for us to clean up
1214 rl_txeof(struct rl_softc *sc)
1216 struct ifnet *ifp = sc->rl_ifp;
1222 * Go through our tx list and free mbufs for those
1223 * frames that have been uploaded.
1226 if (RL_LAST_TXMBUF(sc) == NULL)
1228 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1229 if (!(txstat & (RL_TXSTAT_TX_OK|
1230 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1233 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1235 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1236 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1237 m_freem(RL_LAST_TXMBUF(sc));
1238 RL_LAST_TXMBUF(sc) = NULL;
1240 * If there was a transmit underrun, bump the TX threshold.
1241 * Make sure not to overflow the 63 * 32byte we can address
1242 * with the 6 available bit.
1244 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1245 (sc->rl_txthresh < 2016))
1246 sc->rl_txthresh += 32;
1247 if (txstat & RL_TXSTAT_TX_OK)
1252 if ((txstat & RL_TXSTAT_TXABRT) ||
1253 (txstat & RL_TXSTAT_OUTOFWIN))
1254 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1255 oldthresh = sc->rl_txthresh;
1256 /* error recovery */
1259 /* restore original threshold */
1260 sc->rl_txthresh = oldthresh;
1263 RL_INC(sc->rl_cdata.last_tx);
1264 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1265 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1267 if (RL_LAST_TXMBUF(sc) == NULL)
1269 else if (ifp->if_timer == 0)
1276 struct rl_softc *sc = xsc;
1277 struct mii_data *mii;
1280 mii = device_get_softc(sc->rl_miibus);
1283 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1286 #ifdef DEVICE_POLLING
1288 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1290 struct rl_softc *sc = ifp->if_softc;
1293 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1294 rl_poll_locked(ifp, cmd, count);
1299 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1301 struct rl_softc *sc = ifp->if_softc;
1305 sc->rxcycles = count;
1309 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1310 rl_start_locked(ifp);
1312 if (cmd == POLL_AND_CHECK_STATUS) {
1315 /* We should also check the status register. */
1316 status = CSR_READ_2(sc, RL_ISR);
1317 if (status == 0xffff)
1320 CSR_WRITE_2(sc, RL_ISR, status);
1322 /* XXX We should check behaviour on receiver stalls. */
1324 if (status & RL_ISR_SYSTEM_ERR) {
1330 #endif /* DEVICE_POLLING */
1335 struct rl_softc *sc = arg;
1336 struct ifnet *ifp = sc->rl_ifp;
1344 #ifdef DEVICE_POLLING
1345 if (ifp->if_capenable & IFCAP_POLLING)
1350 status = CSR_READ_2(sc, RL_ISR);
1351 /* If the card has gone away, the read returns 0xffff. */
1352 if (status == 0xffff)
1355 CSR_WRITE_2(sc, RL_ISR, status);
1356 if ((status & RL_INTRS) == 0)
1358 if (status & RL_ISR_RX_OK)
1360 if (status & RL_ISR_RX_ERR)
1362 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1364 if (status & RL_ISR_SYSTEM_ERR) {
1370 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1371 rl_start_locked(ifp);
1378 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1379 * pointers to the fragment pointers.
1382 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1384 struct mbuf *m_new = NULL;
1389 * The RealTek is brain damaged and wants longword-aligned
1390 * TX buffers, plus we can only have one fragment buffer
1391 * per packet. We have to copy pretty much all the time.
1393 m_new = m_defrag(m_head, M_DONTWAIT);
1395 if (m_new == NULL) {
1401 /* Pad frames to at least 60 bytes. */
1402 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1404 * Make security concious people happy: zero out the
1405 * bytes in the pad area, since we don't know what
1406 * this mbuf cluster buffer's previous user might
1409 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1410 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1411 m_head->m_pkthdr.len +=
1412 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1413 m_head->m_len = m_head->m_pkthdr.len;
1416 RL_CUR_TXMBUF(sc) = m_head;
1422 * Main transmit routine.
1425 rl_start(struct ifnet *ifp)
1427 struct rl_softc *sc = ifp->if_softc;
1430 rl_start_locked(ifp);
1435 rl_start_locked(struct ifnet *ifp)
1437 struct rl_softc *sc = ifp->if_softc;
1438 struct mbuf *m_head = NULL;
1442 while (RL_CUR_TXMBUF(sc) == NULL) {
1444 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1449 if (rl_encap(sc, m_head))
1452 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1453 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1455 /* Transmit the frame. */
1456 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1457 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1458 mtod(RL_CUR_TXMBUF(sc), void *),
1459 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1460 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1461 BUS_DMASYNC_PREREAD);
1462 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1463 RL_TXTHRESH(sc->rl_txthresh) |
1464 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1466 RL_INC(sc->rl_cdata.cur_tx);
1468 /* Set a timeout in case the chip goes out to lunch. */
1473 * We broke out of the loop because all our TX slots are
1474 * full. Mark the NIC as busy until it drains some of the
1475 * packets from the queue.
1477 if (RL_CUR_TXMBUF(sc) != NULL)
1478 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1484 struct rl_softc *sc = xsc;
1492 rl_init_locked(struct rl_softc *sc)
1494 struct ifnet *ifp = sc->rl_ifp;
1495 struct mii_data *mii;
1500 mii = device_get_softc(sc->rl_miibus);
1503 * Cancel pending I/O and free all RX/TX buffers.
1508 * Init our MAC address. Even though the chipset
1509 * documentation doesn't mention it, we need to enter "Config
1510 * register write enable" mode to modify the ID registers.
1512 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1513 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1514 *(uint32_t *)(&IF_LLADDR(sc->rl_ifp)[0]));
1515 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1516 *(uint32_t *)(&IF_LLADDR(sc->rl_ifp)[4]));
1517 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1519 /* Init the RX buffer pointer register. */
1520 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1521 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1522 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1523 BUS_DMASYNC_PREWRITE);
1525 /* Init TX descriptors. */
1526 rl_list_tx_init(sc);
1529 * Enable transmit and receive.
1531 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1534 * Set the initial TX and RX configuration.
1536 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1537 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1539 /* Set the individual bit to receive frames for this host only. */
1540 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1541 rxcfg |= RL_RXCFG_RX_INDIV;
1543 /* If we want promiscuous mode, set the allframes bit. */
1544 if (ifp->if_flags & IFF_PROMISC) {
1545 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1546 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1548 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1549 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1552 /* Set capture broadcast bit to capture broadcast frames. */
1553 if (ifp->if_flags & IFF_BROADCAST) {
1554 rxcfg |= RL_RXCFG_RX_BROAD;
1555 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1557 rxcfg &= ~RL_RXCFG_RX_BROAD;
1558 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1561 /* Program the multicast filter, if necessary. */
1564 #ifdef DEVICE_POLLING
1565 /* Disable interrupts if we are polling. */
1566 if (ifp->if_capenable & IFCAP_POLLING)
1567 CSR_WRITE_2(sc, RL_IMR, 0);
1570 /* Enable interrupts. */
1571 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1573 /* Set initial TX threshold */
1574 sc->rl_txthresh = RL_TX_THRESH_INIT;
1576 /* Start RX/TX process. */
1577 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1579 /* Enable receiver and transmitter. */
1580 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1584 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1586 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1587 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1589 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1593 * Set media options.
1596 rl_ifmedia_upd(struct ifnet *ifp)
1598 struct rl_softc *sc = ifp->if_softc;
1599 struct mii_data *mii;
1601 mii = device_get_softc(sc->rl_miibus);
1611 * Report current media status.
1614 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1616 struct rl_softc *sc = ifp->if_softc;
1617 struct mii_data *mii;
1619 mii = device_get_softc(sc->rl_miibus);
1624 ifmr->ifm_active = mii->mii_media_active;
1625 ifmr->ifm_status = mii->mii_media_status;
1629 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1631 struct ifreq *ifr = (struct ifreq *)data;
1632 struct mii_data *mii;
1633 struct rl_softc *sc = ifp->if_softc;
1639 if (ifp->if_flags & IFF_UP) {
1642 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1657 mii = device_get_softc(sc->rl_miibus);
1658 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1661 #ifdef DEVICE_POLLING
1662 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1663 !(ifp->if_capenable & IFCAP_POLLING)) {
1664 error = ether_poll_register(rl_poll, ifp);
1668 /* Disable interrupts */
1669 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1670 ifp->if_capenable |= IFCAP_POLLING;
1675 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1676 ifp->if_capenable & IFCAP_POLLING) {
1677 error = ether_poll_deregister(ifp);
1678 /* Enable interrupts. */
1680 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1681 ifp->if_capenable &= ~IFCAP_POLLING;
1685 #endif /* DEVICE_POLLING */
1688 error = ether_ioctl(ifp, command, data);
1696 rl_watchdog(struct ifnet *ifp)
1698 struct rl_softc *sc = ifp->if_softc;
1702 if_printf(ifp, "watchdog timeout\n");
1713 * Stop the adapter and free any mbufs allocated to the
1717 rl_stop(struct rl_softc *sc)
1720 struct ifnet *ifp = sc->rl_ifp;
1725 callout_stop(&sc->rl_stat_callout);
1726 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1728 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1729 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1730 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1733 * Free the TX list buffers.
1735 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1736 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1737 bus_dmamap_unload(sc->rl_tag,
1738 sc->rl_cdata.rl_tx_dmamap[i]);
1739 bus_dmamap_destroy(sc->rl_tag,
1740 sc->rl_cdata.rl_tx_dmamap[i]);
1741 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1742 sc->rl_cdata.rl_tx_chain[i] = NULL;
1743 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1750 * Device suspend routine. Stop the interface and save some PCI
1751 * settings in case the BIOS doesn't restore them properly on
1755 rl_suspend(device_t dev)
1757 struct rl_softc *sc;
1759 sc = device_get_softc(dev);
1770 * Device resume routine. Restore some PCI settings in case the BIOS
1771 * doesn't, re-enable busmastering, and restart the interface if
1775 rl_resume(device_t dev)
1777 struct rl_softc *sc;
1780 sc = device_get_softc(dev);
1785 /* reinitialize interface if necessary */
1786 if (ifp->if_flags & IFF_UP)
1797 * Stop all chip I/O so that the kernel's probe routines don't
1798 * get confused by errant DMAs when rebooting.
1801 rl_shutdown(device_t dev)
1803 struct rl_softc *sc;
1805 sc = device_get_softc(dev);