2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
86 #ifdef HAVE_KERNEL_OPTION_HEADERS
87 #include "opt_device_polling.h"
90 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/module.h>
98 #include <sys/socket.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
105 #include <net/if_types.h>
109 #include <machine/bus.h>
110 #include <machine/resource.h>
112 #include <sys/rman.h>
114 #include <dev/mii/mii.h>
115 #include <dev/mii/miivar.h>
117 #include <dev/pci/pcireg.h>
118 #include <dev/pci/pcivar.h>
120 MODULE_DEPEND(rl, pci, 1, 1, 1);
121 MODULE_DEPEND(rl, ether, 1, 1, 1);
122 MODULE_DEPEND(rl, miibus, 1, 1, 1);
124 /* "device miibus" required. See GENERIC if you get errors here. */
125 #include "miibus_if.h"
128 * Default to using PIO access for this driver. On SMP systems,
129 * there appear to be problems with memory mapped mode: it looks like
130 * doing too many memory mapped access back to back in rapid succession
131 * can hang the bus. I'm inclined to blame this on crummy design/construction
132 * on the part of RealTek. Memory mapped mode does appear to work on
133 * uniprocessor systems though.
135 #define RL_USEIOSPACE
137 #include <pci/if_rlreg.h>
140 * Various supported device vendors/types and their names.
142 static struct rl_type rl_devs[] = {
143 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
144 "RealTek 8129 10/100BaseTX" },
145 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
146 "RealTek 8139 10/100BaseTX" },
147 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
148 "RealTek 8139 10/100BaseTX" },
149 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
150 "RealTek 8139 10/100BaseTX CardBus" },
151 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
152 "RealTek 8100 10/100BaseTX" },
153 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
154 "Accton MPX 5030/5038 10/100BaseTX" },
155 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
156 "Delta Electronics 8139 10/100BaseTX" },
157 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
158 "Addtron Technolgy 8139 10/100BaseTX" },
159 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
160 "D-Link DFE-530TX+ 10/100BaseTX" },
161 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
162 "D-Link DFE-690TXD 10/100BaseTX" },
163 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
164 "Nortel Networks 10/100BaseTX" },
165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
166 "Corega FEther CB-TXD" },
167 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
168 "Corega FEtherII CB-TXD" },
169 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
170 "Peppercon AG ROL-F" },
171 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
172 "Planex FNW-3603-TX" },
173 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
174 "Planex FNW-3800-TX" },
175 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
177 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
178 "LevelOne FPC-0106TX" },
179 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
180 "Edimax EP-4103DL CardBus" }
183 static int rl_attach(device_t);
184 static int rl_detach(device_t);
185 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
186 static int rl_dma_alloc(struct rl_softc *);
187 static void rl_dma_free(struct rl_softc *);
188 static void rl_eeprom_putbyte(struct rl_softc *, int);
189 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
190 static int rl_encap(struct rl_softc *, struct mbuf **);
191 static int rl_list_tx_init(struct rl_softc *);
192 static int rl_list_rx_init(struct rl_softc *);
193 static int rl_ifmedia_upd(struct ifnet *);
194 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
195 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
196 static void rl_intr(void *);
197 static void rl_init(void *);
198 static void rl_init_locked(struct rl_softc *sc);
199 static void rl_mii_send(struct rl_softc *, uint32_t, int);
200 static void rl_mii_sync(struct rl_softc *);
201 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
202 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
203 static int rl_miibus_readreg(device_t, int, int);
204 static void rl_miibus_statchg(device_t);
205 static int rl_miibus_writereg(device_t, int, int, int);
206 #ifdef DEVICE_POLLING
207 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
208 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
210 static int rl_probe(device_t);
211 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
212 static void rl_reset(struct rl_softc *);
213 static int rl_resume(device_t);
214 static void rl_rxeof(struct rl_softc *);
215 static void rl_setmulti(struct rl_softc *);
216 static int rl_shutdown(device_t);
217 static void rl_start(struct ifnet *);
218 static void rl_start_locked(struct ifnet *);
219 static void rl_stop(struct rl_softc *);
220 static int rl_suspend(device_t);
221 static void rl_tick(void *);
222 static void rl_txeof(struct rl_softc *);
223 static void rl_watchdog(struct rl_softc *);
226 #define RL_RES SYS_RES_IOPORT
227 #define RL_RID RL_PCI_LOIO
229 #define RL_RES SYS_RES_MEMORY
230 #define RL_RID RL_PCI_LOMEM
233 static device_method_t rl_methods[] = {
234 /* Device interface */
235 DEVMETHOD(device_probe, rl_probe),
236 DEVMETHOD(device_attach, rl_attach),
237 DEVMETHOD(device_detach, rl_detach),
238 DEVMETHOD(device_suspend, rl_suspend),
239 DEVMETHOD(device_resume, rl_resume),
240 DEVMETHOD(device_shutdown, rl_shutdown),
243 DEVMETHOD(bus_print_child, bus_generic_print_child),
244 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
247 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
248 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
249 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
254 static driver_t rl_driver = {
257 sizeof(struct rl_softc)
260 static devclass_t rl_devclass;
262 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
263 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
264 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
267 CSR_WRITE_1(sc, RL_EECMD, \
268 CSR_READ_1(sc, RL_EECMD) | x)
271 CSR_WRITE_1(sc, RL_EECMD, \
272 CSR_READ_1(sc, RL_EECMD) & ~x)
275 * Send a read command and address to the EEPROM, check for ACK.
278 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
282 d = addr | sc->rl_eecmd_read;
285 * Feed in each bit and strobe the clock.
287 for (i = 0x400; i; i >>= 1) {
289 EE_SET(RL_EE_DATAIN);
291 EE_CLR(RL_EE_DATAIN);
302 * Read a word of data stored in the EEPROM at address 'addr.'
305 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
310 /* Enter EEPROM access mode. */
311 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
314 * Send address of word we want to read.
316 rl_eeprom_putbyte(sc, addr);
318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
321 * Start reading bits from EEPROM.
323 for (i = 0x8000; i; i >>= 1) {
326 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
332 /* Turn off EEPROM access mode. */
333 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
339 * Read a sequence of words from the EEPROM.
342 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
345 uint16_t word = 0, *ptr;
347 for (i = 0; i < cnt; i++) {
348 rl_eeprom_getword(sc, off + i, &word);
349 ptr = (uint16_t *)(dest + (i * 2));
358 * MII access routines are provided for the 8129, which
359 * doesn't have a built-in PHY. For the 8139, we fake things
360 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
361 * direct access PHY registers.
364 CSR_WRITE_1(sc, RL_MII, \
365 CSR_READ_1(sc, RL_MII) | (x))
368 CSR_WRITE_1(sc, RL_MII, \
369 CSR_READ_1(sc, RL_MII) & ~(x))
372 * Sync the PHYs by setting data bit and strobing the clock 32 times.
375 rl_mii_sync(struct rl_softc *sc)
379 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
381 for (i = 0; i < 32; i++) {
390 * Clock a series of bits through the MII.
393 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
399 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
401 MII_SET(RL_MII_DATAOUT);
403 MII_CLR(RL_MII_DATAOUT);
413 * Read an PHY register through the MII.
416 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
420 /* Set up frame for RX. */
421 frame->mii_stdelim = RL_MII_STARTDELIM;
422 frame->mii_opcode = RL_MII_READOP;
423 frame->mii_turnaround = 0;
426 CSR_WRITE_2(sc, RL_MII, 0);
428 /* Turn on data xmit. */
433 /* Send command/address info. */
434 rl_mii_send(sc, frame->mii_stdelim, 2);
435 rl_mii_send(sc, frame->mii_opcode, 2);
436 rl_mii_send(sc, frame->mii_phyaddr, 5);
437 rl_mii_send(sc, frame->mii_regaddr, 5);
440 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
451 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
456 * Now try reading data bits. If the ack failed, we still
457 * need to clock through 16 cycles to keep the PHY(s) in sync.
460 for(i = 0; i < 16; i++) {
469 for (i = 0x8000; i; i >>= 1) {
473 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
474 frame->mii_data |= i;
487 return (ack ? 1 : 0);
491 * Write to a PHY register through the MII.
494 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
497 /* Set up frame for TX. */
498 frame->mii_stdelim = RL_MII_STARTDELIM;
499 frame->mii_opcode = RL_MII_WRITEOP;
500 frame->mii_turnaround = RL_MII_TURNAROUND;
502 /* Turn on data output. */
507 rl_mii_send(sc, frame->mii_stdelim, 2);
508 rl_mii_send(sc, frame->mii_opcode, 2);
509 rl_mii_send(sc, frame->mii_phyaddr, 5);
510 rl_mii_send(sc, frame->mii_regaddr, 5);
511 rl_mii_send(sc, frame->mii_turnaround, 2);
512 rl_mii_send(sc, frame->mii_data, 16);
527 rl_miibus_readreg(device_t dev, int phy, int reg)
530 struct rl_mii_frame frame;
532 uint16_t rl8139_reg = 0;
534 sc = device_get_softc(dev);
536 if (sc->rl_type == RL_8139) {
537 /* Pretend the internal PHY is only at address 0 */
543 rl8139_reg = RL_BMCR;
546 rl8139_reg = RL_BMSR;
549 rl8139_reg = RL_ANAR;
552 rl8139_reg = RL_ANER;
555 rl8139_reg = RL_LPAR;
561 * Allow the rlphy driver to read the media status
562 * register. If we have a link partner which does not
563 * support NWAY, this is the register which will tell
564 * us the results of parallel detection.
567 rval = CSR_READ_1(sc, RL_MEDIASTAT);
570 device_printf(sc->rl_dev, "bad phy register\n");
573 rval = CSR_READ_2(sc, rl8139_reg);
577 bzero((char *)&frame, sizeof(frame));
578 frame.mii_phyaddr = phy;
579 frame.mii_regaddr = reg;
580 rl_mii_readreg(sc, &frame);
582 return (frame.mii_data);
586 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
589 struct rl_mii_frame frame;
590 uint16_t rl8139_reg = 0;
592 sc = device_get_softc(dev);
594 if (sc->rl_type == RL_8139) {
595 /* Pretend the internal PHY is only at address 0 */
601 rl8139_reg = RL_BMCR;
604 rl8139_reg = RL_BMSR;
607 rl8139_reg = RL_ANAR;
610 rl8139_reg = RL_ANER;
613 rl8139_reg = RL_LPAR;
620 device_printf(sc->rl_dev, "bad phy register\n");
623 CSR_WRITE_2(sc, rl8139_reg, data);
627 bzero((char *)&frame, sizeof(frame));
628 frame.mii_phyaddr = phy;
629 frame.mii_regaddr = reg;
630 frame.mii_data = data;
631 rl_mii_writereg(sc, &frame);
637 rl_miibus_statchg(device_t dev)
641 struct mii_data *mii;
643 sc = device_get_softc(dev);
644 mii = device_get_softc(sc->rl_miibus);
646 if (mii == NULL || ifp == NULL ||
647 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
650 sc->rl_flags &= ~RL_FLAG_LINK;
651 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
652 (IFM_ACTIVE | IFM_AVALID)) {
653 switch (IFM_SUBTYPE(mii->mii_media_active)) {
656 sc->rl_flags |= RL_FLAG_LINK;
663 * RealTek controllers do not provide any interface to
664 * Tx/Rx MACs for resolved speed, duplex and flow-control
670 * Program the 64-bit multicast hash filter.
673 rl_setmulti(struct rl_softc *sc)
675 struct ifnet *ifp = sc->rl_ifp;
677 uint32_t hashes[2] = { 0, 0 };
678 struct ifmultiaddr *ifma;
684 rxfilt = CSR_READ_4(sc, RL_RXCFG);
686 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
687 rxfilt |= RL_RXCFG_RX_MULTI;
688 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
689 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
690 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
694 /* first, zot all the existing hash bits */
695 CSR_WRITE_4(sc, RL_MAR0, 0);
696 CSR_WRITE_4(sc, RL_MAR4, 0);
698 /* now program new ones */
700 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
701 if (ifma->ifma_addr->sa_family != AF_LINK)
703 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
704 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
706 hashes[0] |= (1 << h);
708 hashes[1] |= (1 << (h - 32));
714 rxfilt |= RL_RXCFG_RX_MULTI;
716 rxfilt &= ~RL_RXCFG_RX_MULTI;
718 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
719 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
720 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
724 rl_reset(struct rl_softc *sc)
730 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
732 for (i = 0; i < RL_TIMEOUT; i++) {
734 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
738 device_printf(sc->rl_dev, "reset never completed!\n");
742 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
743 * IDs against our list and return a device name if we find a match.
746 rl_probe(device_t dev)
749 uint16_t devid, revid, vendor;
752 vendor = pci_get_vendor(dev);
753 devid = pci_get_device(dev);
754 revid = pci_get_revid(dev);
756 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
758 /* 8139C+, let re(4) take care of this device. */
763 for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
764 if (vendor == t->rl_vid && devid == t->rl_did) {
765 device_set_desc(dev, t->rl_name);
766 return (BUS_PROBE_DEFAULT);
773 struct rl_dmamap_arg {
774 bus_addr_t rl_busaddr;
778 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
780 struct rl_dmamap_arg *ctx;
785 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
787 ctx = (struct rl_dmamap_arg *)arg;
788 ctx->rl_busaddr = segs[0].ds_addr;
792 * Attach the interface. Allocate softc structures, do ifmedia
793 * setup and ethernet/BPF attach.
796 rl_attach(device_t dev)
798 uint8_t eaddr[ETHER_ADDR_LEN];
803 int error = 0, i, rid;
807 sc = device_get_softc(dev);
808 unit = device_get_unit(dev);
811 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
813 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
815 pci_enable_busmaster(dev);
817 /* Map control/status registers. */
819 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
821 if (sc->rl_res == NULL) {
822 device_printf(dev, "couldn't map ports/memory\n");
829 * Detect the Realtek 8139B. For some reason, this chip is very
830 * unstable when left to autoselect the media
831 * The best workaround is to set the device to the required
832 * media type or to set it to the 10 Meg speed.
834 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
836 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
839 sc->rl_btag = rman_get_bustag(sc->rl_res);
840 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
842 /* Allocate interrupt */
844 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
845 RF_SHAREABLE | RF_ACTIVE);
847 if (sc->rl_irq[0] == NULL) {
848 device_printf(dev, "couldn't map interrupt\n");
854 * Reset the adapter. Only take the lock here as it's needed in
855 * order to call rl_reset().
861 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
862 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
863 if (rl_did != 0x8129)
864 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
867 * Get station address from the EEPROM.
869 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
870 for (i = 0; i < 3; i++) {
871 eaddr[(i * 2) + 0] = as[i] & 0xff;
872 eaddr[(i * 2) + 1] = as[i] >> 8;
876 * Now read the exact device type from the EEPROM to find
877 * out if it's an 8129 or 8139.
879 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
883 while(t->rl_name != NULL) {
884 if (rl_did == t->rl_did) {
885 sc->rl_type = t->rl_basetype;
891 if (sc->rl_type == 0) {
892 device_printf(dev, "unknown device ID: %x assuming 8139\n",
894 sc->rl_type = RL_8139;
896 * Read RL_IDR register to get ethernet address as accessing
897 * EEPROM may not extract correct address.
899 for (i = 0; i < ETHER_ADDR_LEN; i++)
900 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
903 if ((error = rl_dma_alloc(sc)) != 0)
906 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
908 device_printf(dev, "can not if_alloc()\n");
914 if (mii_phy_probe(dev, &sc->rl_miibus,
915 rl_ifmedia_upd, rl_ifmedia_sts)) {
916 device_printf(dev, "MII without any phy!\n");
922 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
923 ifp->if_mtu = ETHERMTU;
924 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
925 ifp->if_ioctl = rl_ioctl;
926 ifp->if_start = rl_start;
927 ifp->if_init = rl_init;
928 ifp->if_capabilities = IFCAP_VLAN_MTU;
929 ifp->if_capenable = ifp->if_capabilities;
930 #ifdef DEVICE_POLLING
931 ifp->if_capabilities |= IFCAP_POLLING;
933 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
934 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
935 IFQ_SET_READY(&ifp->if_snd);
938 * Call MI attach routine.
940 ether_ifattach(ifp, eaddr);
942 /* Hook interrupt last to avoid having to lock softc */
943 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
944 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
946 device_printf(sc->rl_dev, "couldn't set up irq\n");
958 * Shutdown hardware and free up resources. This can be called any
959 * time after the mutex has been initialized. It is called in both
960 * the error case in attach and the normal detach case so it needs
961 * to be careful about only freeing resources that have actually been
965 rl_detach(device_t dev)
970 sc = device_get_softc(dev);
973 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
975 #ifdef DEVICE_POLLING
976 if (ifp->if_capenable & IFCAP_POLLING)
977 ether_poll_deregister(ifp);
979 /* These should only be active if attach succeeded */
980 if (device_is_attached(dev)) {
984 callout_drain(&sc->rl_stat_callout);
991 device_delete_child(dev, sc->rl_miibus);
992 bus_generic_detach(dev);
994 if (sc->rl_intrhand[0])
995 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
997 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
999 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1006 mtx_destroy(&sc->rl_mtx);
1012 rl_dma_alloc(struct rl_softc *sc)
1014 struct rl_dmamap_arg ctx;
1018 * Allocate the parent bus DMA tag appropriate for PCI.
1020 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
1021 1, 0, /* alignment, boundary */
1022 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1023 BUS_SPACE_MAXADDR, /* highaddr */
1024 NULL, NULL, /* filter, filterarg */
1025 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
1026 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1028 NULL, NULL, /* lockfunc, lockarg */
1029 &sc->rl_parent_tag);
1031 device_printf(sc->rl_dev,
1032 "failed to create parent DMA tag.\n");
1035 /* Create DMA tag for Rx memory block. */
1036 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1037 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */
1038 BUS_SPACE_MAXADDR, /* lowaddr */
1039 BUS_SPACE_MAXADDR, /* highaddr */
1040 NULL, NULL, /* filter, filterarg */
1041 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */
1042 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */
1044 NULL, NULL, /* lockfunc, lockarg */
1045 &sc->rl_cdata.rl_rx_tag);
1047 device_printf(sc->rl_dev,
1048 "failed to create Rx memory block DMA tag.\n");
1051 /* Create DMA tag for Tx buffer. */
1052 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1053 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */
1054 BUS_SPACE_MAXADDR, /* lowaddr */
1055 BUS_SPACE_MAXADDR, /* highaddr */
1056 NULL, NULL, /* filter, filterarg */
1057 MCLBYTES, 1, /* maxsize, nsegments */
1058 MCLBYTES, /* maxsegsize */
1060 NULL, NULL, /* lockfunc, lockarg */
1061 &sc->rl_cdata.rl_tx_tag);
1063 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
1068 * Allocate DMA'able memory and load DMA map for Rx memory block.
1070 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
1071 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
1072 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
1074 device_printf(sc->rl_dev,
1075 "failed to allocate Rx DMA memory block.\n");
1079 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
1080 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
1081 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
1083 if (error != 0 || ctx.rl_busaddr == 0) {
1084 device_printf(sc->rl_dev,
1085 "could not load Rx DMA memory block.\n");
1088 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
1090 /* Create DMA maps for Tx buffers. */
1091 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1092 sc->rl_cdata.rl_tx_chain[i] = NULL;
1093 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1094 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
1095 &sc->rl_cdata.rl_tx_dmamap[i]);
1097 device_printf(sc->rl_dev,
1098 "could not create Tx dmamap.\n");
1103 /* Leave a few bytes before the start of the RX ring buffer. */
1104 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1105 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1112 rl_dma_free(struct rl_softc *sc)
1116 /* Rx memory block. */
1117 if (sc->rl_cdata.rl_rx_tag != NULL) {
1118 if (sc->rl_cdata.rl_rx_dmamap != NULL)
1119 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1120 sc->rl_cdata.rl_rx_dmamap);
1121 if (sc->rl_cdata.rl_rx_dmamap != NULL &&
1122 sc->rl_cdata.rl_rx_buf_ptr != NULL)
1123 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1124 sc->rl_cdata.rl_rx_buf_ptr,
1125 sc->rl_cdata.rl_rx_dmamap);
1126 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1127 sc->rl_cdata.rl_rx_buf = NULL;
1128 sc->rl_cdata.rl_rx_dmamap = NULL;
1129 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1130 sc->rl_cdata.rl_tx_tag = NULL;
1134 if (sc->rl_cdata.rl_tx_tag != NULL) {
1135 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1136 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1138 sc->rl_cdata.rl_tx_tag,
1139 sc->rl_cdata.rl_tx_dmamap[i]);
1140 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1142 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1143 sc->rl_cdata.rl_tx_tag = NULL;
1147 if (sc->rl_parent_tag != NULL) {
1148 bus_dma_tag_destroy(sc->rl_parent_tag);
1149 sc->rl_parent_tag = NULL;
1154 * Initialize the transmit descriptors.
1157 rl_list_tx_init(struct rl_softc *sc)
1159 struct rl_chain_data *cd;
1165 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1166 cd->rl_tx_chain[i] = NULL;
1168 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1171 sc->rl_cdata.cur_tx = 0;
1172 sc->rl_cdata.last_tx = 0;
1178 rl_list_rx_init(struct rl_softc *sc)
1183 bzero(sc->rl_cdata.rl_rx_buf_ptr,
1184 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1185 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1186 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1192 * A frame has been uploaded: pass the resulting mbuf chain up to
1193 * the higher level protocols.
1195 * You know there's something wrong with a PCI bus-master chip design
1196 * when you have to use m_devget().
1198 * The receive operation is badly documented in the datasheet, so I'll
1199 * attempt to document it here. The driver provides a buffer area and
1200 * places its base address in the RX buffer start address register.
1201 * The chip then begins copying frames into the RX buffer. Each frame
1202 * is preceded by a 32-bit RX status word which specifies the length
1203 * of the frame and certain other status bits. Each frame (starting with
1204 * the status word) is also 32-bit aligned. The frame length is in the
1205 * first 16 bits of the status word; the lower 15 bits correspond with
1206 * the 'rx status register' mentioned in the datasheet.
1208 * Note: to make the Alpha happy, the frame payload needs to be aligned
1209 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1210 * as the offset argument to m_devget().
1213 rl_rxeof(struct rl_softc *sc)
1216 struct ifnet *ifp = sc->rl_ifp;
1223 uint16_t max_bytes, rx_bytes = 0;
1227 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1228 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1230 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1232 /* Do not try to read past this point. */
1233 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1236 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1238 max_bytes = limit - cur_rx;
1240 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1241 #ifdef DEVICE_POLLING
1242 if (ifp->if_capenable & IFCAP_POLLING) {
1243 if (sc->rxcycles <= 0)
1248 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1249 rxstat = le32toh(*(uint32_t *)rxbufpos);
1252 * Here's a totally undocumented fact for you. When the
1253 * RealTek chip is in the process of copying a packet into
1254 * RAM for you, the length will be 0xfff0. If you spot a
1255 * packet header with this value, you need to stop. The
1256 * datasheet makes absolutely no mention of this and
1257 * RealTek should be shot for this.
1259 total_len = rxstat >> 16;
1260 if (total_len == RL_RXSTAT_UNFINISHED)
1263 if (!(rxstat & RL_RXSTAT_RXOK) ||
1264 total_len < ETHER_MIN_LEN ||
1265 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1271 /* No errors; receive the packet. */
1272 rx_bytes += total_len + 4;
1275 * XXX The RealTek chip includes the CRC with every
1276 * received frame, and there's no way to turn this
1277 * behavior off (at least, I can't find anything in
1278 * the manual that explains how to do it) so we have
1279 * to trim off the CRC manually.
1281 total_len -= ETHER_CRC_LEN;
1284 * Avoid trying to read more bytes than we know
1285 * the chip has prepared for us.
1287 if (rx_bytes > max_bytes)
1290 rxbufpos = sc->rl_cdata.rl_rx_buf +
1291 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1292 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1293 rxbufpos = sc->rl_cdata.rl_rx_buf;
1295 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1296 if (total_len > wrap) {
1297 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1300 m_copyback(m, wrap, total_len - wrap,
1301 sc->rl_cdata.rl_rx_buf);
1302 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1304 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1306 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1309 /* Round up to 32-bit boundary. */
1310 cur_rx = (cur_rx + 3) & ~3;
1311 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1320 (*ifp->if_input)(ifp, m);
1324 /* No need to sync Rx memory block as we didn't mofify it. */
1328 * A frame was downloaded to the chip. It's safe for us to clean up
1332 rl_txeof(struct rl_softc *sc)
1334 struct ifnet *ifp = sc->rl_ifp;
1340 * Go through our tx list and free mbufs for those
1341 * frames that have been uploaded.
1344 if (RL_LAST_TXMBUF(sc) == NULL)
1346 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1347 if (!(txstat & (RL_TXSTAT_TX_OK|
1348 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1351 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1353 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1354 BUS_DMASYNC_POSTWRITE);
1355 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1356 m_freem(RL_LAST_TXMBUF(sc));
1357 RL_LAST_TXMBUF(sc) = NULL;
1359 * If there was a transmit underrun, bump the TX threshold.
1360 * Make sure not to overflow the 63 * 32byte we can address
1361 * with the 6 available bit.
1363 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1364 (sc->rl_txthresh < 2016))
1365 sc->rl_txthresh += 32;
1366 if (txstat & RL_TXSTAT_TX_OK)
1371 if ((txstat & RL_TXSTAT_TXABRT) ||
1372 (txstat & RL_TXSTAT_OUTOFWIN))
1373 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1374 oldthresh = sc->rl_txthresh;
1375 /* error recovery */
1377 /* restore original threshold */
1378 sc->rl_txthresh = oldthresh;
1381 RL_INC(sc->rl_cdata.last_tx);
1382 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1383 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1385 if (RL_LAST_TXMBUF(sc) == NULL)
1386 sc->rl_watchdog_timer = 0;
1392 struct rl_softc *sc = xsc;
1393 struct mii_data *mii;
1396 mii = device_get_softc(sc->rl_miibus);
1398 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1399 rl_miibus_statchg(sc->rl_dev);
1403 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1406 #ifdef DEVICE_POLLING
1408 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1410 struct rl_softc *sc = ifp->if_softc;
1413 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1414 rl_poll_locked(ifp, cmd, count);
1419 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1421 struct rl_softc *sc = ifp->if_softc;
1425 sc->rxcycles = count;
1429 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1430 rl_start_locked(ifp);
1432 if (cmd == POLL_AND_CHECK_STATUS) {
1435 /* We should also check the status register. */
1436 status = CSR_READ_2(sc, RL_ISR);
1437 if (status == 0xffff)
1440 CSR_WRITE_2(sc, RL_ISR, status);
1442 /* XXX We should check behaviour on receiver stalls. */
1444 if (status & RL_ISR_SYSTEM_ERR)
1448 #endif /* DEVICE_POLLING */
1453 struct rl_softc *sc = arg;
1454 struct ifnet *ifp = sc->rl_ifp;
1462 #ifdef DEVICE_POLLING
1463 if (ifp->if_capenable & IFCAP_POLLING)
1468 status = CSR_READ_2(sc, RL_ISR);
1469 /* If the card has gone away, the read returns 0xffff. */
1470 if (status == 0xffff)
1473 CSR_WRITE_2(sc, RL_ISR, status);
1474 if ((status & RL_INTRS) == 0)
1476 if (status & RL_ISR_RX_OK)
1478 if (status & RL_ISR_RX_ERR)
1480 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1482 if (status & RL_ISR_SYSTEM_ERR)
1486 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1487 rl_start_locked(ifp);
1494 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1495 * pointers to the fragment pointers.
1498 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1501 bus_dma_segment_t txsegs[1];
1502 int error, nsegs, padlen;
1509 * Hardware doesn't auto-pad, so we have to make sure
1510 * pad short frames out to the minimum frame length.
1512 if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1513 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1515 * The RealTek is brain damaged and wants longword-aligned
1516 * TX buffers, plus we can only have one fragment buffer
1517 * per packet. We have to copy pretty much all the time.
1519 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1520 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1521 m = m_defrag(*m_head, M_DONTWAIT);
1532 * Make security concious people happy: zero out the
1533 * bytes in the pad area, since we don't know what
1534 * this mbuf cluster buffer's previous user might
1537 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1538 m->m_pkthdr.len += padlen;
1539 m->m_len = m->m_pkthdr.len;
1542 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1543 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1552 RL_CUR_TXMBUF(sc) = m;
1553 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1554 BUS_DMASYNC_PREWRITE);
1555 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1561 * Main transmit routine.
1564 rl_start(struct ifnet *ifp)
1566 struct rl_softc *sc = ifp->if_softc;
1569 rl_start_locked(ifp);
1574 rl_start_locked(struct ifnet *ifp)
1576 struct rl_softc *sc = ifp->if_softc;
1577 struct mbuf *m_head = NULL;
1581 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1582 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1585 while (RL_CUR_TXMBUF(sc) == NULL) {
1587 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1592 if (rl_encap(sc, &m_head)) {
1595 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1596 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1600 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1601 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1603 /* Transmit the frame. */
1604 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1605 RL_TXTHRESH(sc->rl_txthresh) |
1606 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1608 RL_INC(sc->rl_cdata.cur_tx);
1610 /* Set a timeout in case the chip goes out to lunch. */
1611 sc->rl_watchdog_timer = 5;
1615 * We broke out of the loop because all our TX slots are
1616 * full. Mark the NIC as busy until it drains some of the
1617 * packets from the queue.
1619 if (RL_CUR_TXMBUF(sc) != NULL)
1620 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1626 struct rl_softc *sc = xsc;
1634 rl_init_locked(struct rl_softc *sc)
1636 struct ifnet *ifp = sc->rl_ifp;
1637 struct mii_data *mii;
1643 mii = device_get_softc(sc->rl_miibus);
1646 * Cancel pending I/O and free all RX/TX buffers.
1653 * Init our MAC address. Even though the chipset
1654 * documentation doesn't mention it, we need to enter "Config
1655 * register write enable" mode to modify the ID registers.
1657 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1658 bzero(eaddr, sizeof(eaddr));
1659 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1660 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1661 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1662 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1664 /* Init the RX memory block pointer register. */
1665 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1666 RL_RX_8139_BUF_RESERVE);
1667 /* Init TX descriptors. */
1668 rl_list_tx_init(sc);
1669 /* Init Rx memory block. */
1670 rl_list_rx_init(sc);
1673 * Enable transmit and receive.
1675 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1678 * Set the initial TX and RX configuration.
1680 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1681 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1683 /* Set the individual bit to receive frames for this host only. */
1684 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1685 rxcfg |= RL_RXCFG_RX_INDIV;
1687 /* If we want promiscuous mode, set the allframes bit. */
1688 if (ifp->if_flags & IFF_PROMISC) {
1689 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1690 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1692 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1693 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1696 /* Set capture broadcast bit to capture broadcast frames. */
1697 if (ifp->if_flags & IFF_BROADCAST) {
1698 rxcfg |= RL_RXCFG_RX_BROAD;
1699 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1701 rxcfg &= ~RL_RXCFG_RX_BROAD;
1702 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1705 /* Program the multicast filter, if necessary. */
1708 #ifdef DEVICE_POLLING
1709 /* Disable interrupts if we are polling. */
1710 if (ifp->if_capenable & IFCAP_POLLING)
1711 CSR_WRITE_2(sc, RL_IMR, 0);
1714 /* Enable interrupts. */
1715 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1717 /* Set initial TX threshold */
1718 sc->rl_txthresh = RL_TX_THRESH_INIT;
1720 /* Start RX/TX process. */
1721 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1723 /* Enable receiver and transmitter. */
1724 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1726 sc->rl_flags &= ~RL_FLAG_LINK;
1729 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1731 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1732 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1734 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1738 * Set media options.
1741 rl_ifmedia_upd(struct ifnet *ifp)
1743 struct rl_softc *sc = ifp->if_softc;
1744 struct mii_data *mii;
1746 mii = device_get_softc(sc->rl_miibus);
1756 * Report current media status.
1759 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1761 struct rl_softc *sc = ifp->if_softc;
1762 struct mii_data *mii;
1764 mii = device_get_softc(sc->rl_miibus);
1769 ifmr->ifm_active = mii->mii_media_active;
1770 ifmr->ifm_status = mii->mii_media_status;
1774 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1776 struct ifreq *ifr = (struct ifreq *)data;
1777 struct mii_data *mii;
1778 struct rl_softc *sc = ifp->if_softc;
1784 if (ifp->if_flags & IFF_UP) {
1787 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1802 mii = device_get_softc(sc->rl_miibus);
1803 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1806 #ifdef DEVICE_POLLING
1807 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1808 !(ifp->if_capenable & IFCAP_POLLING)) {
1809 error = ether_poll_register(rl_poll, ifp);
1813 /* Disable interrupts */
1814 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1815 ifp->if_capenable |= IFCAP_POLLING;
1820 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1821 ifp->if_capenable & IFCAP_POLLING) {
1822 error = ether_poll_deregister(ifp);
1823 /* Enable interrupts. */
1825 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1826 ifp->if_capenable &= ~IFCAP_POLLING;
1830 #endif /* DEVICE_POLLING */
1833 error = ether_ioctl(ifp, command, data);
1841 rl_watchdog(struct rl_softc *sc)
1846 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1849 device_printf(sc->rl_dev, "watchdog timeout\n");
1850 sc->rl_ifp->if_oerrors++;
1858 * Stop the adapter and free any mbufs allocated to the
1862 rl_stop(struct rl_softc *sc)
1865 struct ifnet *ifp = sc->rl_ifp;
1869 sc->rl_watchdog_timer = 0;
1870 callout_stop(&sc->rl_stat_callout);
1871 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1872 sc->rl_flags &= ~RL_FLAG_LINK;
1874 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1875 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1876 for (i = 0; i < RL_TIMEOUT; i++) {
1878 if ((CSR_READ_1(sc, RL_COMMAND) &
1879 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
1882 if (i == RL_TIMEOUT)
1883 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
1886 * Free the TX list buffers.
1888 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1889 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1890 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1891 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
1892 sc->rl_cdata.rl_tx_dmamap[i],
1893 BUS_DMASYNC_POSTWRITE);
1894 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1895 sc->rl_cdata.rl_tx_dmamap[i]);
1896 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1897 sc->rl_cdata.rl_tx_chain[i] = NULL;
1899 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1906 * Device suspend routine. Stop the interface and save some PCI
1907 * settings in case the BIOS doesn't restore them properly on
1911 rl_suspend(device_t dev)
1913 struct rl_softc *sc;
1915 sc = device_get_softc(dev);
1926 * Device resume routine. Restore some PCI settings in case the BIOS
1927 * doesn't, re-enable busmastering, and restart the interface if
1931 rl_resume(device_t dev)
1933 struct rl_softc *sc;
1936 sc = device_get_softc(dev);
1941 /* reinitialize interface if necessary */
1942 if (ifp->if_flags & IFF_UP)
1953 * Stop all chip I/O so that the kernel's probe routines don't
1954 * get confused by errant DMAs when rebooting.
1957 rl_shutdown(device_t dev)
1959 struct rl_softc *sc;
1961 sc = device_get_softc(dev);