2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * RealTek 8129/8139 PCI NIC driver
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
86 #include <sys/param.h>
87 #include <sys/systm.h>
88 #include <sys/sockio.h>
90 #include <sys/malloc.h>
91 #include <sys/kernel.h>
92 #include <sys/socket.h>
95 #include <net/if_arp.h>
96 #include <net/ethernet.h>
97 #include <net/if_dl.h>
98 #include <net/if_media.h>
102 #include <machine/bus_pio.h>
103 #include <machine/bus_memio.h>
104 #include <machine/bus.h>
105 #include <machine/resource.h>
107 #include <sys/rman.h>
109 #include <dev/mii/mii.h>
110 #include <dev/mii/miivar.h>
112 #include <pci/pcireg.h>
113 #include <pci/pcivar.h>
115 MODULE_DEPEND(rl, miibus, 1, 1, 1);
117 /* "controller miibus0" required. See GENERIC if you get errors here. */
118 #include "miibus_if.h"
121 * Default to using PIO access for this driver. On SMP systems,
122 * there appear to be problems with memory mapped mode: it looks like
123 * doing too many memory mapped access back to back in rapid succession
124 * can hang the bus. I'm inclined to blame this on crummy design/construction
125 * on the part of RealTek. Memory mapped mode does appear to work on
126 * uniprocessor systems though.
128 #define RL_USEIOSPACE
130 #include <pci/if_rlreg.h>
133 static const char rcsid[] =
138 * Various supported device vendors/types and their names.
140 static struct rl_type rl_devs[] = {
141 { RT_VENDORID, RT_DEVICEID_8129,
142 "RealTek 8129 10/100BaseTX" },
143 { RT_VENDORID, RT_DEVICEID_8139,
144 "RealTek 8139 10/100BaseTX" },
145 { RT_VENDORID, RT_DEVICEID_8138,
146 "RealTek 8139 10/100BaseTX CardBus" },
147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
148 "Accton MPX 5030/5038 10/100BaseTX" },
149 { DELTA_VENDORID, DELTA_DEVICEID_8139,
150 "Delta Electronics 8139 10/100BaseTX" },
151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
152 "Addtron Technolgy 8139 10/100BaseTX" },
153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
154 "D-Link DFE-530TX+ 10/100BaseTX" },
158 static int rl_probe (device_t);
159 static int rl_attach (device_t);
160 static int rl_detach (device_t);
162 static int rl_encap (struct rl_softc *, struct mbuf * );
164 static void rl_rxeof (struct rl_softc *);
165 static void rl_txeof (struct rl_softc *);
166 static void rl_intr (void *);
167 static void rl_tick (void *);
168 static void rl_start (struct ifnet *);
169 static int rl_ioctl (struct ifnet *, u_long, caddr_t);
170 static void rl_init (void *);
171 static void rl_stop (struct rl_softc *);
172 static void rl_watchdog (struct ifnet *);
173 static int rl_suspend (device_t);
174 static int rl_resume (device_t);
175 static void rl_shutdown (device_t);
176 static int rl_ifmedia_upd (struct ifnet *);
177 static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
179 static void rl_eeprom_putbyte (struct rl_softc *, int);
180 static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *);
181 static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
182 static void rl_mii_sync (struct rl_softc *);
183 static void rl_mii_send (struct rl_softc *, u_int32_t, int);
184 static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *);
185 static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *);
187 static int rl_miibus_readreg (device_t, int, int);
188 static int rl_miibus_writereg (device_t, int, int, int);
189 static void rl_miibus_statchg (device_t);
191 static u_int8_t rl_calchash (caddr_t);
192 static void rl_setmulti (struct rl_softc *);
193 static void rl_reset (struct rl_softc *);
194 static int rl_list_tx_init (struct rl_softc *);
196 static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int);
197 static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int);
200 #define RL_RES SYS_RES_IOPORT
201 #define RL_RID RL_PCI_LOIO
203 #define RL_RES SYS_RES_MEMORY
204 #define RL_RID RL_PCI_LOMEM
207 static device_method_t rl_methods[] = {
208 /* Device interface */
209 DEVMETHOD(device_probe, rl_probe),
210 DEVMETHOD(device_attach, rl_attach),
211 DEVMETHOD(device_detach, rl_detach),
212 DEVMETHOD(device_suspend, rl_suspend),
213 DEVMETHOD(device_resume, rl_resume),
214 DEVMETHOD(device_shutdown, rl_shutdown),
217 DEVMETHOD(bus_print_child, bus_generic_print_child),
218 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
221 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
222 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
223 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
228 static driver_t rl_driver = {
231 sizeof(struct rl_softc)
234 static devclass_t rl_devclass;
236 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
237 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
238 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
241 CSR_WRITE_1(sc, RL_EECMD, \
242 CSR_READ_1(sc, RL_EECMD) | x)
245 CSR_WRITE_1(sc, RL_EECMD, \
246 CSR_READ_1(sc, RL_EECMD) & ~x)
249 rl_dma_map_rxbuf(arg, segs, nseg, error)
251 bus_dma_segment_t *segs;
257 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
263 rl_dma_map_txbuf(arg, segs, nseg, error)
265 bus_dma_segment_t *segs;
271 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
277 * Send a read command and address to the EEPROM, check for ACK.
279 static void rl_eeprom_putbyte(sc, addr)
285 d = addr | sc->rl_eecmd_read;
288 * Feed in each bit and strobe the clock.
290 for (i = 0x400; i; i >>= 1) {
292 EE_SET(RL_EE_DATAIN);
294 EE_CLR(RL_EE_DATAIN);
307 * Read a word of data stored in the EEPROM at address 'addr.'
309 static void rl_eeprom_getword(sc, addr, dest)
317 /* Enter EEPROM access mode. */
318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
321 * Send address of word we want to read.
323 rl_eeprom_putbyte(sc, addr);
325 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
328 * Start reading bits from EEPROM.
330 for (i = 0x8000; i; i >>= 1) {
333 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
339 /* Turn off EEPROM access mode. */
340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
348 * Read a sequence of words from the EEPROM.
350 static void rl_read_eeprom(sc, dest, off, cnt, swap)
358 u_int16_t word = 0, *ptr;
360 for (i = 0; i < cnt; i++) {
361 rl_eeprom_getword(sc, off + i, &word);
362 ptr = (u_int16_t *)(dest + (i * 2));
374 * MII access routines are provided for the 8129, which
375 * doesn't have a built-in PHY. For the 8139, we fake things
376 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
377 * direct access PHY registers.
380 CSR_WRITE_1(sc, RL_MII, \
381 CSR_READ_1(sc, RL_MII) | x)
384 CSR_WRITE_1(sc, RL_MII, \
385 CSR_READ_1(sc, RL_MII) & ~x)
388 * Sync the PHYs by setting data bit and strobing the clock 32 times.
390 static void rl_mii_sync(sc)
395 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
397 for (i = 0; i < 32; i++) {
408 * Clock a series of bits through the MII.
410 static void rl_mii_send(sc, bits, cnt)
419 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
421 MII_SET(RL_MII_DATAOUT);
423 MII_CLR(RL_MII_DATAOUT);
433 * Read an PHY register through the MII.
435 static int rl_mii_readreg(sc, frame)
437 struct rl_mii_frame *frame;
445 * Set up frame for RX.
447 frame->mii_stdelim = RL_MII_STARTDELIM;
448 frame->mii_opcode = RL_MII_READOP;
449 frame->mii_turnaround = 0;
452 CSR_WRITE_2(sc, RL_MII, 0);
462 * Send command/address info.
464 rl_mii_send(sc, frame->mii_stdelim, 2);
465 rl_mii_send(sc, frame->mii_opcode, 2);
466 rl_mii_send(sc, frame->mii_phyaddr, 5);
467 rl_mii_send(sc, frame->mii_regaddr, 5);
470 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
483 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
486 * Now try reading data bits. If the ack failed, we still
487 * need to clock through 16 cycles to keep the PHY(s) in sync.
490 for(i = 0; i < 16; i++) {
499 for (i = 0x8000; i; i >>= 1) {
503 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
504 frame->mii_data |= i;
526 * Write to a PHY register through the MII.
528 static int rl_mii_writereg(sc, frame)
530 struct rl_mii_frame *frame;
536 * Set up frame for TX.
539 frame->mii_stdelim = RL_MII_STARTDELIM;
540 frame->mii_opcode = RL_MII_WRITEOP;
541 frame->mii_turnaround = RL_MII_TURNAROUND;
544 * Turn on data output.
550 rl_mii_send(sc, frame->mii_stdelim, 2);
551 rl_mii_send(sc, frame->mii_opcode, 2);
552 rl_mii_send(sc, frame->mii_phyaddr, 5);
553 rl_mii_send(sc, frame->mii_regaddr, 5);
554 rl_mii_send(sc, frame->mii_turnaround, 2);
555 rl_mii_send(sc, frame->mii_data, 16);
573 static int rl_miibus_readreg(dev, phy, reg)
578 struct rl_mii_frame frame;
580 u_int16_t rl8139_reg = 0;
582 sc = device_get_softc(dev);
585 if (sc->rl_type == RL_8139) {
586 /* Pretend the internal PHY is only at address 0 */
593 rl8139_reg = RL_BMCR;
596 rl8139_reg = RL_BMSR;
599 rl8139_reg = RL_ANAR;
602 rl8139_reg = RL_ANER;
605 rl8139_reg = RL_LPAR;
613 printf("rl%d: bad phy register\n", sc->rl_unit);
617 rval = CSR_READ_2(sc, rl8139_reg);
622 bzero((char *)&frame, sizeof(frame));
624 frame.mii_phyaddr = phy;
625 frame.mii_regaddr = reg;
626 rl_mii_readreg(sc, &frame);
629 return(frame.mii_data);
632 static int rl_miibus_writereg(dev, phy, reg, data)
637 struct rl_mii_frame frame;
638 u_int16_t rl8139_reg = 0;
640 sc = device_get_softc(dev);
643 if (sc->rl_type == RL_8139) {
644 /* Pretend the internal PHY is only at address 0 */
651 rl8139_reg = RL_BMCR;
654 rl8139_reg = RL_BMSR;
657 rl8139_reg = RL_ANAR;
660 rl8139_reg = RL_ANER;
663 rl8139_reg = RL_LPAR;
671 printf("rl%d: bad phy register\n", sc->rl_unit);
675 CSR_WRITE_2(sc, rl8139_reg, data);
680 bzero((char *)&frame, sizeof(frame));
682 frame.mii_phyaddr = phy;
683 frame.mii_regaddr = reg;
684 frame.mii_data = data;
686 rl_mii_writereg(sc, &frame);
692 static void rl_miibus_statchg(dev)
699 * Calculate CRC of a multicast group address, return the upper 6 bits.
701 static u_int8_t rl_calchash(addr)
704 u_int32_t crc, carry;
708 /* Compute CRC for the address value. */
709 crc = 0xFFFFFFFF; /* initial value */
711 for (i = 0; i < 6; i++) {
713 for (j = 0; j < 8; j++) {
714 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
718 crc = (crc ^ 0x04c11db6) | carry;
722 /* return the filter bit position */
727 * Program the 64-bit multicast hash filter.
729 static void rl_setmulti(sc)
734 u_int32_t hashes[2] = { 0, 0 };
735 struct ifmultiaddr *ifma;
739 ifp = &sc->arpcom.ac_if;
741 rxfilt = CSR_READ_4(sc, RL_RXCFG);
743 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
744 rxfilt |= RL_RXCFG_RX_MULTI;
745 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
746 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
747 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
751 /* first, zot all the existing hash bits */
752 CSR_WRITE_4(sc, RL_MAR0, 0);
753 CSR_WRITE_4(sc, RL_MAR4, 0);
755 /* now program new ones */
756 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
757 if (ifma->ifma_addr->sa_family != AF_LINK)
759 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
761 hashes[0] |= (1 << h);
763 hashes[1] |= (1 << (h - 32));
768 rxfilt |= RL_RXCFG_RX_MULTI;
770 rxfilt &= ~RL_RXCFG_RX_MULTI;
772 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
773 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
774 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
779 static void rl_reset(sc)
784 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
786 for (i = 0; i < RL_TIMEOUT; i++) {
788 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
792 printf("rl%d: reset never completed!\n", sc->rl_unit);
798 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
799 * IDs against our list and return a device name if we find a match.
801 static int rl_probe(dev)
808 while(t->rl_name != NULL) {
809 if ((pci_get_vendor(dev) == t->rl_vid) &&
810 (pci_get_device(dev) == t->rl_did)) {
811 device_set_desc(dev, t->rl_name);
821 * Attach the interface. Allocate softc structures, do ifmedia
822 * setup and ethernet/BPF attach.
824 static int rl_attach(dev)
827 u_char eaddr[ETHER_ADDR_LEN];
831 u_int16_t rl_did = 0;
832 int unit, error = 0, rid;
834 sc = device_get_softc(dev);
835 unit = device_get_unit(dev);
836 bzero(sc, sizeof(struct rl_softc));
838 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
842 * Handle power management nonsense.
845 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
846 u_int32_t iobase, membase, irq;
848 /* Save important PCI config data. */
849 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
850 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
851 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
853 /* Reset the power state. */
854 printf("rl%d: chip is is in D%d power mode "
855 "-- setting to D0\n", unit,
856 pci_get_powerstate(dev));
858 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
860 /* Restore PCI config data. */
861 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
862 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
863 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
867 * Map control/status registers.
869 pci_enable_busmaster(dev);
870 pci_enable_io(dev, SYS_RES_IOPORT);
871 pci_enable_io(dev, SYS_RES_MEMORY);
872 command = pci_read_config(dev, PCIR_COMMAND, 4);
875 if (!(command & PCIM_CMD_PORTEN)) {
876 printf("rl%d: failed to enable I/O ports!\n", unit);
881 if (!(command & PCIM_CMD_MEMEN)) {
882 printf("rl%d: failed to enable memory mapping!\n", unit);
889 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
890 0, ~0, 1, RF_ACTIVE);
892 if (sc->rl_res == NULL) {
893 printf ("rl%d: couldn't map ports/memory\n", unit);
898 /* Detect the Realtek 8139B. For some reason, this chip is very
899 * unstable when left to autoselect the media
900 * The best workaround is to set the device to the required
901 * media type or to set it to the 10 Meg speed.
904 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
905 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit);
908 sc->rl_btag = rman_get_bustag(sc->rl_res);
909 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
912 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
913 RF_SHAREABLE | RF_ACTIVE);
915 if (sc->rl_irq == NULL) {
916 printf("rl%d: couldn't map interrupt\n", unit);
917 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
922 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
923 rl_intr, sc, &sc->rl_intrhand);
926 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
927 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
928 printf("rl%d: couldn't set up irq\n", unit);
932 callout_handle_init(&sc->rl_stat_ch);
934 /* Reset the adapter. */
936 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
937 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0);
938 if (rl_did != 0x8129)
939 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
942 * Get station address from the EEPROM.
944 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
947 * A RealTek chip was detected. Inform the world.
949 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
952 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
955 * Now read the exact device type from the EEPROM to find
956 * out if it's an 8129 or 8139.
958 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
960 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
961 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
962 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS)
963 sc->rl_type = RL_8139;
964 else if (rl_did == RT_DEVICEID_8129)
965 sc->rl_type = RL_8129;
967 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
968 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
969 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
970 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
976 * Allocate the parent bus DMA tag appropriate for PCI.
978 #define RL_NSEG_NEW 32
979 error = bus_dma_tag_create(NULL, /* parent */
980 1, 0, /* alignment, boundary */
981 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
982 BUS_SPACE_MAXADDR, /* highaddr */
983 NULL, NULL, /* filter, filterarg */
984 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
985 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
986 BUS_DMA_ALLOCNOW, /* flags */
990 * Now allocate a tag for the DMA descriptor lists.
991 * All of our lists are allocated as a contiguous block
994 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
995 1, 0, /* alignment, boundary */
996 BUS_SPACE_MAXADDR, /* lowaddr */
997 BUS_SPACE_MAXADDR, /* highaddr */
998 NULL, NULL, /* filter, filterarg */
999 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
1000 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1005 * Now allocate a chunk of DMA-able memory based on the
1006 * tag we just created.
1008 error = bus_dmamem_alloc(sc->rl_tag,
1009 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT,
1010 &sc->rl_cdata.rl_rx_dmamap);
1012 if (sc->rl_cdata.rl_rx_buf == NULL) {
1013 printf("rl%d: no memory for list buffers!\n", unit);
1014 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1015 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1016 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1017 bus_dma_tag_destroy(sc->rl_tag);
1022 /* Leave a few bytes before the start of the RX ring buffer. */
1023 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1024 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1027 if (mii_phy_probe(dev, &sc->rl_miibus,
1028 rl_ifmedia_upd, rl_ifmedia_sts)) {
1029 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1030 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1031 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1032 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1033 bus_dmamem_free(sc->rl_tag,
1034 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap);
1035 bus_dma_tag_destroy(sc->rl_tag);
1040 ifp = &sc->arpcom.ac_if;
1042 ifp->if_unit = unit;
1043 ifp->if_name = "rl";
1044 ifp->if_mtu = ETHERMTU;
1045 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1046 ifp->if_ioctl = rl_ioctl;
1047 ifp->if_output = ether_output;
1048 ifp->if_start = rl_start;
1049 ifp->if_watchdog = rl_watchdog;
1050 ifp->if_init = rl_init;
1051 ifp->if_baudrate = 10000000;
1052 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1055 * Call MI attach routine.
1057 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1063 mtx_destroy(&sc->rl_mtx);
1067 static int rl_detach(dev)
1070 struct rl_softc *sc;
1073 sc = device_get_softc(dev);
1075 ifp = &sc->arpcom.ac_if;
1077 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1080 bus_generic_detach(dev);
1081 device_delete_child(dev, sc->rl_miibus);
1083 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1084 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1085 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1087 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1088 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1089 sc->rl_cdata.rl_rx_dmamap);
1090 bus_dma_tag_destroy(sc->rl_tag);
1091 bus_dma_tag_destroy(sc->rl_parent_tag);
1094 mtx_destroy(&sc->rl_mtx);
1100 * Initialize the transmit descriptors.
1102 static int rl_list_tx_init(sc)
1103 struct rl_softc *sc;
1105 struct rl_chain_data *cd;
1109 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1110 cd->rl_tx_chain[i] = NULL;
1112 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1115 sc->rl_cdata.cur_tx = 0;
1116 sc->rl_cdata.last_tx = 0;
1122 * A frame has been uploaded: pass the resulting mbuf chain up to
1123 * the higher level protocols.
1125 * You know there's something wrong with a PCI bus-master chip design
1126 * when you have to use m_devget().
1128 * The receive operation is badly documented in the datasheet, so I'll
1129 * attempt to document it here. The driver provides a buffer area and
1130 * places its base address in the RX buffer start address register.
1131 * The chip then begins copying frames into the RX buffer. Each frame
1132 * is preceded by a 32-bit RX status word which specifies the length
1133 * of the frame and certain other status bits. Each frame (starting with
1134 * the status word) is also 32-bit aligned. The frame length is in the
1135 * first 16 bits of the status word; the lower 15 bits correspond with
1136 * the 'rx status register' mentioned in the datasheet.
1138 * Note: to make the Alpha happy, the frame payload needs to be aligned
1139 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1140 * as the offset argument to m_devget().
1142 static void rl_rxeof(sc)
1143 struct rl_softc *sc;
1145 struct ether_header *eh;
1154 u_int16_t rx_bytes = 0, max_bytes;
1156 ifp = &sc->arpcom.ac_if;
1158 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1159 BUS_DMASYNC_POSTWRITE);
1161 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1163 /* Do not try to read past this point. */
1164 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1167 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1169 max_bytes = limit - cur_rx;
1171 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1172 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1173 rxstat = *(u_int32_t *)rxbufpos;
1176 * Here's a totally undocumented fact for you. When the
1177 * RealTek chip is in the process of copying a packet into
1178 * RAM for you, the length will be 0xfff0. If you spot a
1179 * packet header with this value, you need to stop. The
1180 * datasheet makes absolutely no mention of this and
1181 * RealTek should be shot for this.
1183 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1186 if (!(rxstat & RL_RXSTAT_RXOK)) {
1192 /* No errors; receive the packet. */
1193 total_len = rxstat >> 16;
1194 rx_bytes += total_len + 4;
1197 * XXX The RealTek chip includes the CRC with every
1198 * received frame, and there's no way to turn this
1199 * behavior off (at least, I can't find anything in
1200 * the manual that explains how to do it) so we have
1201 * to trim off the CRC manually.
1203 total_len -= ETHER_CRC_LEN;
1206 * Avoid trying to read more bytes than we know
1207 * the chip has prepared for us.
1209 if (rx_bytes > max_bytes)
1212 rxbufpos = sc->rl_cdata.rl_rx_buf +
1213 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1215 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1216 rxbufpos = sc->rl_cdata.rl_rx_buf;
1218 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1220 if (total_len > wrap) {
1221 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1226 m_copyback(m, wrap, total_len - wrap,
1227 sc->rl_cdata.rl_rx_buf);
1229 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1231 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1236 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1240 * Round up to 32-bit boundary.
1242 cur_rx = (cur_rx + 3) & ~3;
1243 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1248 eh = mtod(m, struct ether_header *);
1251 /* Remove header from mbuf and pass it on. */
1252 m_adj(m, sizeof(struct ether_header));
1253 ether_input(ifp, eh, m);
1260 * A frame was downloaded to the chip. It's safe for us to clean up
1263 static void rl_txeof(sc)
1264 struct rl_softc *sc;
1269 ifp = &sc->arpcom.ac_if;
1271 /* Clear the timeout timer. */
1275 * Go through our tx list and free mbufs for those
1276 * frames that have been uploaded.
1279 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1280 if (!(txstat & (RL_TXSTAT_TX_OK|
1281 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1284 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1286 if (RL_LAST_TXMBUF(sc) != NULL) {
1287 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1288 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1289 m_freem(RL_LAST_TXMBUF(sc));
1290 RL_LAST_TXMBUF(sc) = NULL;
1292 if (txstat & RL_TXSTAT_TX_OK)
1297 if ((txstat & RL_TXSTAT_TXABRT) ||
1298 (txstat & RL_TXSTAT_OUTOFWIN))
1299 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1300 oldthresh = sc->rl_txthresh;
1301 /* error recovery */
1305 * If there was a transmit underrun,
1306 * bump the TX threshold.
1308 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1309 sc->rl_txthresh = oldthresh + 32;
1312 RL_INC(sc->rl_cdata.last_tx);
1313 ifp->if_flags &= ~IFF_OACTIVE;
1314 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1319 static void rl_tick(xsc)
1322 struct rl_softc *sc;
1323 struct mii_data *mii;
1327 mii = device_get_softc(sc->rl_miibus);
1331 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1337 static void rl_intr(arg)
1340 struct rl_softc *sc;
1346 if (sc->suspended) {
1351 ifp = &sc->arpcom.ac_if;
1353 /* Disable interrupts. */
1354 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1358 status = CSR_READ_2(sc, RL_ISR);
1360 CSR_WRITE_2(sc, RL_ISR, status);
1362 if ((status & RL_INTRS) == 0)
1365 if (status & RL_ISR_RX_OK)
1368 if (status & RL_ISR_RX_ERR)
1371 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1374 if (status & RL_ISR_SYSTEM_ERR) {
1381 /* Re-enable interrupts. */
1382 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1384 if (ifp->if_snd.ifq_head != NULL)
1393 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1394 * pointers to the fragment pointers.
1396 static int rl_encap(sc, m_head)
1397 struct rl_softc *sc;
1398 struct mbuf *m_head;
1400 struct mbuf *m_new = NULL;
1403 * The RealTek is brain damaged and wants longword-aligned
1404 * TX buffers, plus we can only have one fragment buffer
1405 * per packet. We have to copy pretty much all the time.
1408 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1411 if (m_head->m_pkthdr.len > MHLEN) {
1412 MCLGET(m_new, M_DONTWAIT);
1413 if (!(m_new->m_flags & M_EXT)) {
1418 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1419 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1423 /* Pad frames to at least 60 bytes. */
1424 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1426 * Make security concious people happy: zero out the
1427 * bytes in the pad area, since we don't know what
1428 * this mbuf cluster buffer's previous user might
1431 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1432 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1433 m_head->m_pkthdr.len +=
1434 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1435 m_head->m_len = m_head->m_pkthdr.len;
1438 RL_CUR_TXMBUF(sc) = m_head;
1444 * Main transmit routine.
1447 static void rl_start(ifp)
1450 struct rl_softc *sc;
1451 struct mbuf *m_head = NULL;
1456 while(RL_CUR_TXMBUF(sc) == NULL) {
1457 IF_DEQUEUE(&ifp->if_snd, m_head);
1461 if (rl_encap(sc, m_head)) {
1462 IF_PREPEND(&ifp->if_snd, m_head);
1463 ifp->if_flags |= IFF_OACTIVE;
1468 * If there's a BPF listener, bounce a copy of this frame
1472 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1475 * Transmit the frame.
1477 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1478 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1479 mtod(RL_CUR_TXMBUF(sc), void *),
1480 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1481 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1482 BUS_DMASYNC_PREREAD);
1483 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1484 RL_TXTHRESH(sc->rl_txthresh) |
1485 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1487 RL_INC(sc->rl_cdata.cur_tx);
1491 * We broke out of the loop because all our TX slots are
1492 * full. Mark the NIC as busy until it drains some of the
1493 * packets from the queue.
1495 if (RL_CUR_TXMBUF(sc) != NULL)
1496 ifp->if_flags |= IFF_OACTIVE;
1499 * Set a timeout in case the chip goes out to lunch.
1507 static void rl_init(xsc)
1510 struct rl_softc *sc = xsc;
1511 struct ifnet *ifp = &sc->arpcom.ac_if;
1512 struct mii_data *mii;
1514 u_int32_t rxcfg = 0;
1517 mii = device_get_softc(sc->rl_miibus);
1520 * Cancel pending I/O and free all RX/TX buffers.
1524 /* Init our MAC address */
1525 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1526 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1529 /* Init the RX buffer pointer register. */
1530 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1531 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1532 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1533 BUS_DMASYNC_PREWRITE);
1535 /* Init TX descriptors. */
1536 rl_list_tx_init(sc);
1539 * Enable transmit and receive.
1541 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1544 * Set the initial TX and RX configuration.
1546 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1547 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1549 /* Set the individual bit to receive frames for this host only. */
1550 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1551 rxcfg |= RL_RXCFG_RX_INDIV;
1553 /* If we want promiscuous mode, set the allframes bit. */
1554 if (ifp->if_flags & IFF_PROMISC) {
1555 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1556 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1558 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1559 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1563 * Set capture broadcast bit to capture broadcast frames.
1565 if (ifp->if_flags & IFF_BROADCAST) {
1566 rxcfg |= RL_RXCFG_RX_BROAD;
1567 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1569 rxcfg &= ~RL_RXCFG_RX_BROAD;
1570 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1574 * Program the multicast filter, if necessary.
1579 * Enable interrupts.
1581 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1583 /* Set initial TX threshold */
1584 sc->rl_txthresh = RL_TX_THRESH_INIT;
1586 /* Start RX/TX process. */
1587 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1589 /* Enable receiver and transmitter. */
1590 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1594 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1596 ifp->if_flags |= IFF_RUNNING;
1597 ifp->if_flags &= ~IFF_OACTIVE;
1599 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1606 * Set media options.
1608 static int rl_ifmedia_upd(ifp)
1611 struct rl_softc *sc;
1612 struct mii_data *mii;
1615 mii = device_get_softc(sc->rl_miibus);
1622 * Report current media status.
1624 static void rl_ifmedia_sts(ifp, ifmr)
1626 struct ifmediareq *ifmr;
1628 struct rl_softc *sc;
1629 struct mii_data *mii;
1632 mii = device_get_softc(sc->rl_miibus);
1635 ifmr->ifm_active = mii->mii_media_active;
1636 ifmr->ifm_status = mii->mii_media_status;
1641 static int rl_ioctl(ifp, command, data)
1646 struct rl_softc *sc = ifp->if_softc;
1647 struct ifreq *ifr = (struct ifreq *) data;
1648 struct mii_data *mii;
1657 error = ether_ioctl(ifp, command, data);
1660 if (ifp->if_flags & IFF_UP) {
1663 if (ifp->if_flags & IFF_RUNNING)
1675 mii = device_get_softc(sc->rl_miibus);
1676 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1688 static void rl_watchdog(ifp)
1691 struct rl_softc *sc;
1695 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1707 * Stop the adapter and free any mbufs allocated to the
1710 static void rl_stop(sc)
1711 struct rl_softc *sc;
1717 ifp = &sc->arpcom.ac_if;
1720 untimeout(rl_tick, sc, sc->rl_stat_ch);
1722 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1723 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1724 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1727 * Free the TX list buffers.
1729 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1730 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1731 bus_dmamap_unload(sc->rl_tag,
1732 sc->rl_cdata.rl_tx_dmamap[i]);
1733 bus_dmamap_destroy(sc->rl_tag,
1734 sc->rl_cdata.rl_tx_dmamap[i]);
1735 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1736 sc->rl_cdata.rl_tx_chain[i] = NULL;
1737 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1741 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1747 * Device suspend routine. Stop the interface and save some PCI
1748 * settings in case the BIOS doesn't restore them properly on
1751 static int rl_suspend(dev)
1755 struct rl_softc *sc;
1757 sc = device_get_softc(dev);
1761 for (i = 0; i < 5; i++)
1762 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
1763 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1764 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1765 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1766 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1774 * Device resume routine. Restore some PCI settings in case the BIOS
1775 * doesn't, re-enable busmastering, and restart the interface if
1778 static int rl_resume(dev)
1782 struct rl_softc *sc;
1785 sc = device_get_softc(dev);
1786 ifp = &sc->arpcom.ac_if;
1788 /* better way to do this? */
1789 for (i = 0; i < 5; i++)
1790 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
1791 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1792 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1793 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1794 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1796 /* reenable busmastering */
1797 pci_enable_busmaster(dev);
1798 pci_enable_io(dev, RL_RES);
1800 /* reinitialize interface if necessary */
1801 if (ifp->if_flags & IFF_UP)
1810 * Stop all chip I/O so that the kernel's probe routines don't
1811 * get confused by errant DMAs when rebooting.
1813 static void rl_shutdown(dev)
1816 struct rl_softc *sc;
1818 sc = device_get_softc(dev);