2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
86 #include <sys/param.h>
87 #include <sys/endian.h>
88 #include <sys/systm.h>
89 #include <sys/sockio.h>
91 #include <sys/malloc.h>
92 #include <sys/kernel.h>
93 #include <sys/module.h>
94 #include <sys/socket.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
105 #include <machine/bus.h>
106 #include <machine/resource.h>
108 #include <sys/rman.h>
110 #include <dev/mii/mii.h>
111 #include <dev/mii/miivar.h>
113 #include <dev/pci/pcireg.h>
114 #include <dev/pci/pcivar.h>
116 MODULE_DEPEND(rl, pci, 1, 1, 1);
117 MODULE_DEPEND(rl, ether, 1, 1, 1);
118 MODULE_DEPEND(rl, miibus, 1, 1, 1);
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
124 * Default to using PIO access for this driver. On SMP systems,
125 * there appear to be problems with memory mapped mode: it looks like
126 * doing too many memory mapped access back to back in rapid succession
127 * can hang the bus. I'm inclined to blame this on crummy design/construction
128 * on the part of RealTek. Memory mapped mode does appear to work on
129 * uniprocessor systems though.
131 #define RL_USEIOSPACE
133 #include <pci/if_rlreg.h>
136 * Various supported device vendors/types and their names.
138 static struct rl_type rl_devs[] = {
139 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
140 "RealTek 8129 10/100BaseTX" },
141 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
142 "RealTek 8139 10/100BaseTX" },
143 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
144 "RealTek 8139 10/100BaseTX CardBus" },
145 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
146 "RealTek 8100 10/100BaseTX" },
147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
148 "Accton MPX 5030/5038 10/100BaseTX" },
149 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
150 "Delta Electronics 8139 10/100BaseTX" },
151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
152 "Addtron Technolgy 8139 10/100BaseTX" },
153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
154 "D-Link DFE-530TX+ 10/100BaseTX" },
155 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
156 "D-Link DFE-690TXD 10/100BaseTX" },
157 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
158 "Nortel Networks 10/100BaseTX" },
159 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
160 "Corega FEther CB-TXD" },
161 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
162 "Corega FEtherII CB-TXD" },
163 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
164 "Peppercon AG ROL-F" },
165 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
166 "Planex FNW-3800-TX" },
167 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
169 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
170 "LevelOne FPC-0106TX" },
171 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
172 "Edimax EP-4103DL CardBus" },
176 static int rl_attach(device_t);
177 static int rl_detach(device_t);
178 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
179 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
180 static void rl_eeprom_putbyte(struct rl_softc *, int);
181 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
182 static int rl_encap(struct rl_softc *, struct mbuf * );
183 static int rl_list_tx_init(struct rl_softc *);
184 static int rl_ifmedia_upd(struct ifnet *);
185 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
186 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
187 static void rl_intr(void *);
188 static void rl_init(void *);
189 static void rl_init_locked(struct rl_softc *sc);
190 static void rl_mii_send(struct rl_softc *, uint32_t, int);
191 static void rl_mii_sync(struct rl_softc *);
192 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
193 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
194 static int rl_miibus_readreg(device_t, int, int);
195 static void rl_miibus_statchg(device_t);
196 static int rl_miibus_writereg(device_t, int, int, int);
197 #ifdef DEVICE_POLLING
198 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd,
200 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd,
203 static int rl_probe(device_t);
204 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
205 static void rl_reset(struct rl_softc *);
206 static int rl_resume(device_t);
207 static void rl_rxeof(struct rl_softc *);
208 static void rl_setmulti(struct rl_softc *);
209 static void rl_shutdown(device_t);
210 static void rl_start(struct ifnet *);
211 static void rl_start_locked(struct ifnet *);
212 static void rl_stop(struct rl_softc *);
213 static int rl_suspend(device_t);
214 static void rl_tick(void *);
215 static void rl_txeof(struct rl_softc *);
216 static void rl_watchdog(struct ifnet *);
219 #define RL_RES SYS_RES_IOPORT
220 #define RL_RID RL_PCI_LOIO
222 #define RL_RES SYS_RES_MEMORY
223 #define RL_RID RL_PCI_LOMEM
226 static device_method_t rl_methods[] = {
227 /* Device interface */
228 DEVMETHOD(device_probe, rl_probe),
229 DEVMETHOD(device_attach, rl_attach),
230 DEVMETHOD(device_detach, rl_detach),
231 DEVMETHOD(device_suspend, rl_suspend),
232 DEVMETHOD(device_resume, rl_resume),
233 DEVMETHOD(device_shutdown, rl_shutdown),
236 DEVMETHOD(bus_print_child, bus_generic_print_child),
237 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
240 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
241 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
242 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
247 static driver_t rl_driver = {
250 sizeof(struct rl_softc)
253 static devclass_t rl_devclass;
255 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
256 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
257 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
260 CSR_WRITE_1(sc, RL_EECMD, \
261 CSR_READ_1(sc, RL_EECMD) | x)
264 CSR_WRITE_1(sc, RL_EECMD, \
265 CSR_READ_1(sc, RL_EECMD) & ~x)
268 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
270 struct rl_softc *sc = arg;
272 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
276 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
278 struct rl_softc *sc = arg;
280 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
284 * Send a read command and address to the EEPROM, check for ACK.
287 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
291 d = addr | sc->rl_eecmd_read;
294 * Feed in each bit and strobe the clock.
296 for (i = 0x400; i; i >>= 1) {
298 EE_SET(RL_EE_DATAIN);
300 EE_CLR(RL_EE_DATAIN);
311 * Read a word of data stored in the EEPROM at address 'addr.'
314 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
319 /* Enter EEPROM access mode. */
320 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
323 * Send address of word we want to read.
325 rl_eeprom_putbyte(sc, addr);
327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
330 * Start reading bits from EEPROM.
332 for (i = 0x8000; i; i >>= 1) {
335 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
341 /* Turn off EEPROM access mode. */
342 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
348 * Read a sequence of words from the EEPROM.
351 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
354 uint16_t word = 0, *ptr;
356 for (i = 0; i < cnt; i++) {
357 rl_eeprom_getword(sc, off + i, &word);
358 ptr = (uint16_t *)(dest + (i * 2));
367 * MII access routines are provided for the 8129, which
368 * doesn't have a built-in PHY. For the 8139, we fake things
369 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
370 * direct access PHY registers.
373 CSR_WRITE_1(sc, RL_MII, \
374 CSR_READ_1(sc, RL_MII) | (x))
377 CSR_WRITE_1(sc, RL_MII, \
378 CSR_READ_1(sc, RL_MII) & ~(x))
381 * Sync the PHYs by setting data bit and strobing the clock 32 times.
384 rl_mii_sync(struct rl_softc *sc)
388 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
390 for (i = 0; i < 32; i++) {
399 * Clock a series of bits through the MII.
402 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
408 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
410 MII_SET(RL_MII_DATAOUT);
412 MII_CLR(RL_MII_DATAOUT);
422 * Read an PHY register through the MII.
425 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
431 /* Set up frame for RX. */
432 frame->mii_stdelim = RL_MII_STARTDELIM;
433 frame->mii_opcode = RL_MII_READOP;
434 frame->mii_turnaround = 0;
437 CSR_WRITE_2(sc, RL_MII, 0);
439 /* Turn on data xmit. */
444 /* Send command/address info. */
445 rl_mii_send(sc, frame->mii_stdelim, 2);
446 rl_mii_send(sc, frame->mii_opcode, 2);
447 rl_mii_send(sc, frame->mii_phyaddr, 5);
448 rl_mii_send(sc, frame->mii_regaddr, 5);
451 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
462 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
467 * Now try reading data bits. If the ack failed, we still
468 * need to clock through 16 cycles to keep the PHY(s) in sync.
471 for(i = 0; i < 16; i++) {
480 for (i = 0x8000; i; i >>= 1) {
484 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
485 frame->mii_data |= i;
500 return (ack ? 1 : 0);
504 * Write to a PHY register through the MII.
507 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
512 /* Set up frame for TX. */
513 frame->mii_stdelim = RL_MII_STARTDELIM;
514 frame->mii_opcode = RL_MII_WRITEOP;
515 frame->mii_turnaround = RL_MII_TURNAROUND;
517 /* Turn on data output. */
522 rl_mii_send(sc, frame->mii_stdelim, 2);
523 rl_mii_send(sc, frame->mii_opcode, 2);
524 rl_mii_send(sc, frame->mii_phyaddr, 5);
525 rl_mii_send(sc, frame->mii_regaddr, 5);
526 rl_mii_send(sc, frame->mii_turnaround, 2);
527 rl_mii_send(sc, frame->mii_data, 16);
544 rl_miibus_readreg(device_t dev, int phy, int reg)
547 struct rl_mii_frame frame;
549 uint16_t rl8139_reg = 0;
551 sc = device_get_softc(dev);
553 if (sc->rl_type == RL_8139) {
554 /* Pretend the internal PHY is only at address 0 */
560 rl8139_reg = RL_BMCR;
563 rl8139_reg = RL_BMSR;
566 rl8139_reg = RL_ANAR;
569 rl8139_reg = RL_ANER;
572 rl8139_reg = RL_LPAR;
578 * Allow the rlphy driver to read the media status
579 * register. If we have a link partner which does not
580 * support NWAY, this is the register which will tell
581 * us the results of parallel detection.
584 rval = CSR_READ_1(sc, RL_MEDIASTAT);
587 if_printf(sc->rl_ifp, "bad phy register\n");
590 rval = CSR_READ_2(sc, rl8139_reg);
594 bzero((char *)&frame, sizeof(frame));
595 frame.mii_phyaddr = phy;
596 frame.mii_regaddr = reg;
597 rl_mii_readreg(sc, &frame);
599 return (frame.mii_data);
603 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
606 struct rl_mii_frame frame;
607 uint16_t rl8139_reg = 0;
609 sc = device_get_softc(dev);
611 if (sc->rl_type == RL_8139) {
612 /* Pretend the internal PHY is only at address 0 */
618 rl8139_reg = RL_BMCR;
621 rl8139_reg = RL_BMSR;
624 rl8139_reg = RL_ANAR;
627 rl8139_reg = RL_ANER;
630 rl8139_reg = RL_LPAR;
637 if_printf(sc->rl_ifp, "bad phy register\n");
640 CSR_WRITE_2(sc, rl8139_reg, data);
644 bzero((char *)&frame, sizeof(frame));
645 frame.mii_phyaddr = phy;
646 frame.mii_regaddr = reg;
647 frame.mii_data = data;
648 rl_mii_writereg(sc, &frame);
654 rl_miibus_statchg(device_t dev)
659 * Program the 64-bit multicast hash filter.
662 rl_setmulti(struct rl_softc *sc)
664 struct ifnet *ifp = sc->rl_ifp;
666 uint32_t hashes[2] = { 0, 0 };
667 struct ifmultiaddr *ifma;
673 rxfilt = CSR_READ_4(sc, RL_RXCFG);
675 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
676 rxfilt |= RL_RXCFG_RX_MULTI;
677 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
678 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
679 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
683 /* first, zot all the existing hash bits */
684 CSR_WRITE_4(sc, RL_MAR0, 0);
685 CSR_WRITE_4(sc, RL_MAR4, 0);
687 /* now program new ones */
688 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
689 if (ifma->ifma_addr->sa_family != AF_LINK)
691 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
692 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
694 hashes[0] |= (1 << h);
696 hashes[1] |= (1 << (h - 32));
701 rxfilt |= RL_RXCFG_RX_MULTI;
703 rxfilt &= ~RL_RXCFG_RX_MULTI;
705 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
706 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
707 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
711 rl_reset(struct rl_softc *sc)
717 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
719 for (i = 0; i < RL_TIMEOUT; i++) {
721 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
725 if_printf(sc->rl_ifp, "reset never completed!\n");
729 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
730 * IDs against our list and return a device name if we find a match.
733 rl_probe(device_t dev)
736 struct rl_type *t = rl_devs;
740 sc = device_get_softc(dev);
742 while (t->rl_name != NULL) {
743 if ((pci_get_vendor(dev) == t->rl_vid) &&
744 (pci_get_device(dev) == t->rl_did)) {
746 * Temporarily map the I/O space
747 * so we can read the chip ID register.
750 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
752 if (sc->rl_res == NULL) {
754 "couldn't map ports/memory\n");
757 sc->rl_btag = rman_get_bustag(sc->rl_res);
758 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
760 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
761 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
763 /* Don't attach to 8139C+ or 8169/8110 chips. */
764 if (hwrev == RL_HWREV_8139CPLUS ||
765 (hwrev == RL_HWREV_8169 &&
766 t->rl_did == RT_DEVICEID_8169) ||
767 hwrev == RL_HWREV_8169S ||
768 hwrev == RL_HWREV_8110S) {
773 device_set_desc(dev, t->rl_name);
774 return (BUS_PROBE_DEFAULT);
783 * Attach the interface. Allocate softc structures, do ifmedia
784 * setup and ethernet/BPF attach.
787 rl_attach(device_t dev)
789 uint8_t eaddr[ETHER_ADDR_LEN];
794 int error = 0, i, rid;
798 sc = device_get_softc(dev);
799 unit = device_get_unit(dev);
801 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
804 pci_enable_busmaster(dev);
806 /* Map control/status registers. */
808 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
810 if (sc->rl_res == NULL) {
811 device_printf(dev, "couldn't map ports/memory\n");
818 * Detect the Realtek 8139B. For some reason, this chip is very
819 * unstable when left to autoselect the media
820 * The best workaround is to set the device to the required
821 * media type or to set it to the 10 Meg speed.
823 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
825 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
828 sc->rl_btag = rman_get_bustag(sc->rl_res);
829 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
831 /* Allocate interrupt */
833 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
834 RF_SHAREABLE | RF_ACTIVE);
836 if (sc->rl_irq == NULL) {
837 device_printf(dev, "couldn't map interrupt\n");
843 * Reset the adapter. Only take the lock here as it's needed in
844 * order to call rl_reset().
850 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
851 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
852 if (rl_did != 0x8129)
853 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
856 * Get station address from the EEPROM.
858 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
859 for (i = 0; i < 3; i++) {
860 eaddr[(i * 2) + 0] = as[i] & 0xff;
861 eaddr[(i * 2) + 1] = as[i] >> 8;
867 * Now read the exact device type from the EEPROM to find
868 * out if it's an 8129 or 8139.
870 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
874 while(t->rl_name != NULL) {
875 if (rl_did == t->rl_did) {
876 sc->rl_type = t->rl_basetype;
882 if (sc->rl_type == 0) {
883 device_printf(dev, "unknown device ID: %x\n", rl_did);
889 * Allocate the parent bus DMA tag appropriate for PCI.
891 #define RL_NSEG_NEW 32
892 error = bus_dma_tag_create(NULL, /* parent */
893 1, 0, /* alignment, boundary */
894 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
895 BUS_SPACE_MAXADDR, /* highaddr */
896 NULL, NULL, /* filter, filterarg */
897 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
898 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
899 BUS_DMA_ALLOCNOW, /* flags */
900 NULL, NULL, /* lockfunc, lockarg */
906 * Now allocate a tag for the DMA descriptor lists.
907 * All of our lists are allocated as a contiguous block
910 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
911 1, 0, /* alignment, boundary */
912 BUS_SPACE_MAXADDR, /* lowaddr */
913 BUS_SPACE_MAXADDR, /* highaddr */
914 NULL, NULL, /* filter, filterarg */
915 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
916 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
917 BUS_DMA_ALLOCNOW, /* flags */
918 NULL, NULL, /* lockfunc, lockarg */
924 * Now allocate a chunk of DMA-able memory based on the
925 * tag we just created.
927 error = bus_dmamem_alloc(sc->rl_tag,
928 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
929 &sc->rl_cdata.rl_rx_dmamap);
931 device_printf(dev, "no memory for list buffers!\n");
932 bus_dma_tag_destroy(sc->rl_tag);
937 /* Leave a few bytes before the start of the RX ring buffer. */
938 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
939 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
941 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
943 device_printf(dev, "can not if_alloc()\n");
949 if (mii_phy_probe(dev, &sc->rl_miibus,
950 rl_ifmedia_upd, rl_ifmedia_sts)) {
951 device_printf(dev, "MII without any phy!\n");
957 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
958 ifp->if_mtu = ETHERMTU;
959 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
960 ifp->if_ioctl = rl_ioctl;
961 ifp->if_start = rl_start;
962 ifp->if_watchdog = rl_watchdog;
963 ifp->if_init = rl_init;
964 ifp->if_baudrate = 10000000;
965 ifp->if_capabilities = IFCAP_VLAN_MTU;
966 #ifdef DEVICE_POLLING
967 ifp->if_capabilities |= IFCAP_POLLING;
969 ifp->if_capenable = ifp->if_capabilities;
970 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
971 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
972 IFQ_SET_READY(&ifp->if_snd);
974 callout_handle_init(&sc->rl_stat_ch);
977 * Call MI attach routine.
979 ether_ifattach(ifp, eaddr);
981 /* Hook interrupt last to avoid having to lock softc */
982 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
983 rl_intr, sc, &sc->rl_intrhand);
985 if_printf(ifp, "couldn't set up irq\n");
998 * Shutdown hardware and free up resources. This can be called any
999 * time after the mutex has been initialized. It is called in both
1000 * the error case in attach and the normal detach case so it needs
1001 * to be careful about only freeing resources that have actually been
1005 rl_detach(device_t dev)
1007 struct rl_softc *sc;
1011 sc = device_get_softc(dev);
1014 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1015 attached = device_is_attached(dev);
1016 /* These should only be active if attach succeeded */
1018 ether_ifdetach(ifp);
1028 device_delete_child(dev, sc->rl_miibus);
1029 bus_generic_detach(dev);
1031 if (sc->rl_intrhand)
1032 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1034 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1036 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1039 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1040 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1041 sc->rl_cdata.rl_rx_dmamap);
1042 bus_dma_tag_destroy(sc->rl_tag);
1044 if (sc->rl_parent_tag)
1045 bus_dma_tag_destroy(sc->rl_parent_tag);
1048 mtx_destroy(&sc->rl_mtx);
1054 * Initialize the transmit descriptors.
1057 rl_list_tx_init(struct rl_softc *sc)
1059 struct rl_chain_data *cd;
1065 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1066 cd->rl_tx_chain[i] = NULL;
1068 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1071 sc->rl_cdata.cur_tx = 0;
1072 sc->rl_cdata.last_tx = 0;
1078 * A frame has been uploaded: pass the resulting mbuf chain up to
1079 * the higher level protocols.
1081 * You know there's something wrong with a PCI bus-master chip design
1082 * when you have to use m_devget().
1084 * The receive operation is badly documented in the datasheet, so I'll
1085 * attempt to document it here. The driver provides a buffer area and
1086 * places its base address in the RX buffer start address register.
1087 * The chip then begins copying frames into the RX buffer. Each frame
1088 * is preceded by a 32-bit RX status word which specifies the length
1089 * of the frame and certain other status bits. Each frame (starting with
1090 * the status word) is also 32-bit aligned. The frame length is in the
1091 * first 16 bits of the status word; the lower 15 bits correspond with
1092 * the 'rx status register' mentioned in the datasheet.
1094 * Note: to make the Alpha happy, the frame payload needs to be aligned
1095 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1096 * as the offset argument to m_devget().
1099 rl_rxeof(struct rl_softc *sc)
1102 struct ifnet *ifp = sc->rl_ifp;
1109 uint16_t max_bytes, rx_bytes = 0;
1113 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1114 BUS_DMASYNC_POSTREAD);
1116 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1118 /* Do not try to read past this point. */
1119 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1122 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1124 max_bytes = limit - cur_rx;
1126 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1127 #ifdef DEVICE_POLLING
1128 if (ifp->if_flags & IFF_POLLING) {
1129 if (sc->rxcycles <= 0)
1133 #endif /* DEVICE_POLLING */
1134 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1135 rxstat = le32toh(*(uint32_t *)rxbufpos);
1138 * Here's a totally undocumented fact for you. When the
1139 * RealTek chip is in the process of copying a packet into
1140 * RAM for you, the length will be 0xfff0. If you spot a
1141 * packet header with this value, you need to stop. The
1142 * datasheet makes absolutely no mention of this and
1143 * RealTek should be shot for this.
1145 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1148 if (!(rxstat & RL_RXSTAT_RXOK)) {
1154 /* No errors; receive the packet. */
1155 total_len = rxstat >> 16;
1156 rx_bytes += total_len + 4;
1159 * XXX The RealTek chip includes the CRC with every
1160 * received frame, and there's no way to turn this
1161 * behavior off (at least, I can't find anything in
1162 * the manual that explains how to do it) so we have
1163 * to trim off the CRC manually.
1165 total_len -= ETHER_CRC_LEN;
1168 * Avoid trying to read more bytes than we know
1169 * the chip has prepared for us.
1171 if (rx_bytes > max_bytes)
1174 rxbufpos = sc->rl_cdata.rl_rx_buf +
1175 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1176 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1177 rxbufpos = sc->rl_cdata.rl_rx_buf;
1179 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1180 if (total_len > wrap) {
1181 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1186 m_copyback(m, wrap, total_len - wrap,
1187 sc->rl_cdata.rl_rx_buf);
1189 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1191 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1195 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1198 /* Round up to 32-bit boundary. */
1199 cur_rx = (cur_rx + 3) & ~3;
1200 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1207 (*ifp->if_input)(ifp, m);
1213 * A frame was downloaded to the chip. It's safe for us to clean up
1217 rl_txeof(struct rl_softc *sc)
1219 struct ifnet *ifp = sc->rl_ifp;
1225 * Go through our tx list and free mbufs for those
1226 * frames that have been uploaded.
1229 if (RL_LAST_TXMBUF(sc) == NULL)
1231 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1232 if (!(txstat & (RL_TXSTAT_TX_OK|
1233 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1236 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1238 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1239 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1240 m_freem(RL_LAST_TXMBUF(sc));
1241 RL_LAST_TXMBUF(sc) = NULL;
1243 * If there was a transmit underrun, bump the TX threshold.
1244 * Make sure not to overflow the 63 * 32byte we can address
1245 * with the 6 available bit.
1247 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1248 (sc->rl_txthresh < 2016))
1249 sc->rl_txthresh += 32;
1250 if (txstat & RL_TXSTAT_TX_OK)
1255 if ((txstat & RL_TXSTAT_TXABRT) ||
1256 (txstat & RL_TXSTAT_OUTOFWIN))
1257 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1258 oldthresh = sc->rl_txthresh;
1259 /* error recovery */
1262 /* restore original threshold */
1263 sc->rl_txthresh = oldthresh;
1266 RL_INC(sc->rl_cdata.last_tx);
1267 ifp->if_flags &= ~IFF_OACTIVE;
1268 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1270 if (RL_LAST_TXMBUF(sc) == NULL)
1272 else if (ifp->if_timer == 0)
1279 struct rl_softc *sc = xsc;
1280 struct mii_data *mii;
1283 mii = device_get_softc(sc->rl_miibus);
1286 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1290 #ifdef DEVICE_POLLING
1292 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1294 struct rl_softc *sc = ifp->if_softc;
1297 rl_poll_locked(ifp, cmd, count);
1302 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1304 struct rl_softc *sc = ifp->if_softc;
1308 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1309 ether_poll_deregister(ifp);
1310 cmd = POLL_DEREGISTER;
1313 if (cmd == POLL_DEREGISTER) {
1314 /* Final call; enable interrupts. */
1315 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1319 sc->rxcycles = count;
1323 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1324 rl_start_locked(ifp);
1326 if (cmd == POLL_AND_CHECK_STATUS) {
1329 /* We should also check the status register. */
1330 status = CSR_READ_2(sc, RL_ISR);
1331 if (status == 0xffff)
1334 CSR_WRITE_2(sc, RL_ISR, status);
1336 /* XXX We should check behaviour on receiver stalls. */
1338 if (status & RL_ISR_SYSTEM_ERR) {
1344 #endif /* DEVICE_POLLING */
1349 struct rl_softc *sc = arg;
1350 struct ifnet *ifp = sc->rl_ifp;
1358 #ifdef DEVICE_POLLING
1359 if (ifp->if_flags & IFF_POLLING)
1362 if ((ifp->if_capenable & IFCAP_POLLING) &&
1363 ether_poll_register(rl_poll, ifp)) {
1364 /* Disable interrupts. */
1365 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1366 rl_poll_locked(ifp, 0, 1);
1369 #endif /* DEVICE_POLLING */
1372 status = CSR_READ_2(sc, RL_ISR);
1373 /* If the card has gone away, the read returns 0xffff. */
1374 if (status == 0xffff)
1377 CSR_WRITE_2(sc, RL_ISR, status);
1378 if ((status & RL_INTRS) == 0)
1380 if (status & RL_ISR_RX_OK)
1382 if (status & RL_ISR_RX_ERR)
1384 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1386 if (status & RL_ISR_SYSTEM_ERR) {
1392 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1393 rl_start_locked(ifp);
1400 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1401 * pointers to the fragment pointers.
1404 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1406 struct mbuf *m_new = NULL;
1411 * The RealTek is brain damaged and wants longword-aligned
1412 * TX buffers, plus we can only have one fragment buffer
1413 * per packet. We have to copy pretty much all the time.
1415 m_new = m_defrag(m_head, M_DONTWAIT);
1417 if (m_new == NULL) {
1423 /* Pad frames to at least 60 bytes. */
1424 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1426 * Make security concious people happy: zero out the
1427 * bytes in the pad area, since we don't know what
1428 * this mbuf cluster buffer's previous user might
1431 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1432 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1433 m_head->m_pkthdr.len +=
1434 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1435 m_head->m_len = m_head->m_pkthdr.len;
1438 RL_CUR_TXMBUF(sc) = m_head;
1444 * Main transmit routine.
1447 rl_start(struct ifnet *ifp)
1449 struct rl_softc *sc = ifp->if_softc;
1452 rl_start_locked(ifp);
1457 rl_start_locked(struct ifnet *ifp)
1459 struct rl_softc *sc = ifp->if_softc;
1460 struct mbuf *m_head = NULL;
1464 while (RL_CUR_TXMBUF(sc) == NULL) {
1466 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1471 if (rl_encap(sc, m_head))
1474 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1475 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1477 /* Transmit the frame. */
1478 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1479 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1480 mtod(RL_CUR_TXMBUF(sc), void *),
1481 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1482 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1483 BUS_DMASYNC_PREREAD);
1484 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1485 RL_TXTHRESH(sc->rl_txthresh) |
1486 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1488 RL_INC(sc->rl_cdata.cur_tx);
1490 /* Set a timeout in case the chip goes out to lunch. */
1495 * We broke out of the loop because all our TX slots are
1496 * full. Mark the NIC as busy until it drains some of the
1497 * packets from the queue.
1499 if (RL_CUR_TXMBUF(sc) != NULL)
1500 ifp->if_flags |= IFF_OACTIVE;
1506 struct rl_softc *sc = xsc;
1514 rl_init_locked(struct rl_softc *sc)
1516 struct ifnet *ifp = sc->rl_ifp;
1517 struct mii_data *mii;
1522 mii = device_get_softc(sc->rl_miibus);
1525 * Cancel pending I/O and free all RX/TX buffers.
1530 * Init our MAC address. Even though the chipset
1531 * documentation doesn't mention it, we need to enter "Config
1532 * register write enable" mode to modify the ID registers.
1534 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1535 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1536 *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[0]));
1537 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1538 *(uint32_t *)(&IFP2ENADDR(sc->rl_ifp)[4]));
1539 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1541 /* Init the RX buffer pointer register. */
1542 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1543 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1544 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1545 BUS_DMASYNC_PREWRITE);
1547 /* Init TX descriptors. */
1548 rl_list_tx_init(sc);
1551 * Enable transmit and receive.
1553 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1556 * Set the initial TX and RX configuration.
1558 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1559 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1561 /* Set the individual bit to receive frames for this host only. */
1562 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1563 rxcfg |= RL_RXCFG_RX_INDIV;
1565 /* If we want promiscuous mode, set the allframes bit. */
1566 if (ifp->if_flags & IFF_PROMISC) {
1567 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1568 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1570 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1571 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1574 /* Set capture broadcast bit to capture broadcast frames. */
1575 if (ifp->if_flags & IFF_BROADCAST) {
1576 rxcfg |= RL_RXCFG_RX_BROAD;
1577 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1579 rxcfg &= ~RL_RXCFG_RX_BROAD;
1580 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1583 /* Program the multicast filter, if necessary. */
1586 #ifdef DEVICE_POLLING
1587 /* Disable interrupts if we are polling. */
1588 if (ifp->if_flags & IFF_POLLING)
1589 CSR_WRITE_2(sc, RL_IMR, 0);
1591 #endif /* DEVICE_POLLING */
1592 /* Enable interrupts. */
1593 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1595 /* Set initial TX threshold */
1596 sc->rl_txthresh = RL_TX_THRESH_INIT;
1598 /* Start RX/TX process. */
1599 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1601 /* Enable receiver and transmitter. */
1602 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1606 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1608 ifp->if_flags |= IFF_RUNNING;
1609 ifp->if_flags &= ~IFF_OACTIVE;
1611 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1615 * Set media options.
1618 rl_ifmedia_upd(struct ifnet *ifp)
1620 struct rl_softc *sc = ifp->if_softc;
1621 struct mii_data *mii;
1623 mii = device_get_softc(sc->rl_miibus);
1631 * Report current media status.
1634 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1636 struct rl_softc *sc = ifp->if_softc;
1637 struct mii_data *mii;
1639 mii = device_get_softc(sc->rl_miibus);
1642 ifmr->ifm_active = mii->mii_media_active;
1643 ifmr->ifm_status = mii->mii_media_status;
1647 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1649 struct ifreq *ifr = (struct ifreq *)data;
1650 struct mii_data *mii;
1651 struct rl_softc *sc = ifp->if_softc;
1657 if (ifp->if_flags & IFF_UP) {
1660 if (ifp->if_flags & IFF_RUNNING)
1675 mii = device_get_softc(sc->rl_miibus);
1676 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1679 ifp->if_capenable &= ~IFCAP_POLLING;
1680 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING;
1683 error = ether_ioctl(ifp, command, data);
1691 rl_watchdog(struct ifnet *ifp)
1693 struct rl_softc *sc = ifp->if_softc;
1697 if_printf(ifp, "watchdog timeout\n");
1708 * Stop the adapter and free any mbufs allocated to the
1712 rl_stop(struct rl_softc *sc)
1715 struct ifnet *ifp = sc->rl_ifp;
1720 untimeout(rl_tick, sc, sc->rl_stat_ch);
1721 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1722 #ifdef DEVICE_POLLING
1723 ether_poll_deregister(ifp);
1724 #endif /* DEVICE_POLLING */
1726 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1727 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1728 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1731 * Free the TX list buffers.
1733 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1734 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1735 bus_dmamap_unload(sc->rl_tag,
1736 sc->rl_cdata.rl_tx_dmamap[i]);
1737 bus_dmamap_destroy(sc->rl_tag,
1738 sc->rl_cdata.rl_tx_dmamap[i]);
1739 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1740 sc->rl_cdata.rl_tx_chain[i] = NULL;
1741 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1748 * Device suspend routine. Stop the interface and save some PCI
1749 * settings in case the BIOS doesn't restore them properly on
1753 rl_suspend(device_t dev)
1755 struct rl_softc *sc;
1757 sc = device_get_softc(dev);
1768 * Device resume routine. Restore some PCI settings in case the BIOS
1769 * doesn't, re-enable busmastering, and restart the interface if
1773 rl_resume(device_t dev)
1775 struct rl_softc *sc;
1778 sc = device_get_softc(dev);
1783 /* reinitialize interface if necessary */
1784 if (ifp->if_flags & IFF_UP)
1795 * Stop all chip I/O so that the kernel's probe routines don't
1796 * get confused by errant DMAs when rebooting.
1799 rl_shutdown(device_t dev)
1801 struct rl_softc *sc;
1803 sc = device_get_softc(dev);