2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $Id: if_rl.c,v 1.18 1999/07/02 04:17:14 peter Exp $
36 * RealTek 8129/8139 PCI NIC driver
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
92 #include <sys/malloc.h>
93 #include <sys/kernel.h>
94 #include <sys/socket.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
106 #include <vm/vm.h> /* for vtophys */
107 #include <vm/pmap.h> /* for vtophys */
108 #include <machine/clock.h> /* for DELAY */
109 #include <machine/bus_pio.h>
110 #include <machine/bus_memio.h>
111 #include <machine/bus.h>
113 #include <pci/pcireg.h>
114 #include <pci/pcivar.h>
117 * Default to using PIO access for this driver. On SMP systems,
118 * there appear to be problems with memory mapped mode: it looks like
119 * doing too many memory mapped access back to back in rapid succession
120 * can hang the bus. I'm inclined to blame this on crummy design/construction
121 * on the part of RealTek. Memory mapped mode does appear to work on
122 * uniprocessor systems though.
124 #define RL_USEIOSPACE
126 #include <pci/if_rlreg.h>
129 static const char rcsid[] =
130 "$Id: if_rl.c,v 1.18 1999/07/02 04:17:14 peter Exp $";
134 * Various supported device vendors/types and their names.
136 static struct rl_type rl_devs[] = {
137 { RT_VENDORID, RT_DEVICEID_8129,
138 "RealTek 8129 10/100BaseTX" },
139 { RT_VENDORID, RT_DEVICEID_8139,
140 "RealTek 8139 10/100BaseTX" },
141 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
142 "Accton MPX 5030/5038 10/100BaseTX" },
143 { DELTA_VENDORID, DELTA_DEVICEID_8139,
144 "Delta Electronics 8139 10/100BaseTX" },
145 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
146 "Addtron Technolgy 8139 10/100BaseTX" },
147 { SIS_VENDORID, SIS_DEVICEID_8139,
148 "SiS 900 10/100BaseTX" },
153 * Various supported PHY vendors/types and their names. Note that
154 * this driver will work with pretty much any MII-compliant PHY,
155 * so failure to positively identify the chip is not a fatal error.
158 static struct rl_type rl_phys[] = {
159 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
160 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
161 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
162 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" },
163 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
164 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
165 { 0, 0, "<MII-compliant physical interface>" }
168 static unsigned long rl_count = 0;
169 static const char *rl_probe __P((pcici_t, pcidi_t));
170 static void rl_attach __P((pcici_t, int));
172 static int rl_encap __P((struct rl_softc *, struct mbuf * ));
174 static void rl_rxeof __P((struct rl_softc *));
175 static void rl_txeof __P((struct rl_softc *));
176 static void rl_intr __P((void *));
177 static void rl_start __P((struct ifnet *));
178 static int rl_ioctl __P((struct ifnet *, u_long, caddr_t));
179 static void rl_init __P((void *));
180 static void rl_stop __P((struct rl_softc *));
181 static void rl_watchdog __P((struct ifnet *));
182 static void rl_shutdown __P((int, void *));
183 static int rl_ifmedia_upd __P((struct ifnet *));
184 static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
186 static void rl_eeprom_putbyte __P((struct rl_softc *, int));
187 static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *));
188 static void rl_read_eeprom __P((struct rl_softc *, caddr_t,
190 static void rl_mii_sync __P((struct rl_softc *));
191 static void rl_mii_send __P((struct rl_softc *, u_int32_t, int));
192 static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *));
193 static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *));
195 static u_int16_t rl_phy_readreg __P((struct rl_softc *, int));
196 static void rl_phy_writereg __P((struct rl_softc *, int, int));
198 static void rl_autoneg_xmit __P((struct rl_softc *));
199 static void rl_autoneg_mii __P((struct rl_softc *, int, int));
200 static void rl_setmode_mii __P((struct rl_softc *, int));
201 static void rl_getmode_mii __P((struct rl_softc *));
202 static u_int8_t rl_calchash __P((caddr_t));
203 static void rl_setmulti __P((struct rl_softc *));
204 static void rl_reset __P((struct rl_softc *));
205 static int rl_list_tx_init __P((struct rl_softc *));
208 CSR_WRITE_1(sc, RL_EECMD, \
209 CSR_READ_1(sc, RL_EECMD) | x)
212 CSR_WRITE_1(sc, RL_EECMD, \
213 CSR_READ_1(sc, RL_EECMD) & ~x)
216 * Send a read command and address to the EEPROM, check for ACK.
218 static void rl_eeprom_putbyte(sc, addr)
224 d = addr | RL_EECMD_READ;
227 * Feed in each bit and stobe the clock.
229 for (i = 0x400; i; i >>= 1) {
231 EE_SET(RL_EE_DATAIN);
233 EE_CLR(RL_EE_DATAIN);
246 * Read a word of data stored in the EEPROM at address 'addr.'
248 static void rl_eeprom_getword(sc, addr, dest)
256 /* Enter EEPROM access mode. */
257 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
260 * Send address of word we want to read.
262 rl_eeprom_putbyte(sc, addr);
264 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
267 * Start reading bits from EEPROM.
269 for (i = 0x8000; i; i >>= 1) {
272 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
278 /* Turn off EEPROM access mode. */
279 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
287 * Read a sequence of words from the EEPROM.
289 static void rl_read_eeprom(sc, dest, off, cnt, swap)
297 u_int16_t word = 0, *ptr;
299 for (i = 0; i < cnt; i++) {
300 rl_eeprom_getword(sc, off + i, &word);
301 ptr = (u_int16_t *)(dest + (i * 2));
313 * MII access routines are provided for the 8129, which
314 * doesn't have a built-in PHY. For the 8139, we fake things
315 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
316 * direct access PHY registers.
319 CSR_WRITE_1(sc, RL_MII, \
320 CSR_READ_1(sc, RL_MII) | x)
323 CSR_WRITE_1(sc, RL_MII, \
324 CSR_READ_1(sc, RL_MII) & ~x)
327 * Sync the PHYs by setting data bit and strobing the clock 32 times.
329 static void rl_mii_sync(sc)
334 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
336 for (i = 0; i < 32; i++) {
347 * Clock a series of bits through the MII.
349 static void rl_mii_send(sc, bits, cnt)
358 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
360 MII_SET(RL_MII_DATAOUT);
362 MII_CLR(RL_MII_DATAOUT);
372 * Read an PHY register through the MII.
374 static int rl_mii_readreg(sc, frame)
376 struct rl_mii_frame *frame;
384 * Set up frame for RX.
386 frame->mii_stdelim = RL_MII_STARTDELIM;
387 frame->mii_opcode = RL_MII_READOP;
388 frame->mii_turnaround = 0;
391 CSR_WRITE_2(sc, RL_MII, 0);
401 * Send command/address info.
403 rl_mii_send(sc, frame->mii_stdelim, 2);
404 rl_mii_send(sc, frame->mii_opcode, 2);
405 rl_mii_send(sc, frame->mii_phyaddr, 5);
406 rl_mii_send(sc, frame->mii_regaddr, 5);
409 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
422 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
425 * Now try reading data bits. If the ack failed, we still
426 * need to clock through 16 cycles to keep the PHY(s) in sync.
429 for(i = 0; i < 16; i++) {
438 for (i = 0x8000; i; i >>= 1) {
442 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
443 frame->mii_data |= i;
465 * Write to a PHY register through the MII.
467 static int rl_mii_writereg(sc, frame)
469 struct rl_mii_frame *frame;
476 * Set up frame for TX.
479 frame->mii_stdelim = RL_MII_STARTDELIM;
480 frame->mii_opcode = RL_MII_WRITEOP;
481 frame->mii_turnaround = RL_MII_TURNAROUND;
484 * Turn on data output.
490 rl_mii_send(sc, frame->mii_stdelim, 2);
491 rl_mii_send(sc, frame->mii_opcode, 2);
492 rl_mii_send(sc, frame->mii_phyaddr, 5);
493 rl_mii_send(sc, frame->mii_regaddr, 5);
494 rl_mii_send(sc, frame->mii_turnaround, 2);
495 rl_mii_send(sc, frame->mii_data, 16);
513 static u_int16_t rl_phy_readreg(sc, reg)
517 struct rl_mii_frame frame;
519 u_int16_t rl8139_reg = 0;
521 if (sc->rl_type == RL_8139) {
524 rl8139_reg = RL_BMCR;
527 rl8139_reg = RL_BMSR;
530 rl8139_reg = RL_ANAR;
533 rl8139_reg = RL_LPAR;
536 printf("rl%d: bad phy register\n", sc->rl_unit);
539 rval = CSR_READ_2(sc, rl8139_reg);
543 bzero((char *)&frame, sizeof(frame));
545 frame.mii_phyaddr = sc->rl_phy_addr;
546 frame.mii_regaddr = reg;
547 rl_mii_readreg(sc, &frame);
549 return(frame.mii_data);
552 static void rl_phy_writereg(sc, reg, data)
557 struct rl_mii_frame frame;
558 u_int16_t rl8139_reg = 0;
560 if (sc->rl_type == RL_8139) {
563 rl8139_reg = RL_BMCR;
566 rl8139_reg = RL_BMSR;
569 rl8139_reg = RL_ANAR;
572 rl8139_reg = RL_LPAR;
575 printf("rl%d: bad phy register\n", sc->rl_unit);
578 CSR_WRITE_2(sc, rl8139_reg, data);
582 bzero((char *)&frame, sizeof(frame));
584 frame.mii_phyaddr = sc->rl_phy_addr;
585 frame.mii_regaddr = reg;
586 frame.mii_data = data;
588 rl_mii_writereg(sc, &frame);
594 * Calculate CRC of a multicast group address, return the upper 6 bits.
596 static u_int8_t rl_calchash(addr)
599 u_int32_t crc, carry;
603 /* Compute CRC for the address value. */
604 crc = 0xFFFFFFFF; /* initial value */
606 for (i = 0; i < 6; i++) {
608 for (j = 0; j < 8; j++) {
609 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
613 crc = (crc ^ 0x04c11db6) | carry;
617 /* return the filter bit position */
622 * Program the 64-bit multicast hash filter.
624 static void rl_setmulti(sc)
629 u_int32_t hashes[2] = { 0, 0 };
630 struct ifmultiaddr *ifma;
634 ifp = &sc->arpcom.ac_if;
636 rxfilt = CSR_READ_4(sc, RL_RXCFG);
638 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
639 rxfilt |= RL_RXCFG_RX_MULTI;
640 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
641 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
642 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
646 /* first, zot all the existing hash bits */
647 CSR_WRITE_4(sc, RL_MAR0, 0);
648 CSR_WRITE_4(sc, RL_MAR4, 0);
650 /* now program new ones */
651 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
652 ifma = ifma->ifma_link.le_next) {
653 if (ifma->ifma_addr->sa_family != AF_LINK)
655 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
657 hashes[0] |= (1 << h);
659 hashes[1] |= (1 << (h - 32));
664 rxfilt |= RL_RXCFG_RX_MULTI;
666 rxfilt &= ~RL_RXCFG_RX_MULTI;
668 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
669 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
670 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
676 * Initiate an autonegotiation session.
678 static void rl_autoneg_xmit(sc)
683 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
685 while(rl_phy_readreg(sc, PHY_BMCR)
688 phy_sts = rl_phy_readreg(sc, PHY_BMCR);
689 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
690 rl_phy_writereg(sc, PHY_BMCR, phy_sts);
696 * Invoke autonegotiation on a PHY. Also used with the 8139 internal
699 static void rl_autoneg_mii(sc, flag, verbose)
704 u_int16_t phy_sts = 0, media, advert, ability;
709 ifp = &sc->arpcom.ac_if;
712 * The 100baseT4 PHY sometimes has the 'autoneg supported'
713 * bit cleared in the status register, but has the 'autoneg enabled'
714 * bit set in the control register. This is a contradiction, and
715 * I'm not sure how to handle it. If you want to force an attempt
716 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
717 * and see what happens.
719 #ifndef FORCE_AUTONEG_TFOUR
721 * First, see if autoneg is supported. If not, there's
722 * no point in continuing.
724 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
725 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
727 printf("rl%d: autonegotiation not supported\n",
734 case RL_FLAG_FORCEDELAY:
736 * XXX Never use this option anywhere but in the probe
737 * routine: making the kernel stop dead in its tracks
738 * for three whole seconds after we've gone multi-user
739 * is really bad manners.
744 case RL_FLAG_SCHEDDELAY:
746 * Wait for the transmitter to go idle before starting
747 * an autoneg session, otherwise rl_start() may clobber
748 * our timeout, and we don't want to allow transmission
749 * during an autoneg session since that can screw it up.
751 if (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx) {
752 sc->rl_want_auto = 1;
758 sc->rl_want_auto = 0;
761 case RL_FLAG_DELAYTIMEO:
766 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag);
770 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
772 printf("rl%d: autoneg complete, ", sc->rl_unit);
773 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
776 printf("rl%d: autoneg not complete, ", sc->rl_unit);
779 media = rl_phy_readreg(sc, PHY_BMCR);
781 /* Link is good. Report modes and set duplex mode. */
782 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
784 printf("link status good ");
785 advert = rl_phy_readreg(sc, PHY_ANAR);
786 ability = rl_phy_readreg(sc, PHY_LPAR);
788 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
789 ifm->ifm_media = IFM_ETHER|IFM_100_T4;
790 media |= PHY_BMCR_SPEEDSEL;
791 media &= ~PHY_BMCR_DUPLEX;
792 printf("(100baseT4)\n");
793 } else if (advert & PHY_ANAR_100BTXFULL &&
794 ability & PHY_ANAR_100BTXFULL) {
795 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
796 media |= PHY_BMCR_SPEEDSEL;
797 media |= PHY_BMCR_DUPLEX;
798 printf("(full-duplex, 100Mbps)\n");
799 } else if (advert & PHY_ANAR_100BTXHALF &&
800 ability & PHY_ANAR_100BTXHALF) {
801 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
802 media |= PHY_BMCR_SPEEDSEL;
803 media &= ~PHY_BMCR_DUPLEX;
804 printf("(half-duplex, 100Mbps)\n");
805 } else if (advert & PHY_ANAR_10BTFULL &&
806 ability & PHY_ANAR_10BTFULL) {
807 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
808 media &= ~PHY_BMCR_SPEEDSEL;
809 media |= PHY_BMCR_DUPLEX;
810 printf("(full-duplex, 10Mbps)\n");
812 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
813 media &= ~PHY_BMCR_SPEEDSEL;
814 media &= ~PHY_BMCR_DUPLEX;
815 printf("(half-duplex, 10Mbps)\n");
818 /* Set ASIC's duplex mode to match the PHY. */
819 rl_phy_writereg(sc, PHY_BMCR, media);
822 printf("no carrier\n");
827 if (sc->rl_tx_pend) {
836 static void rl_getmode_mii(sc)
842 ifp = &sc->arpcom.ac_if;
844 bmsr = rl_phy_readreg(sc, PHY_BMSR);
846 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr);
849 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
851 if (bmsr & PHY_BMSR_10BTHALF) {
853 printf("rl%d: 10Mbps half-duplex mode supported\n",
855 ifmedia_add(&sc->ifmedia,
856 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
857 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
860 if (bmsr & PHY_BMSR_10BTFULL) {
862 printf("rl%d: 10Mbps full-duplex mode supported\n",
864 ifmedia_add(&sc->ifmedia,
865 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
866 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
869 if (bmsr & PHY_BMSR_100BTXHALF) {
871 printf("rl%d: 100Mbps half-duplex mode supported\n",
873 ifp->if_baudrate = 100000000;
874 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
875 ifmedia_add(&sc->ifmedia,
876 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
877 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
880 if (bmsr & PHY_BMSR_100BTXFULL) {
882 printf("rl%d: 100Mbps full-duplex mode supported\n",
884 ifp->if_baudrate = 100000000;
885 ifmedia_add(&sc->ifmedia,
886 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
887 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
890 /* Some also support 100BaseT4. */
891 if (bmsr & PHY_BMSR_100BT4) {
893 printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit);
894 ifp->if_baudrate = 100000000;
895 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
896 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
897 #ifdef FORCE_AUTONEG_TFOUR
899 printf("rl%d: forcing on autoneg support for BT4\n",
901 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
902 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
906 if (bmsr & PHY_BMSR_CANAUTONEG) {
908 printf("rl%d: autoneg supported\n", sc->rl_unit);
909 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
910 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
917 * Set speed and duplex mode.
919 static void rl_setmode_mii(sc, media)
925 printf("rl%d: selecting MII, ", sc->rl_unit);
927 bmcr = rl_phy_readreg(sc, PHY_BMCR);
929 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
930 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
932 if (IFM_SUBTYPE(media) == IFM_100_T4) {
933 printf("100Mbps/T4, half-duplex\n");
934 bmcr |= PHY_BMCR_SPEEDSEL;
935 bmcr &= ~PHY_BMCR_DUPLEX;
938 if (IFM_SUBTYPE(media) == IFM_100_TX) {
940 bmcr |= PHY_BMCR_SPEEDSEL;
943 if (IFM_SUBTYPE(media) == IFM_10_T) {
945 bmcr &= ~PHY_BMCR_SPEEDSEL;
948 if ((media & IFM_GMASK) == IFM_FDX) {
949 printf("full duplex\n");
950 bmcr |= PHY_BMCR_DUPLEX;
952 printf("half duplex\n");
953 bmcr &= ~PHY_BMCR_DUPLEX;
956 rl_phy_writereg(sc, PHY_BMCR, bmcr);
961 static void rl_reset(sc)
966 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
968 for (i = 0; i < RL_TIMEOUT; i++) {
970 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
974 printf("rl%d: reset never completed!\n", sc->rl_unit);
980 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
981 * IDs against our list and return a device name if we find a match.
984 rl_probe(config_id, device_id)
992 while(t->rl_name != NULL) {
993 if ((device_id & 0xFFFF) == t->rl_vid &&
994 ((device_id >> 16) & 0xFFFF) == t->rl_did) {
1004 * Attach the interface. Allocate softc structures, do ifmedia
1005 * setup and ethernet/BPF attach.
1008 rl_attach(config_id, unit)
1013 #ifndef RL_USEIOSPACE
1014 vm_offset_t pbase, vbase;
1016 u_char eaddr[ETHER_ADDR_LEN];
1018 struct rl_softc *sc;
1020 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1022 u_int16_t phy_vid, phy_did, phy_sts;
1023 u_int16_t rl_did = 0;
1027 sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT);
1029 printf("rl%d: no memory for softc struct!\n", unit);
1032 bzero(sc, sizeof(struct rl_softc));
1035 * Handle power management nonsense.
1038 command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF;
1039 if (command == 0x01) {
1041 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL);
1042 if (command & RL_PSTATE_MASK) {
1043 u_int32_t iobase, membase, irq;
1045 /* Save important PCI config data. */
1046 iobase = pci_conf_read(config_id, RL_PCI_LOIO);
1047 membase = pci_conf_read(config_id, RL_PCI_LOMEM);
1048 irq = pci_conf_read(config_id, RL_PCI_INTLINE);
1050 /* Reset the power state. */
1051 printf("rl%d: chip is is in D%d power mode "
1052 "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
1053 command &= 0xFFFFFFFC;
1054 pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command);
1056 /* Restore PCI config data. */
1057 pci_conf_write(config_id, RL_PCI_LOIO, iobase);
1058 pci_conf_write(config_id, RL_PCI_LOMEM, membase);
1059 pci_conf_write(config_id, RL_PCI_INTLINE, irq);
1064 * Map control/status registers.
1066 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1067 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1068 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1069 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1071 #ifdef RL_USEIOSPACE
1072 if (!(command & PCIM_CMD_PORTEN)) {
1073 printf("rl%d: failed to enable I/O ports!\n", unit);
1078 if (!pci_map_port(config_id, RL_PCI_LOIO,
1079 (pci_port_t *)&(sc->rl_bhandle))) {
1080 printf ("rl%d: couldn't map ports\n", unit);
1084 sc->rl_btag = I386_BUS_SPACE_IO;
1087 sc->rl_btag = ALPHA_BUS_SPACE_IO;
1090 if (!(command & PCIM_CMD_MEMEN)) {
1091 printf("rl%d: failed to enable memory mapping!\n", unit);
1095 if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) {
1096 printf ("rl%d: couldn't map memory\n", unit);
1100 sc->rl_btag = I386_BUS_SPACE_MEM;
1103 sc->rl_btag = ALPHA_BUS_SPACE_MEM;
1105 sc->rl_bhandle = vbase;
1108 /* Allocate interrupt */
1109 if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) {
1110 printf("rl%d: couldn't map interrupt\n", unit);
1114 /* Reset the adapter. */
1118 * Get station address from the EEPROM.
1120 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
1123 * A RealTek chip was detected. Inform the world.
1125 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1128 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1131 * Now read the exact device type from the EEPROM to find
1132 * out if it's an 8129 or 8139.
1134 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1136 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
1137 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
1138 rl_did == SIS_DEVICEID_8139)
1139 sc->rl_type = RL_8139;
1140 else if (rl_did == RT_DEVICEID_8129)
1141 sc->rl_type = RL_8129;
1143 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1148 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 32, M_DEVBUF,
1149 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
1151 if (sc->rl_cdata.rl_rx_buf == NULL) {
1153 printf("rl%d: no memory for list buffers!\n", unit);
1157 /* Leave a few bytes before the start of the RX ring buffer. */
1158 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1159 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1161 ifp = &sc->arpcom.ac_if;
1163 ifp->if_unit = unit;
1164 ifp->if_name = "rl";
1165 ifp->if_mtu = ETHERMTU;
1166 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1167 ifp->if_ioctl = rl_ioctl;
1168 ifp->if_output = ether_output;
1169 ifp->if_start = rl_start;
1170 ifp->if_watchdog = rl_watchdog;
1171 ifp->if_init = rl_init;
1172 ifp->if_baudrate = 10000000;
1173 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1175 if (sc->rl_type == RL_8129) {
1177 printf("rl%d: probing for a PHY\n", sc->rl_unit);
1178 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) {
1180 printf("rl%d: checking address: %d\n",
1182 sc->rl_phy_addr = i;
1183 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1185 while(rl_phy_readreg(sc, PHY_BMCR)
1187 if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR)))
1191 phy_vid = rl_phy_readreg(sc, PHY_VENID);
1192 phy_did = rl_phy_readreg(sc, PHY_DEVID);
1194 printf("rl%d: found PHY at address %d, ",
1195 sc->rl_unit, sc->rl_phy_addr);
1197 printf("vendor id: %x device id: %x\n",
1201 if (phy_vid == p->rl_vid &&
1202 (phy_did | 0x000F) == p->rl_did) {
1208 if (sc->rl_pinfo == NULL)
1209 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN];
1211 printf("rl%d: PHY type: %s\n",
1212 sc->rl_unit, sc->rl_pinfo->rl_name);
1214 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1221 ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts);
1225 /* Choose a default media. */
1226 media = IFM_ETHER|IFM_AUTO;
1227 ifmedia_set(&sc->ifmedia, media);
1229 rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1);
1232 * Call MI attach routines.
1235 ether_ifattach(ifp);
1238 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1240 at_shutdown(rl_shutdown, sc, SHUTDOWN_POST_SYNC);
1248 * Initialize the transmit descriptors.
1250 static int rl_list_tx_init(sc)
1251 struct rl_softc *sc;
1253 struct rl_chain_data *cd;
1257 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1258 cd->rl_tx_chain[i] = NULL;
1260 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1263 sc->rl_cdata.cur_tx = 0;
1264 sc->rl_cdata.last_tx = 0;
1270 * A frame has been uploaded: pass the resulting mbuf chain up to
1271 * the higher level protocols.
1273 * You know there's something wrong with a PCI bus-master chip design
1274 * when you have to use m_devget().
1276 * The receive operation is badly documented in the datasheet, so I'll
1277 * attempt to document it here. The driver provides a buffer area and
1278 * places its base address in the RX buffer start address register.
1279 * The chip then begins copying frames into the RX buffer. Each frame
1280 * is preceeded by a 32-bit RX status word which specifies the length
1281 * of the frame and certain other status bits. Each frame (starting with
1282 * the status word) is also 32-bit aligned. The frame length is in the
1283 * first 16 bits of the status word; the lower 15 bits correspond with
1284 * the 'rx status register' mentioned in the datasheet.
1286 * Note: to make the Alpha happy, the frame payload needs to be aligned
1287 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1288 * the ring buffer starting at an address two bytes before the actual
1289 * data location. We can then shave off the first two bytes using m_adj().
1290 * The reason we do this is because m_devget() doesn't let us specify an
1291 * offset into the mbuf storage space, so we have to artificially create
1292 * one. The ring is allocated in such a way that there are a few unused
1293 * bytes of space preceecing it so that it will be safe for us to do the
1294 * 2-byte backstep even if reading from the ring at offset 0.
1296 static void rl_rxeof(sc)
1297 struct rl_softc *sc;
1299 struct ether_header *eh;
1308 u_int16_t rx_bytes = 0, max_bytes;
1310 ifp = &sc->arpcom.ac_if;
1312 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1314 /* Do not try to read past this point. */
1315 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1318 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1320 max_bytes = limit - cur_rx;
1322 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1323 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1324 rxstat = *(u_int32_t *)rxbufpos;
1327 * Here's a totally undocumented fact for you. When the
1328 * RealTek chip is in the process of copying a packet into
1329 * RAM for you, the length will be 0xfff0. If you spot a
1330 * packet header with this value, you need to stop. The
1331 * datasheet makes absolutely no mention of this and
1332 * RealTek should be shot for this.
1334 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1337 if (!(rxstat & RL_RXSTAT_RXOK)) {
1339 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT|
1340 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR|
1341 RL_RXSTAT_ALIGNERR)) {
1342 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB);
1343 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB|
1345 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1346 CSR_WRITE_4(sc, RL_RXADDR,
1347 vtophys(sc->rl_cdata.rl_rx_buf));
1348 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1354 /* No errors; receive the packet. */
1355 total_len = rxstat >> 16;
1356 rx_bytes += total_len + 4;
1359 * XXX The RealTek chip includes the CRC with every
1360 * received frame, and there's no way to turn this
1361 * behavior off (at least, I can't find anything in
1362 * the manual that explains how to do it) so we have
1363 * to trim off the CRC manually.
1365 total_len -= ETHER_CRC_LEN;
1368 * Avoid trying to read more bytes than we know
1369 * the chip has prepared for us.
1371 if (rx_bytes > max_bytes)
1374 rxbufpos = sc->rl_cdata.rl_rx_buf +
1375 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1377 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1378 rxbufpos = sc->rl_cdata.rl_rx_buf;
1380 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1382 if (total_len > wrap) {
1383 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1384 wrap + RL_ETHER_ALIGN, 0, ifp, NULL);
1387 printf("rl%d: out of mbufs, tried to "
1388 "copy %d bytes\n", sc->rl_unit, wrap);
1391 m_adj(m, RL_ETHER_ALIGN);
1392 m_copyback(m, wrap, total_len - wrap,
1393 sc->rl_cdata.rl_rx_buf);
1395 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1397 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1398 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1401 printf("rl%d: out of mbufs, tried to "
1402 "copy %d bytes\n", sc->rl_unit, total_len);
1404 m_adj(m, RL_ETHER_ALIGN);
1405 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1409 * Round up to 32-bit boundary.
1411 cur_rx = (cur_rx + 3) & ~3;
1412 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1417 eh = mtod(m, struct ether_header *);
1422 * Handle BPF listeners. Let the BPF user see the packet, but
1423 * don't pass it up to the ether_input() layer unless it's
1424 * a broadcast packet, multicast packet, matches our ethernet
1425 * address or the interface is in promiscuous mode.
1429 if (ifp->if_flags & IFF_PROMISC &&
1430 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1432 (eh->ether_dhost[0] & 1) == 0)) {
1438 /* Remove header from mbuf and pass it on. */
1439 m_adj(m, sizeof(struct ether_header));
1440 ether_input(ifp, eh, m);
1447 * A frame was downloaded to the chip. It's safe for us to clean up
1450 static void rl_txeof(sc)
1451 struct rl_softc *sc;
1456 ifp = &sc->arpcom.ac_if;
1458 /* Clear the timeout timer. */
1462 * Go through our tx list and free mbufs for those
1463 * frames that have been uploaded.
1466 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1467 if (!(txstat & (RL_TXSTAT_TX_OK|
1468 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1471 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1473 if (RL_LAST_TXMBUF(sc) != NULL) {
1474 m_freem(RL_LAST_TXMBUF(sc));
1475 RL_LAST_TXMBUF(sc) = NULL;
1477 if (txstat & RL_TXSTAT_TX_OK)
1481 if ((txstat & RL_TXSTAT_TXABRT) ||
1482 (txstat & RL_TXSTAT_OUTOFWIN))
1483 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1485 RL_INC(sc->rl_cdata.last_tx);
1486 ifp->if_flags &= ~IFF_OACTIVE;
1487 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1489 if (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) {
1490 if (sc->rl_want_auto)
1491 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1497 static void rl_intr(arg)
1500 struct rl_softc *sc;
1505 ifp = &sc->arpcom.ac_if;
1507 /* Disable interrupts. */
1508 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1512 status = CSR_READ_2(sc, RL_ISR);
1514 CSR_WRITE_2(sc, RL_ISR, status);
1516 if ((status & RL_INTRS) == 0)
1519 if (status & RL_ISR_RX_OK)
1522 if (status & RL_ISR_RX_ERR)
1525 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1528 if (status & RL_ISR_SYSTEM_ERR) {
1535 /* Re-enable interrupts. */
1536 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1538 if (ifp->if_snd.ifq_head != NULL) {
1546 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1547 * pointers to the fragment pointers.
1549 static int rl_encap(sc, m_head)
1550 struct rl_softc *sc;
1551 struct mbuf *m_head;
1553 struct mbuf *m_new = NULL;
1556 * The RealTek is brain damaged and wants longword-aligned
1557 * TX buffers, plus we can only have one fragment buffer
1558 * per packet. We have to copy pretty much all the time.
1561 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1562 if (m_new == NULL) {
1563 printf("rl%d: no memory for tx list", sc->rl_unit);
1566 if (m_head->m_pkthdr.len > MHLEN) {
1567 MCLGET(m_new, M_DONTWAIT);
1568 if (!(m_new->m_flags & M_EXT)) {
1570 printf("rl%d: no memory for tx list",
1575 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1576 mtod(m_new, caddr_t));
1577 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1581 /* Pad frames to at least 60 bytes. */
1582 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1583 m_head->m_pkthdr.len +=
1584 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1585 m_head->m_len = m_head->m_pkthdr.len;
1588 RL_CUR_TXMBUF(sc) = m_head;
1594 * Main transmit routine.
1597 static void rl_start(ifp)
1600 struct rl_softc *sc;
1601 struct mbuf *m_head = NULL;
1605 if (sc->rl_autoneg) {
1610 while(RL_CUR_TXMBUF(sc) == NULL) {
1611 IF_DEQUEUE(&ifp->if_snd, m_head);
1615 rl_encap(sc, m_head);
1619 * If there's a BPF listener, bounce a copy of this frame
1623 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1626 * Transmit the frame.
1628 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
1629 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t)));
1630 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1631 RL_TX_EARLYTHRESH | RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1633 RL_INC(sc->rl_cdata.cur_tx);
1637 * We broke out of the loop because all our TX slots are
1638 * full. Mark the NIC as busy until it drains some of the
1639 * packets from the queue.
1641 if (RL_CUR_TXMBUF(sc) != NULL)
1642 ifp->if_flags |= IFF_OACTIVE;
1645 * Set a timeout in case the chip goes out to lunch.
1652 static void rl_init(xsc)
1655 struct rl_softc *sc = xsc;
1656 struct ifnet *ifp = &sc->arpcom.ac_if;
1658 u_int32_t rxcfg = 0;
1659 u_int16_t phy_bmcr = 0;
1667 * XXX Hack for the 8139: the built-in autoneg logic's state
1668 * gets reset by rl_init() when we don't want it to. Try
1669 * to preserve it. (For 8129 cards with real external PHYs,
1670 * the BMCR register doesn't change, but this doesn't hurt.)
1672 if (sc->rl_type == RL_8139)
1673 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR);
1676 * Cancel pending I/O and free all RX/TX buffers.
1680 /* Init our MAC address */
1681 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1682 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1685 /* Init the RX buffer pointer register. */
1686 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1688 /* Init TX descriptors. */
1689 rl_list_tx_init(sc);
1692 * Enable transmit and receive.
1694 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1697 * Set the initial TX and RX configuration.
1699 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1700 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1702 /* Set the individual bit to receive frames for this host only. */
1703 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1704 rxcfg |= RL_RXCFG_RX_INDIV;
1706 /* If we want promiscuous mode, set the allframes bit. */
1707 if (ifp->if_flags & IFF_PROMISC) {
1708 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1709 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1711 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1712 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1716 * Set capture broadcast bit to capture broadcast frames.
1718 if (ifp->if_flags & IFF_BROADCAST) {
1719 rxcfg |= RL_RXCFG_RX_BROAD;
1720 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1722 rxcfg &= ~RL_RXCFG_RX_BROAD;
1723 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1727 * Program the multicast filter, if necessary.
1732 * Enable interrupts.
1734 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1736 /* Start RX/TX process. */
1737 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1739 /* Enable receiver and transmitter. */
1740 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1742 /* Restore state of BMCR */
1743 if (sc->rl_pinfo != NULL)
1744 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1746 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1748 ifp->if_flags |= IFF_RUNNING;
1749 ifp->if_flags &= ~IFF_OACTIVE;
1757 * Set media options.
1759 static int rl_ifmedia_upd(ifp)
1762 struct rl_softc *sc;
1763 struct ifmedia *ifm;
1768 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1771 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1772 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1774 rl_setmode_mii(sc, ifm->ifm_media);
1780 * Report current media status.
1782 static void rl_ifmedia_sts(ifp, ifmr)
1784 struct ifmediareq *ifmr;
1786 struct rl_softc *sc;
1787 u_int16_t advert = 0, ability = 0;
1791 if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1792 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1793 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
1795 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
1797 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1798 ifmr->ifm_active |= IFM_FDX;
1800 ifmr->ifm_active |= IFM_HDX;
1804 ability = rl_phy_readreg(sc, PHY_LPAR);
1805 advert = rl_phy_readreg(sc, PHY_ANAR);
1806 if (advert & PHY_ANAR_100BT4 &&
1807 ability & PHY_ANAR_100BT4) {
1808 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
1809 } else if (advert & PHY_ANAR_100BTXFULL &&
1810 ability & PHY_ANAR_100BTXFULL) {
1811 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
1812 } else if (advert & PHY_ANAR_100BTXHALF &&
1813 ability & PHY_ANAR_100BTXHALF) {
1814 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
1815 } else if (advert & PHY_ANAR_10BTFULL &&
1816 ability & PHY_ANAR_10BTFULL) {
1817 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
1818 } else if (advert & PHY_ANAR_10BTHALF &&
1819 ability & PHY_ANAR_10BTHALF) {
1820 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
1826 static int rl_ioctl(ifp, command, data)
1831 struct rl_softc *sc = ifp->if_softc;
1832 struct ifreq *ifr = (struct ifreq *) data;
1841 error = ether_ioctl(ifp, command, data);
1844 if (ifp->if_flags & IFF_UP) {
1847 if (ifp->if_flags & IFF_RUNNING)
1859 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1871 static void rl_watchdog(ifp)
1874 struct rl_softc *sc;
1878 if (sc->rl_autoneg) {
1879 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1);
1883 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1885 if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1886 printf("rl%d: no carrier - transceiver cable problem?\n",
1896 * Stop the adapter and free any mbufs allocated to the
1899 static void rl_stop(sc)
1900 struct rl_softc *sc;
1905 ifp = &sc->arpcom.ac_if;
1908 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1909 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1912 * Free the TX list buffers.
1914 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1915 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1916 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1917 sc->rl_cdata.rl_tx_chain[i] = NULL;
1918 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1922 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1928 * Stop all chip I/O so that the kernel's probe routines don't
1929 * get confused by errant DMAs when rebooting.
1931 static void rl_shutdown(howto, arg)
1935 struct rl_softc *sc = (struct rl_softc *)arg;
1943 static struct pci_device rl_device = {
1950 COMPAT_PCI_DRIVER(rl, rl_device);