2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $Id: if_rl.c,v 1.14 1999/04/24 20:14:01 peter Exp $
36 * RealTek 8129/8139 PCI NIC driver
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
92 #include <sys/malloc.h>
93 #include <sys/kernel.h>
94 #include <sys/socket.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
106 #include <vm/vm.h> /* for vtophys */
107 #include <vm/pmap.h> /* for vtophys */
108 #include <machine/clock.h> /* for DELAY */
109 #include <machine/bus_pio.h>
110 #include <machine/bus_memio.h>
111 #include <machine/bus.h>
113 #include <pci/pcireg.h>
114 #include <pci/pcivar.h>
117 * Default to using PIO access for this driver. On SMP systems,
118 * there appear to be problems with memory mapped mode: it looks like
119 * doing too many memory mapped access back to back in rapid succession
120 * can hang the bus. I'm inclined to blame this on crummy design/construction
121 * on the part of RealTek. Memory mapped mode does appear to work on
122 * uniprocessor systems though.
124 #define RL_USEIOSPACE
126 #include <pci/if_rlreg.h>
129 static const char rcsid[] =
130 "$Id: if_rl.c,v 1.14 1999/04/24 20:14:01 peter Exp $";
134 * Various supported device vendors/types and their names.
136 static struct rl_type rl_devs[] = {
137 { RT_VENDORID, RT_DEVICEID_8129,
138 "RealTek 8129 10/100BaseTX" },
139 { RT_VENDORID, RT_DEVICEID_8139,
140 "RealTek 8139 10/100BaseTX" },
141 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
142 "Accton MPX 5030/5038 10/100BaseTX" },
143 { DELTA_VENDORID, DELTA_DEVICEID_8139,
144 "Delta Electronics 8139 10/100BaseTX" },
145 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
146 "Addtron Technolgy 8139 10/100BaseTX" },
151 * Various supported PHY vendors/types and their names. Note that
152 * this driver will work with pretty much any MII-compliant PHY,
153 * so failure to positively identify the chip is not a fatal error.
156 static struct rl_type rl_phys[] = {
157 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
158 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
159 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
160 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" },
161 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
162 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
163 { 0, 0, "<MII-compliant physical interface>" }
166 static unsigned long rl_count = 0;
167 static const char *rl_probe __P((pcici_t, pcidi_t));
168 static void rl_attach __P((pcici_t, int));
170 static int rl_encap __P((struct rl_softc *, struct mbuf * ));
172 static void rl_rxeof __P((struct rl_softc *));
173 static void rl_txeof __P((struct rl_softc *));
174 static void rl_intr __P((void *));
175 static void rl_start __P((struct ifnet *));
176 static int rl_ioctl __P((struct ifnet *, u_long, caddr_t));
177 static void rl_init __P((void *));
178 static void rl_stop __P((struct rl_softc *));
179 static void rl_watchdog __P((struct ifnet *));
180 static void rl_shutdown __P((int, void *));
181 static int rl_ifmedia_upd __P((struct ifnet *));
182 static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
184 static void rl_eeprom_putbyte __P((struct rl_softc *, int));
185 static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *));
186 static void rl_read_eeprom __P((struct rl_softc *, caddr_t,
188 static void rl_mii_sync __P((struct rl_softc *));
189 static void rl_mii_send __P((struct rl_softc *, u_int32_t, int));
190 static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *));
191 static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *));
193 static u_int16_t rl_phy_readreg __P((struct rl_softc *, int));
194 static void rl_phy_writereg __P((struct rl_softc *, int, int));
196 static void rl_autoneg_xmit __P((struct rl_softc *));
197 static void rl_autoneg_mii __P((struct rl_softc *, int, int));
198 static void rl_setmode_mii __P((struct rl_softc *, int));
199 static void rl_getmode_mii __P((struct rl_softc *));
200 static u_int8_t rl_calchash __P((caddr_t));
201 static void rl_setmulti __P((struct rl_softc *));
202 static void rl_reset __P((struct rl_softc *));
203 static int rl_list_tx_init __P((struct rl_softc *));
206 CSR_WRITE_1(sc, RL_EECMD, \
207 CSR_READ_1(sc, RL_EECMD) | x)
210 CSR_WRITE_1(sc, RL_EECMD, \
211 CSR_READ_1(sc, RL_EECMD) & ~x)
214 * Send a read command and address to the EEPROM, check for ACK.
216 static void rl_eeprom_putbyte(sc, addr)
222 d = addr | RL_EECMD_READ;
225 * Feed in each bit and stobe the clock.
227 for (i = 0x400; i; i >>= 1) {
229 EE_SET(RL_EE_DATAIN);
231 EE_CLR(RL_EE_DATAIN);
244 * Read a word of data stored in the EEPROM at address 'addr.'
246 static void rl_eeprom_getword(sc, addr, dest)
254 /* Enter EEPROM access mode. */
255 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
258 * Send address of word we want to read.
260 rl_eeprom_putbyte(sc, addr);
262 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
265 * Start reading bits from EEPROM.
267 for (i = 0x8000; i; i >>= 1) {
270 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
276 /* Turn off EEPROM access mode. */
277 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
285 * Read a sequence of words from the EEPROM.
287 static void rl_read_eeprom(sc, dest, off, cnt, swap)
295 u_int16_t word = 0, *ptr;
297 for (i = 0; i < cnt; i++) {
298 rl_eeprom_getword(sc, off + i, &word);
299 ptr = (u_int16_t *)(dest + (i * 2));
311 * MII access routines are provided for the 8129, which
312 * doesn't have a built-in PHY. For the 8139, we fake things
313 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
314 * direct access PHY registers.
317 CSR_WRITE_1(sc, RL_MII, \
318 CSR_READ_1(sc, RL_MII) | x)
321 CSR_WRITE_1(sc, RL_MII, \
322 CSR_READ_1(sc, RL_MII) & ~x)
325 * Sync the PHYs by setting data bit and strobing the clock 32 times.
327 static void rl_mii_sync(sc)
332 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
334 for (i = 0; i < 32; i++) {
345 * Clock a series of bits through the MII.
347 static void rl_mii_send(sc, bits, cnt)
356 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
358 MII_SET(RL_MII_DATAOUT);
360 MII_CLR(RL_MII_DATAOUT);
370 * Read an PHY register through the MII.
372 static int rl_mii_readreg(sc, frame)
374 struct rl_mii_frame *frame;
382 * Set up frame for RX.
384 frame->mii_stdelim = RL_MII_STARTDELIM;
385 frame->mii_opcode = RL_MII_READOP;
386 frame->mii_turnaround = 0;
389 CSR_WRITE_2(sc, RL_MII, 0);
399 * Send command/address info.
401 rl_mii_send(sc, frame->mii_stdelim, 2);
402 rl_mii_send(sc, frame->mii_opcode, 2);
403 rl_mii_send(sc, frame->mii_phyaddr, 5);
404 rl_mii_send(sc, frame->mii_regaddr, 5);
407 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
420 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
423 * Now try reading data bits. If the ack failed, we still
424 * need to clock through 16 cycles to keep the PHY(s) in sync.
427 for(i = 0; i < 16; i++) {
436 for (i = 0x8000; i; i >>= 1) {
440 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
441 frame->mii_data |= i;
463 * Write to a PHY register through the MII.
465 static int rl_mii_writereg(sc, frame)
467 struct rl_mii_frame *frame;
474 * Set up frame for TX.
477 frame->mii_stdelim = RL_MII_STARTDELIM;
478 frame->mii_opcode = RL_MII_WRITEOP;
479 frame->mii_turnaround = RL_MII_TURNAROUND;
482 * Turn on data output.
488 rl_mii_send(sc, frame->mii_stdelim, 2);
489 rl_mii_send(sc, frame->mii_opcode, 2);
490 rl_mii_send(sc, frame->mii_phyaddr, 5);
491 rl_mii_send(sc, frame->mii_regaddr, 5);
492 rl_mii_send(sc, frame->mii_turnaround, 2);
493 rl_mii_send(sc, frame->mii_data, 16);
511 static u_int16_t rl_phy_readreg(sc, reg)
515 struct rl_mii_frame frame;
517 u_int16_t rl8139_reg = 0;
519 if (sc->rl_type == RL_8139) {
522 rl8139_reg = RL_BMCR;
525 rl8139_reg = RL_BMSR;
528 rl8139_reg = RL_ANAR;
531 rl8139_reg = RL_LPAR;
534 printf("rl%d: bad phy register\n", sc->rl_unit);
537 rval = CSR_READ_2(sc, rl8139_reg);
541 bzero((char *)&frame, sizeof(frame));
543 frame.mii_phyaddr = sc->rl_phy_addr;
544 frame.mii_regaddr = reg;
545 rl_mii_readreg(sc, &frame);
547 return(frame.mii_data);
550 static void rl_phy_writereg(sc, reg, data)
555 struct rl_mii_frame frame;
556 u_int16_t rl8139_reg = 0;
558 if (sc->rl_type == RL_8139) {
561 rl8139_reg = RL_BMCR;
564 rl8139_reg = RL_BMSR;
567 rl8139_reg = RL_ANAR;
570 rl8139_reg = RL_LPAR;
573 printf("rl%d: bad phy register\n", sc->rl_unit);
576 CSR_WRITE_2(sc, rl8139_reg, data);
580 bzero((char *)&frame, sizeof(frame));
582 frame.mii_phyaddr = sc->rl_phy_addr;
583 frame.mii_regaddr = reg;
584 frame.mii_data = data;
586 rl_mii_writereg(sc, &frame);
592 * Calculate CRC of a multicast group address, return the upper 6 bits.
594 static u_int8_t rl_calchash(addr)
597 u_int32_t crc, carry;
601 /* Compute CRC for the address value. */
602 crc = 0xFFFFFFFF; /* initial value */
604 for (i = 0; i < 6; i++) {
606 for (j = 0; j < 8; j++) {
607 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
611 crc = (crc ^ 0x04c11db6) | carry;
615 /* return the filter bit position */
620 * Program the 64-bit multicast hash filter.
622 static void rl_setmulti(sc)
627 u_int32_t hashes[2] = { 0, 0 };
628 struct ifmultiaddr *ifma;
632 ifp = &sc->arpcom.ac_if;
634 rxfilt = CSR_READ_4(sc, RL_RXCFG);
636 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
637 rxfilt |= RL_RXCFG_RX_MULTI;
638 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
639 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
640 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
644 /* first, zot all the existing hash bits */
645 CSR_WRITE_4(sc, RL_MAR0, 0);
646 CSR_WRITE_4(sc, RL_MAR4, 0);
648 /* now program new ones */
649 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
650 ifma = ifma->ifma_link.le_next) {
651 if (ifma->ifma_addr->sa_family != AF_LINK)
653 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
655 hashes[0] |= (1 << h);
657 hashes[1] |= (1 << (h - 32));
662 rxfilt |= RL_RXCFG_RX_MULTI;
664 rxfilt &= ~RL_RXCFG_RX_MULTI;
666 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
667 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
668 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
674 * Initiate an autonegotiation session.
676 static void rl_autoneg_xmit(sc)
681 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
683 while(rl_phy_readreg(sc, PHY_BMCR)
686 phy_sts = rl_phy_readreg(sc, PHY_BMCR);
687 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
688 rl_phy_writereg(sc, PHY_BMCR, phy_sts);
694 * Invoke autonegotiation on a PHY. Also used with the 8139 internal
697 static void rl_autoneg_mii(sc, flag, verbose)
702 u_int16_t phy_sts = 0, media, advert, ability;
707 ifp = &sc->arpcom.ac_if;
710 * The 100baseT4 PHY sometimes has the 'autoneg supported'
711 * bit cleared in the status register, but has the 'autoneg enabled'
712 * bit set in the control register. This is a contradiction, and
713 * I'm not sure how to handle it. If you want to force an attempt
714 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
715 * and see what happens.
717 #ifndef FORCE_AUTONEG_TFOUR
719 * First, see if autoneg is supported. If not, there's
720 * no point in continuing.
722 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
723 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
725 printf("rl%d: autonegotiation not supported\n",
732 case RL_FLAG_FORCEDELAY:
734 * XXX Never use this option anywhere but in the probe
735 * routine: making the kernel stop dead in its tracks
736 * for three whole seconds after we've gone multi-user
737 * is really bad manners.
742 case RL_FLAG_SCHEDDELAY:
744 * Wait for the transmitter to go idle before starting
745 * an autoneg session, otherwise rl_start() may clobber
746 * our timeout, and we don't want to allow transmission
747 * during an autoneg session since that can screw it up.
749 if (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx) {
750 sc->rl_want_auto = 1;
756 sc->rl_want_auto = 0;
759 case RL_FLAG_DELAYTIMEO:
764 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag);
768 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
770 printf("rl%d: autoneg complete, ", sc->rl_unit);
771 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
774 printf("rl%d: autoneg not complete, ", sc->rl_unit);
777 media = rl_phy_readreg(sc, PHY_BMCR);
779 /* Link is good. Report modes and set duplex mode. */
780 if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
782 printf("link status good ");
783 advert = rl_phy_readreg(sc, PHY_ANAR);
784 ability = rl_phy_readreg(sc, PHY_LPAR);
786 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
787 ifm->ifm_media = IFM_ETHER|IFM_100_T4;
788 media |= PHY_BMCR_SPEEDSEL;
789 media &= ~PHY_BMCR_DUPLEX;
790 printf("(100baseT4)\n");
791 } else if (advert & PHY_ANAR_100BTXFULL &&
792 ability & PHY_ANAR_100BTXFULL) {
793 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
794 media |= PHY_BMCR_SPEEDSEL;
795 media |= PHY_BMCR_DUPLEX;
796 printf("(full-duplex, 100Mbps)\n");
797 } else if (advert & PHY_ANAR_100BTXHALF &&
798 ability & PHY_ANAR_100BTXHALF) {
799 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
800 media |= PHY_BMCR_SPEEDSEL;
801 media &= ~PHY_BMCR_DUPLEX;
802 printf("(half-duplex, 100Mbps)\n");
803 } else if (advert & PHY_ANAR_10BTFULL &&
804 ability & PHY_ANAR_10BTFULL) {
805 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
806 media &= ~PHY_BMCR_SPEEDSEL;
807 media |= PHY_BMCR_DUPLEX;
808 printf("(full-duplex, 10Mbps)\n");
810 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
811 media &= ~PHY_BMCR_SPEEDSEL;
812 media &= ~PHY_BMCR_DUPLEX;
813 printf("(half-duplex, 10Mbps)\n");
816 /* Set ASIC's duplex mode to match the PHY. */
817 rl_phy_writereg(sc, PHY_BMCR, media);
820 printf("no carrier\n");
825 if (sc->rl_tx_pend) {
834 static void rl_getmode_mii(sc)
840 ifp = &sc->arpcom.ac_if;
842 bmsr = rl_phy_readreg(sc, PHY_BMSR);
844 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr);
847 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
849 if (bmsr & PHY_BMSR_10BTHALF) {
851 printf("rl%d: 10Mbps half-duplex mode supported\n",
853 ifmedia_add(&sc->ifmedia,
854 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
855 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
858 if (bmsr & PHY_BMSR_10BTFULL) {
860 printf("rl%d: 10Mbps full-duplex mode supported\n",
862 ifmedia_add(&sc->ifmedia,
863 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
864 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
867 if (bmsr & PHY_BMSR_100BTXHALF) {
869 printf("rl%d: 100Mbps half-duplex mode supported\n",
871 ifp->if_baudrate = 100000000;
872 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
873 ifmedia_add(&sc->ifmedia,
874 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
875 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
878 if (bmsr & PHY_BMSR_100BTXFULL) {
880 printf("rl%d: 100Mbps full-duplex mode supported\n",
882 ifp->if_baudrate = 100000000;
883 ifmedia_add(&sc->ifmedia,
884 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
885 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
888 /* Some also support 100BaseT4. */
889 if (bmsr & PHY_BMSR_100BT4) {
891 printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit);
892 ifp->if_baudrate = 100000000;
893 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
894 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
895 #ifdef FORCE_AUTONEG_TFOUR
897 printf("rl%d: forcing on autoneg support for BT4\n",
899 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
900 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
904 if (bmsr & PHY_BMSR_CANAUTONEG) {
906 printf("rl%d: autoneg supported\n", sc->rl_unit);
907 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
908 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
915 * Set speed and duplex mode.
917 static void rl_setmode_mii(sc, media)
923 printf("rl%d: selecting MII, ", sc->rl_unit);
925 bmcr = rl_phy_readreg(sc, PHY_BMCR);
927 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
928 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
930 if (IFM_SUBTYPE(media) == IFM_100_T4) {
931 printf("100Mbps/T4, half-duplex\n");
932 bmcr |= PHY_BMCR_SPEEDSEL;
933 bmcr &= ~PHY_BMCR_DUPLEX;
936 if (IFM_SUBTYPE(media) == IFM_100_TX) {
938 bmcr |= PHY_BMCR_SPEEDSEL;
941 if (IFM_SUBTYPE(media) == IFM_10_T) {
943 bmcr &= ~PHY_BMCR_SPEEDSEL;
946 if ((media & IFM_GMASK) == IFM_FDX) {
947 printf("full duplex\n");
948 bmcr |= PHY_BMCR_DUPLEX;
950 printf("half duplex\n");
951 bmcr &= ~PHY_BMCR_DUPLEX;
954 rl_phy_writereg(sc, PHY_BMCR, bmcr);
959 static void rl_reset(sc)
964 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
966 for (i = 0; i < RL_TIMEOUT; i++) {
968 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
972 printf("rl%d: reset never completed!\n", sc->rl_unit);
978 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
979 * IDs against our list and return a device name if we find a match.
982 rl_probe(config_id, device_id)
990 while(t->rl_name != NULL) {
991 if ((device_id & 0xFFFF) == t->rl_vid &&
992 ((device_id >> 16) & 0xFFFF) == t->rl_did) {
1002 * Attach the interface. Allocate softc structures, do ifmedia
1003 * setup and ethernet/BPF attach.
1006 rl_attach(config_id, unit)
1011 #ifndef RL_USEIOSPACE
1012 vm_offset_t pbase, vbase;
1014 u_char eaddr[ETHER_ADDR_LEN];
1016 struct rl_softc *sc;
1018 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1020 u_int16_t phy_vid, phy_did, phy_sts;
1021 u_int16_t rl_did = 0;
1025 sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT);
1027 printf("rl%d: no memory for softc struct!\n", unit);
1030 bzero(sc, sizeof(struct rl_softc));
1033 * Handle power management nonsense.
1036 command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF;
1037 if (command == 0x01) {
1039 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL);
1040 if (command & RL_PSTATE_MASK) {
1041 u_int32_t iobase, membase, irq;
1043 /* Save important PCI config data. */
1044 iobase = pci_conf_read(config_id, RL_PCI_LOIO);
1045 membase = pci_conf_read(config_id, RL_PCI_LOMEM);
1046 irq = pci_conf_read(config_id, RL_PCI_INTLINE);
1048 /* Reset the power state. */
1049 printf("rl%d: chip is is in D%d power mode "
1050 "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
1051 command &= 0xFFFFFFFC;
1052 pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command);
1054 /* Restore PCI config data. */
1055 pci_conf_write(config_id, RL_PCI_LOIO, iobase);
1056 pci_conf_write(config_id, RL_PCI_LOMEM, membase);
1057 pci_conf_write(config_id, RL_PCI_INTLINE, irq);
1062 * Map control/status registers.
1064 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1065 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1066 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1067 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1069 #ifdef RL_USEIOSPACE
1070 if (!(command & PCIM_CMD_PORTEN)) {
1071 printf("rl%d: failed to enable I/O ports!\n", unit);
1076 if (!pci_map_port(config_id, RL_PCI_LOIO,
1077 (u_int16_t *)&(sc->rl_bhandle))) {
1078 printf ("rl%d: couldn't map ports\n", unit);
1081 sc->rl_btag = I386_BUS_SPACE_IO;
1083 if (!(command & PCIM_CMD_MEMEN)) {
1084 printf("rl%d: failed to enable memory mapping!\n", unit);
1088 if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) {
1089 printf ("rl%d: couldn't map memory\n", unit);
1092 sc->rl_btag = I386_BUS_SPACE_MEM;
1093 sc->rl_bhandle = vbase;
1096 /* Allocate interrupt */
1097 if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) {
1098 printf("rl%d: couldn't map interrupt\n", unit);
1102 /* Reset the adapter. */
1106 * Get station address from the EEPROM.
1108 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
1111 * A RealTek chip was detected. Inform the world.
1113 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1116 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1119 * Now read the exact device type from the EEPROM to find
1120 * out if it's an 8129 or 8139.
1122 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1124 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
1125 rl_did == DELTA_DEVICEID_8139)
1126 sc->rl_type = RL_8139;
1127 else if (rl_did == RT_DEVICEID_8129)
1128 sc->rl_type = RL_8129;
1130 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1135 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 16, M_DEVBUF,
1136 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
1138 if (sc->rl_cdata.rl_rx_buf == NULL) {
1140 printf("rl%d: no memory for list buffers!\n", unit);
1144 ifp = &sc->arpcom.ac_if;
1146 ifp->if_unit = unit;
1147 ifp->if_name = "rl";
1148 ifp->if_mtu = ETHERMTU;
1149 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1150 ifp->if_ioctl = rl_ioctl;
1151 ifp->if_output = ether_output;
1152 ifp->if_start = rl_start;
1153 ifp->if_watchdog = rl_watchdog;
1154 ifp->if_init = rl_init;
1155 ifp->if_baudrate = 10000000;
1156 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1158 if (sc->rl_type == RL_8129) {
1160 printf("rl%d: probing for a PHY\n", sc->rl_unit);
1161 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) {
1163 printf("rl%d: checking address: %d\n",
1165 sc->rl_phy_addr = i;
1166 rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1168 while(rl_phy_readreg(sc, PHY_BMCR)
1170 if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR)))
1174 phy_vid = rl_phy_readreg(sc, PHY_VENID);
1175 phy_did = rl_phy_readreg(sc, PHY_DEVID);
1177 printf("rl%d: found PHY at address %d, ",
1178 sc->rl_unit, sc->rl_phy_addr);
1180 printf("vendor id: %x device id: %x\n",
1184 if (phy_vid == p->rl_vid &&
1185 (phy_did | 0x000F) == p->rl_did) {
1191 if (sc->rl_pinfo == NULL)
1192 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN];
1194 printf("rl%d: PHY type: %s\n",
1195 sc->rl_unit, sc->rl_pinfo->rl_name);
1197 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1204 ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts);
1208 /* Choose a default media. */
1209 media = IFM_ETHER|IFM_AUTO;
1210 ifmedia_set(&sc->ifmedia, media);
1212 rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1);
1215 * Call MI attach routines.
1218 ether_ifattach(ifp);
1221 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1223 at_shutdown(rl_shutdown, sc, SHUTDOWN_POST_SYNC);
1231 * Initialize the transmit descriptors.
1233 static int rl_list_tx_init(sc)
1234 struct rl_softc *sc;
1236 struct rl_chain_data *cd;
1240 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1241 cd->rl_tx_chain[i] = NULL;
1242 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1245 sc->rl_cdata.cur_tx = 0;
1246 sc->rl_cdata.last_tx = 0;
1252 * A frame has been uploaded: pass the resulting mbuf chain up to
1253 * the higher level protocols.
1255 * You know there's something wrong with a PCI bus-master chip design
1256 * when you have to use m_devget().
1258 * The receive operation is badly documented in the datasheet, so I'll
1259 * attempt to document it here. The driver provides a buffer area and
1260 * places its base address in the RX buffer start address register.
1261 * The chip then begins copying frames into the RX buffer. Each frame
1262 * is preceeded by a 32-bit RX status word which specifies the length
1263 * of the frame and certain other status bits. Each frame (starting with
1264 * the status word) is also 32-bit aligned. The frame length is in the
1265 * first 16 bits of the status word; the lower 15 bits correspond with
1266 * the 'rx status register' mentioned in the datasheet.
1268 static void rl_rxeof(sc)
1269 struct rl_softc *sc;
1271 struct ether_header *eh;
1280 u_int16_t rx_bytes = 0, max_bytes;
1282 ifp = &sc->arpcom.ac_if;
1284 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1286 /* Do not try to read past this point. */
1287 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1290 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1292 max_bytes = limit - cur_rx;
1294 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1295 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1296 rxstat = *(u_int32_t *)rxbufpos;
1299 * Here's a totally undocumented fact for you. When the
1300 * RealTek chip is in the process of copying a packet into
1301 * RAM for you, the length will be 0xfff0. If you spot a
1302 * packet header with this value, you need to stop. The
1303 * datasheet makes absolutely no mention of this and
1304 * RealTek should be shot for this.
1306 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1309 if (!(rxstat & RL_RXSTAT_RXOK)) {
1311 if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT|
1312 RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR|
1313 RL_RXSTAT_ALIGNERR)) {
1314 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB);
1315 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB|
1317 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1318 CSR_WRITE_4(sc, RL_RXADDR,
1319 vtophys(sc->rl_cdata.rl_rx_buf));
1320 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1326 /* No errors; receive the packet. */
1327 total_len = rxstat >> 16;
1328 rx_bytes += total_len + 4;
1331 * XXX The RealTek chip includes the CRC with every
1332 * received frame, and there's no way to turn this
1333 * behavior off (at least, I can't find anything in
1334 * the manual that explains how to do it) so we have
1335 * to trim off the CRC manually.
1337 total_len -= ETHER_CRC_LEN;
1340 * Avoid trying to read more bytes than we know
1341 * the chip has prepared for us.
1343 if (rx_bytes > max_bytes)
1346 rxbufpos = sc->rl_cdata.rl_rx_buf +
1347 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1349 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1350 rxbufpos = sc->rl_cdata.rl_rx_buf;
1352 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1354 if (total_len > wrap) {
1355 m = m_devget(rxbufpos, wrap, 0, ifp, NULL);
1358 printf("rl%d: out of mbufs, tried to "
1359 "copy %d bytes\n", sc->rl_unit, wrap);
1362 m_copyback(m, wrap, total_len - wrap,
1363 sc->rl_cdata.rl_rx_buf);
1364 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1366 m = m_devget(rxbufpos, total_len, 0, ifp, NULL);
1369 printf("rl%d: out of mbufs, tried to "
1370 "copy %d bytes\n", sc->rl_unit, total_len);
1372 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1376 * Round up to 32-bit boundary.
1378 cur_rx = (cur_rx + 3) & ~3;
1379 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1384 eh = mtod(m, struct ether_header *);
1389 * Handle BPF listeners. Let the BPF user see the packet, but
1390 * don't pass it up to the ether_input() layer unless it's
1391 * a broadcast packet, multicast packet, matches our ethernet
1392 * address or the interface is in promiscuous mode.
1396 if (ifp->if_flags & IFF_PROMISC &&
1397 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1399 (eh->ether_dhost[0] & 1) == 0)) {
1405 /* Remove header from mbuf and pass it on. */
1406 m_adj(m, sizeof(struct ether_header));
1407 ether_input(ifp, eh, m);
1414 * A frame was downloaded to the chip. It's safe for us to clean up
1417 static void rl_txeof(sc)
1418 struct rl_softc *sc;
1423 ifp = &sc->arpcom.ac_if;
1425 /* Clear the timeout timer. */
1429 * Go through our tx list and free mbufs for those
1430 * frames that have been uploaded.
1433 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1434 if (!(txstat & (RL_TXSTAT_TX_OK|
1435 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1438 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1440 if (RL_LAST_TXMBUF(sc) != NULL) {
1441 m_freem(RL_LAST_TXMBUF(sc));
1442 RL_LAST_TXMBUF(sc) = NULL;
1444 if (txstat & RL_TXSTAT_TX_OK)
1448 if ((txstat & RL_TXSTAT_TXABRT) ||
1449 (txstat & RL_TXSTAT_OUTOFWIN))
1450 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1452 RL_INC(sc->rl_cdata.last_tx);
1453 ifp->if_flags &= ~IFF_OACTIVE;
1454 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1456 if (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) {
1457 if (sc->rl_want_auto)
1458 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1464 static void rl_intr(arg)
1467 struct rl_softc *sc;
1472 ifp = &sc->arpcom.ac_if;
1474 /* Disable interrupts. */
1475 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1479 status = CSR_READ_2(sc, RL_ISR);
1481 CSR_WRITE_2(sc, RL_ISR, status);
1483 if ((status & RL_INTRS) == 0)
1486 if (status & RL_ISR_RX_OK)
1489 if (status & RL_ISR_RX_ERR)
1492 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1495 if (status & RL_ISR_SYSTEM_ERR) {
1502 /* Re-enable interrupts. */
1503 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1505 if (ifp->if_snd.ifq_head != NULL) {
1513 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1514 * pointers to the fragment pointers.
1516 static int rl_encap(sc, m_head)
1517 struct rl_softc *sc;
1518 struct mbuf *m_head;
1520 struct mbuf *m_new = NULL;
1523 * The RealTek is brain damaged and wants longword-aligned
1524 * TX buffers, plus we can only have one fragment buffer
1525 * per packet. We have to copy pretty much all the time.
1528 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1529 if (m_new == NULL) {
1530 printf("rl%d: no memory for tx list", sc->rl_unit);
1533 if (m_head->m_pkthdr.len > MHLEN) {
1534 MCLGET(m_new, M_DONTWAIT);
1535 if (!(m_new->m_flags & M_EXT)) {
1537 printf("rl%d: no memory for tx list",
1542 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1543 mtod(m_new, caddr_t));
1544 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1548 /* Pad frames to at least 60 bytes. */
1549 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1550 m_head->m_pkthdr.len +=
1551 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1552 m_head->m_len = m_head->m_pkthdr.len;
1555 RL_CUR_TXMBUF(sc) = m_head;
1561 * Main transmit routine.
1564 static void rl_start(ifp)
1567 struct rl_softc *sc;
1568 struct mbuf *m_head = NULL;
1572 if (sc->rl_autoneg) {
1577 while(RL_CUR_TXMBUF(sc) == NULL) {
1578 IF_DEQUEUE(&ifp->if_snd, m_head);
1582 rl_encap(sc, m_head);
1586 * If there's a BPF listener, bounce a copy of this frame
1590 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1593 * Transmit the frame.
1595 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc),
1596 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t)));
1597 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1598 RL_TX_EARLYTHRESH | RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1600 RL_INC(sc->rl_cdata.cur_tx);
1604 * We broke out of the loop because all our TX slots are
1605 * full. Mark the NIC as busy until it drains some of the
1606 * packets from the queue.
1608 if (RL_CUR_TXMBUF(sc) != NULL)
1609 ifp->if_flags |= IFF_OACTIVE;
1612 * Set a timeout in case the chip goes out to lunch.
1619 static void rl_init(xsc)
1622 struct rl_softc *sc = xsc;
1623 struct ifnet *ifp = &sc->arpcom.ac_if;
1625 u_int32_t rxcfg = 0;
1626 u_int16_t phy_bmcr = 0;
1634 * XXX Hack for the 8139: the built-in autoneg logic's state
1635 * gets reset by rl_init() when we don't want it to. Try
1636 * to preserve it. (For 8129 cards with real external PHYs,
1637 * the BMCR register doesn't change, but this doesn't hurt.)
1639 if (sc->rl_type == RL_8139)
1640 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR);
1643 * Cancel pending I/O and free all RX/TX buffers.
1647 /* Init our MAC address */
1648 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1649 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1652 /* Init the RX buffer pointer register. */
1653 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1655 /* Init TX descriptors. */
1656 rl_list_tx_init(sc);
1659 * Enable transmit and receive.
1661 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1664 * Set the initial TX and RX configuration.
1666 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1667 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1669 /* Set the individual bit to receive frames for this host only. */
1670 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1671 rxcfg |= RL_RXCFG_RX_INDIV;
1673 /* If we want promiscuous mode, set the allframes bit. */
1674 if (ifp->if_flags & IFF_PROMISC) {
1675 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1676 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1678 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1679 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1683 * Set capture broadcast bit to capture broadcast frames.
1685 if (ifp->if_flags & IFF_BROADCAST) {
1686 rxcfg |= RL_RXCFG_RX_BROAD;
1687 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1689 rxcfg &= ~RL_RXCFG_RX_BROAD;
1690 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1694 * Program the multicast filter, if necessary.
1699 * Enable interrupts.
1701 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1703 /* Start RX/TX process. */
1704 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1706 /* Enable receiver and transmitter. */
1707 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1709 /* Restore state of BMCR */
1710 if (sc->rl_pinfo != NULL)
1711 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1713 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1715 ifp->if_flags |= IFF_RUNNING;
1716 ifp->if_flags &= ~IFF_OACTIVE;
1724 * Set media options.
1726 static int rl_ifmedia_upd(ifp)
1729 struct rl_softc *sc;
1730 struct ifmedia *ifm;
1735 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1738 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1739 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1741 rl_setmode_mii(sc, ifm->ifm_media);
1747 * Report current media status.
1749 static void rl_ifmedia_sts(ifp, ifmr)
1751 struct ifmediareq *ifmr;
1753 struct rl_softc *sc;
1754 u_int16_t advert = 0, ability = 0;
1758 if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1759 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1760 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
1762 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
1764 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1765 ifmr->ifm_active |= IFM_FDX;
1767 ifmr->ifm_active |= IFM_HDX;
1771 ability = rl_phy_readreg(sc, PHY_LPAR);
1772 advert = rl_phy_readreg(sc, PHY_ANAR);
1773 if (advert & PHY_ANAR_100BT4 &&
1774 ability & PHY_ANAR_100BT4) {
1775 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
1776 } else if (advert & PHY_ANAR_100BTXFULL &&
1777 ability & PHY_ANAR_100BTXFULL) {
1778 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
1779 } else if (advert & PHY_ANAR_100BTXHALF &&
1780 ability & PHY_ANAR_100BTXHALF) {
1781 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
1782 } else if (advert & PHY_ANAR_10BTFULL &&
1783 ability & PHY_ANAR_10BTFULL) {
1784 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
1785 } else if (advert & PHY_ANAR_10BTHALF &&
1786 ability & PHY_ANAR_10BTHALF) {
1787 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
1793 static int rl_ioctl(ifp, command, data)
1798 struct rl_softc *sc = ifp->if_softc;
1799 struct ifreq *ifr = (struct ifreq *) data;
1808 error = ether_ioctl(ifp, command, data);
1811 if (ifp->if_flags & IFF_UP) {
1814 if (ifp->if_flags & IFF_RUNNING)
1826 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1838 static void rl_watchdog(ifp)
1841 struct rl_softc *sc;
1845 if (sc->rl_autoneg) {
1846 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1);
1850 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1852 if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1853 printf("rl%d: no carrier - transceiver cable problem?\n",
1863 * Stop the adapter and free any mbufs allocated to the
1866 static void rl_stop(sc)
1867 struct rl_softc *sc;
1872 ifp = &sc->arpcom.ac_if;
1875 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1876 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1879 * Free the TX list buffers.
1881 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1882 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1883 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1884 sc->rl_cdata.rl_tx_chain[i] = NULL;
1885 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1889 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1895 * Stop all chip I/O so that the kernel's probe routines don't
1896 * get confused by errant DMAs when rebooting.
1898 static void rl_shutdown(howto, arg)
1902 struct rl_softc *sc = (struct rl_softc *)arg;
1910 static struct pci_device rl_device = {
1917 COMPAT_PCI_DRIVER(rl, rl_device);