sys/pci/if_rl.c

   1 /*
   2  * Copyright (c) 1997, 1998
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  *      $Id: if_rl.c,v 1.14 1998/11/18 20:27:28 wpaul Exp $
  33  */
  34
  35 /*
  36  * RealTek 8129/8139 PCI NIC driver
  37  *
  38  * Supports several extremely cheap PCI 10/100 adapters based on
  39  * the RealTek chipset. Datasheets can be obtained from
  40  * www.realtek.com.tw.
  41  *
  42  * Written by Bill Paul <wpaul@ctr.columbia.edu>
  43  * Electrical Engineering Department
  44  * Columbia University, New York City
  45  */
  46
  47 /*
  48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
  49  * probably the worst PCI ethernet controller ever made, with the possible
  50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
  51  * DMA, but it has a terrible interface that nullifies any performance
  52  * gains that bus-master DMA usually offers.
  53  *
  54  * For transmission, the chip offers a series of four TX descriptor
  55  * registers. Each transmit frame must be in a contiguous buffer, aligned
  56  * on a doubleword (32-bit) boundary. This means we almost always have to
  57  * do mbuf copies in order to transmit a frame, except in the unlikely
  58  * case where a) the packet fits into a single mbuf, and b) the packet
  59  * is 32-bit aligned within the mbuf's data area. The presence of only
  60  * four descriptor registers means that we can never have more than four
  61  * packets queued for transmission at any one time.
  62  *
  63  * Reception is not much better. The driver has to allocate a single large
  64  * buffer area (up to 64K in size) into which the chip will DMA received
  65  * frames. Because we don't know where within this region received packets
  66  * will begin or end, we have no choice but to copy data from the buffer
  67  * area into mbufs in order to pass the packets up to the higher protocol
  68  * levels.
  69  *
  70  * It's impossible given this rotten design to really achieve decent
  71  * performance at 100Mbps, unless you happen to have a 400Mhz PII or
  72  * some equally overmuscled CPU to drive it.
  73  *
  74  * On the bright side, the 8139 does have a built-in PHY, although
  75  * rather than using an MDIO serial interface like most other NICs, the
  76  * PHY registers are directly accessible through the 8139's register
  77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
  78  * filter.
  79  *
  80  * The 8129 chip is an older version of the 8139 that uses an external PHY
  81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
  82  * the 8139 lets you directly access the on-board PHY registers. We need
  83  * to select which interface to use depending on the chip type.
  84  *
  85  * Note: beware of trying to use the Linux RealTek driver as a reference
  86  * for information about the RealTek chip. It contains several bogosities.
  87  * It contains definitions for several undocumented registers which it
  88  * claims are 'required for proper operation' yet it does not use these
  89  * registers anywhere in the code. It also refers to some undocumented
  90  * 'Twister tuning codes' which it doesn't use anywhere. It also contains
  91  * bit definitions for several registers which are totally ignored: magic
  92  * numbers are used instead, making the code hard to read.
  93  */
  94
  95 #include "bpfilter.h"
  96
  97 #include <sys/param.h>
  98 #include <sys/systm.h>
  99 #include <sys/sockio.h>
 100 #include <sys/mbuf.h>
 101 #include <sys/malloc.h>
 102 #include <sys/kernel.h>
 103 #include <sys/socket.h>
 104
 105 #include <net/if.h>
 106 #include <net/if_arp.h>
 107 #include <net/ethernet.h>
 108 #include <net/if_dl.h>
 109 #include <net/if_media.h>
 110
 111 #if NBPFILTER > 0
 112 #include <net/bpf.h>
 113 #endif
 114
 115 #include <vm/vm.h>              /* for vtophys */
 116 #include <vm/pmap.h>            /* for vtophys */
 117 #include <machine/clock.h>      /* for DELAY */
 118
 119 #include <pci/pcireg.h>
 120 #include <pci/pcivar.h>
 121
 122 /*
 123  * Default to using PIO access for this driver. On SMP systems,
 124  * there appear to be problems with memory mapped mode: it looks like
 125  * doing too many memory mapped access back to back in rapid succession
 126  * can hang the bus. I'm inclined to blame this on crummy design/construction
 127  * on the part of RealTek. Memory mapped mode does appear to work on
 128  * uniprocessor systems though.
 129  */
 130 #define RL_USEIOSPACE
 131
 132 #include <pci/if_rlreg.h>
 133
 134 #ifndef lint
 135 static char rcsid[] =
 136         "$Id: if_rl.c,v 1.14 1998/11/18 20:27:28 wpaul Exp $";
 137 #endif
 138
 139 /*
 140  * Various supported device vendors/types and their names.
 141  */
 142 static struct rl_type rl_devs[] = {
 143         { RT_VENDORID, RT_DEVICEID_8129,
 144                 "RealTek 8129 10/100BaseTX" },
 145         { RT_VENDORID, RT_DEVICEID_8139,
 146                 "RealTek 8139 10/100BaseTX" },
 147         { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
 148                 "Accton MPX 5030/5038 10/100BaseTX" },
 149         { 0, 0, NULL }
 150 };
 151
 152 /*
 153  * Various supported PHY vendors/types and their names. Note that
 154  * this driver will work with pretty much any MII-compliant PHY,
 155  * so failure to positively identify the chip is not a fatal error.
 156  */
 157
 158 static struct rl_type rl_phys[] = {
 159         { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
 160         { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
 161         { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
 162         { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" },
 163         { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
 164         { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
 165         { 0, 0, "<MII-compliant physical interface>" }
 166 };
 167
 168 static unsigned long rl_count = 0;
 169 static char *rl_probe           __P((pcici_t, pcidi_t));
 170 static void rl_attach           __P((pcici_t, int));
 171
 172 static int rl_encap             __P((struct rl_softc *, struct rl_chain *,
 173                                                 struct mbuf * ));
 174
 175 static void rl_rxeof            __P((struct rl_softc *));
 176 static void rl_txeof            __P((struct rl_softc *));
 177 static void rl_txeoc            __P((struct rl_softc *));
 178 static void rl_intr             __P((void *));
 179 static void rl_start            __P((struct ifnet *));
 180 static int rl_ioctl             __P((struct ifnet *, u_long, caddr_t));
 181 static void rl_init             __P((void *));
 182 static void rl_stop             __P((struct rl_softc *));
 183 static void rl_watchdog         __P((struct ifnet *));
 184 static void rl_shutdown         __P((int, void *));
 185 static int rl_ifmedia_upd       __P((struct ifnet *));
 186 static void rl_ifmedia_sts      __P((struct ifnet *, struct ifmediareq *));
 187
 188 static void rl_eeprom_putbyte   __P((struct rl_softc *, u_int8_t));
 189 static void rl_eeprom_getword   __P((struct rl_softc *, u_int8_t, u_int16_t *));
 190 static void rl_read_eeprom      __P((struct rl_softc *, caddr_t,
 191                                         int, int, int));
 192 static void rl_mii_sync         __P((struct rl_softc *));
 193 static void rl_mii_send         __P((struct rl_softc *, u_int32_t, int));
 194 static int rl_mii_readreg       __P((struct rl_softc *, struct rl_mii_frame *));
 195 static int rl_mii_writereg      __P((struct rl_softc *, struct rl_mii_frame *));
 196
 197 static u_int16_t rl_phy_readreg __P((struct rl_softc *, int));
 198 static void rl_phy_writereg     __P((struct rl_softc *, u_int16_t, u_int16_t));
 199
 200 static void rl_autoneg_xmit     __P((struct rl_softc *));
 201 static void rl_autoneg_mii      __P((struct rl_softc *, int, int));
 202 static void rl_setmode_mii      __P((struct rl_softc *, int));
 203 static void rl_getmode_mii      __P((struct rl_softc *));
 204 static u_int8_t rl_calchash     __P((u_int8_t *));
 205 static void rl_setmulti         __P((struct rl_softc *));
 206 static void rl_reset            __P((struct rl_softc *));
 207 static int rl_list_tx_init      __P((struct rl_softc *));
 208
 209 #define EE_SET(x)                                       \
 210         CSR_WRITE_1(sc, RL_EECMD,                       \
 211                 CSR_READ_1(sc, RL_EECMD) | x)
 212
 213 #define EE_CLR(x)                                       \
 214         CSR_WRITE_1(sc, RL_EECMD,                       \
 215                 CSR_READ_1(sc, RL_EECMD) & ~x)
 216
 217 /*
 218  * Send a read command and address to the EEPROM, check for ACK.
 219  */
 220 static void rl_eeprom_putbyte(sc, addr)
 221         struct rl_softc         *sc;
 222         u_int8_t                addr;
 223 {
 224         register int            d, i;
 225
 226         d = addr | RL_EECMD_READ;
 227
 228         /*
 229          * Feed in each bit and stobe the clock.
 230          */
 231         for (i = 0x400; i; i >>= 1) {
 232                 if (d & i) {
 233                         EE_SET(RL_EE_DATAIN);
 234                 } else {
 235                         EE_CLR(RL_EE_DATAIN);
 236                 }
 237                 DELAY(100);
 238                 EE_SET(RL_EE_CLK);
 239                 DELAY(150);
 240                 EE_CLR(RL_EE_CLK);
 241                 DELAY(100);
 242         }
 243
 244         return;
 245 }
 246
 247 /*
 248  * Read a word of data stored in the EEPROM at address 'addr.'
 249  */
 250 static void rl_eeprom_getword(sc, addr, dest)
 251         struct rl_softc         *sc;
 252         u_int8_t                addr;
 253         u_int16_t               *dest;
 254 {
 255         register int            i;
 256         u_int16_t               word = 0;
 257
 258         /* Enter EEPROM access mode. */
 259         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 260
 261         /*
 262          * Send address of word we want to read.
 263          */
 264         rl_eeprom_putbyte(sc, addr);
 265
 266         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 267
 268         /*
 269          * Start reading bits from EEPROM.
 270          */
 271         for (i = 0x8000; i; i >>= 1) {
 272                 EE_SET(RL_EE_CLK);
 273                 DELAY(100);
 274                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
 275                         word |= i;
 276                 EE_CLR(RL_EE_CLK);
 277                 DELAY(100);
 278         }
 279
 280         /* Turn off EEPROM access mode. */
 281         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 282
 283         *dest = word;
 284
 285         return;
 286 }
 287
 288 /*
 289  * Read a sequence of words from the EEPROM.
 290  */
 291 static void rl_read_eeprom(sc, dest, off, cnt, swap)
 292         struct rl_softc         *sc;
 293         caddr_t                 dest;
 294         int                     off;
 295         int                     cnt;
 296         int                     swap;
 297 {
 298         int                     i;
 299         u_int16_t               word = 0, *ptr;
 300
 301         for (i = 0; i < cnt; i++) {
 302                 rl_eeprom_getword(sc, off + i, &word);
 303                 ptr = (u_int16_t *)(dest + (i * 2));
 304                 if (swap)
 305                         *ptr = ntohs(word);
 306                 else
 307                         *ptr = word;
 308         }
 309
 310         return;
 311 }
 312
 313
 314 /*
 315  * MII access routines are provided for the 8129, which
 316  * doesn't have a built-in PHY. For the 8139, we fake things
 317  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
 318  * direct access PHY registers.
 319  */
 320 #define MII_SET(x)                                      \
 321         CSR_WRITE_1(sc, RL_MII,                         \
 322                 CSR_READ_1(sc, RL_MII) | x)
 323
 324 #define MII_CLR(x)                                      \
 325         CSR_WRITE_1(sc, RL_MII,                         \
 326                 CSR_READ_1(sc, RL_MII) & ~x)
 327
 328 /*
 329  * Sync the PHYs by setting data bit and strobing the clock 32 times.
 330  */
 331 static void rl_mii_sync(sc)
 332         struct rl_softc         *sc;
 333 {
 334         register int            i;
 335
 336         MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
 337
 338         for (i = 0; i < 32; i++) {
 339                 MII_SET(RL_MII_CLK);
 340                 DELAY(1);
 341                 MII_CLR(RL_MII_CLK);
 342                 DELAY(1);
 343         }
 344
 345         return;
 346 }
 347
 348 /*
 349  * Clock a series of bits through the MII.
 350  */
 351 static void rl_mii_send(sc, bits, cnt)
 352         struct rl_softc         *sc;
 353         u_int32_t               bits;
 354         int                     cnt;
 355 {
 356         int                     i;
 357
 358         MII_CLR(RL_MII_CLK);
 359
 360         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
 361                 if (bits & i) {
 362                         MII_SET(RL_MII_DATAOUT);
 363                 } else {
 364                         MII_CLR(RL_MII_DATAOUT);
 365                 }
 366                 DELAY(1);
 367                 MII_CLR(RL_MII_CLK);
 368                 DELAY(1);
 369                 MII_SET(RL_MII_CLK);
 370         }
 371 }
 372
 373 /*
 374  * Read an PHY register through the MII.
 375  */
 376 static int rl_mii_readreg(sc, frame)
 377         struct rl_softc         *sc;
 378         struct rl_mii_frame     *frame;
 379
 380 {
 381         int                     i, ack, s;
 382
 383         s = splimp();
 384
 385         /*
 386          * Set up frame for RX.
 387          */
 388         frame->mii_stdelim = RL_MII_STARTDELIM;
 389         frame->mii_opcode = RL_MII_READOP;
 390         frame->mii_turnaround = 0;
 391         frame->mii_data = 0;
 392
 393         CSR_WRITE_2(sc, RL_MII, 0);
 394
 395         /*
 396          * Turn on data xmit.
 397          */
 398         MII_SET(RL_MII_DIR);
 399
 400         rl_mii_sync(sc);
 401
 402         /*
 403          * Send command/address info.
 404          */
 405         rl_mii_send(sc, frame->mii_stdelim, 2);
 406         rl_mii_send(sc, frame->mii_opcode, 2);
 407         rl_mii_send(sc, frame->mii_phyaddr, 5);
 408         rl_mii_send(sc, frame->mii_regaddr, 5);
 409
 410         /* Idle bit */
 411         MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
 412         DELAY(1);
 413         MII_SET(RL_MII_CLK);
 414         DELAY(1);
 415
 416         /* Turn off xmit. */
 417         MII_CLR(RL_MII_DIR);
 418
 419         /* Check for ack */
 420         MII_CLR(RL_MII_CLK);
 421         DELAY(1);
 422         MII_SET(RL_MII_CLK);
 423         DELAY(1);
 424         ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
 425
 426         /*
 427          * Now try reading data bits. If the ack failed, we still
 428          * need to clock through 16 cycles to keep the PHY(s) in sync.
 429          */
 430         if (ack) {
 431                 for(i = 0; i < 16; i++) {
 432                         MII_CLR(RL_MII_CLK);
 433                         DELAY(1);
 434                         MII_SET(RL_MII_CLK);
 435                         DELAY(1);
 436                 }
 437                 goto fail;
 438         }
 439
 440         for (i = 0x8000; i; i >>= 1) {
 441                 MII_CLR(RL_MII_CLK);
 442                 DELAY(1);
 443                 if (!ack) {
 444                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
 445                                 frame->mii_data |= i;
 446                         DELAY(1);
 447                 }
 448                 MII_SET(RL_MII_CLK);
 449                 DELAY(1);
 450         }
 451
 452 fail:
 453
 454         MII_CLR(RL_MII_CLK);
 455         DELAY(1);
 456         MII_SET(RL_MII_CLK);
 457         DELAY(1);
 458
 459         splx(s);
 460
 461         if (ack)
 462                 return(1);
 463         return(0);
 464 }
 465
 466 /*
 467  * Write to a PHY register through the MII.
 468  */
 469 static int rl_mii_writereg(sc, frame)
 470         struct rl_softc         *sc;
 471         struct rl_mii_frame     *frame;
 472
 473 {
 474         int                     s;
 475
 476         s = splimp();
 477         /*
 478          * Set up frame for TX.
 479          */
 480
 481         frame->mii_stdelim = RL_MII_STARTDELIM;
 482         frame->mii_opcode = RL_MII_WRITEOP;
 483         frame->mii_turnaround = RL_MII_TURNAROUND;
 484
 485         /*
 486          * Turn on data output.
 487          */
 488         MII_SET(RL_MII_DIR);
 489
 490         rl_mii_sync(sc);
 491
 492         rl_mii_send(sc, frame->mii_stdelim, 2);
 493         rl_mii_send(sc, frame->mii_opcode, 2);
 494         rl_mii_send(sc, frame->mii_phyaddr, 5);
 495         rl_mii_send(sc, frame->mii_regaddr, 5);
 496         rl_mii_send(sc, frame->mii_turnaround, 2);
 497         rl_mii_send(sc, frame->mii_data, 16);
 498
 499         /* Idle bit. */
 500         MII_SET(RL_MII_CLK);
 501         DELAY(1);
 502         MII_CLR(RL_MII_CLK);
 503         DELAY(1);
 504
 505         /*
 506          * Turn off xmit.
 507          */
 508         MII_CLR(RL_MII_DIR);
 509
 510         splx(s);
 511
 512         return(0);
 513 }
 514
 515 static u_int16_t rl_phy_readreg(sc, reg)
 516         struct rl_softc         *sc;
 517         int                     reg;
 518 {
 519         struct rl_mii_frame     frame;
 520         u_int16_t               rval = 0;
 521         u_int16_t               rl8139_reg = 0;
 522
 523         if (sc->rl_type == RL_8139) {
 524                 switch(reg) {
 525                 case PHY_BMCR:
 526                         rl8139_reg = RL_BMCR;
 527                         break;
 528                 case PHY_BMSR:
 529                         rl8139_reg = RL_BMSR;
 530                         break;
 531                 case PHY_ANAR:
 532                         rl8139_reg = RL_ANAR;
 533                         break;
 534                 case PHY_LPAR:
 535                         rl8139_reg = RL_LPAR;
 536                         break;
 537                 default:
 538                         printf("rl%d: bad phy register\n", sc->rl_unit);
 539                         return(0);
 540                 }
 541                 rval = CSR_READ_2(sc, rl8139_reg);
 542                 return(rval);
 543         }
 544
 545         bzero((char *)&frame, sizeof(frame));
 546
 547         frame.mii_phyaddr = sc->rl_phy_addr;
 548         frame.mii_regaddr = reg;
 549         rl_mii_readreg(sc, &frame);
 550
 551         return(frame.mii_data);
 552 }
 553
 554 static void rl_phy_writereg(sc, reg, data)
 555         struct rl_softc         *sc;
 556         u_int16_t               reg;
 557         u_int16_t               data;
 558 {
 559         struct rl_mii_frame     frame;
 560         u_int16_t               rl8139_reg = 0;
 561
 562         if (sc->rl_type == RL_8139) {
 563                 switch(reg) {
 564                 case PHY_BMCR:
 565                         rl8139_reg = RL_BMCR;
 566                         break;
 567                 case PHY_BMSR:
 568                         rl8139_reg = RL_BMSR;
 569                         break;
 570                 case PHY_ANAR:
 571                         rl8139_reg = RL_ANAR;
 572                         break;
 573                 case PHY_LPAR:
 574                         rl8139_reg = RL_LPAR;
 575                         break;
 576                 default:
 577                         printf("rl%d: bad phy register\n", sc->rl_unit);
 578                         return;
 579                 }
 580                 CSR_WRITE_2(sc, rl8139_reg, data);
 581         }
 582
 583         bzero((char *)&frame, sizeof(frame));
 584
 585         frame.mii_phyaddr = sc->rl_phy_addr;
 586         frame.mii_regaddr = reg;
 587         frame.mii_data = data;
 588
 589         rl_mii_writereg(sc, &frame);
 590
 591         return;
 592 }
 593
 594 /*
 595  * Calculate CRC of a multicast group address, return the lower 6 bits.
 596  */
 597 static u_int8_t rl_calchash(addr)
 598         u_int8_t                *addr;
 599 {
 600         u_int32_t               crc, carry;
 601         int                     i, j;
 602         u_int8_t                c;
 603
 604         /* Compute CRC for the address value. */
 605         crc = 0xFFFFFFFF; /* initial value */
 606
 607         for (i = 0; i < 6; i++) {
 608                 c = *(addr + i);
 609                 for (j = 0; j < 8; j++) {
 610                         carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
 611                         crc <<= 1;
 612                         c >>= 1;
 613                         if (carry)
 614                                 crc = (crc ^ 0x04c11db6) | carry;
 615                 }
 616         }
 617
 618         /* return the filter bit position */
 619         return(crc & 0x0000003F);
 620 }
 621
 622 /*
 623  * Program the 64-bit multicast hash filter.
 624  */
 625 static void rl_setmulti(sc)
 626         struct rl_softc         *sc;
 627 {
 628         struct ifnet            *ifp;
 629         int                     h = 0;
 630         u_int32_t               hashes[2] = { 0, 0 };
 631         struct ifmultiaddr      *ifma;
 632         u_int32_t               rxfilt;
 633         int                     mcnt = 0;
 634
 635         ifp = &sc->arpcom.ac_if;
 636
 637         rxfilt = CSR_READ_4(sc, RL_RXCFG);
 638
 639         if (ifp->if_flags & IFF_ALLMULTI) {
 640                 rxfilt |= RL_RXCFG_RX_MULTI;
 641                 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 642                 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
 643                 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
 644                 return;
 645         }
 646
 647         /* first, zot all the existing hash bits */
 648         CSR_WRITE_4(sc, RL_MAR0, 0);
 649         CSR_WRITE_4(sc, RL_MAR4, 0);
 650
 651         /* now program new ones */
 652         for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
 653                                 ifma = ifma->ifma_link.le_next) {
 654                 if (ifma->ifma_addr->sa_family != AF_LINK)
 655                         continue;
 656                 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 657                 if (h < 32)
 658                         hashes[0] |= (1 << h);
 659                 else
 660                         hashes[1] |= (1 << (h - 32));
 661                 mcnt++;
 662         }
 663
 664         if (mcnt)
 665                 rxfilt |= RL_RXCFG_RX_MULTI;
 666         else
 667                 rxfilt &= ~RL_RXCFG_RX_MULTI;
 668
 669         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 670         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
 671         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
 672
 673         return;
 674 }
 675
 676 /*
 677  * Initiate an autonegotiation session.
 678  */
 679 static void rl_autoneg_xmit(sc)
 680         struct rl_softc         *sc;
 681 {
 682         u_int16_t               phy_sts;
 683
 684         rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
 685         DELAY(500);
 686         while(rl_phy_readreg(sc, PHY_BMCR)
 687                         & PHY_BMCR_RESET);
 688
 689         phy_sts = rl_phy_readreg(sc, PHY_BMCR);
 690         phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
 691         rl_phy_writereg(sc, PHY_BMCR, phy_sts);
 692
 693         return;
 694 }
 695
 696 /*
 697  * Invoke autonegotiation on a PHY. Also used with the 8139 internal
 698  * transceiver.
 699  */
 700 static void rl_autoneg_mii(sc, flag, verbose)
 701         struct rl_softc         *sc;
 702         int                     flag;
 703         int                     verbose;
 704 {
 705         u_int16_t               phy_sts = 0, media, advert, ability;
 706         struct ifnet            *ifp;
 707         struct ifmedia          *ifm;
 708
 709         ifm = &sc->ifmedia;
 710         ifp = &sc->arpcom.ac_if;
 711
 712         /*
 713          * The 100baseT4 PHY sometimes has the 'autoneg supported'
 714          * bit cleared in the status register, but has the 'autoneg enabled'
 715          * bit set in the control register. This is a contradiction, and
 716          * I'm not sure how to handle it. If you want to force an attempt
 717          * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
 718          * and see what happens.
 719          */
 720 #ifndef FORCE_AUTONEG_TFOUR
 721         /*
 722          * First, see if autoneg is supported. If not, there's
 723          * no point in continuing.
 724          */
 725         phy_sts = rl_phy_readreg(sc, PHY_BMSR);
 726         if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
 727                 if (verbose)
 728                         printf("rl%d: autonegotiation not supported\n",
 729                                                         sc->rl_unit);
 730                 return;
 731         }
 732 #endif
 733
 734         switch (flag) {
 735         case RL_FLAG_FORCEDELAY:
 736                 /*
 737                  * XXX Never use this option anywhere but in the probe
 738                  * routine: making the kernel stop dead in its tracks
 739                  * for three whole seconds after we've gone multi-user
 740                  * is really bad manners.
 741                  */
 742                 rl_autoneg_xmit(sc);
 743                 DELAY(5000000);
 744                 break;
 745         case RL_FLAG_SCHEDDELAY:
 746                 /*
 747                  * Wait for the transmitter to go idle before starting
 748                  * an autoneg session, otherwise rl_start() may clobber
 749                  * our timeout, and we don't want to allow transmission
 750                  * during an autoneg session since that can screw it up.
 751                  */
 752                 if (sc->rl_cdata.rl_tx_cnt) {
 753                         sc->rl_want_auto = 1;
 754                         return;
 755                 }
 756                 rl_autoneg_xmit(sc);
 757                 ifp->if_timer = 5;
 758                 sc->rl_autoneg = 1;
 759                 sc->rl_want_auto = 0;
 760                 return;
 761                 break;
 762         case RL_FLAG_DELAYTIMEO:
 763                 ifp->if_timer = 0;
 764                 sc->rl_autoneg = 0;
 765                 break;
 766         default:
 767                 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag);
 768                 return;
 769         }
 770
 771         if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
 772                 if (verbose)
 773                         printf("rl%d: autoneg complete, ", sc->rl_unit);
 774                 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
 775         } else {
 776                 if (verbose)
 777                         printf("rl%d: autoneg not complete, ", sc->rl_unit);
 778         }
 779
 780         media = rl_phy_readreg(sc, PHY_BMCR);
 781
 782         /* Link is good. Report modes and set duplex mode. */
 783         if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
 784                 if (verbose)
 785                         printf("link status good ");
 786                 advert = rl_phy_readreg(sc, PHY_ANAR);
 787                 ability = rl_phy_readreg(sc, PHY_LPAR);
 788
 789                 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
 790                         ifm->ifm_media = IFM_ETHER|IFM_100_T4;
 791                         media |= PHY_BMCR_SPEEDSEL;
 792                         media &= ~PHY_BMCR_DUPLEX;
 793                         printf("(100baseT4)\n");
 794                 } else if (advert & PHY_ANAR_100BTXFULL &&
 795                         ability & PHY_ANAR_100BTXFULL) {
 796                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
 797                         media |= PHY_BMCR_SPEEDSEL;
 798                         media |= PHY_BMCR_DUPLEX;
 799                         printf("(full-duplex, 100Mbps)\n");
 800                 } else if (advert & PHY_ANAR_100BTXHALF &&
 801                         ability & PHY_ANAR_100BTXHALF) {
 802                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
 803                         media |= PHY_BMCR_SPEEDSEL;
 804                         media &= ~PHY_BMCR_DUPLEX;
 805                         printf("(half-duplex, 100Mbps)\n");
 806                 } else if (advert & PHY_ANAR_10BTFULL &&
 807                         ability & PHY_ANAR_10BTFULL) {
 808                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
 809                         media &= ~PHY_BMCR_SPEEDSEL;
 810                         media |= PHY_BMCR_DUPLEX;
 811                         printf("(full-duplex, 10Mbps)\n");
 812                 } else if (advert & PHY_ANAR_10BTHALF &&
 813                         ability & PHY_ANAR_10BTHALF) {
 814                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
 815                         media &= ~PHY_BMCR_SPEEDSEL;
 816                         media &= ~PHY_BMCR_DUPLEX;
 817                         printf("(half-duplex, 10Mbps)\n");
 818                 } else {
 819                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
 820                         media &= ~PHY_BMCR_SPEEDSEL;
 821                         media &= ~PHY_BMCR_DUPLEX;
 822                         printf("(unknown mode! forcing half-duplex, 10Mbps)\n");
 823                 }
 824
 825                 /* Set ASIC's duplex mode to match the PHY. */
 826                 rl_phy_writereg(sc, PHY_BMCR, media);
 827         } else {
 828                 if (verbose)
 829                         printf("no carrier\n");
 830         }
 831
 832         rl_init(sc);
 833
 834         if (sc->rl_tx_pend) {
 835                 sc->rl_autoneg = 0;
 836                 sc->rl_tx_pend = 0;
 837                 rl_start(ifp);
 838         }
 839
 840         return;
 841 }
 842
 843 static void rl_getmode_mii(sc)
 844         struct rl_softc         *sc;
 845 {
 846         u_int16_t               bmsr;
 847         struct ifnet            *ifp;
 848
 849         ifp = &sc->arpcom.ac_if;
 850
 851         bmsr = rl_phy_readreg(sc, PHY_BMSR);
 852         if (bootverbose)
 853                 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr);
 854
 855         /* fallback */
 856         sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
 857
 858         if (bmsr & PHY_BMSR_10BTHALF) {
 859                 if (bootverbose)
 860                         printf("rl%d: 10Mbps half-duplex mode supported\n",
 861                                                                 sc->rl_unit);
 862                 ifmedia_add(&sc->ifmedia,
 863                         IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
 864                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 865         }
 866
 867         if (bmsr & PHY_BMSR_10BTFULL) {
 868                 if (bootverbose)
 869                         printf("rl%d: 10Mbps full-duplex mode supported\n",
 870                                                                 sc->rl_unit);
 871                 ifmedia_add(&sc->ifmedia,
 872                         IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
 873                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
 874         }
 875
 876         if (bmsr & PHY_BMSR_100BTXHALF) {
 877                 if (bootverbose)
 878                         printf("rl%d: 100Mbps half-duplex mode supported\n",
 879                                                                 sc->rl_unit);
 880                 ifp->if_baudrate = 100000000;
 881                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
 882                 ifmedia_add(&sc->ifmedia,
 883                         IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
 884                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
 885         }
 886
 887         if (bmsr & PHY_BMSR_100BTXFULL) {
 888                 if (bootverbose)
 889                         printf("rl%d: 100Mbps full-duplex mode supported\n",
 890                                                                 sc->rl_unit);
 891                 ifp->if_baudrate = 100000000;
 892                 ifmedia_add(&sc->ifmedia,
 893                         IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
 894                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
 895         }
 896
 897         /* Some also support 100BaseT4. */
 898         if (bmsr & PHY_BMSR_100BT4) {
 899                 if (bootverbose)
 900                         printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit);
 901                 ifp->if_baudrate = 100000000;
 902                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
 903                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
 904 #ifdef FORCE_AUTONEG_TFOUR
 905                 if (bootverbose)
 906                         printf("rl%d: forcing on autoneg support for BT4\n",
 907                                                          sc->rl_unit);
 908                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
 909                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
 910 #endif
 911         }
 912
 913         if (bmsr & PHY_BMSR_CANAUTONEG) {
 914                 if (bootverbose)
 915                         printf("rl%d: autoneg supported\n", sc->rl_unit);
 916                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 917                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
 918         }
 919
 920         return;
 921 }
 922
 923 /*
 924  * Set speed and duplex mode.
 925  */
 926 static void rl_setmode_mii(sc, media)
 927         struct rl_softc         *sc;
 928         int                     media;
 929 {
 930         u_int16_t               bmcr;
 931
 932         printf("rl%d: selecting MII, ", sc->rl_unit);
 933
 934         bmcr = rl_phy_readreg(sc, PHY_BMCR);
 935
 936         bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
 937                         PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
 938
 939         if (IFM_SUBTYPE(media) == IFM_100_T4) {
 940                 printf("100Mbps/T4, half-duplex\n");
 941                 bmcr |= PHY_BMCR_SPEEDSEL;
 942                 bmcr &= ~PHY_BMCR_DUPLEX;
 943         }
 944
 945         if (IFM_SUBTYPE(media) == IFM_100_TX) {
 946                 printf("100Mbps, ");
 947                 bmcr |= PHY_BMCR_SPEEDSEL;
 948         }
 949
 950         if (IFM_SUBTYPE(media) == IFM_10_T) {
 951                 printf("10Mbps, ");
 952                 bmcr &= ~PHY_BMCR_SPEEDSEL;
 953         }
 954
 955         if ((media & IFM_GMASK) == IFM_FDX) {
 956                 printf("full duplex\n");
 957                 bmcr |= PHY_BMCR_DUPLEX;
 958         } else {
 959                 printf("half duplex\n");
 960                 bmcr &= ~PHY_BMCR_DUPLEX;
 961         }
 962
 963         rl_phy_writereg(sc, PHY_BMCR, bmcr);
 964
 965         return;
 966 }
 967
 968 static void rl_reset(sc)
 969         struct rl_softc         *sc;
 970 {
 971         register int            i;
 972
 973         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
 974
 975         for (i = 0; i < RL_TIMEOUT; i++) {
 976                 DELAY(10);
 977                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
 978                         break;
 979         }
 980         if (i == RL_TIMEOUT)
 981                 printf("rl%d: reset never completed!\n", sc->rl_unit);
 982
 983         return;
 984 }
 985
 986 /*
 987  * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
 988  * IDs against our list and return a device name if we find a match.
 989  */
 990 static char *
 991 rl_probe(config_id, device_id)
 992         pcici_t                 config_id;
 993         pcidi_t                 device_id;
 994 {
 995         struct rl_type          *t;
 996
 997         t = rl_devs;
 998
 999         while(t->rl_name != NULL) {
1000                 if ((device_id & 0xFFFF) == t->rl_vid &&
1001                     ((device_id >> 16) & 0xFFFF) == t->rl_did) {
1002                         return(t->rl_name);
1003                 }
1004                 t++;
1005         }
1006
1007         return(NULL);
1008 }
1009
1010 /*
1011  * Attach the interface. Allocate softc structures, do ifmedia
1012  * setup and ethernet/BPF attach.
1013  */
1014 static void
1015 rl_attach(config_id, unit)
1016         pcici_t                 config_id;
1017         int                     unit;
1018 {
1019         int                     s, i;
1020 #ifndef RL_USEIOSPACE
1021         vm_offset_t             pbase, vbase;
1022 #endif
1023         u_char                  eaddr[ETHER_ADDR_LEN];
1024         u_int32_t               command;
1025         struct rl_softc         *sc;
1026         struct ifnet            *ifp;
1027         int                     media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1028         struct rl_type          *p;
1029         u_int16_t               phy_vid, phy_did, phy_sts;
1030         u_int16_t               rl_did = 0;
1031
1032         s = splimp();
1033
1034         sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT);
1035         if (sc == NULL) {
1036                 printf("rl%d: no memory for softc struct!\n", unit);
1037                 return;
1038         }
1039         bzero(sc, sizeof(struct rl_softc));
1040
1041         /*
1042          * Handle power management nonsense.
1043          */
1044
1045         command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF;
1046         if (command == 0x01) {
1047
1048                 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL);
1049                 if (command & RL_PSTATE_MASK) {
1050                         u_int32_t               iobase, membase, irq;
1051
1052                         /* Save important PCI config data. */
1053                         iobase = pci_conf_read(config_id, RL_PCI_LOIO);
1054                         membase = pci_conf_read(config_id, RL_PCI_LOMEM);
1055                         irq = pci_conf_read(config_id, RL_PCI_INTLINE);
1056
1057                         /* Reset the power state. */
1058                         printf("rl%d: chip is is in D%d power mode "
1059                         "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
1060                         command &= 0xFFFFFFFC;
1061                         pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command);
1062
1063                         /* Restore PCI config data. */
1064                         pci_conf_write(config_id, RL_PCI_LOIO, iobase);
1065                         pci_conf_write(config_id, RL_PCI_LOMEM, membase);
1066                         pci_conf_write(config_id, RL_PCI_INTLINE, irq);
1067                 }
1068         }
1069
1070         /*
1071          * Map control/status registers.
1072          */
1073         command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1074         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1075         pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1076         command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1077
1078 #ifdef RL_USEIOSPACE
1079         if (!(command & PCIM_CMD_PORTEN)) {
1080                 printf("rl%d: failed to enable I/O ports!\n", unit);
1081                 free(sc, M_DEVBUF);
1082                 goto fail;
1083         }
1084
1085         sc->iobase = pci_conf_read(config_id, RL_PCI_LOIO) & 0xFFFFFFFC;
1086 #else
1087         if (!(command & PCIM_CMD_MEMEN)) {
1088                 printf("rl%d: failed to enable memory mapping!\n", unit);
1089                 goto fail;
1090         }
1091
1092         if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) {
1093                 printf ("rl%d: couldn't map memory\n", unit);
1094                 goto fail;
1095         }
1096         sc->csr = (volatile caddr_t)vbase;
1097 #endif
1098
1099         /* Allocate interrupt */
1100         if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) {
1101                 printf("rl%d: couldn't map interrupt\n", unit);
1102                 goto fail;
1103         }
1104
1105         /* Reset the adapter. */
1106         rl_reset(sc);
1107
1108         /*
1109          * Get station address from the EEPROM.
1110          */
1111         rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
1112
1113         /*
1114          * A RealTek chip was detected. Inform the world.
1115          */
1116         printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1117
1118         sc->rl_unit = unit;
1119         bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1120
1121         /*
1122          * Now read the exact device type from the EEPROM to find
1123          * out if it's an 8129 or 8139.
1124          */
1125         rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1126
1127         if (rl_did == RT_DEVICEID_8139)
1128                 sc->rl_type = RL_8139;
1129         else if (rl_did == RT_DEVICEID_8129)
1130                 sc->rl_type = RL_8129;
1131         else {
1132                 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1133                 free(sc, M_DEVBUF);
1134                 goto fail;
1135         }
1136
1137         sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 16, M_DEVBUF,
1138                 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
1139
1140         if (sc->rl_cdata.rl_rx_buf == NULL) {
1141                 free(sc, M_DEVBUF);
1142                 printf("rl%d: no memory for list buffers!\n", unit);
1143                 goto fail;
1144         }
1145
1146         ifp = &sc->arpcom.ac_if;
1147         ifp->if_softc = sc;
1148         ifp->if_unit = unit;
1149         ifp->if_name = "rl";
1150         ifp->if_mtu = ETHERMTU;
1151         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1152         ifp->if_ioctl = rl_ioctl;
1153         ifp->if_output = ether_output;
1154         ifp->if_start = rl_start;
1155         ifp->if_watchdog = rl_watchdog;
1156         ifp->if_init = rl_init;
1157         ifp->if_baudrate = 10000000;
1158
1159         if (sc->rl_type == RL_8129) {
1160                 if (bootverbose)
1161                         printf("rl%d: probing for a PHY\n", sc->rl_unit);
1162                 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) {
1163                         if (bootverbose)
1164                                 printf("rl%d: checking address: %d\n",
1165                                                         sc->rl_unit, i);
1166                         sc->rl_phy_addr = i;
1167                         rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1168                         DELAY(500);
1169                         while(rl_phy_readreg(sc, PHY_BMCR)
1170                                         & PHY_BMCR_RESET);
1171                         if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR)))
1172                                 break;
1173                 }
1174                 if (phy_sts) {
1175                         phy_vid = rl_phy_readreg(sc, PHY_VENID);
1176                         phy_did = rl_phy_readreg(sc, PHY_DEVID);
1177                         if (bootverbose)
1178                                 printf("rl%d: found PHY at address %d, ",
1179                                                 sc->rl_unit, sc->rl_phy_addr);
1180                         if (bootverbose)
1181                                 printf("vendor id: %x device id: %x\n",
1182                                         phy_vid, phy_did);
1183                         p = rl_phys;
1184                         while(p->rl_vid) {
1185                                 if (phy_vid == p->rl_vid &&
1186                                         (phy_did | 0x000F) == p->rl_did) {
1187                                         sc->rl_pinfo = p;
1188                                         break;
1189                                 }
1190                                 p++;
1191                         }
1192                         if (sc->rl_pinfo == NULL)
1193                                 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN];
1194                         if (bootverbose)
1195                                 printf("rl%d: PHY type: %s\n",
1196                                         sc->rl_unit, sc->rl_pinfo->rl_name);
1197                 } else {
1198                         printf("rl%d: MII without any phy!\n", sc->rl_unit);
1199                 }
1200         }
1201
1202         /*
1203          * Do ifmedia setup.
1204          */
1205         ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts);
1206
1207         rl_getmode_mii(sc);
1208
1209         /* Choose a default media. */
1210         media = IFM_ETHER|IFM_AUTO;
1211         ifmedia_set(&sc->ifmedia, media);
1212
1213         rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1);
1214
1215         /*
1216          * Call MI attach routines.
1217          */
1218         if_attach(ifp);
1219         ether_ifattach(ifp);
1220
1221 #if NBPFILTER > 0
1222         bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1223 #endif
1224         at_shutdown(rl_shutdown, sc, SHUTDOWN_POST_SYNC);
1225
1226 fail:
1227         splx(s);
1228         return;
1229 }
1230
1231 /*
1232  * Initialize the transmit descriptors.
1233  */
1234 static int rl_list_tx_init(sc)
1235         struct rl_softc         *sc;
1236 {
1237         struct rl_chain_data    *cd;
1238         int                     i;
1239
1240         cd = &sc->rl_cdata;
1241         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1242                 cd->rl_tx_chain[i].rl_desc = i * 4;
1243                 CSR_WRITE_4(sc, RL_TXADDR0 + cd->rl_tx_chain[i].rl_desc, 0);
1244                 CSR_WRITE_4(sc, RL_TXSTAT0 + cd->rl_tx_chain[i].rl_desc, 0);
1245                 if (i == (RL_TX_LIST_CNT - 1))
1246                         cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[0];
1247                 else
1248                         cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[i + 1];
1249         }
1250
1251         sc->rl_cdata.rl_tx_cnt = 0;
1252         cd->rl_tx_cur = cd->rl_tx_free = &cd->rl_tx_chain[0];
1253
1254         return(0);
1255 }
1256
1257 /*
1258  * A frame has been uploaded: pass the resulting mbuf chain up to
1259  * the higher level protocols.
1260  *
1261  * You know there's something wrong with a PCI bus-master chip design
1262  * when you have to use m_devget().
1263  *
1264  * The receive operation is badly documented in the datasheet, so I'll
1265  * attempt to document it here. The driver provides a buffer area and
1266  * places its base address in the RX buffer start address register.
1267  * The chip then begins copying frames into the RX buffer. Each frame
1268  * is preceeded by a 32-bit RX status word which specifies the length
1269  * of the frame and certain other status bits. Each frame (starting with
1270  * the status word) is also 32-bit aligned. The frame length is in the
1271  * first 16 bits of the status word; the lower 15 bits correspond with
1272  * the 'rx status register' mentioned in the datasheet.
1273  */
1274 static void rl_rxeof(sc)
1275         struct rl_softc         *sc;
1276 {
1277         struct ether_header     *eh;
1278         struct mbuf             *m;
1279         struct ifnet            *ifp;
1280         int                     total_len = 0;
1281         u_int32_t               rxstat;
1282         caddr_t                 rxbufpos;
1283         int                     wrap = 0;
1284         u_int16_t               cur_rx;
1285         u_int16_t               limit;
1286         u_int16_t               rx_bytes = 0, max_bytes;
1287
1288         ifp = &sc->arpcom.ac_if;
1289
1290         cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1291
1292         /* Do not try to read past this point. */
1293         limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1294
1295         if (limit < cur_rx)
1296                 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1297         else
1298                 max_bytes = limit - cur_rx;
1299
1300         while((CSR_READ_1(sc, RL_COMMAND) & 1) == 0) {
1301                 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1302                 rxstat = *(u_int32_t *)rxbufpos;
1303
1304                 /*
1305                  * Here's a totally undocumented fact for you. When the
1306                  * RealTek chip is in the process of copying a packet into
1307                  * RAM for you, the length will be 0xfff0. If you spot a
1308                  * packet header with this value, you need to stop. The
1309                  * datasheet makes absolutely no mention of this and
1310                  * RealTek should be shot for this.
1311                  */
1312                 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1313                         break;
1314
1315                 if (!(rxstat & RL_RXSTAT_RXOK)) {
1316                         ifp->if_ierrors++;
1317                         if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT|
1318                                         RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR|
1319                                         RL_RXSTAT_ALIGNERR)) {
1320                                 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB);
1321                                 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB|
1322                                                         RL_CMD_RX_ENB);
1323                                 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1324                                 CSR_WRITE_4(sc, RL_RXADDR,
1325                                         vtophys(sc->rl_cdata.rl_rx_buf));
1326                                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1327                                 cur_rx = 0;
1328                         }
1329                         break;
1330                 }
1331
1332                 /* No errors; receive the packet. */
1333                 total_len = rxstat >> 16;
1334                 rx_bytes += total_len + 4;
1335
1336                 /*
1337                  * Avoid trying to read more bytes than we know
1338                  * the chip has prepared for us.
1339                  */
1340                 if (rx_bytes > max_bytes)
1341                         break;
1342
1343                 rxbufpos = sc->rl_cdata.rl_rx_buf +
1344                         ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1345
1346                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1347                         rxbufpos = sc->rl_cdata.rl_rx_buf;
1348
1349                 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1350
1351                 if (total_len > wrap) {
1352                         m = m_devget(rxbufpos, wrap, 0, ifp, NULL);
1353                         if (m == NULL) {
1354                                 ifp->if_ierrors++;
1355                                 printf("rl%d: out of mbufs, tried to "
1356                                         "copy %d bytes\n", sc->rl_unit, wrap);
1357                         }
1358                         else
1359                                 m_copyback(m, wrap, total_len - wrap,
1360                                         sc->rl_cdata.rl_rx_buf);
1361                         cur_rx = (total_len - wrap);
1362                 } else {
1363                         m = m_devget(rxbufpos, total_len, 0, ifp, NULL);
1364                         if (m == NULL) {
1365                                 ifp->if_ierrors++;
1366                                 printf("rl%d: out of mbufs, tried to "
1367                                 "copy %d bytes\n", sc->rl_unit, total_len);
1368                         }
1369                         cur_rx += total_len + 4;
1370                 }
1371
1372                 /*
1373                  * Round up to 32-bit boundary.
1374                  */
1375                 cur_rx = (cur_rx + 3) & ~3;
1376                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1377
1378                 if (m == NULL)
1379                         continue;
1380
1381                 eh = mtod(m, struct ether_header *);
1382                 ifp->if_ipackets++;
1383
1384 #if NBPFILTER > 0
1385                 /*
1386                  * Handle BPF listeners. Let the BPF user see the packet, but
1387                  * don't pass it up to the ether_input() layer unless it's
1388                  * a broadcast packet, multicast packet, matches our ethernet
1389                  * address or the interface is in promiscuous mode.
1390                  */
1391                 if (ifp->if_bpf) {
1392                         bpf_mtap(ifp, m);
1393                         if (ifp->if_flags & IFF_PROMISC &&
1394                                 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1395                                                 ETHER_ADDR_LEN) &&
1396                                         (eh->ether_dhost[0] & 1) == 0)) {
1397                                 m_freem(m);
1398                                 continue;
1399                         }
1400                 }
1401 #endif
1402                 /* Remove header from mbuf and pass it on. */
1403                 m_adj(m, sizeof(struct ether_header));
1404                 ether_input(ifp, eh, m);
1405         }
1406
1407         return;
1408 }
1409
1410 /*
1411  * A frame was downloaded to the chip. It's safe for us to clean up
1412  * the list buffers.
1413  */
1414 static void rl_txeof(sc)
1415         struct rl_softc         *sc;
1416 {
1417         struct rl_chain         *cur_tx;
1418         struct ifnet            *ifp;
1419         u_int32_t               txstat;
1420
1421         ifp = &sc->arpcom.ac_if;
1422
1423         /* Clear the timeout timer. */
1424         ifp->if_timer = 0;
1425
1426         /*
1427          * Go through our tx list and free mbufs for those
1428          * frames that have been uploaded.
1429          */
1430         if (sc->rl_cdata.rl_tx_free == NULL)
1431                 return;
1432
1433         while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) {
1434                 cur_tx = sc->rl_cdata.rl_tx_free;
1435                 txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc);
1436
1437                 if (!(txstat & RL_TXSTAT_TX_OK))
1438                         break;
1439
1440                 if (txstat & RL_TXSTAT_COLLCNT)
1441                         ifp->if_collisions +=
1442                                         (txstat & RL_TXSTAT_COLLCNT) >> 24;
1443
1444                 sc->rl_cdata.rl_tx_free = cur_tx->rl_next;
1445
1446                 sc->rl_cdata.rl_tx_cnt--;
1447                 m_freem(cur_tx->rl_mbuf);
1448                 cur_tx->rl_mbuf = NULL;
1449                 ifp->if_opackets++;
1450         }
1451
1452         if (!sc->rl_cdata.rl_tx_cnt) {
1453                 ifp->if_flags &= ~IFF_OACTIVE;
1454                 if (sc->rl_want_auto)
1455                         rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1456         } else {
1457                 if (ifp->if_snd.ifq_head != NULL)
1458                         rl_start(ifp);
1459         }
1460
1461         return;
1462 }
1463
1464 /*
1465  * TX error handler.
1466  */
1467 static void rl_txeoc(sc)
1468         struct rl_softc         *sc;
1469 {
1470         u_int32_t               txstat;
1471         struct rl_chain         *cur_tx;
1472         struct ifnet            *ifp;
1473
1474         ifp = &sc->arpcom.ac_if;
1475
1476         if (sc->rl_cdata.rl_tx_free == NULL)
1477                 return;
1478
1479         while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) {
1480                 cur_tx = sc->rl_cdata.rl_tx_free;
1481                 txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc);
1482
1483                 if (!(txstat & RL_TXSTAT_OWN))
1484                         break;
1485
1486                 if (!(txstat & RL_TXSTAT_TX_OK)) {
1487                         ifp->if_oerrors++;
1488                         if (txstat & RL_TXSTAT_COLLCNT)
1489                                 ifp->if_collisions +=
1490                                         (txstat & RL_TXSTAT_COLLCNT) >> 24;
1491                         CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc,
1492                                 vtophys(mtod(cur_tx->rl_mbuf, caddr_t)));
1493                         CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc,
1494                                 RL_TX_EARLYTHRESH |
1495                                         cur_tx->rl_mbuf->m_pkthdr.len);
1496                         break;
1497                 } else {
1498                         if (txstat & RL_TXSTAT_COLLCNT)
1499                                 ifp->if_collisions +=
1500                                         (txstat & RL_TXSTAT_COLLCNT) >> 24;
1501                         sc->rl_cdata.rl_tx_free = cur_tx->rl_next;
1502
1503                         sc->rl_cdata.rl_tx_cnt--;
1504                         m_freem(cur_tx->rl_mbuf);
1505                         cur_tx->rl_mbuf = NULL;
1506                         ifp->if_opackets++;
1507                 }
1508         }
1509
1510         return;
1511 }
1512
1513 static void rl_intr(arg)
1514         void                    *arg;
1515 {
1516         struct rl_softc         *sc;
1517         struct ifnet            *ifp;
1518         u_int16_t               status;
1519
1520         sc = arg;
1521         ifp = &sc->arpcom.ac_if;
1522
1523         /* Disable interrupts. */
1524         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1525
1526         for (;;) {
1527
1528                 status = CSR_READ_2(sc, RL_ISR);
1529                 if (status)
1530                         CSR_WRITE_2(sc, RL_ISR, status);
1531
1532                 if ((status & RL_INTRS) == 0)
1533                         break;
1534
1535                 if (status & RL_ISR_RX_OK)
1536                         rl_rxeof(sc);
1537
1538                 if (status & RL_ISR_RX_ERR)
1539                         rl_rxeof(sc);
1540
1541                 if (status & RL_ISR_TX_OK)
1542                         rl_txeof(sc);
1543
1544                 if (status & RL_ISR_TX_ERR)
1545                         rl_txeoc(sc);
1546
1547                 if (status & RL_ISR_SYSTEM_ERR) {
1548                         rl_reset(sc);
1549                         rl_init(sc);
1550                 }
1551
1552         }
1553
1554         /* Re-enable interrupts. */
1555         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1556
1557         if (ifp->if_snd.ifq_head != NULL) {
1558                 rl_start(ifp);
1559         }
1560
1561         return;
1562 }
1563
1564 /*
1565  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1566  * pointers to the fragment pointers.
1567  */
1568 static int rl_encap(sc, c, m_head)
1569         struct rl_softc         *sc;
1570         struct rl_chain         *c;
1571         struct mbuf             *m_head;
1572 {
1573         struct mbuf             *m;
1574         struct mbuf             *m_new = NULL;
1575
1576         /*
1577          * There are two possible encapsulation mechanisms
1578          * that we can use: an efficient one, and a very lossy
1579          * one. The efficient one only happens very rarely,
1580          * whereas the lossy one can and most likely will happen
1581          * all the time.
1582          * The efficient case happens if:
1583          * - the packet fits in a single mbuf
1584          * - the packet is 32-bit aligned within the mbuf data area
1585          * In this case, we can DMA from the mbuf directly.
1586          * The lossy case covers everything else. Bah.
1587          */
1588
1589         m = m_head;
1590
1591         MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1592         if (m_new == NULL) {
1593                 printf("rl%d: no memory for tx list", sc->rl_unit);
1594                 return(1);
1595         }
1596         if (m_head->m_pkthdr.len > MHLEN) {
1597                 MCLGET(m_new, M_DONTWAIT);
1598                 if (!(m_new->m_flags & M_EXT)) {
1599                         m_freem(m_new);
1600                         printf("rl%d: no memory for tx list",
1601                                         sc->rl_unit);
1602                         return(1);
1603                 }
1604         }
1605         m_copydata(m_head, 0, m_head->m_pkthdr.len,
1606                                 mtod(m_new, caddr_t));
1607         m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1608         m_freem(m_head);
1609         m_head = m_new;
1610
1611         /* Pad frames to at least 60 bytes. */
1612         if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1613                 m_head->m_pkthdr.len +=
1614                         (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1615                 m_head->m_len = m_head->m_pkthdr.len;
1616         }
1617
1618         c->rl_mbuf = m_head;
1619
1620         return(0);
1621 }
1622
1623 /*
1624  * Main transmit routine.
1625  */
1626
1627 static void rl_start(ifp)
1628         struct ifnet            *ifp;
1629 {
1630         struct rl_softc         *sc;
1631         struct mbuf             *m_head = NULL;
1632         struct rl_chain         *cur_tx = NULL;
1633
1634         sc = ifp->if_softc;
1635
1636         if (sc->rl_autoneg) {
1637                 sc->rl_tx_pend = 1;
1638                 return;
1639         }
1640
1641         /*
1642          * Check for an available queue slot. If there are none,
1643          * punt.
1644          */
1645         if (sc->rl_cdata.rl_tx_cur->rl_mbuf != NULL) {
1646                 ifp->if_flags |= IFF_OACTIVE;
1647                 return;
1648         }
1649
1650         while(sc->rl_cdata.rl_tx_cur->rl_mbuf == NULL) {
1651                 IF_DEQUEUE(&ifp->if_snd, m_head);
1652                 if (m_head == NULL)
1653                         break;
1654
1655
1656                 /* Pick a descriptor off the free list. */
1657                 cur_tx = sc->rl_cdata.rl_tx_cur;
1658                 sc->rl_cdata.rl_tx_cur = cur_tx->rl_next;
1659                 sc->rl_cdata.rl_tx_cnt++;
1660
1661                 /* Pack the data into the descriptor. */
1662                 rl_encap(sc, cur_tx, m_head);
1663
1664 #if NBPFILTER > 0
1665                 /*
1666                  * If there's a BPF listener, bounce a copy of this frame
1667                  * to him.
1668                  */
1669                 if (ifp->if_bpf)
1670                         bpf_mtap(ifp, cur_tx->rl_mbuf);
1671 #endif
1672                 /*
1673                  * Transmit the frame.
1674                  */
1675                 CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc,
1676                                 vtophys(mtod(cur_tx->rl_mbuf, caddr_t)));
1677                 CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc,
1678                         RL_TX_EARLYTHRESH | cur_tx->rl_mbuf->m_pkthdr.len);
1679         }
1680
1681         /*
1682          * Set a timeout in case the chip goes out to lunch.
1683          */
1684         ifp->if_timer = 5;
1685
1686         return;
1687 }
1688
1689 static void rl_init(xsc)
1690         void                    *xsc;
1691 {
1692         struct rl_softc         *sc = xsc;
1693         struct ifnet            *ifp = &sc->arpcom.ac_if;
1694         int                     s, i;
1695         u_int32_t               rxcfg = 0;
1696         u_int16_t               phy_bmcr = 0;
1697
1698         if (sc->rl_autoneg)
1699                 return;
1700
1701         s = splimp();
1702
1703         /*
1704          * XXX Hack for the 8139: the built-in autoneg logic's state
1705          * gets reset by rl_init() when we don't want it to. Try
1706          * to preserve it. (For 8129 cards with real external PHYs,
1707          * the BMCR register doesn't change, but this doesn't hurt.)
1708          */
1709         if (sc->rl_type == RL_8139)
1710                 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR);
1711
1712         /*
1713          * Cancel pending I/O and free all RX/TX buffers.
1714          */
1715         rl_stop(sc);
1716
1717         /* Init our MAC address */
1718         for (i = 0; i < ETHER_ADDR_LEN; i++) {
1719                 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1720         }
1721
1722         /* Init the RX buffer pointer register. */
1723         CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1724
1725         /* Init TX descriptors. */
1726         rl_list_tx_init(sc);
1727
1728         /*
1729          * Enable transmit and receive.
1730          */
1731         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1732
1733         /*
1734          * Set the buffer size values.
1735          */
1736         CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1737
1738         /* Set the individual bit to receive frames for this host only. */
1739         rxcfg = CSR_READ_4(sc, RL_RXCFG);
1740         rxcfg |= RL_RXCFG_RX_INDIV;
1741
1742         /* If we want promiscuous mode, set the allframes bit. */
1743         if (ifp->if_flags & IFF_PROMISC) {
1744                 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1745                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1746         } else {
1747                 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1748                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1749         }
1750
1751         /*
1752          * Set capture broadcast bit to capture broadcast frames.
1753          */
1754         if (ifp->if_flags & IFF_BROADCAST) {
1755                 rxcfg |= RL_RXCFG_RX_BROAD;
1756                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1757         } else {
1758                 rxcfg &= ~RL_RXCFG_RX_BROAD;
1759                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1760         }
1761
1762         /*
1763          * Program the multicast filter, if necessary.
1764          */
1765         rl_setmulti(sc);
1766
1767         /*
1768          * Enable interrupts.
1769          */
1770         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1771
1772         /* Start RX/TX process. */
1773         CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1774
1775         /* Enable receiver and transmitter. */
1776         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1777
1778         /* Restore state of BMCR */
1779         if (sc->rl_pinfo != NULL)
1780                 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1781
1782         CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1783
1784         ifp->if_flags |= IFF_RUNNING;
1785         ifp->if_flags &= ~IFF_OACTIVE;
1786
1787         (void)splx(s);
1788
1789         return;
1790 }
1791
1792 /*
1793  * Set media options.
1794  */
1795 static int rl_ifmedia_upd(ifp)
1796         struct ifnet            *ifp;
1797 {
1798         struct rl_softc         *sc;
1799         struct ifmedia          *ifm;
1800
1801         sc = ifp->if_softc;
1802         ifm = &sc->ifmedia;
1803
1804         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1805                 return(EINVAL);
1806
1807         if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1808                 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1809         else
1810                 rl_setmode_mii(sc, ifm->ifm_media);
1811
1812         return(0);
1813 }
1814
1815 /*
1816  * Report current media status.
1817  */
1818 static void rl_ifmedia_sts(ifp, ifmr)
1819         struct ifnet            *ifp;
1820         struct ifmediareq       *ifmr;
1821 {
1822         struct rl_softc         *sc;
1823         u_int16_t               advert = 0, ability = 0;
1824
1825         sc = ifp->if_softc;
1826
1827         if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1828                 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1829                         ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
1830                 else
1831                         ifmr->ifm_active = IFM_ETHER|IFM_10_T;
1832
1833                 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1834                         ifmr->ifm_active |= IFM_FDX;
1835                 else
1836                         ifmr->ifm_active |= IFM_HDX;
1837                 return;
1838         }
1839
1840         ability = rl_phy_readreg(sc, PHY_LPAR);
1841         advert = rl_phy_readreg(sc, PHY_ANAR);
1842         if (advert & PHY_ANAR_100BT4 &&
1843                 ability & PHY_ANAR_100BT4) {
1844                 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
1845         } else if (advert & PHY_ANAR_100BTXFULL &&
1846                 ability & PHY_ANAR_100BTXFULL) {
1847                 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
1848         } else if (advert & PHY_ANAR_100BTXHALF &&
1849                 ability & PHY_ANAR_100BTXHALF) {
1850                 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
1851         } else if (advert & PHY_ANAR_10BTFULL &&
1852                 ability & PHY_ANAR_10BTFULL) {
1853                 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
1854         } else if (advert & PHY_ANAR_10BTHALF &&
1855                 ability & PHY_ANAR_10BTHALF) {
1856                 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
1857         }
1858
1859         return;
1860 }
1861
1862 static int rl_ioctl(ifp, command, data)
1863         struct ifnet            *ifp;
1864         u_long                  command;
1865         caddr_t                 data;
1866 {
1867         struct rl_softc         *sc = ifp->if_softc;
1868         struct ifreq            *ifr = (struct ifreq *) data;
1869         int                     s, error = 0;
1870
1871         s = splimp();
1872
1873         switch(command) {
1874         case SIOCSIFADDR:
1875         case SIOCGIFADDR:
1876         case SIOCSIFMTU:
1877                 error = ether_ioctl(ifp, command, data);
1878                 break;
1879         case SIOCSIFFLAGS:
1880                 if (ifp->if_flags & IFF_UP) {
1881                         rl_init(sc);
1882                 } else {
1883                         if (ifp->if_flags & IFF_RUNNING)
1884                                 rl_stop(sc);
1885                 }
1886                 error = 0;
1887                 break;
1888         case SIOCADDMULTI:
1889         case SIOCDELMULTI:
1890                 rl_setmulti(sc);
1891                 error = 0;
1892                 break;
1893         case SIOCGIFMEDIA:
1894         case SIOCSIFMEDIA:
1895                 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1896                 break;
1897         default:
1898                 error = EINVAL;
1899                 break;
1900         }
1901
1902         (void)splx(s);
1903
1904         return(error);
1905 }
1906
1907 static void rl_watchdog(ifp)
1908         struct ifnet            *ifp;
1909 {
1910         struct rl_softc         *sc;
1911
1912         sc = ifp->if_softc;
1913
1914         if (sc->rl_autoneg) {
1915                 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1);
1916                 return;
1917         }
1918
1919         printf("rl%d: watchdog timeout\n", sc->rl_unit);
1920         ifp->if_oerrors++;
1921         if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1922                 printf("rl%d: no carrier - transceiver cable problem?\n",
1923                                                                 sc->rl_unit);
1924         rl_txeoc(sc);
1925         rl_txeof(sc);
1926         rl_rxeof(sc);
1927         rl_init(sc);
1928
1929         return;
1930 }
1931
1932 /*
1933  * Stop the adapter and free any mbufs allocated to the
1934  * RX and TX lists.
1935  */
1936 static void rl_stop(sc)
1937         struct rl_softc         *sc;
1938 {
1939         register int            i;
1940         struct ifnet            *ifp;
1941
1942         ifp = &sc->arpcom.ac_if;
1943         ifp->if_timer = 0;
1944
1945         CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1946         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1947
1948         /*
1949          * Free the TX list buffers.
1950          */
1951         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1952                 if (sc->rl_cdata.rl_tx_chain[i].rl_mbuf != NULL) {
1953                         m_freem(sc->rl_cdata.rl_tx_chain[i].rl_mbuf);
1954                         sc->rl_cdata.rl_tx_chain[i].rl_mbuf = NULL;
1955                         CSR_WRITE_4(sc, RL_TXADDR0 +
1956                         sc->rl_cdata.rl_tx_chain[i].rl_desc, 0x00000000);
1957                 }
1958         }
1959
1960         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1961
1962         return;
1963 }
1964
1965 /*
1966  * Stop all chip I/O so that the kernel's probe routines don't
1967  * get confused by errant DMAs when rebooting.
1968  */
1969 static void rl_shutdown(howto, arg)
1970         int                     howto;
1971         void                    *arg;
1972 {
1973         struct rl_softc         *sc = (struct rl_softc *)arg;
1974
1975         rl_stop(sc);
1976
1977         return;
1978 }
1979
1980
1981 static struct pci_device rl_device = {
1982         "rl",
1983         rl_probe,
1984         rl_attach,
1985         &rl_count,
1986         NULL
1987 };
1988 DATA_SET(pcidevice_set, rl_device);