sys/pci/if_rl.c

   1 /*
   2  * Copyright (c) 1997, 1998
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  *      $Id: if_rl.c,v 1.22 1999/02/23 06:42:42 wpaul Exp $
  33  */
  34
  35 /*
  36  * RealTek 8129/8139 PCI NIC driver
  37  *
  38  * Supports several extremely cheap PCI 10/100 adapters based on
  39  * the RealTek chipset. Datasheets can be obtained from
  40  * www.realtek.com.tw.
  41  *
  42  * Written by Bill Paul <wpaul@ctr.columbia.edu>
  43  * Electrical Engineering Department
  44  * Columbia University, New York City
  45  */
  46
  47 /*
  48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
  49  * probably the worst PCI ethernet controller ever made, with the possible
  50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
  51  * DMA, but it has a terrible interface that nullifies any performance
  52  * gains that bus-master DMA usually offers.
  53  *
  54  * For transmission, the chip offers a series of four TX descriptor
  55  * registers. Each transmit frame must be in a contiguous buffer, aligned
  56  * on a longword (32-bit) boundary. This means we almost always have to
  57  * do mbuf copies in order to transmit a frame, except in the unlikely
  58  * case where a) the packet fits into a single mbuf, and b) the packet
  59  * is 32-bit aligned within the mbuf's data area. The presence of only
  60  * four descriptor registers means that we can never have more than four
  61  * packets queued for transmission at any one time.
  62  *
  63  * Reception is not much better. The driver has to allocate a single large
  64  * buffer area (up to 64K in size) into which the chip will DMA received
  65  * frames. Because we don't know where within this region received packets
  66  * will begin or end, we have no choice but to copy data from the buffer
  67  * area into mbufs in order to pass the packets up to the higher protocol
  68  * levels.
  69  *
  70  * It's impossible given this rotten design to really achieve decent
  71  * performance at 100Mbps, unless you happen to have a 400Mhz PII or
  72  * some equally overmuscled CPU to drive it.
  73  *
  74  * On the bright side, the 8139 does have a built-in PHY, although
  75  * rather than using an MDIO serial interface like most other NICs, the
  76  * PHY registers are directly accessible through the 8139's register
  77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
  78  * filter.
  79  *
  80  * The 8129 chip is an older version of the 8139 that uses an external PHY
  81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
  82  * the 8139 lets you directly access the on-board PHY registers. We need
  83  * to select which interface to use depending on the chip type.
  84  */
  85
  86 #include "bpfilter.h"
  87
  88 #include <sys/param.h>
  89 #include <sys/systm.h>
  90 #include <sys/sockio.h>
  91 #include <sys/mbuf.h>
  92 #include <sys/malloc.h>
  93 #include <sys/kernel.h>
  94 #include <sys/socket.h>
  95
  96 #include <net/if.h>
  97 #include <net/if_arp.h>
  98 #include <net/ethernet.h>
  99 #include <net/if_dl.h>
 100 #include <net/if_media.h>
 101
 102 #if NBPFILTER > 0
 103 #include <net/bpf.h>
 104 #endif
 105
 106 #include <vm/vm.h>              /* for vtophys */
 107 #include <vm/pmap.h>            /* for vtophys */
 108 #include <machine/clock.h>      /* for DELAY */
 109 #include <machine/bus_pio.h>
 110 #include <machine/bus_memio.h>
 111 #include <machine/bus.h>
 112
 113 #include <pci/pcireg.h>
 114 #include <pci/pcivar.h>
 115
 116 /*
 117  * Default to using PIO access for this driver. On SMP systems,
 118  * there appear to be problems with memory mapped mode: it looks like
 119  * doing too many memory mapped access back to back in rapid succession
 120  * can hang the bus. I'm inclined to blame this on crummy design/construction
 121  * on the part of RealTek. Memory mapped mode does appear to work on
 122  * uniprocessor systems though.
 123  */
 124 #define RL_USEIOSPACE
 125
 126 #include <pci/if_rlreg.h>
 127
 128 #ifndef lint
 129 static const char rcsid[] =
 130         "$Id: if_rl.c,v 1.22 1999/02/23 06:42:42 wpaul Exp $";
 131 #endif
 132
 133 /*
 134  * Various supported device vendors/types and their names.
 135  */
 136 static struct rl_type rl_devs[] = {
 137         { RT_VENDORID, RT_DEVICEID_8129,
 138                 "RealTek 8129 10/100BaseTX" },
 139         { RT_VENDORID, RT_DEVICEID_8139,
 140                 "RealTek 8139 10/100BaseTX" },
 141         { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
 142                 "Accton MPX 5030/5038 10/100BaseTX" },
 143         { DELTA_VENDORID, DELTA_DEVICEID_8139,
 144                 "Delta Electronics 8139 10/100BaseTX" },
 145         { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
 146                 "Addtron Technolgy 8139 10/100BaseTX" },
 147         { 0, 0, NULL }
 148 };
 149
 150 /*
 151  * Various supported PHY vendors/types and their names. Note that
 152  * this driver will work with pretty much any MII-compliant PHY,
 153  * so failure to positively identify the chip is not a fatal error.
 154  */
 155
 156 static struct rl_type rl_phys[] = {
 157         { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
 158         { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
 159         { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
 160         { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" },
 161         { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
 162         { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
 163         { 0, 0, "<MII-compliant physical interface>" }
 164 };
 165
 166 static unsigned long rl_count = 0;
 167 static const char *rl_probe     __P((pcici_t, pcidi_t));
 168 static void rl_attach           __P((pcici_t, int));
 169
 170 static int rl_encap             __P((struct rl_softc *, struct rl_chain *,
 171                                                 struct mbuf * ));
 172
 173 static void rl_rxeof            __P((struct rl_softc *));
 174 static void rl_txeof            __P((struct rl_softc *));
 175 static void rl_txeoc            __P((struct rl_softc *));
 176 static void rl_intr             __P((void *));
 177 static void rl_start            __P((struct ifnet *));
 178 static int rl_ioctl             __P((struct ifnet *, u_long, caddr_t));
 179 static void rl_init             __P((void *));
 180 static void rl_stop             __P((struct rl_softc *));
 181 static void rl_watchdog         __P((struct ifnet *));
 182 static void rl_shutdown         __P((int, void *));
 183 static int rl_ifmedia_upd       __P((struct ifnet *));
 184 static void rl_ifmedia_sts      __P((struct ifnet *, struct ifmediareq *));
 185
 186 static void rl_eeprom_putbyte   __P((struct rl_softc *, int));
 187 static void rl_eeprom_getword   __P((struct rl_softc *, int, u_int16_t *));
 188 static void rl_read_eeprom      __P((struct rl_softc *, caddr_t,
 189                                         int, int, int));
 190 static void rl_mii_sync         __P((struct rl_softc *));
 191 static void rl_mii_send         __P((struct rl_softc *, u_int32_t, int));
 192 static int rl_mii_readreg       __P((struct rl_softc *, struct rl_mii_frame *));
 193 static int rl_mii_writereg      __P((struct rl_softc *, struct rl_mii_frame *));
 194
 195 static u_int16_t rl_phy_readreg __P((struct rl_softc *, int));
 196 static void rl_phy_writereg     __P((struct rl_softc *, int, int));
 197
 198 static void rl_autoneg_xmit     __P((struct rl_softc *));
 199 static void rl_autoneg_mii      __P((struct rl_softc *, int, int));
 200 static void rl_setmode_mii      __P((struct rl_softc *, int));
 201 static void rl_getmode_mii      __P((struct rl_softc *));
 202 static u_int8_t rl_calchash     __P((caddr_t));
 203 static void rl_setmulti         __P((struct rl_softc *));
 204 static void rl_reset            __P((struct rl_softc *));
 205 static int rl_list_tx_init      __P((struct rl_softc *));
 206
 207 #define EE_SET(x)                                       \
 208         CSR_WRITE_1(sc, RL_EECMD,                       \
 209                 CSR_READ_1(sc, RL_EECMD) | x)
 210
 211 #define EE_CLR(x)                                       \
 212         CSR_WRITE_1(sc, RL_EECMD,                       \
 213                 CSR_READ_1(sc, RL_EECMD) & ~x)
 214
 215 /*
 216  * Send a read command and address to the EEPROM, check for ACK.
 217  */
 218 static void rl_eeprom_putbyte(sc, addr)
 219         struct rl_softc         *sc;
 220         int                     addr;
 221 {
 222         register int            d, i;
 223
 224         d = addr | RL_EECMD_READ;
 225
 226         /*
 227          * Feed in each bit and stobe the clock.
 228          */
 229         for (i = 0x400; i; i >>= 1) {
 230                 if (d & i) {
 231                         EE_SET(RL_EE_DATAIN);
 232                 } else {
 233                         EE_CLR(RL_EE_DATAIN);
 234                 }
 235                 DELAY(100);
 236                 EE_SET(RL_EE_CLK);
 237                 DELAY(150);
 238                 EE_CLR(RL_EE_CLK);
 239                 DELAY(100);
 240         }
 241
 242         return;
 243 }
 244
 245 /*
 246  * Read a word of data stored in the EEPROM at address 'addr.'
 247  */
 248 static void rl_eeprom_getword(sc, addr, dest)
 249         struct rl_softc         *sc;
 250         int                     addr;
 251         u_int16_t               *dest;
 252 {
 253         register int            i;
 254         u_int16_t               word = 0;
 255
 256         /* Enter EEPROM access mode. */
 257         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 258
 259         /*
 260          * Send address of word we want to read.
 261          */
 262         rl_eeprom_putbyte(sc, addr);
 263
 264         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 265
 266         /*
 267          * Start reading bits from EEPROM.
 268          */
 269         for (i = 0x8000; i; i >>= 1) {
 270                 EE_SET(RL_EE_CLK);
 271                 DELAY(100);
 272                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
 273                         word |= i;
 274                 EE_CLR(RL_EE_CLK);
 275                 DELAY(100);
 276         }
 277
 278         /* Turn off EEPROM access mode. */
 279         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 280
 281         *dest = word;
 282
 283         return;
 284 }
 285
 286 /*
 287  * Read a sequence of words from the EEPROM.
 288  */
 289 static void rl_read_eeprom(sc, dest, off, cnt, swap)
 290         struct rl_softc         *sc;
 291         caddr_t                 dest;
 292         int                     off;
 293         int                     cnt;
 294         int                     swap;
 295 {
 296         int                     i;
 297         u_int16_t               word = 0, *ptr;
 298
 299         for (i = 0; i < cnt; i++) {
 300                 rl_eeprom_getword(sc, off + i, &word);
 301                 ptr = (u_int16_t *)(dest + (i * 2));
 302                 if (swap)
 303                         *ptr = ntohs(word);
 304                 else
 305                         *ptr = word;
 306         }
 307
 308         return;
 309 }
 310
 311
 312 /*
 313  * MII access routines are provided for the 8129, which
 314  * doesn't have a built-in PHY. For the 8139, we fake things
 315  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
 316  * direct access PHY registers.
 317  */
 318 #define MII_SET(x)                                      \
 319         CSR_WRITE_1(sc, RL_MII,                         \
 320                 CSR_READ_1(sc, RL_MII) | x)
 321
 322 #define MII_CLR(x)                                      \
 323         CSR_WRITE_1(sc, RL_MII,                         \
 324                 CSR_READ_1(sc, RL_MII) & ~x)
 325
 326 /*
 327  * Sync the PHYs by setting data bit and strobing the clock 32 times.
 328  */
 329 static void rl_mii_sync(sc)
 330         struct rl_softc         *sc;
 331 {
 332         register int            i;
 333
 334         MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
 335
 336         for (i = 0; i < 32; i++) {
 337                 MII_SET(RL_MII_CLK);
 338                 DELAY(1);
 339                 MII_CLR(RL_MII_CLK);
 340                 DELAY(1);
 341         }
 342
 343         return;
 344 }
 345
 346 /*
 347  * Clock a series of bits through the MII.
 348  */
 349 static void rl_mii_send(sc, bits, cnt)
 350         struct rl_softc         *sc;
 351         u_int32_t               bits;
 352         int                     cnt;
 353 {
 354         int                     i;
 355
 356         MII_CLR(RL_MII_CLK);
 357
 358         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
 359                 if (bits & i) {
 360                         MII_SET(RL_MII_DATAOUT);
 361                 } else {
 362                         MII_CLR(RL_MII_DATAOUT);
 363                 }
 364                 DELAY(1);
 365                 MII_CLR(RL_MII_CLK);
 366                 DELAY(1);
 367                 MII_SET(RL_MII_CLK);
 368         }
 369 }
 370
 371 /*
 372  * Read an PHY register through the MII.
 373  */
 374 static int rl_mii_readreg(sc, frame)
 375         struct rl_softc         *sc;
 376         struct rl_mii_frame     *frame;
 377
 378 {
 379         int                     i, ack, s;
 380
 381         s = splimp();
 382
 383         /*
 384          * Set up frame for RX.
 385          */
 386         frame->mii_stdelim = RL_MII_STARTDELIM;
 387         frame->mii_opcode = RL_MII_READOP;
 388         frame->mii_turnaround = 0;
 389         frame->mii_data = 0;
 390
 391         CSR_WRITE_2(sc, RL_MII, 0);
 392
 393         /*
 394          * Turn on data xmit.
 395          */
 396         MII_SET(RL_MII_DIR);
 397
 398         rl_mii_sync(sc);
 399
 400         /*
 401          * Send command/address info.
 402          */
 403         rl_mii_send(sc, frame->mii_stdelim, 2);
 404         rl_mii_send(sc, frame->mii_opcode, 2);
 405         rl_mii_send(sc, frame->mii_phyaddr, 5);
 406         rl_mii_send(sc, frame->mii_regaddr, 5);
 407
 408         /* Idle bit */
 409         MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
 410         DELAY(1);
 411         MII_SET(RL_MII_CLK);
 412         DELAY(1);
 413
 414         /* Turn off xmit. */
 415         MII_CLR(RL_MII_DIR);
 416
 417         /* Check for ack */
 418         MII_CLR(RL_MII_CLK);
 419         DELAY(1);
 420         MII_SET(RL_MII_CLK);
 421         DELAY(1);
 422         ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
 423
 424         /*
 425          * Now try reading data bits. If the ack failed, we still
 426          * need to clock through 16 cycles to keep the PHY(s) in sync.
 427          */
 428         if (ack) {
 429                 for(i = 0; i < 16; i++) {
 430                         MII_CLR(RL_MII_CLK);
 431                         DELAY(1);
 432                         MII_SET(RL_MII_CLK);
 433                         DELAY(1);
 434                 }
 435                 goto fail;
 436         }
 437
 438         for (i = 0x8000; i; i >>= 1) {
 439                 MII_CLR(RL_MII_CLK);
 440                 DELAY(1);
 441                 if (!ack) {
 442                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
 443                                 frame->mii_data |= i;
 444                         DELAY(1);
 445                 }
 446                 MII_SET(RL_MII_CLK);
 447                 DELAY(1);
 448         }
 449
 450 fail:
 451
 452         MII_CLR(RL_MII_CLK);
 453         DELAY(1);
 454         MII_SET(RL_MII_CLK);
 455         DELAY(1);
 456
 457         splx(s);
 458
 459         if (ack)
 460                 return(1);
 461         return(0);
 462 }
 463
 464 /*
 465  * Write to a PHY register through the MII.
 466  */
 467 static int rl_mii_writereg(sc, frame)
 468         struct rl_softc         *sc;
 469         struct rl_mii_frame     *frame;
 470
 471 {
 472         int                     s;
 473
 474         s = splimp();
 475         /*
 476          * Set up frame for TX.
 477          */
 478
 479         frame->mii_stdelim = RL_MII_STARTDELIM;
 480         frame->mii_opcode = RL_MII_WRITEOP;
 481         frame->mii_turnaround = RL_MII_TURNAROUND;
 482
 483         /*
 484          * Turn on data output.
 485          */
 486         MII_SET(RL_MII_DIR);
 487
 488         rl_mii_sync(sc);
 489
 490         rl_mii_send(sc, frame->mii_stdelim, 2);
 491         rl_mii_send(sc, frame->mii_opcode, 2);
 492         rl_mii_send(sc, frame->mii_phyaddr, 5);
 493         rl_mii_send(sc, frame->mii_regaddr, 5);
 494         rl_mii_send(sc, frame->mii_turnaround, 2);
 495         rl_mii_send(sc, frame->mii_data, 16);
 496
 497         /* Idle bit. */
 498         MII_SET(RL_MII_CLK);
 499         DELAY(1);
 500         MII_CLR(RL_MII_CLK);
 501         DELAY(1);
 502
 503         /*
 504          * Turn off xmit.
 505          */
 506         MII_CLR(RL_MII_DIR);
 507
 508         splx(s);
 509
 510         return(0);
 511 }
 512
 513 static u_int16_t rl_phy_readreg(sc, reg)
 514         struct rl_softc         *sc;
 515         int                     reg;
 516 {
 517         struct rl_mii_frame     frame;
 518         u_int16_t               rval = 0;
 519         u_int16_t               rl8139_reg = 0;
 520
 521         if (sc->rl_type == RL_8139) {
 522                 switch(reg) {
 523                 case PHY_BMCR:
 524                         rl8139_reg = RL_BMCR;
 525                         break;
 526                 case PHY_BMSR:
 527                         rl8139_reg = RL_BMSR;
 528                         break;
 529                 case PHY_ANAR:
 530                         rl8139_reg = RL_ANAR;
 531                         break;
 532                 case PHY_LPAR:
 533                         rl8139_reg = RL_LPAR;
 534                         break;
 535                 default:
 536                         printf("rl%d: bad phy register\n", sc->rl_unit);
 537                         return(0);
 538                 }
 539                 rval = CSR_READ_2(sc, rl8139_reg);
 540                 return(rval);
 541         }
 542
 543         bzero((char *)&frame, sizeof(frame));
 544
 545         frame.mii_phyaddr = sc->rl_phy_addr;
 546         frame.mii_regaddr = reg;
 547         rl_mii_readreg(sc, &frame);
 548
 549         return(frame.mii_data);
 550 }
 551
 552 static void rl_phy_writereg(sc, reg, data)
 553         struct rl_softc         *sc;
 554         int                     reg;
 555         int                     data;
 556 {
 557         struct rl_mii_frame     frame;
 558         u_int16_t               rl8139_reg = 0;
 559
 560         if (sc->rl_type == RL_8139) {
 561                 switch(reg) {
 562                 case PHY_BMCR:
 563                         rl8139_reg = RL_BMCR;
 564                         break;
 565                 case PHY_BMSR:
 566                         rl8139_reg = RL_BMSR;
 567                         break;
 568                 case PHY_ANAR:
 569                         rl8139_reg = RL_ANAR;
 570                         break;
 571                 case PHY_LPAR:
 572                         rl8139_reg = RL_LPAR;
 573                         break;
 574                 default:
 575                         printf("rl%d: bad phy register\n", sc->rl_unit);
 576                         return;
 577                 }
 578                 CSR_WRITE_2(sc, rl8139_reg, data);
 579                 return;
 580         }
 581
 582         bzero((char *)&frame, sizeof(frame));
 583
 584         frame.mii_phyaddr = sc->rl_phy_addr;
 585         frame.mii_regaddr = reg;
 586         frame.mii_data = data;
 587
 588         rl_mii_writereg(sc, &frame);
 589
 590         return;
 591 }
 592
 593 /*
 594  * Calculate CRC of a multicast group address, return the upper 6 bits.
 595  */
 596 static u_int8_t rl_calchash(addr)
 597         caddr_t                 addr;
 598 {
 599         u_int32_t               crc, carry;
 600         int                     i, j;
 601         u_int8_t                c;
 602
 603         /* Compute CRC for the address value. */
 604         crc = 0xFFFFFFFF; /* initial value */
 605
 606         for (i = 0; i < 6; i++) {
 607                 c = *(addr + i);
 608                 for (j = 0; j < 8; j++) {
 609                         carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
 610                         crc <<= 1;
 611                         c >>= 1;
 612                         if (carry)
 613                                 crc = (crc ^ 0x04c11db6) | carry;
 614                 }
 615         }
 616
 617         /* return the filter bit position */
 618         return(crc >> 26);
 619 }
 620
 621 /*
 622  * Program the 64-bit multicast hash filter.
 623  */
 624 static void rl_setmulti(sc)
 625         struct rl_softc         *sc;
 626 {
 627         struct ifnet            *ifp;
 628         int                     h = 0;
 629         u_int32_t               hashes[2] = { 0, 0 };
 630         struct ifmultiaddr      *ifma;
 631         u_int32_t               rxfilt;
 632         int                     mcnt = 0;
 633
 634         ifp = &sc->arpcom.ac_if;
 635
 636         rxfilt = CSR_READ_4(sc, RL_RXCFG);
 637
 638         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 639                 rxfilt |= RL_RXCFG_RX_MULTI;
 640                 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 641                 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
 642                 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
 643                 return;
 644         }
 645
 646         /* first, zot all the existing hash bits */
 647         CSR_WRITE_4(sc, RL_MAR0, 0);
 648         CSR_WRITE_4(sc, RL_MAR4, 0);
 649
 650         /* now program new ones */
 651         for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
 652                                 ifma = ifma->ifma_link.le_next) {
 653                 if (ifma->ifma_addr->sa_family != AF_LINK)
 654                         continue;
 655                 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 656                 if (h < 32)
 657                         hashes[0] |= (1 << h);
 658                 else
 659                         hashes[1] |= (1 << (h - 32));
 660                 mcnt++;
 661         }
 662
 663         if (mcnt)
 664                 rxfilt |= RL_RXCFG_RX_MULTI;
 665         else
 666                 rxfilt &= ~RL_RXCFG_RX_MULTI;
 667
 668         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 669         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
 670         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
 671
 672         return;
 673 }
 674
 675 /*
 676  * Initiate an autonegotiation session.
 677  */
 678 static void rl_autoneg_xmit(sc)
 679         struct rl_softc         *sc;
 680 {
 681         u_int16_t               phy_sts;
 682
 683         rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
 684         DELAY(500);
 685         while(rl_phy_readreg(sc, PHY_BMCR)
 686                         & PHY_BMCR_RESET);
 687
 688         phy_sts = rl_phy_readreg(sc, PHY_BMCR);
 689         phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
 690         rl_phy_writereg(sc, PHY_BMCR, phy_sts);
 691
 692         return;
 693 }
 694
 695 /*
 696  * Invoke autonegotiation on a PHY. Also used with the 8139 internal
 697  * transceiver.
 698  */
 699 static void rl_autoneg_mii(sc, flag, verbose)
 700         struct rl_softc         *sc;
 701         int                     flag;
 702         int                     verbose;
 703 {
 704         u_int16_t               phy_sts = 0, media, advert, ability;
 705         struct ifnet            *ifp;
 706         struct ifmedia          *ifm;
 707
 708         ifm = &sc->ifmedia;
 709         ifp = &sc->arpcom.ac_if;
 710
 711         /*
 712          * The 100baseT4 PHY sometimes has the 'autoneg supported'
 713          * bit cleared in the status register, but has the 'autoneg enabled'
 714          * bit set in the control register. This is a contradiction, and
 715          * I'm not sure how to handle it. If you want to force an attempt
 716          * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
 717          * and see what happens.
 718          */
 719 #ifndef FORCE_AUTONEG_TFOUR
 720         /*
 721          * First, see if autoneg is supported. If not, there's
 722          * no point in continuing.
 723          */
 724         phy_sts = rl_phy_readreg(sc, PHY_BMSR);
 725         if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
 726                 if (verbose)
 727                         printf("rl%d: autonegotiation not supported\n",
 728                                                         sc->rl_unit);
 729                 return;
 730         }
 731 #endif
 732
 733         switch (flag) {
 734         case RL_FLAG_FORCEDELAY:
 735                 /*
 736                  * XXX Never use this option anywhere but in the probe
 737                  * routine: making the kernel stop dead in its tracks
 738                  * for three whole seconds after we've gone multi-user
 739                  * is really bad manners.
 740                  */
 741                 rl_autoneg_xmit(sc);
 742                 DELAY(5000000);
 743                 break;
 744         case RL_FLAG_SCHEDDELAY:
 745                 /*
 746                  * Wait for the transmitter to go idle before starting
 747                  * an autoneg session, otherwise rl_start() may clobber
 748                  * our timeout, and we don't want to allow transmission
 749                  * during an autoneg session since that can screw it up.
 750                  */
 751                 if (sc->rl_cdata.rl_tx_cnt) {
 752                         sc->rl_want_auto = 1;
 753                         return;
 754                 }
 755                 rl_autoneg_xmit(sc);
 756                 ifp->if_timer = 5;
 757                 sc->rl_autoneg = 1;
 758                 sc->rl_want_auto = 0;
 759                 return;
 760                 break;
 761         case RL_FLAG_DELAYTIMEO:
 762                 ifp->if_timer = 0;
 763                 sc->rl_autoneg = 0;
 764                 break;
 765         default:
 766                 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag);
 767                 return;
 768         }
 769
 770         if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
 771                 if (verbose)
 772                         printf("rl%d: autoneg complete, ", sc->rl_unit);
 773                 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
 774         } else {
 775                 if (verbose)
 776                         printf("rl%d: autoneg not complete, ", sc->rl_unit);
 777         }
 778
 779         media = rl_phy_readreg(sc, PHY_BMCR);
 780
 781         /* Link is good. Report modes and set duplex mode. */
 782         if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
 783                 if (verbose)
 784                         printf("link status good ");
 785                 advert = rl_phy_readreg(sc, PHY_ANAR);
 786                 ability = rl_phy_readreg(sc, PHY_LPAR);
 787
 788                 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
 789                         ifm->ifm_media = IFM_ETHER|IFM_100_T4;
 790                         media |= PHY_BMCR_SPEEDSEL;
 791                         media &= ~PHY_BMCR_DUPLEX;
 792                         printf("(100baseT4)\n");
 793                 } else if (advert & PHY_ANAR_100BTXFULL &&
 794                         ability & PHY_ANAR_100BTXFULL) {
 795                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
 796                         media |= PHY_BMCR_SPEEDSEL;
 797                         media |= PHY_BMCR_DUPLEX;
 798                         printf("(full-duplex, 100Mbps)\n");
 799                 } else if (advert & PHY_ANAR_100BTXHALF &&
 800                         ability & PHY_ANAR_100BTXHALF) {
 801                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
 802                         media |= PHY_BMCR_SPEEDSEL;
 803                         media &= ~PHY_BMCR_DUPLEX;
 804                         printf("(half-duplex, 100Mbps)\n");
 805                 } else if (advert & PHY_ANAR_10BTFULL &&
 806                         ability & PHY_ANAR_10BTFULL) {
 807                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
 808                         media &= ~PHY_BMCR_SPEEDSEL;
 809                         media |= PHY_BMCR_DUPLEX;
 810                         printf("(full-duplex, 10Mbps)\n");
 811                 } else {
 812                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
 813                         media &= ~PHY_BMCR_SPEEDSEL;
 814                         media &= ~PHY_BMCR_DUPLEX;
 815                         printf("(half-duplex, 10Mbps)\n");
 816                 }
 817
 818                 /* Set ASIC's duplex mode to match the PHY. */
 819                 rl_phy_writereg(sc, PHY_BMCR, media);
 820         } else {
 821                 if (verbose)
 822                         printf("no carrier\n");
 823         }
 824
 825         rl_init(sc);
 826
 827         if (sc->rl_tx_pend) {
 828                 sc->rl_autoneg = 0;
 829                 sc->rl_tx_pend = 0;
 830                 rl_start(ifp);
 831         }
 832
 833         return;
 834 }
 835
 836 static void rl_getmode_mii(sc)
 837         struct rl_softc         *sc;
 838 {
 839         u_int16_t               bmsr;
 840         struct ifnet            *ifp;
 841
 842         ifp = &sc->arpcom.ac_if;
 843
 844         bmsr = rl_phy_readreg(sc, PHY_BMSR);
 845         if (bootverbose)
 846                 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr);
 847
 848         /* fallback */
 849         sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
 850
 851         if (bmsr & PHY_BMSR_10BTHALF) {
 852                 if (bootverbose)
 853                         printf("rl%d: 10Mbps half-duplex mode supported\n",
 854                                                                 sc->rl_unit);
 855                 ifmedia_add(&sc->ifmedia,
 856                         IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
 857                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 858         }
 859
 860         if (bmsr & PHY_BMSR_10BTFULL) {
 861                 if (bootverbose)
 862                         printf("rl%d: 10Mbps full-duplex mode supported\n",
 863                                                                 sc->rl_unit);
 864                 ifmedia_add(&sc->ifmedia,
 865                         IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
 866                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
 867         }
 868
 869         if (bmsr & PHY_BMSR_100BTXHALF) {
 870                 if (bootverbose)
 871                         printf("rl%d: 100Mbps half-duplex mode supported\n",
 872                                                                 sc->rl_unit);
 873                 ifp->if_baudrate = 100000000;
 874                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
 875                 ifmedia_add(&sc->ifmedia,
 876                         IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
 877                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
 878         }
 879
 880         if (bmsr & PHY_BMSR_100BTXFULL) {
 881                 if (bootverbose)
 882                         printf("rl%d: 100Mbps full-duplex mode supported\n",
 883                                                                 sc->rl_unit);
 884                 ifp->if_baudrate = 100000000;
 885                 ifmedia_add(&sc->ifmedia,
 886                         IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
 887                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
 888         }
 889
 890         /* Some also support 100BaseT4. */
 891         if (bmsr & PHY_BMSR_100BT4) {
 892                 if (bootverbose)
 893                         printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit);
 894                 ifp->if_baudrate = 100000000;
 895                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
 896                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
 897 #ifdef FORCE_AUTONEG_TFOUR
 898                 if (bootverbose)
 899                         printf("rl%d: forcing on autoneg support for BT4\n",
 900                                                          sc->rl_unit);
 901                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
 902                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
 903 #endif
 904         }
 905
 906         if (bmsr & PHY_BMSR_CANAUTONEG) {
 907                 if (bootverbose)
 908                         printf("rl%d: autoneg supported\n", sc->rl_unit);
 909                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 910                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
 911         }
 912
 913         return;
 914 }
 915
 916 /*
 917  * Set speed and duplex mode.
 918  */
 919 static void rl_setmode_mii(sc, media)
 920         struct rl_softc         *sc;
 921         int                     media;
 922 {
 923         u_int16_t               bmcr;
 924
 925         printf("rl%d: selecting MII, ", sc->rl_unit);
 926
 927         bmcr = rl_phy_readreg(sc, PHY_BMCR);
 928
 929         bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
 930                         PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
 931
 932         if (IFM_SUBTYPE(media) == IFM_100_T4) {
 933                 printf("100Mbps/T4, half-duplex\n");
 934                 bmcr |= PHY_BMCR_SPEEDSEL;
 935                 bmcr &= ~PHY_BMCR_DUPLEX;
 936         }
 937
 938         if (IFM_SUBTYPE(media) == IFM_100_TX) {
 939                 printf("100Mbps, ");
 940                 bmcr |= PHY_BMCR_SPEEDSEL;
 941         }
 942
 943         if (IFM_SUBTYPE(media) == IFM_10_T) {
 944                 printf("10Mbps, ");
 945                 bmcr &= ~PHY_BMCR_SPEEDSEL;
 946         }
 947
 948         if ((media & IFM_GMASK) == IFM_FDX) {
 949                 printf("full duplex\n");
 950                 bmcr |= PHY_BMCR_DUPLEX;
 951         } else {
 952                 printf("half duplex\n");
 953                 bmcr &= ~PHY_BMCR_DUPLEX;
 954         }
 955
 956         rl_phy_writereg(sc, PHY_BMCR, bmcr);
 957
 958         return;
 959 }
 960
 961 static void rl_reset(sc)
 962         struct rl_softc         *sc;
 963 {
 964         register int            i;
 965
 966         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
 967
 968         for (i = 0; i < RL_TIMEOUT; i++) {
 969                 DELAY(10);
 970                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
 971                         break;
 972         }
 973         if (i == RL_TIMEOUT)
 974                 printf("rl%d: reset never completed!\n", sc->rl_unit);
 975
 976         return;
 977 }
 978
 979 /*
 980  * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
 981  * IDs against our list and return a device name if we find a match.
 982  */
 983 static const char *
 984 rl_probe(config_id, device_id)
 985         pcici_t                 config_id;
 986         pcidi_t                 device_id;
 987 {
 988         struct rl_type          *t;
 989
 990         t = rl_devs;
 991
 992         while(t->rl_name != NULL) {
 993                 if ((device_id & 0xFFFF) == t->rl_vid &&
 994                     ((device_id >> 16) & 0xFFFF) == t->rl_did) {
 995                         return(t->rl_name);
 996                 }
 997                 t++;
 998         }
 999
1000         return(NULL);
1001 }
1002
1003 /*
1004  * Attach the interface. Allocate softc structures, do ifmedia
1005  * setup and ethernet/BPF attach.
1006  */
1007 static void
1008 rl_attach(config_id, unit)
1009         pcici_t                 config_id;
1010         int                     unit;
1011 {
1012         int                     s, i;
1013 #ifndef RL_USEIOSPACE
1014         vm_offset_t             pbase, vbase;
1015 #endif
1016         u_char                  eaddr[ETHER_ADDR_LEN];
1017         u_int32_t               command;
1018         struct rl_softc         *sc;
1019         struct ifnet            *ifp;
1020         int                     media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1021         struct rl_type          *p;
1022         u_int16_t               phy_vid, phy_did, phy_sts;
1023         u_int16_t               rl_did = 0;
1024
1025         s = splimp();
1026
1027         sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT);
1028         if (sc == NULL) {
1029                 printf("rl%d: no memory for softc struct!\n", unit);
1030                 return;
1031         }
1032         bzero(sc, sizeof(struct rl_softc));
1033
1034         /*
1035          * Handle power management nonsense.
1036          */
1037
1038         command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF;
1039         if (command == 0x01) {
1040
1041                 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL);
1042                 if (command & RL_PSTATE_MASK) {
1043                         u_int32_t               iobase, membase, irq;
1044
1045                         /* Save important PCI config data. */
1046                         iobase = pci_conf_read(config_id, RL_PCI_LOIO);
1047                         membase = pci_conf_read(config_id, RL_PCI_LOMEM);
1048                         irq = pci_conf_read(config_id, RL_PCI_INTLINE);
1049
1050                         /* Reset the power state. */
1051                         printf("rl%d: chip is is in D%d power mode "
1052                         "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
1053                         command &= 0xFFFFFFFC;
1054                         pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command);
1055
1056                         /* Restore PCI config data. */
1057                         pci_conf_write(config_id, RL_PCI_LOIO, iobase);
1058                         pci_conf_write(config_id, RL_PCI_LOMEM, membase);
1059                         pci_conf_write(config_id, RL_PCI_INTLINE, irq);
1060                 }
1061         }
1062
1063         /*
1064          * Map control/status registers.
1065          */
1066         command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1067         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1068         pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1069         command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1070
1071 #ifdef RL_USEIOSPACE
1072         if (!(command & PCIM_CMD_PORTEN)) {
1073                 printf("rl%d: failed to enable I/O ports!\n", unit);
1074                 free(sc, M_DEVBUF);
1075                 goto fail;
1076         }
1077
1078         if (!pci_map_port(config_id, RL_PCI_LOIO,
1079                                 (u_int16_t *)&(sc->rl_bhandle))) {
1080                 printf ("rl%d: couldn't map ports\n", unit);
1081                 goto fail;
1082         }
1083         sc->rl_btag = I386_BUS_SPACE_IO;
1084 #else
1085         if (!(command & PCIM_CMD_MEMEN)) {
1086                 printf("rl%d: failed to enable memory mapping!\n", unit);
1087                 goto fail;
1088         }
1089
1090         if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) {
1091                 printf ("rl%d: couldn't map memory\n", unit);
1092                 goto fail;
1093         }
1094         sc->rl_btag = I386_BUS_SPACE_MEM;
1095         sc->rl_bhandle = vbase;
1096 #endif
1097
1098         /* Allocate interrupt */
1099         if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) {
1100                 printf("rl%d: couldn't map interrupt\n", unit);
1101                 goto fail;
1102         }
1103
1104         /* Reset the adapter. */
1105         rl_reset(sc);
1106
1107         /*
1108          * Get station address from the EEPROM.
1109          */
1110         rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
1111
1112         /*
1113          * A RealTek chip was detected. Inform the world.
1114          */
1115         printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1116
1117         sc->rl_unit = unit;
1118         bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1119
1120         /*
1121          * Now read the exact device type from the EEPROM to find
1122          * out if it's an 8129 or 8139.
1123          */
1124         rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1125
1126         if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
1127                 rl_did == DELTA_DEVICEID_8139)
1128                 sc->rl_type = RL_8139;
1129         else if (rl_did == RT_DEVICEID_8129)
1130                 sc->rl_type = RL_8129;
1131         else {
1132                 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1133                 free(sc, M_DEVBUF);
1134                 goto fail;
1135         }
1136
1137         sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 16, M_DEVBUF,
1138                 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
1139
1140         if (sc->rl_cdata.rl_rx_buf == NULL) {
1141                 free(sc, M_DEVBUF);
1142                 printf("rl%d: no memory for list buffers!\n", unit);
1143                 goto fail;
1144         }
1145
1146         ifp = &sc->arpcom.ac_if;
1147         ifp->if_softc = sc;
1148         ifp->if_unit = unit;
1149         ifp->if_name = "rl";
1150         ifp->if_mtu = ETHERMTU;
1151         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1152         ifp->if_ioctl = rl_ioctl;
1153         ifp->if_output = ether_output;
1154         ifp->if_start = rl_start;
1155         ifp->if_watchdog = rl_watchdog;
1156         ifp->if_init = rl_init;
1157         ifp->if_baudrate = 10000000;
1158         ifp->if_snd.ifq_maxlen = RL_TX_LIST_CNT - 1;
1159
1160         if (sc->rl_type == RL_8129) {
1161                 if (bootverbose)
1162                         printf("rl%d: probing for a PHY\n", sc->rl_unit);
1163                 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) {
1164                         if (bootverbose)
1165                                 printf("rl%d: checking address: %d\n",
1166                                                         sc->rl_unit, i);
1167                         sc->rl_phy_addr = i;
1168                         rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1169                         DELAY(500);
1170                         while(rl_phy_readreg(sc, PHY_BMCR)
1171                                         & PHY_BMCR_RESET);
1172                         if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR)))
1173                                 break;
1174                 }
1175                 if (phy_sts) {
1176                         phy_vid = rl_phy_readreg(sc, PHY_VENID);
1177                         phy_did = rl_phy_readreg(sc, PHY_DEVID);
1178                         if (bootverbose)
1179                                 printf("rl%d: found PHY at address %d, ",
1180                                                 sc->rl_unit, sc->rl_phy_addr);
1181                         if (bootverbose)
1182                                 printf("vendor id: %x device id: %x\n",
1183                                         phy_vid, phy_did);
1184                         p = rl_phys;
1185                         while(p->rl_vid) {
1186                                 if (phy_vid == p->rl_vid &&
1187                                         (phy_did | 0x000F) == p->rl_did) {
1188                                         sc->rl_pinfo = p;
1189                                         break;
1190                                 }
1191                                 p++;
1192                         }
1193                         if (sc->rl_pinfo == NULL)
1194                                 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN];
1195                         if (bootverbose)
1196                                 printf("rl%d: PHY type: %s\n",
1197                                         sc->rl_unit, sc->rl_pinfo->rl_name);
1198                 } else {
1199                         printf("rl%d: MII without any phy!\n", sc->rl_unit);
1200                 }
1201         }
1202
1203         /*
1204          * Do ifmedia setup.
1205          */
1206         ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts);
1207
1208         rl_getmode_mii(sc);
1209
1210         /* Choose a default media. */
1211         media = IFM_ETHER|IFM_AUTO;
1212         ifmedia_set(&sc->ifmedia, media);
1213
1214         rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1);
1215
1216         /*
1217          * Call MI attach routines.
1218          */
1219         if_attach(ifp);
1220         ether_ifattach(ifp);
1221
1222 #if NBPFILTER > 0
1223         bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1224 #endif
1225         at_shutdown(rl_shutdown, sc, SHUTDOWN_POST_SYNC);
1226
1227 fail:
1228         splx(s);
1229         return;
1230 }
1231
1232 /*
1233  * Initialize the transmit descriptors.
1234  */
1235 static int rl_list_tx_init(sc)
1236         struct rl_softc         *sc;
1237 {
1238         struct rl_chain_data    *cd;
1239         int                     i;
1240
1241         cd = &sc->rl_cdata;
1242         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1243                 cd->rl_tx_chain[i].rl_desc = i * 4;
1244                 CSR_WRITE_4(sc, RL_TXADDR0 + cd->rl_tx_chain[i].rl_desc, 0);
1245                 CSR_WRITE_4(sc, RL_TXSTAT0 + cd->rl_tx_chain[i].rl_desc, 0);
1246                 if (i == (RL_TX_LIST_CNT - 1))
1247                         cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[0];
1248                 else
1249                         cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[i + 1];
1250         }
1251
1252         sc->rl_cdata.rl_tx_cnt = 0;
1253         cd->rl_tx_cur = cd->rl_tx_free = &cd->rl_tx_chain[0];
1254
1255         return(0);
1256 }
1257
1258 /*
1259  * A frame has been uploaded: pass the resulting mbuf chain up to
1260  * the higher level protocols.
1261  *
1262  * You know there's something wrong with a PCI bus-master chip design
1263  * when you have to use m_devget().
1264  *
1265  * The receive operation is badly documented in the datasheet, so I'll
1266  * attempt to document it here. The driver provides a buffer area and
1267  * places its base address in the RX buffer start address register.
1268  * The chip then begins copying frames into the RX buffer. Each frame
1269  * is preceeded by a 32-bit RX status word which specifies the length
1270  * of the frame and certain other status bits. Each frame (starting with
1271  * the status word) is also 32-bit aligned. The frame length is in the
1272  * first 16 bits of the status word; the lower 15 bits correspond with
1273  * the 'rx status register' mentioned in the datasheet.
1274  */
1275 static void rl_rxeof(sc)
1276         struct rl_softc         *sc;
1277 {
1278         struct ether_header     *eh;
1279         struct mbuf             *m;
1280         struct ifnet            *ifp;
1281         int                     total_len = 0;
1282         u_int32_t               rxstat;
1283         caddr_t                 rxbufpos;
1284         int                     wrap = 0;
1285         u_int16_t               cur_rx;
1286         u_int16_t               limit;
1287         u_int16_t               rx_bytes = 0, max_bytes;
1288
1289         ifp = &sc->arpcom.ac_if;
1290
1291         cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1292
1293         /* Do not try to read past this point. */
1294         limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1295
1296         if (limit < cur_rx)
1297                 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1298         else
1299                 max_bytes = limit - cur_rx;
1300
1301         while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1302                 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1303                 rxstat = *(u_int32_t *)rxbufpos;
1304
1305                 /*
1306                  * Here's a totally undocumented fact for you. When the
1307                  * RealTek chip is in the process of copying a packet into
1308                  * RAM for you, the length will be 0xfff0. If you spot a
1309                  * packet header with this value, you need to stop. The
1310                  * datasheet makes absolutely no mention of this and
1311                  * RealTek should be shot for this.
1312                  */
1313                 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1314                         break;
1315
1316                 if (!(rxstat & RL_RXSTAT_RXOK)) {
1317                         ifp->if_ierrors++;
1318                         if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT|
1319                                         RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR|
1320                                         RL_RXSTAT_ALIGNERR)) {
1321                                 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB);
1322                                 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB|
1323                                                         RL_CMD_RX_ENB);
1324                                 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1325                                 CSR_WRITE_4(sc, RL_RXADDR,
1326                                         vtophys(sc->rl_cdata.rl_rx_buf));
1327                                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1328                                 cur_rx = 0;
1329                         }
1330                         break;
1331                 }
1332
1333                 /* No errors; receive the packet. */
1334                 total_len = rxstat >> 16;
1335                 rx_bytes += total_len + 4;
1336
1337                 /*
1338                  * XXX The RealTek chip includes the CRC with every
1339                  * received frame, and there's no way to turn this
1340                  * behavior off (at least, I can't find anything in
1341                  * the manual that explains how to do it) so we have
1342                  * to trim off the CRC manually.
1343                  */
1344                 total_len -= ETHER_CRC_LEN;
1345
1346                 /*
1347                  * Avoid trying to read more bytes than we know
1348                  * the chip has prepared for us.
1349                  */
1350                 if (rx_bytes > max_bytes)
1351                         break;
1352
1353                 rxbufpos = sc->rl_cdata.rl_rx_buf +
1354                         ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1355
1356                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1357                         rxbufpos = sc->rl_cdata.rl_rx_buf;
1358
1359                 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1360
1361                 if (total_len > wrap) {
1362                         m = m_devget(rxbufpos, wrap, 0, ifp, NULL);
1363                         if (m == NULL) {
1364                                 ifp->if_ierrors++;
1365                                 printf("rl%d: out of mbufs, tried to "
1366                                         "copy %d bytes\n", sc->rl_unit, wrap);
1367                         }
1368                         else
1369                                 m_copyback(m, wrap, total_len - wrap,
1370                                         sc->rl_cdata.rl_rx_buf);
1371                         cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1372                 } else {
1373                         m = m_devget(rxbufpos, total_len, 0, ifp, NULL);
1374                         if (m == NULL) {
1375                                 ifp->if_ierrors++;
1376                                 printf("rl%d: out of mbufs, tried to "
1377                                 "copy %d bytes\n", sc->rl_unit, total_len);
1378                         }
1379                         cur_rx += total_len + 4 + ETHER_CRC_LEN;
1380                 }
1381
1382                 /*
1383                  * Round up to 32-bit boundary.
1384                  */
1385                 cur_rx = (cur_rx + 3) & ~3;
1386                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1387
1388                 if (m == NULL)
1389                         continue;
1390
1391                 eh = mtod(m, struct ether_header *);
1392                 ifp->if_ipackets++;
1393
1394 #if NBPFILTER > 0
1395                 /*
1396                  * Handle BPF listeners. Let the BPF user see the packet, but
1397                  * don't pass it up to the ether_input() layer unless it's
1398                  * a broadcast packet, multicast packet, matches our ethernet
1399                  * address or the interface is in promiscuous mode.
1400                  */
1401                 if (ifp->if_bpf) {
1402                         bpf_mtap(ifp, m);
1403                         if (ifp->if_flags & IFF_PROMISC &&
1404                                 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1405                                                 ETHER_ADDR_LEN) &&
1406                                         (eh->ether_dhost[0] & 1) == 0)) {
1407                                 m_freem(m);
1408                                 continue;
1409                         }
1410                 }
1411 #endif
1412                 /* Remove header from mbuf and pass it on. */
1413                 m_adj(m, sizeof(struct ether_header));
1414                 ether_input(ifp, eh, m);
1415         }
1416
1417         return;
1418 }
1419
1420 /*
1421  * A frame was downloaded to the chip. It's safe for us to clean up
1422  * the list buffers.
1423  */
1424 static void rl_txeof(sc)
1425         struct rl_softc         *sc;
1426 {
1427         struct rl_chain         *cur_tx;
1428         struct ifnet            *ifp;
1429         u_int32_t               txstat;
1430
1431         ifp = &sc->arpcom.ac_if;
1432
1433         /* Clear the timeout timer. */
1434         ifp->if_timer = 0;
1435
1436         /*
1437          * Go through our tx list and free mbufs for those
1438          * frames that have been uploaded.
1439          */
1440         if (sc->rl_cdata.rl_tx_free == NULL)
1441                 return;
1442
1443         while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) {
1444                 cur_tx = sc->rl_cdata.rl_tx_free;
1445                 txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc);
1446
1447                 if (!(txstat & RL_TXSTAT_TX_OK))
1448                         break;
1449
1450                 if (txstat & RL_TXSTAT_COLLCNT)
1451                         ifp->if_collisions +=
1452                                         (txstat & RL_TXSTAT_COLLCNT) >> 24;
1453
1454                 sc->rl_cdata.rl_tx_free = cur_tx->rl_next;
1455
1456                 sc->rl_cdata.rl_tx_cnt--;
1457                 m_freem(cur_tx->rl_mbuf);
1458                 cur_tx->rl_mbuf = NULL;
1459                 ifp->if_opackets++;
1460         }
1461
1462         if (!sc->rl_cdata.rl_tx_cnt) {
1463                 ifp->if_flags &= ~IFF_OACTIVE;
1464                 if (sc->rl_want_auto)
1465                         rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1466         } else {
1467                 if (ifp->if_snd.ifq_head != NULL)
1468                         rl_start(ifp);
1469         }
1470
1471         return;
1472 }
1473
1474 /*
1475  * TX error handler.
1476  */
1477 static void rl_txeoc(sc)
1478         struct rl_softc         *sc;
1479 {
1480         u_int32_t               txstat;
1481         struct rl_chain         *cur_tx;
1482         struct ifnet            *ifp;
1483
1484         ifp = &sc->arpcom.ac_if;
1485
1486         if (sc->rl_cdata.rl_tx_free == NULL)
1487                 return;
1488
1489         while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) {
1490                 cur_tx = sc->rl_cdata.rl_tx_free;
1491                 txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc);
1492
1493                 if (!(txstat & RL_TXSTAT_OWN))
1494                         break;
1495
1496                 if (!(txstat & RL_TXSTAT_TX_OK)) {
1497                         ifp->if_oerrors++;
1498                         if (txstat & RL_TXSTAT_COLLCNT)
1499                                 ifp->if_collisions +=
1500                                         (txstat & RL_TXSTAT_COLLCNT) >> 24;
1501                         CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc,
1502                                 vtophys(mtod(cur_tx->rl_mbuf, caddr_t)));
1503                         CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc,
1504                                 RL_TX_EARLYTHRESH |
1505                                         cur_tx->rl_mbuf->m_pkthdr.len);
1506                         break;
1507                 } else {
1508                         if (txstat & RL_TXSTAT_COLLCNT)
1509                                 ifp->if_collisions +=
1510                                         (txstat & RL_TXSTAT_COLLCNT) >> 24;
1511                         sc->rl_cdata.rl_tx_free = cur_tx->rl_next;
1512
1513                         sc->rl_cdata.rl_tx_cnt--;
1514                         m_freem(cur_tx->rl_mbuf);
1515                         cur_tx->rl_mbuf = NULL;
1516                         ifp->if_opackets++;
1517                 }
1518         }
1519
1520         return;
1521 }
1522
1523 static void rl_intr(arg)
1524         void                    *arg;
1525 {
1526         struct rl_softc         *sc;
1527         struct ifnet            *ifp;
1528         u_int16_t               status;
1529
1530         sc = arg;
1531         ifp = &sc->arpcom.ac_if;
1532
1533         /* Disable interrupts. */
1534         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1535
1536         for (;;) {
1537
1538                 status = CSR_READ_2(sc, RL_ISR);
1539                 if (status)
1540                         CSR_WRITE_2(sc, RL_ISR, status);
1541
1542                 if ((status & RL_INTRS) == 0)
1543                         break;
1544
1545                 if (status & RL_ISR_RX_OK)
1546                         rl_rxeof(sc);
1547
1548                 if (status & RL_ISR_RX_ERR)
1549                         rl_rxeof(sc);
1550
1551                 if (status & RL_ISR_TX_OK)
1552                         rl_txeof(sc);
1553
1554                 if (status & RL_ISR_TX_ERR)
1555                         rl_txeoc(sc);
1556
1557                 if (status & RL_ISR_SYSTEM_ERR) {
1558                         rl_reset(sc);
1559                         rl_init(sc);
1560                 }
1561
1562         }
1563
1564         /* Re-enable interrupts. */
1565         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1566
1567         if (ifp->if_snd.ifq_head != NULL) {
1568                 rl_start(ifp);
1569         }
1570
1571         return;
1572 }
1573
1574 /*
1575  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1576  * pointers to the fragment pointers.
1577  */
1578 static int rl_encap(sc, c, m_head)
1579         struct rl_softc         *sc;
1580         struct rl_chain         *c;
1581         struct mbuf             *m_head;
1582 {
1583         struct mbuf             *m;
1584         struct mbuf             *m_new = NULL;
1585
1586         /*
1587          * There are two possible encapsulation mechanisms
1588          * that we can use: an efficient one, and a very lossy
1589          * one. The efficient one only happens very rarely,
1590          * whereas the lossy one can and most likely will happen
1591          * all the time.
1592          * The efficient case happens if:
1593          * - the packet fits in a single mbuf
1594          * - the packet is 32-bit aligned within the mbuf data area
1595          * In this case, we can DMA from the mbuf directly.
1596          * The lossy case covers everything else. Bah.
1597          */
1598
1599         m = m_head;
1600
1601         MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1602         if (m_new == NULL) {
1603                 printf("rl%d: no memory for tx list", sc->rl_unit);
1604                 return(1);
1605         }
1606         if (m_head->m_pkthdr.len > MHLEN) {
1607                 MCLGET(m_new, M_DONTWAIT);
1608                 if (!(m_new->m_flags & M_EXT)) {
1609                         m_freem(m_new);
1610                         printf("rl%d: no memory for tx list",
1611                                         sc->rl_unit);
1612                         return(1);
1613                 }
1614         }
1615         m_copydata(m_head, 0, m_head->m_pkthdr.len,
1616                                 mtod(m_new, caddr_t));
1617         m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1618         m_freem(m_head);
1619         m_head = m_new;
1620
1621         /* Pad frames to at least 60 bytes. */
1622         if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1623                 m_head->m_pkthdr.len +=
1624                         (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1625                 m_head->m_len = m_head->m_pkthdr.len;
1626         }
1627
1628         c->rl_mbuf = m_head;
1629
1630         return(0);
1631 }
1632
1633 /*
1634  * Main transmit routine.
1635  */
1636
1637 static void rl_start(ifp)
1638         struct ifnet            *ifp;
1639 {
1640         struct rl_softc         *sc;
1641         struct mbuf             *m_head = NULL;
1642         struct rl_chain         *cur_tx = NULL;
1643
1644         sc = ifp->if_softc;
1645
1646         if (sc->rl_autoneg) {
1647                 sc->rl_tx_pend = 1;
1648                 return;
1649         }
1650
1651         /*
1652          * Check for an available queue slot. If there are none,
1653          * punt.
1654          */
1655         if (sc->rl_cdata.rl_tx_cur->rl_mbuf != NULL) {
1656                 ifp->if_flags |= IFF_OACTIVE;
1657                 return;
1658         }
1659
1660         while(sc->rl_cdata.rl_tx_cur->rl_mbuf == NULL) {
1661                 IF_DEQUEUE(&ifp->if_snd, m_head);
1662                 if (m_head == NULL)
1663                         break;
1664
1665
1666                 /* Pick a descriptor off the free list. */
1667                 cur_tx = sc->rl_cdata.rl_tx_cur;
1668                 sc->rl_cdata.rl_tx_cur = cur_tx->rl_next;
1669                 sc->rl_cdata.rl_tx_cnt++;
1670
1671                 /* Pack the data into the descriptor. */
1672                 rl_encap(sc, cur_tx, m_head);
1673
1674 #if NBPFILTER > 0
1675                 /*
1676                  * If there's a BPF listener, bounce a copy of this frame
1677                  * to him.
1678                  */
1679                 if (ifp->if_bpf)
1680                         bpf_mtap(ifp, cur_tx->rl_mbuf);
1681 #endif
1682                 /*
1683                  * Transmit the frame.
1684                  */
1685                 CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc,
1686                                 vtophys(mtod(cur_tx->rl_mbuf, caddr_t)));
1687                 CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc,
1688                         RL_TX_EARLYTHRESH | cur_tx->rl_mbuf->m_pkthdr.len);
1689         }
1690
1691         /*
1692          * Set a timeout in case the chip goes out to lunch.
1693          */
1694         ifp->if_timer = 5;
1695
1696         return;
1697 }
1698
1699 static void rl_init(xsc)
1700         void                    *xsc;
1701 {
1702         struct rl_softc         *sc = xsc;
1703         struct ifnet            *ifp = &sc->arpcom.ac_if;
1704         int                     s, i;
1705         u_int32_t               rxcfg = 0;
1706         u_int16_t               phy_bmcr = 0;
1707
1708         if (sc->rl_autoneg)
1709                 return;
1710
1711         s = splimp();
1712
1713         /*
1714          * XXX Hack for the 8139: the built-in autoneg logic's state
1715          * gets reset by rl_init() when we don't want it to. Try
1716          * to preserve it. (For 8129 cards with real external PHYs,
1717          * the BMCR register doesn't change, but this doesn't hurt.)
1718          */
1719         if (sc->rl_type == RL_8139)
1720                 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR);
1721
1722         /*
1723          * Cancel pending I/O and free all RX/TX buffers.
1724          */
1725         rl_stop(sc);
1726
1727         /* Init our MAC address */
1728         for (i = 0; i < ETHER_ADDR_LEN; i++) {
1729                 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1730         }
1731
1732         /* Init the RX buffer pointer register. */
1733         CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1734
1735         /* Init TX descriptors. */
1736         rl_list_tx_init(sc);
1737
1738         /*
1739          * Enable transmit and receive.
1740          */
1741         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1742
1743         /*
1744          * Set the buffer size values.
1745          */
1746         CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1747
1748         /* Set the individual bit to receive frames for this host only. */
1749         rxcfg = CSR_READ_4(sc, RL_RXCFG);
1750         rxcfg |= RL_RXCFG_RX_INDIV;
1751
1752         /* If we want promiscuous mode, set the allframes bit. */
1753         if (ifp->if_flags & IFF_PROMISC) {
1754                 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1755                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1756         } else {
1757                 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1758                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1759         }
1760
1761         /*
1762          * Set capture broadcast bit to capture broadcast frames.
1763          */
1764         if (ifp->if_flags & IFF_BROADCAST) {
1765                 rxcfg |= RL_RXCFG_RX_BROAD;
1766                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1767         } else {
1768                 rxcfg &= ~RL_RXCFG_RX_BROAD;
1769                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1770         }
1771
1772         /*
1773          * Program the multicast filter, if necessary.
1774          */
1775         rl_setmulti(sc);
1776
1777         /*
1778          * Enable interrupts.
1779          */
1780         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1781
1782         /* Start RX/TX process. */
1783         CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1784
1785         /* Enable receiver and transmitter. */
1786         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1787
1788         /* Restore state of BMCR */
1789         if (sc->rl_pinfo != NULL)
1790                 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1791
1792         CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1793
1794         ifp->if_flags |= IFF_RUNNING;
1795         ifp->if_flags &= ~IFF_OACTIVE;
1796
1797         (void)splx(s);
1798
1799         return;
1800 }
1801
1802 /*
1803  * Set media options.
1804  */
1805 static int rl_ifmedia_upd(ifp)
1806         struct ifnet            *ifp;
1807 {
1808         struct rl_softc         *sc;
1809         struct ifmedia          *ifm;
1810
1811         sc = ifp->if_softc;
1812         ifm = &sc->ifmedia;
1813
1814         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1815                 return(EINVAL);
1816
1817         if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1818                 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1819         else
1820                 rl_setmode_mii(sc, ifm->ifm_media);
1821
1822         return(0);
1823 }
1824
1825 /*
1826  * Report current media status.
1827  */
1828 static void rl_ifmedia_sts(ifp, ifmr)
1829         struct ifnet            *ifp;
1830         struct ifmediareq       *ifmr;
1831 {
1832         struct rl_softc         *sc;
1833         u_int16_t               advert = 0, ability = 0;
1834
1835         sc = ifp->if_softc;
1836
1837         if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1838                 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1839                         ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
1840                 else
1841                         ifmr->ifm_active = IFM_ETHER|IFM_10_T;
1842
1843                 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1844                         ifmr->ifm_active |= IFM_FDX;
1845                 else
1846                         ifmr->ifm_active |= IFM_HDX;
1847                 return;
1848         }
1849
1850         ability = rl_phy_readreg(sc, PHY_LPAR);
1851         advert = rl_phy_readreg(sc, PHY_ANAR);
1852         if (advert & PHY_ANAR_100BT4 &&
1853                 ability & PHY_ANAR_100BT4) {
1854                 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
1855         } else if (advert & PHY_ANAR_100BTXFULL &&
1856                 ability & PHY_ANAR_100BTXFULL) {
1857                 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
1858         } else if (advert & PHY_ANAR_100BTXHALF &&
1859                 ability & PHY_ANAR_100BTXHALF) {
1860                 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
1861         } else if (advert & PHY_ANAR_10BTFULL &&
1862                 ability & PHY_ANAR_10BTFULL) {
1863                 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
1864         } else if (advert & PHY_ANAR_10BTHALF &&
1865                 ability & PHY_ANAR_10BTHALF) {
1866                 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
1867         }
1868
1869         return;
1870 }
1871
1872 static int rl_ioctl(ifp, command, data)
1873         struct ifnet            *ifp;
1874         u_long                  command;
1875         caddr_t                 data;
1876 {
1877         struct rl_softc         *sc = ifp->if_softc;
1878         struct ifreq            *ifr = (struct ifreq *) data;
1879         int                     s, error = 0;
1880
1881         s = splimp();
1882
1883         switch(command) {
1884         case SIOCSIFADDR:
1885         case SIOCGIFADDR:
1886         case SIOCSIFMTU:
1887                 error = ether_ioctl(ifp, command, data);
1888                 break;
1889         case SIOCSIFFLAGS:
1890                 if (ifp->if_flags & IFF_UP) {
1891                         rl_init(sc);
1892                 } else {
1893                         if (ifp->if_flags & IFF_RUNNING)
1894                                 rl_stop(sc);
1895                 }
1896                 error = 0;
1897                 break;
1898         case SIOCADDMULTI:
1899         case SIOCDELMULTI:
1900                 rl_setmulti(sc);
1901                 error = 0;
1902                 break;
1903         case SIOCGIFMEDIA:
1904         case SIOCSIFMEDIA:
1905                 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1906                 break;
1907         default:
1908                 error = EINVAL;
1909                 break;
1910         }
1911
1912         (void)splx(s);
1913
1914         return(error);
1915 }
1916
1917 static void rl_watchdog(ifp)
1918         struct ifnet            *ifp;
1919 {
1920         struct rl_softc         *sc;
1921
1922         sc = ifp->if_softc;
1923
1924         if (sc->rl_autoneg) {
1925                 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1);
1926                 return;
1927         }
1928
1929         printf("rl%d: watchdog timeout\n", sc->rl_unit);
1930         ifp->if_oerrors++;
1931         if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1932                 printf("rl%d: no carrier - transceiver cable problem?\n",
1933                                                                 sc->rl_unit);
1934         rl_txeoc(sc);
1935         rl_txeof(sc);
1936         rl_rxeof(sc);
1937         rl_init(sc);
1938
1939         return;
1940 }
1941
1942 /*
1943  * Stop the adapter and free any mbufs allocated to the
1944  * RX and TX lists.
1945  */
1946 static void rl_stop(sc)
1947         struct rl_softc         *sc;
1948 {
1949         register int            i;
1950         struct ifnet            *ifp;
1951
1952         ifp = &sc->arpcom.ac_if;
1953         ifp->if_timer = 0;
1954
1955         CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1956         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1957
1958         /*
1959          * Free the TX list buffers.
1960          */
1961         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1962                 if (sc->rl_cdata.rl_tx_chain[i].rl_mbuf != NULL) {
1963                         m_freem(sc->rl_cdata.rl_tx_chain[i].rl_mbuf);
1964                         sc->rl_cdata.rl_tx_chain[i].rl_mbuf = NULL;
1965                         CSR_WRITE_4(sc, RL_TXADDR0 +
1966                         sc->rl_cdata.rl_tx_chain[i].rl_desc, 0x00000000);
1967                 }
1968         }
1969
1970         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1971
1972         return;
1973 }
1974
1975 /*
1976  * Stop all chip I/O so that the kernel's probe routines don't
1977  * get confused by errant DMAs when rebooting.
1978  */
1979 static void rl_shutdown(howto, arg)
1980         int                     howto;
1981         void                    *arg;
1982 {
1983         struct rl_softc         *sc = (struct rl_softc *)arg;
1984
1985         rl_stop(sc);
1986
1987         return;
1988 }
1989
1990
1991 static struct pci_device rl_device = {
1992         "rl",
1993         rl_probe,
1994         rl_attach,
1995         &rl_count,
1996         NULL
1997 };
1998 DATA_SET(pcidevice_set, rl_device);