2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
86 #ifdef HAVE_KERNEL_OPTION_HEADERS
87 #include "opt_device_polling.h"
90 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/module.h>
98 #include <sys/socket.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
105 #include <net/if_types.h>
109 #include <machine/bus.h>
110 #include <machine/resource.h>
112 #include <sys/rman.h>
114 #include <dev/mii/mii.h>
115 #include <dev/mii/miivar.h>
117 #include <dev/pci/pcireg.h>
118 #include <dev/pci/pcivar.h>
120 MODULE_DEPEND(rl, pci, 1, 1, 1);
121 MODULE_DEPEND(rl, ether, 1, 1, 1);
122 MODULE_DEPEND(rl, miibus, 1, 1, 1);
124 /* "device miibus" required. See GENERIC if you get errors here. */
125 #include "miibus_if.h"
128 * Default to using PIO access for this driver. On SMP systems,
129 * there appear to be problems with memory mapped mode: it looks like
130 * doing too many memory mapped access back to back in rapid succession
131 * can hang the bus. I'm inclined to blame this on crummy design/construction
132 * on the part of RealTek. Memory mapped mode does appear to work on
133 * uniprocessor systems though.
135 #define RL_USEIOSPACE
137 #include <pci/if_rlreg.h>
140 * Various supported device vendors/types and their names.
142 static struct rl_type rl_devs[] = {
143 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
144 "RealTek 8129 10/100BaseTX" },
145 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
146 "RealTek 8139 10/100BaseTX" },
147 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
148 "RealTek 8139 10/100BaseTX CardBus" },
149 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
150 "RealTek 8100 10/100BaseTX" },
151 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
152 "Accton MPX 5030/5038 10/100BaseTX" },
153 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
154 "Delta Electronics 8139 10/100BaseTX" },
155 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
156 "Addtron Technolgy 8139 10/100BaseTX" },
157 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
158 "D-Link DFE-530TX+ 10/100BaseTX" },
159 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
160 "D-Link DFE-690TXD 10/100BaseTX" },
161 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
162 "Nortel Networks 10/100BaseTX" },
163 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
164 "Corega FEther CB-TXD" },
165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
166 "Corega FEtherII CB-TXD" },
167 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
168 "Peppercon AG ROL-F" },
169 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
170 "Planex FNW-3603-TX" },
171 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
172 "Planex FNW-3800-TX" },
173 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
175 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
176 "LevelOne FPC-0106TX" },
177 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
178 "Edimax EP-4103DL CardBus" }
181 static int rl_attach(device_t);
182 static int rl_detach(device_t);
183 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
184 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
185 static void rl_eeprom_putbyte(struct rl_softc *, int);
186 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
187 static int rl_encap(struct rl_softc *, struct mbuf * );
188 static int rl_list_tx_init(struct rl_softc *);
189 static int rl_ifmedia_upd(struct ifnet *);
190 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
191 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
192 static void rl_intr(void *);
193 static void rl_init(void *);
194 static void rl_init_locked(struct rl_softc *sc);
195 static void rl_mii_send(struct rl_softc *, uint32_t, int);
196 static void rl_mii_sync(struct rl_softc *);
197 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
198 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
199 static int rl_miibus_readreg(device_t, int, int);
200 static void rl_miibus_statchg(device_t);
201 static int rl_miibus_writereg(device_t, int, int, int);
202 #ifdef DEVICE_POLLING
203 static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
204 static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
206 static int rl_probe(device_t);
207 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
208 static void rl_reset(struct rl_softc *);
209 static int rl_resume(device_t);
210 static void rl_rxeof(struct rl_softc *);
211 static void rl_setmulti(struct rl_softc *);
212 static int rl_shutdown(device_t);
213 static void rl_start(struct ifnet *);
214 static void rl_start_locked(struct ifnet *);
215 static void rl_stop(struct rl_softc *);
216 static int rl_suspend(device_t);
217 static void rl_tick(void *);
218 static void rl_txeof(struct rl_softc *);
219 static void rl_watchdog(struct rl_softc *);
222 #define RL_RES SYS_RES_IOPORT
223 #define RL_RID RL_PCI_LOIO
225 #define RL_RES SYS_RES_MEMORY
226 #define RL_RID RL_PCI_LOMEM
229 static device_method_t rl_methods[] = {
230 /* Device interface */
231 DEVMETHOD(device_probe, rl_probe),
232 DEVMETHOD(device_attach, rl_attach),
233 DEVMETHOD(device_detach, rl_detach),
234 DEVMETHOD(device_suspend, rl_suspend),
235 DEVMETHOD(device_resume, rl_resume),
236 DEVMETHOD(device_shutdown, rl_shutdown),
239 DEVMETHOD(bus_print_child, bus_generic_print_child),
240 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
243 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
244 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
245 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
250 static driver_t rl_driver = {
253 sizeof(struct rl_softc)
256 static devclass_t rl_devclass;
258 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
259 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
260 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
263 CSR_WRITE_1(sc, RL_EECMD, \
264 CSR_READ_1(sc, RL_EECMD) | x)
267 CSR_WRITE_1(sc, RL_EECMD, \
268 CSR_READ_1(sc, RL_EECMD) & ~x)
271 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
273 struct rl_softc *sc = arg;
275 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
279 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
281 struct rl_softc *sc = arg;
283 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
287 * Send a read command and address to the EEPROM, check for ACK.
290 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
294 d = addr | sc->rl_eecmd_read;
297 * Feed in each bit and strobe the clock.
299 for (i = 0x400; i; i >>= 1) {
301 EE_SET(RL_EE_DATAIN);
303 EE_CLR(RL_EE_DATAIN);
314 * Read a word of data stored in the EEPROM at address 'addr.'
317 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
322 /* Enter EEPROM access mode. */
323 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
326 * Send address of word we want to read.
328 rl_eeprom_putbyte(sc, addr);
330 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
333 * Start reading bits from EEPROM.
335 for (i = 0x8000; i; i >>= 1) {
338 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
344 /* Turn off EEPROM access mode. */
345 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
351 * Read a sequence of words from the EEPROM.
354 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
357 uint16_t word = 0, *ptr;
359 for (i = 0; i < cnt; i++) {
360 rl_eeprom_getword(sc, off + i, &word);
361 ptr = (uint16_t *)(dest + (i * 2));
370 * MII access routines are provided for the 8129, which
371 * doesn't have a built-in PHY. For the 8139, we fake things
372 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
373 * direct access PHY registers.
376 CSR_WRITE_1(sc, RL_MII, \
377 CSR_READ_1(sc, RL_MII) | (x))
380 CSR_WRITE_1(sc, RL_MII, \
381 CSR_READ_1(sc, RL_MII) & ~(x))
384 * Sync the PHYs by setting data bit and strobing the clock 32 times.
387 rl_mii_sync(struct rl_softc *sc)
391 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
393 for (i = 0; i < 32; i++) {
402 * Clock a series of bits through the MII.
405 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
411 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
413 MII_SET(RL_MII_DATAOUT);
415 MII_CLR(RL_MII_DATAOUT);
425 * Read an PHY register through the MII.
428 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
432 /* Set up frame for RX. */
433 frame->mii_stdelim = RL_MII_STARTDELIM;
434 frame->mii_opcode = RL_MII_READOP;
435 frame->mii_turnaround = 0;
438 CSR_WRITE_2(sc, RL_MII, 0);
440 /* Turn on data xmit. */
445 /* Send command/address info. */
446 rl_mii_send(sc, frame->mii_stdelim, 2);
447 rl_mii_send(sc, frame->mii_opcode, 2);
448 rl_mii_send(sc, frame->mii_phyaddr, 5);
449 rl_mii_send(sc, frame->mii_regaddr, 5);
452 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
463 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
468 * Now try reading data bits. If the ack failed, we still
469 * need to clock through 16 cycles to keep the PHY(s) in sync.
472 for(i = 0; i < 16; i++) {
481 for (i = 0x8000; i; i >>= 1) {
485 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
486 frame->mii_data |= i;
499 return (ack ? 1 : 0);
503 * Write to a PHY register through the MII.
506 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
509 /* Set up frame for TX. */
510 frame->mii_stdelim = RL_MII_STARTDELIM;
511 frame->mii_opcode = RL_MII_WRITEOP;
512 frame->mii_turnaround = RL_MII_TURNAROUND;
514 /* Turn on data output. */
519 rl_mii_send(sc, frame->mii_stdelim, 2);
520 rl_mii_send(sc, frame->mii_opcode, 2);
521 rl_mii_send(sc, frame->mii_phyaddr, 5);
522 rl_mii_send(sc, frame->mii_regaddr, 5);
523 rl_mii_send(sc, frame->mii_turnaround, 2);
524 rl_mii_send(sc, frame->mii_data, 16);
539 rl_miibus_readreg(device_t dev, int phy, int reg)
542 struct rl_mii_frame frame;
544 uint16_t rl8139_reg = 0;
546 sc = device_get_softc(dev);
548 if (sc->rl_type == RL_8139) {
549 /* Pretend the internal PHY is only at address 0 */
555 rl8139_reg = RL_BMCR;
558 rl8139_reg = RL_BMSR;
561 rl8139_reg = RL_ANAR;
564 rl8139_reg = RL_ANER;
567 rl8139_reg = RL_LPAR;
573 * Allow the rlphy driver to read the media status
574 * register. If we have a link partner which does not
575 * support NWAY, this is the register which will tell
576 * us the results of parallel detection.
579 rval = CSR_READ_1(sc, RL_MEDIASTAT);
582 device_printf(sc->rl_dev, "bad phy register\n");
585 rval = CSR_READ_2(sc, rl8139_reg);
589 bzero((char *)&frame, sizeof(frame));
590 frame.mii_phyaddr = phy;
591 frame.mii_regaddr = reg;
592 rl_mii_readreg(sc, &frame);
594 return (frame.mii_data);
598 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
601 struct rl_mii_frame frame;
602 uint16_t rl8139_reg = 0;
604 sc = device_get_softc(dev);
606 if (sc->rl_type == RL_8139) {
607 /* Pretend the internal PHY is only at address 0 */
613 rl8139_reg = RL_BMCR;
616 rl8139_reg = RL_BMSR;
619 rl8139_reg = RL_ANAR;
622 rl8139_reg = RL_ANER;
625 rl8139_reg = RL_LPAR;
632 device_printf(sc->rl_dev, "bad phy register\n");
635 CSR_WRITE_2(sc, rl8139_reg, data);
639 bzero((char *)&frame, sizeof(frame));
640 frame.mii_phyaddr = phy;
641 frame.mii_regaddr = reg;
642 frame.mii_data = data;
643 rl_mii_writereg(sc, &frame);
649 rl_miibus_statchg(device_t dev)
654 * Program the 64-bit multicast hash filter.
657 rl_setmulti(struct rl_softc *sc)
659 struct ifnet *ifp = sc->rl_ifp;
661 uint32_t hashes[2] = { 0, 0 };
662 struct ifmultiaddr *ifma;
668 rxfilt = CSR_READ_4(sc, RL_RXCFG);
670 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
671 rxfilt |= RL_RXCFG_RX_MULTI;
672 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
673 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
674 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
678 /* first, zot all the existing hash bits */
679 CSR_WRITE_4(sc, RL_MAR0, 0);
680 CSR_WRITE_4(sc, RL_MAR4, 0);
682 /* now program new ones */
684 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
685 if (ifma->ifma_addr->sa_family != AF_LINK)
687 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
688 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
690 hashes[0] |= (1 << h);
692 hashes[1] |= (1 << (h - 32));
698 rxfilt |= RL_RXCFG_RX_MULTI;
700 rxfilt &= ~RL_RXCFG_RX_MULTI;
702 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
703 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
704 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
708 rl_reset(struct rl_softc *sc)
714 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
716 for (i = 0; i < RL_TIMEOUT; i++) {
718 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
722 device_printf(sc->rl_dev, "reset never completed!\n");
726 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
727 * IDs against our list and return a device name if we find a match.
730 rl_probe(device_t dev)
733 uint16_t devid, revid, vendor;
736 vendor = pci_get_vendor(dev);
737 devid = pci_get_device(dev);
738 revid = pci_get_revid(dev);
740 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
742 /* 8139C+, let re(4) take care of this device. */
747 for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
748 if (vendor == t->rl_vid && devid == t->rl_did) {
749 device_set_desc(dev, t->rl_name);
750 return (BUS_PROBE_DEFAULT);
758 * Attach the interface. Allocate softc structures, do ifmedia
759 * setup and ethernet/BPF attach.
762 rl_attach(device_t dev)
764 uint8_t eaddr[ETHER_ADDR_LEN];
769 int error = 0, i, rid;
773 sc = device_get_softc(dev);
774 unit = device_get_unit(dev);
777 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
779 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
781 pci_enable_busmaster(dev);
783 /* Map control/status registers. */
785 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
787 if (sc->rl_res == NULL) {
788 device_printf(dev, "couldn't map ports/memory\n");
795 * Detect the Realtek 8139B. For some reason, this chip is very
796 * unstable when left to autoselect the media
797 * The best workaround is to set the device to the required
798 * media type or to set it to the 10 Meg speed.
800 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
802 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
805 sc->rl_btag = rman_get_bustag(sc->rl_res);
806 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
808 /* Allocate interrupt */
810 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
811 RF_SHAREABLE | RF_ACTIVE);
813 if (sc->rl_irq[0] == NULL) {
814 device_printf(dev, "couldn't map interrupt\n");
820 * Reset the adapter. Only take the lock here as it's needed in
821 * order to call rl_reset().
827 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
828 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
829 if (rl_did != 0x8129)
830 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
833 * Get station address from the EEPROM.
835 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
836 for (i = 0; i < 3; i++) {
837 eaddr[(i * 2) + 0] = as[i] & 0xff;
838 eaddr[(i * 2) + 1] = as[i] >> 8;
842 * Now read the exact device type from the EEPROM to find
843 * out if it's an 8129 or 8139.
845 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
849 while(t->rl_name != NULL) {
850 if (rl_did == t->rl_did) {
851 sc->rl_type = t->rl_basetype;
857 if (sc->rl_type == 0) {
858 device_printf(dev, "unknown device ID: %x\n", rl_did);
864 * Allocate the parent bus DMA tag appropriate for PCI.
866 #define RL_NSEG_NEW 32
867 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
868 1, 0, /* alignment, boundary */
869 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
870 BUS_SPACE_MAXADDR, /* highaddr */
871 NULL, NULL, /* filter, filterarg */
872 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
873 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
874 BUS_DMA_ALLOCNOW, /* flags */
875 NULL, NULL, /* lockfunc, lockarg */
881 * Now allocate a tag for the DMA descriptor lists.
882 * All of our lists are allocated as a contiguous block
885 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
886 1, 0, /* alignment, boundary */
887 BUS_SPACE_MAXADDR, /* lowaddr */
888 BUS_SPACE_MAXADDR, /* highaddr */
889 NULL, NULL, /* filter, filterarg */
890 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
891 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
892 BUS_DMA_ALLOCNOW, /* flags */
893 NULL, NULL, /* lockfunc, lockarg */
899 * Now allocate a chunk of DMA-able memory based on the
900 * tag we just created.
902 error = bus_dmamem_alloc(sc->rl_tag,
903 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
904 &sc->rl_cdata.rl_rx_dmamap);
906 device_printf(dev, "no memory for list buffers!\n");
907 bus_dma_tag_destroy(sc->rl_tag);
912 /* Leave a few bytes before the start of the RX ring buffer. */
913 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
914 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
916 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
918 device_printf(dev, "can not if_alloc()\n");
924 if (mii_phy_probe(dev, &sc->rl_miibus,
925 rl_ifmedia_upd, rl_ifmedia_sts)) {
926 device_printf(dev, "MII without any phy!\n");
932 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
933 ifp->if_mtu = ETHERMTU;
934 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
935 ifp->if_ioctl = rl_ioctl;
936 ifp->if_start = rl_start;
937 ifp->if_init = rl_init;
938 ifp->if_capabilities = IFCAP_VLAN_MTU;
939 ifp->if_capenable = ifp->if_capabilities;
940 #ifdef DEVICE_POLLING
941 ifp->if_capabilities |= IFCAP_POLLING;
943 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
944 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
945 IFQ_SET_READY(&ifp->if_snd);
948 * Call MI attach routine.
950 ether_ifattach(ifp, eaddr);
952 /* Hook interrupt last to avoid having to lock softc */
953 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
954 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
956 device_printf(sc->rl_dev, "couldn't set up irq\n");
968 * Shutdown hardware and free up resources. This can be called any
969 * time after the mutex has been initialized. It is called in both
970 * the error case in attach and the normal detach case so it needs
971 * to be careful about only freeing resources that have actually been
975 rl_detach(device_t dev)
980 sc = device_get_softc(dev);
983 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
985 #ifdef DEVICE_POLLING
986 if (ifp->if_capenable & IFCAP_POLLING)
987 ether_poll_deregister(ifp);
989 /* These should only be active if attach succeeded */
990 if (device_is_attached(dev)) {
994 callout_drain(&sc->rl_stat_callout);
1001 device_delete_child(dev, sc->rl_miibus);
1002 bus_generic_detach(dev);
1004 if (sc->rl_intrhand[0])
1005 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1007 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
1009 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1015 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1016 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1017 sc->rl_cdata.rl_rx_dmamap);
1018 bus_dma_tag_destroy(sc->rl_tag);
1020 if (sc->rl_parent_tag)
1021 bus_dma_tag_destroy(sc->rl_parent_tag);
1023 mtx_destroy(&sc->rl_mtx);
1029 * Initialize the transmit descriptors.
1032 rl_list_tx_init(struct rl_softc *sc)
1034 struct rl_chain_data *cd;
1040 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1041 cd->rl_tx_chain[i] = NULL;
1043 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1046 sc->rl_cdata.cur_tx = 0;
1047 sc->rl_cdata.last_tx = 0;
1053 * A frame has been uploaded: pass the resulting mbuf chain up to
1054 * the higher level protocols.
1056 * You know there's something wrong with a PCI bus-master chip design
1057 * when you have to use m_devget().
1059 * The receive operation is badly documented in the datasheet, so I'll
1060 * attempt to document it here. The driver provides a buffer area and
1061 * places its base address in the RX buffer start address register.
1062 * The chip then begins copying frames into the RX buffer. Each frame
1063 * is preceded by a 32-bit RX status word which specifies the length
1064 * of the frame and certain other status bits. Each frame (starting with
1065 * the status word) is also 32-bit aligned. The frame length is in the
1066 * first 16 bits of the status word; the lower 15 bits correspond with
1067 * the 'rx status register' mentioned in the datasheet.
1069 * Note: to make the Alpha happy, the frame payload needs to be aligned
1070 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1071 * as the offset argument to m_devget().
1074 rl_rxeof(struct rl_softc *sc)
1077 struct ifnet *ifp = sc->rl_ifp;
1084 uint16_t max_bytes, rx_bytes = 0;
1088 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1089 BUS_DMASYNC_POSTREAD);
1091 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1093 /* Do not try to read past this point. */
1094 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1097 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1099 max_bytes = limit - cur_rx;
1101 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1102 #ifdef DEVICE_POLLING
1103 if (ifp->if_capenable & IFCAP_POLLING) {
1104 if (sc->rxcycles <= 0)
1109 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1110 rxstat = le32toh(*(uint32_t *)rxbufpos);
1113 * Here's a totally undocumented fact for you. When the
1114 * RealTek chip is in the process of copying a packet into
1115 * RAM for you, the length will be 0xfff0. If you spot a
1116 * packet header with this value, you need to stop. The
1117 * datasheet makes absolutely no mention of this and
1118 * RealTek should be shot for this.
1120 total_len = rxstat >> 16;
1121 if (total_len == RL_RXSTAT_UNFINISHED)
1124 if (!(rxstat & RL_RXSTAT_RXOK) ||
1125 total_len < ETHER_MIN_LEN ||
1126 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1132 /* No errors; receive the packet. */
1133 rx_bytes += total_len + 4;
1136 * XXX The RealTek chip includes the CRC with every
1137 * received frame, and there's no way to turn this
1138 * behavior off (at least, I can't find anything in
1139 * the manual that explains how to do it) so we have
1140 * to trim off the CRC manually.
1142 total_len -= ETHER_CRC_LEN;
1145 * Avoid trying to read more bytes than we know
1146 * the chip has prepared for us.
1148 if (rx_bytes > max_bytes)
1151 rxbufpos = sc->rl_cdata.rl_rx_buf +
1152 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1153 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1154 rxbufpos = sc->rl_cdata.rl_rx_buf;
1156 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1157 if (total_len > wrap) {
1158 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1163 m_copyback(m, wrap, total_len - wrap,
1164 sc->rl_cdata.rl_rx_buf);
1166 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1168 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1172 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1175 /* Round up to 32-bit boundary. */
1176 cur_rx = (cur_rx + 3) & ~3;
1177 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1184 (*ifp->if_input)(ifp, m);
1190 * A frame was downloaded to the chip. It's safe for us to clean up
1194 rl_txeof(struct rl_softc *sc)
1196 struct ifnet *ifp = sc->rl_ifp;
1202 * Go through our tx list and free mbufs for those
1203 * frames that have been uploaded.
1206 if (RL_LAST_TXMBUF(sc) == NULL)
1208 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1209 if (!(txstat & (RL_TXSTAT_TX_OK|
1210 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1213 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1215 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1216 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1217 m_freem(RL_LAST_TXMBUF(sc));
1218 RL_LAST_TXMBUF(sc) = NULL;
1220 * If there was a transmit underrun, bump the TX threshold.
1221 * Make sure not to overflow the 63 * 32byte we can address
1222 * with the 6 available bit.
1224 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1225 (sc->rl_txthresh < 2016))
1226 sc->rl_txthresh += 32;
1227 if (txstat & RL_TXSTAT_TX_OK)
1232 if ((txstat & RL_TXSTAT_TXABRT) ||
1233 (txstat & RL_TXSTAT_OUTOFWIN))
1234 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1235 oldthresh = sc->rl_txthresh;
1236 /* error recovery */
1239 /* restore original threshold */
1240 sc->rl_txthresh = oldthresh;
1243 RL_INC(sc->rl_cdata.last_tx);
1244 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1245 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1247 if (RL_LAST_TXMBUF(sc) == NULL)
1248 sc->rl_watchdog_timer = 0;
1249 else if (sc->rl_watchdog_timer == 0)
1250 sc->rl_watchdog_timer = 5;
1256 struct rl_softc *sc = xsc;
1257 struct mii_data *mii;
1260 mii = device_get_softc(sc->rl_miibus);
1265 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1268 #ifdef DEVICE_POLLING
1270 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1272 struct rl_softc *sc = ifp->if_softc;
1275 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1276 rl_poll_locked(ifp, cmd, count);
1281 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1283 struct rl_softc *sc = ifp->if_softc;
1287 sc->rxcycles = count;
1291 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1292 rl_start_locked(ifp);
1294 if (cmd == POLL_AND_CHECK_STATUS) {
1297 /* We should also check the status register. */
1298 status = CSR_READ_2(sc, RL_ISR);
1299 if (status == 0xffff)
1302 CSR_WRITE_2(sc, RL_ISR, status);
1304 /* XXX We should check behaviour on receiver stalls. */
1306 if (status & RL_ISR_SYSTEM_ERR) {
1312 #endif /* DEVICE_POLLING */
1317 struct rl_softc *sc = arg;
1318 struct ifnet *ifp = sc->rl_ifp;
1326 #ifdef DEVICE_POLLING
1327 if (ifp->if_capenable & IFCAP_POLLING)
1332 status = CSR_READ_2(sc, RL_ISR);
1333 /* If the card has gone away, the read returns 0xffff. */
1334 if (status == 0xffff)
1337 CSR_WRITE_2(sc, RL_ISR, status);
1338 if ((status & RL_INTRS) == 0)
1340 if (status & RL_ISR_RX_OK)
1342 if (status & RL_ISR_RX_ERR)
1344 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1346 if (status & RL_ISR_SYSTEM_ERR) {
1352 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1353 rl_start_locked(ifp);
1360 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1361 * pointers to the fragment pointers.
1364 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1366 struct mbuf *m_new = NULL;
1371 * The RealTek is brain damaged and wants longword-aligned
1372 * TX buffers, plus we can only have one fragment buffer
1373 * per packet. We have to copy pretty much all the time.
1375 m_new = m_defrag(m_head, M_DONTWAIT);
1377 if (m_new == NULL) {
1383 /* Pad frames to at least 60 bytes. */
1384 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1386 * Make security concious people happy: zero out the
1387 * bytes in the pad area, since we don't know what
1388 * this mbuf cluster buffer's previous user might
1391 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1392 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1393 m_head->m_pkthdr.len +=
1394 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1395 m_head->m_len = m_head->m_pkthdr.len;
1398 RL_CUR_TXMBUF(sc) = m_head;
1404 * Main transmit routine.
1407 rl_start(struct ifnet *ifp)
1409 struct rl_softc *sc = ifp->if_softc;
1412 rl_start_locked(ifp);
1417 rl_start_locked(struct ifnet *ifp)
1419 struct rl_softc *sc = ifp->if_softc;
1420 struct mbuf *m_head = NULL;
1424 while (RL_CUR_TXMBUF(sc) == NULL) {
1426 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1431 if (rl_encap(sc, m_head))
1434 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1435 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1437 /* Transmit the frame. */
1438 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1439 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1440 mtod(RL_CUR_TXMBUF(sc), void *),
1441 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1442 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1443 BUS_DMASYNC_PREREAD);
1444 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1445 RL_TXTHRESH(sc->rl_txthresh) |
1446 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1448 RL_INC(sc->rl_cdata.cur_tx);
1450 /* Set a timeout in case the chip goes out to lunch. */
1451 sc->rl_watchdog_timer = 5;
1455 * We broke out of the loop because all our TX slots are
1456 * full. Mark the NIC as busy until it drains some of the
1457 * packets from the queue.
1459 if (RL_CUR_TXMBUF(sc) != NULL)
1460 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1466 struct rl_softc *sc = xsc;
1474 rl_init_locked(struct rl_softc *sc)
1476 struct ifnet *ifp = sc->rl_ifp;
1477 struct mii_data *mii;
1483 mii = device_get_softc(sc->rl_miibus);
1486 * Cancel pending I/O and free all RX/TX buffers.
1491 * Init our MAC address. Even though the chipset
1492 * documentation doesn't mention it, we need to enter "Config
1493 * register write enable" mode to modify the ID registers.
1495 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1496 bzero(eaddr, sizeof(eaddr));
1497 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1498 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1499 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1500 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1502 /* Init the RX buffer pointer register. */
1503 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1504 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1505 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1506 BUS_DMASYNC_PREWRITE);
1508 /* Init TX descriptors. */
1509 rl_list_tx_init(sc);
1512 * Enable transmit and receive.
1514 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1517 * Set the initial TX and RX configuration.
1519 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1520 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1522 /* Set the individual bit to receive frames for this host only. */
1523 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1524 rxcfg |= RL_RXCFG_RX_INDIV;
1526 /* If we want promiscuous mode, set the allframes bit. */
1527 if (ifp->if_flags & IFF_PROMISC) {
1528 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1529 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1531 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1532 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1535 /* Set capture broadcast bit to capture broadcast frames. */
1536 if (ifp->if_flags & IFF_BROADCAST) {
1537 rxcfg |= RL_RXCFG_RX_BROAD;
1538 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1540 rxcfg &= ~RL_RXCFG_RX_BROAD;
1541 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1544 /* Program the multicast filter, if necessary. */
1547 #ifdef DEVICE_POLLING
1548 /* Disable interrupts if we are polling. */
1549 if (ifp->if_capenable & IFCAP_POLLING)
1550 CSR_WRITE_2(sc, RL_IMR, 0);
1553 /* Enable interrupts. */
1554 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1556 /* Set initial TX threshold */
1557 sc->rl_txthresh = RL_TX_THRESH_INIT;
1559 /* Start RX/TX process. */
1560 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1562 /* Enable receiver and transmitter. */
1563 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1567 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1569 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1570 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1572 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1576 * Set media options.
1579 rl_ifmedia_upd(struct ifnet *ifp)
1581 struct rl_softc *sc = ifp->if_softc;
1582 struct mii_data *mii;
1584 mii = device_get_softc(sc->rl_miibus);
1594 * Report current media status.
1597 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1599 struct rl_softc *sc = ifp->if_softc;
1600 struct mii_data *mii;
1602 mii = device_get_softc(sc->rl_miibus);
1607 ifmr->ifm_active = mii->mii_media_active;
1608 ifmr->ifm_status = mii->mii_media_status;
1612 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1614 struct ifreq *ifr = (struct ifreq *)data;
1615 struct mii_data *mii;
1616 struct rl_softc *sc = ifp->if_softc;
1622 if (ifp->if_flags & IFF_UP) {
1625 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1640 mii = device_get_softc(sc->rl_miibus);
1641 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1644 #ifdef DEVICE_POLLING
1645 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1646 !(ifp->if_capenable & IFCAP_POLLING)) {
1647 error = ether_poll_register(rl_poll, ifp);
1651 /* Disable interrupts */
1652 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1653 ifp->if_capenable |= IFCAP_POLLING;
1658 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1659 ifp->if_capenable & IFCAP_POLLING) {
1660 error = ether_poll_deregister(ifp);
1661 /* Enable interrupts. */
1663 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1664 ifp->if_capenable &= ~IFCAP_POLLING;
1668 #endif /* DEVICE_POLLING */
1671 error = ether_ioctl(ifp, command, data);
1679 rl_watchdog(struct rl_softc *sc)
1684 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1687 device_printf(sc->rl_dev, "watchdog timeout\n");
1688 sc->rl_ifp->if_oerrors++;
1696 * Stop the adapter and free any mbufs allocated to the
1700 rl_stop(struct rl_softc *sc)
1703 struct ifnet *ifp = sc->rl_ifp;
1707 sc->rl_watchdog_timer = 0;
1708 callout_stop(&sc->rl_stat_callout);
1709 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1711 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1712 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1713 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1716 * Free the TX list buffers.
1718 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1719 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1720 bus_dmamap_unload(sc->rl_tag,
1721 sc->rl_cdata.rl_tx_dmamap[i]);
1722 bus_dmamap_destroy(sc->rl_tag,
1723 sc->rl_cdata.rl_tx_dmamap[i]);
1724 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1725 sc->rl_cdata.rl_tx_chain[i] = NULL;
1726 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1733 * Device suspend routine. Stop the interface and save some PCI
1734 * settings in case the BIOS doesn't restore them properly on
1738 rl_suspend(device_t dev)
1740 struct rl_softc *sc;
1742 sc = device_get_softc(dev);
1753 * Device resume routine. Restore some PCI settings in case the BIOS
1754 * doesn't, re-enable busmastering, and restart the interface if
1758 rl_resume(device_t dev)
1760 struct rl_softc *sc;
1763 sc = device_get_softc(dev);
1768 /* reinitialize interface if necessary */
1769 if (ifp->if_flags & IFF_UP)
1780 * Stop all chip I/O so that the kernel's probe routines don't
1781 * get confused by errant DMAs when rebooting.
1784 rl_shutdown(device_t dev)
1786 struct rl_softc *sc;
1788 sc = device_get_softc(dev);