sys/pci/if_rl.c

   1 /*
   2  * Copyright (c) 1997, 1998
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  *      $Id: if_rl.c,v 1.10 1999/01/22 15:25:04 wpaul Exp $
  33  */
  34
  35 /*
  36  * RealTek 8129/8139 PCI NIC driver
  37  *
  38  * Supports several extremely cheap PCI 10/100 adapters based on
  39  * the RealTek chipset. Datasheets can be obtained from
  40  * www.realtek.com.tw.
  41  *
  42  * Written by Bill Paul <wpaul@ctr.columbia.edu>
  43  * Electrical Engineering Department
  44  * Columbia University, New York City
  45  */
  46
  47 /*
  48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
  49  * probably the worst PCI ethernet controller ever made, with the possible
  50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
  51  * DMA, but it has a terrible interface that nullifies any performance
  52  * gains that bus-master DMA usually offers.
  53  *
  54  * For transmission, the chip offers a series of four TX descriptor
  55  * registers. Each transmit frame must be in a contiguous buffer, aligned
  56  * on a longword (32-bit) boundary. This means we almost always have to
  57  * do mbuf copies in order to transmit a frame, except in the unlikely
  58  * case where a) the packet fits into a single mbuf, and b) the packet
  59  * is 32-bit aligned within the mbuf's data area. The presence of only
  60  * four descriptor registers means that we can never have more than four
  61  * packets queued for transmission at any one time.
  62  *
  63  * Reception is not much better. The driver has to allocate a single large
  64  * buffer area (up to 64K in size) into which the chip will DMA received
  65  * frames. Because we don't know where within this region received packets
  66  * will begin or end, we have no choice but to copy data from the buffer
  67  * area into mbufs in order to pass the packets up to the higher protocol
  68  * levels.
  69  *
  70  * It's impossible given this rotten design to really achieve decent
  71  * performance at 100Mbps, unless you happen to have a 400Mhz PII or
  72  * some equally overmuscled CPU to drive it.
  73  *
  74  * On the bright side, the 8139 does have a built-in PHY, although
  75  * rather than using an MDIO serial interface like most other NICs, the
  76  * PHY registers are directly accessible through the 8139's register
  77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
  78  * filter.
  79  *
  80  * The 8129 chip is an older version of the 8139 that uses an external PHY
  81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
  82  * the 8139 lets you directly access the on-board PHY registers. We need
  83  * to select which interface to use depending on the chip type.
  84  */
  85
  86 #include "bpfilter.h"
  87
  88 #include <sys/param.h>
  89 #include <sys/systm.h>
  90 #include <sys/sockio.h>
  91 #include <sys/mbuf.h>
  92 #include <sys/malloc.h>
  93 #include <sys/kernel.h>
  94 #include <sys/socket.h>
  95
  96 #include <net/if.h>
  97 #include <net/if_arp.h>
  98 #include <net/ethernet.h>
  99 #include <net/if_dl.h>
 100 #include <net/if_media.h>
 101
 102 #if NBPFILTER > 0
 103 #include <net/bpf.h>
 104 #endif
 105
 106 #include <vm/vm.h>              /* for vtophys */
 107 #include <vm/pmap.h>            /* for vtophys */
 108 #include <machine/clock.h>      /* for DELAY */
 109 #include <machine/bus_pio.h>
 110 #include <machine/bus_memio.h>
 111 #include <machine/bus.h>
 112
 113 #include <pci/pcireg.h>
 114 #include <pci/pcivar.h>
 115
 116 /*
 117  * Default to using PIO access for this driver. On SMP systems,
 118  * there appear to be problems with memory mapped mode: it looks like
 119  * doing too many memory mapped access back to back in rapid succession
 120  * can hang the bus. I'm inclined to blame this on crummy design/construction
 121  * on the part of RealTek. Memory mapped mode does appear to work on
 122  * uniprocessor systems though.
 123  */
 124 #define RL_USEIOSPACE
 125
 126 #include <pci/if_rlreg.h>
 127
 128 #ifndef lint
 129 static const char rcsid[] =
 130         "$Id: if_rl.c,v 1.10 1999/01/22 15:25:04 wpaul Exp $";
 131 #endif
 132
 133 /*
 134  * Various supported device vendors/types and their names.
 135  */
 136 static struct rl_type rl_devs[] = {
 137         { RT_VENDORID, RT_DEVICEID_8129,
 138                 "RealTek 8129 10/100BaseTX" },
 139         { RT_VENDORID, RT_DEVICEID_8139,
 140                 "RealTek 8139 10/100BaseTX" },
 141         { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
 142                 "Accton MPX 5030/5038 10/100BaseTX" },
 143         { 0, 0, NULL }
 144 };
 145
 146 /*
 147  * Various supported PHY vendors/types and their names. Note that
 148  * this driver will work with pretty much any MII-compliant PHY,
 149  * so failure to positively identify the chip is not a fatal error.
 150  */
 151
 152 static struct rl_type rl_phys[] = {
 153         { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
 154         { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
 155         { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
 156         { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" },
 157         { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
 158         { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
 159         { 0, 0, "<MII-compliant physical interface>" }
 160 };
 161
 162 static unsigned long rl_count = 0;
 163 static const char *rl_probe     __P((pcici_t, pcidi_t));
 164 static void rl_attach           __P((pcici_t, int));
 165
 166 static int rl_encap             __P((struct rl_softc *, struct rl_chain *,
 167                                                 struct mbuf * ));
 168
 169 static void rl_rxeof            __P((struct rl_softc *));
 170 static void rl_txeof            __P((struct rl_softc *));
 171 static void rl_txeoc            __P((struct rl_softc *));
 172 static void rl_intr             __P((void *));
 173 static void rl_start            __P((struct ifnet *));
 174 static int rl_ioctl             __P((struct ifnet *, u_long, caddr_t));
 175 static void rl_init             __P((void *));
 176 static void rl_stop             __P((struct rl_softc *));
 177 static void rl_watchdog         __P((struct ifnet *));
 178 static void rl_shutdown         __P((int, void *));
 179 static int rl_ifmedia_upd       __P((struct ifnet *));
 180 static void rl_ifmedia_sts      __P((struct ifnet *, struct ifmediareq *));
 181
 182 static void rl_eeprom_putbyte   __P((struct rl_softc *, int));
 183 static void rl_eeprom_getword   __P((struct rl_softc *, int, u_int16_t *));
 184 static void rl_read_eeprom      __P((struct rl_softc *, caddr_t,
 185                                         int, int, int));
 186 static void rl_mii_sync         __P((struct rl_softc *));
 187 static void rl_mii_send         __P((struct rl_softc *, u_int32_t, int));
 188 static int rl_mii_readreg       __P((struct rl_softc *, struct rl_mii_frame *));
 189 static int rl_mii_writereg      __P((struct rl_softc *, struct rl_mii_frame *));
 190
 191 static u_int16_t rl_phy_readreg __P((struct rl_softc *, int));
 192 static void rl_phy_writereg     __P((struct rl_softc *, int, int));
 193
 194 static void rl_autoneg_xmit     __P((struct rl_softc *));
 195 static void rl_autoneg_mii      __P((struct rl_softc *, int, int));
 196 static void rl_setmode_mii      __P((struct rl_softc *, int));
 197 static void rl_getmode_mii      __P((struct rl_softc *));
 198 static u_int8_t rl_calchash     __P((caddr_t));
 199 static void rl_setmulti         __P((struct rl_softc *));
 200 static void rl_reset            __P((struct rl_softc *));
 201 static int rl_list_tx_init      __P((struct rl_softc *));
 202
 203 #define EE_SET(x)                                       \
 204         CSR_WRITE_1(sc, RL_EECMD,                       \
 205                 CSR_READ_1(sc, RL_EECMD) | x)
 206
 207 #define EE_CLR(x)                                       \
 208         CSR_WRITE_1(sc, RL_EECMD,                       \
 209                 CSR_READ_1(sc, RL_EECMD) & ~x)
 210
 211 /*
 212  * Send a read command and address to the EEPROM, check for ACK.
 213  */
 214 static void rl_eeprom_putbyte(sc, addr)
 215         struct rl_softc         *sc;
 216         int                     addr;
 217 {
 218         register int            d, i;
 219
 220         d = addr | RL_EECMD_READ;
 221
 222         /*
 223          * Feed in each bit and stobe the clock.
 224          */
 225         for (i = 0x400; i; i >>= 1) {
 226                 if (d & i) {
 227                         EE_SET(RL_EE_DATAIN);
 228                 } else {
 229                         EE_CLR(RL_EE_DATAIN);
 230                 }
 231                 DELAY(100);
 232                 EE_SET(RL_EE_CLK);
 233                 DELAY(150);
 234                 EE_CLR(RL_EE_CLK);
 235                 DELAY(100);
 236         }
 237
 238         return;
 239 }
 240
 241 /*
 242  * Read a word of data stored in the EEPROM at address 'addr.'
 243  */
 244 static void rl_eeprom_getword(sc, addr, dest)
 245         struct rl_softc         *sc;
 246         int                     addr;
 247         u_int16_t               *dest;
 248 {
 249         register int            i;
 250         u_int16_t               word = 0;
 251
 252         /* Enter EEPROM access mode. */
 253         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 254
 255         /*
 256          * Send address of word we want to read.
 257          */
 258         rl_eeprom_putbyte(sc, addr);
 259
 260         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 261
 262         /*
 263          * Start reading bits from EEPROM.
 264          */
 265         for (i = 0x8000; i; i >>= 1) {
 266                 EE_SET(RL_EE_CLK);
 267                 DELAY(100);
 268                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
 269                         word |= i;
 270                 EE_CLR(RL_EE_CLK);
 271                 DELAY(100);
 272         }
 273
 274         /* Turn off EEPROM access mode. */
 275         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 276
 277         *dest = word;
 278
 279         return;
 280 }
 281
 282 /*
 283  * Read a sequence of words from the EEPROM.
 284  */
 285 static void rl_read_eeprom(sc, dest, off, cnt, swap)
 286         struct rl_softc         *sc;
 287         caddr_t                 dest;
 288         int                     off;
 289         int                     cnt;
 290         int                     swap;
 291 {
 292         int                     i;
 293         u_int16_t               word = 0, *ptr;
 294
 295         for (i = 0; i < cnt; i++) {
 296                 rl_eeprom_getword(sc, off + i, &word);
 297                 ptr = (u_int16_t *)(dest + (i * 2));
 298                 if (swap)
 299                         *ptr = ntohs(word);
 300                 else
 301                         *ptr = word;
 302         }
 303
 304         return;
 305 }
 306
 307
 308 /*
 309  * MII access routines are provided for the 8129, which
 310  * doesn't have a built-in PHY. For the 8139, we fake things
 311  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
 312  * direct access PHY registers.
 313  */
 314 #define MII_SET(x)                                      \
 315         CSR_WRITE_1(sc, RL_MII,                         \
 316                 CSR_READ_1(sc, RL_MII) | x)
 317
 318 #define MII_CLR(x)                                      \
 319         CSR_WRITE_1(sc, RL_MII,                         \
 320                 CSR_READ_1(sc, RL_MII) & ~x)
 321
 322 /*
 323  * Sync the PHYs by setting data bit and strobing the clock 32 times.
 324  */
 325 static void rl_mii_sync(sc)
 326         struct rl_softc         *sc;
 327 {
 328         register int            i;
 329
 330         MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
 331
 332         for (i = 0; i < 32; i++) {
 333                 MII_SET(RL_MII_CLK);
 334                 DELAY(1);
 335                 MII_CLR(RL_MII_CLK);
 336                 DELAY(1);
 337         }
 338
 339         return;
 340 }
 341
 342 /*
 343  * Clock a series of bits through the MII.
 344  */
 345 static void rl_mii_send(sc, bits, cnt)
 346         struct rl_softc         *sc;
 347         u_int32_t               bits;
 348         int                     cnt;
 349 {
 350         int                     i;
 351
 352         MII_CLR(RL_MII_CLK);
 353
 354         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
 355                 if (bits & i) {
 356                         MII_SET(RL_MII_DATAOUT);
 357                 } else {
 358                         MII_CLR(RL_MII_DATAOUT);
 359                 }
 360                 DELAY(1);
 361                 MII_CLR(RL_MII_CLK);
 362                 DELAY(1);
 363                 MII_SET(RL_MII_CLK);
 364         }
 365 }
 366
 367 /*
 368  * Read an PHY register through the MII.
 369  */
 370 static int rl_mii_readreg(sc, frame)
 371         struct rl_softc         *sc;
 372         struct rl_mii_frame     *frame;
 373
 374 {
 375         int                     i, ack, s;
 376
 377         s = splimp();
 378
 379         /*
 380          * Set up frame for RX.
 381          */
 382         frame->mii_stdelim = RL_MII_STARTDELIM;
 383         frame->mii_opcode = RL_MII_READOP;
 384         frame->mii_turnaround = 0;
 385         frame->mii_data = 0;
 386
 387         CSR_WRITE_2(sc, RL_MII, 0);
 388
 389         /*
 390          * Turn on data xmit.
 391          */
 392         MII_SET(RL_MII_DIR);
 393
 394         rl_mii_sync(sc);
 395
 396         /*
 397          * Send command/address info.
 398          */
 399         rl_mii_send(sc, frame->mii_stdelim, 2);
 400         rl_mii_send(sc, frame->mii_opcode, 2);
 401         rl_mii_send(sc, frame->mii_phyaddr, 5);
 402         rl_mii_send(sc, frame->mii_regaddr, 5);
 403
 404         /* Idle bit */
 405         MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
 406         DELAY(1);
 407         MII_SET(RL_MII_CLK);
 408         DELAY(1);
 409
 410         /* Turn off xmit. */
 411         MII_CLR(RL_MII_DIR);
 412
 413         /* Check for ack */
 414         MII_CLR(RL_MII_CLK);
 415         DELAY(1);
 416         MII_SET(RL_MII_CLK);
 417         DELAY(1);
 418         ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
 419
 420         /*
 421          * Now try reading data bits. If the ack failed, we still
 422          * need to clock through 16 cycles to keep the PHY(s) in sync.
 423          */
 424         if (ack) {
 425                 for(i = 0; i < 16; i++) {
 426                         MII_CLR(RL_MII_CLK);
 427                         DELAY(1);
 428                         MII_SET(RL_MII_CLK);
 429                         DELAY(1);
 430                 }
 431                 goto fail;
 432         }
 433
 434         for (i = 0x8000; i; i >>= 1) {
 435                 MII_CLR(RL_MII_CLK);
 436                 DELAY(1);
 437                 if (!ack) {
 438                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
 439                                 frame->mii_data |= i;
 440                         DELAY(1);
 441                 }
 442                 MII_SET(RL_MII_CLK);
 443                 DELAY(1);
 444         }
 445
 446 fail:
 447
 448         MII_CLR(RL_MII_CLK);
 449         DELAY(1);
 450         MII_SET(RL_MII_CLK);
 451         DELAY(1);
 452
 453         splx(s);
 454
 455         if (ack)
 456                 return(1);
 457         return(0);
 458 }
 459
 460 /*
 461  * Write to a PHY register through the MII.
 462  */
 463 static int rl_mii_writereg(sc, frame)
 464         struct rl_softc         *sc;
 465         struct rl_mii_frame     *frame;
 466
 467 {
 468         int                     s;
 469
 470         s = splimp();
 471         /*
 472          * Set up frame for TX.
 473          */
 474
 475         frame->mii_stdelim = RL_MII_STARTDELIM;
 476         frame->mii_opcode = RL_MII_WRITEOP;
 477         frame->mii_turnaround = RL_MII_TURNAROUND;
 478
 479         /*
 480          * Turn on data output.
 481          */
 482         MII_SET(RL_MII_DIR);
 483
 484         rl_mii_sync(sc);
 485
 486         rl_mii_send(sc, frame->mii_stdelim, 2);
 487         rl_mii_send(sc, frame->mii_opcode, 2);
 488         rl_mii_send(sc, frame->mii_phyaddr, 5);
 489         rl_mii_send(sc, frame->mii_regaddr, 5);
 490         rl_mii_send(sc, frame->mii_turnaround, 2);
 491         rl_mii_send(sc, frame->mii_data, 16);
 492
 493         /* Idle bit. */
 494         MII_SET(RL_MII_CLK);
 495         DELAY(1);
 496         MII_CLR(RL_MII_CLK);
 497         DELAY(1);
 498
 499         /*
 500          * Turn off xmit.
 501          */
 502         MII_CLR(RL_MII_DIR);
 503
 504         splx(s);
 505
 506         return(0);
 507 }
 508
 509 static u_int16_t rl_phy_readreg(sc, reg)
 510         struct rl_softc         *sc;
 511         int                     reg;
 512 {
 513         struct rl_mii_frame     frame;
 514         u_int16_t               rval = 0;
 515         u_int16_t               rl8139_reg = 0;
 516
 517         if (sc->rl_type == RL_8139) {
 518                 switch(reg) {
 519                 case PHY_BMCR:
 520                         rl8139_reg = RL_BMCR;
 521                         break;
 522                 case PHY_BMSR:
 523                         rl8139_reg = RL_BMSR;
 524                         break;
 525                 case PHY_ANAR:
 526                         rl8139_reg = RL_ANAR;
 527                         break;
 528                 case PHY_LPAR:
 529                         rl8139_reg = RL_LPAR;
 530                         break;
 531                 default:
 532                         printf("rl%d: bad phy register\n", sc->rl_unit);
 533                         return(0);
 534                 }
 535                 rval = CSR_READ_2(sc, rl8139_reg);
 536                 return(rval);
 537         }
 538
 539         bzero((char *)&frame, sizeof(frame));
 540
 541         frame.mii_phyaddr = sc->rl_phy_addr;
 542         frame.mii_regaddr = reg;
 543         rl_mii_readreg(sc, &frame);
 544
 545         return(frame.mii_data);
 546 }
 547
 548 static void rl_phy_writereg(sc, reg, data)
 549         struct rl_softc         *sc;
 550         int                     reg;
 551         int                     data;
 552 {
 553         struct rl_mii_frame     frame;
 554         u_int16_t               rl8139_reg = 0;
 555
 556         if (sc->rl_type == RL_8139) {
 557                 switch(reg) {
 558                 case PHY_BMCR:
 559                         rl8139_reg = RL_BMCR;
 560                         break;
 561                 case PHY_BMSR:
 562                         rl8139_reg = RL_BMSR;
 563                         break;
 564                 case PHY_ANAR:
 565                         rl8139_reg = RL_ANAR;
 566                         break;
 567                 case PHY_LPAR:
 568                         rl8139_reg = RL_LPAR;
 569                         break;
 570                 default:
 571                         printf("rl%d: bad phy register\n", sc->rl_unit);
 572                         return;
 573                 }
 574                 CSR_WRITE_2(sc, rl8139_reg, data);
 575                 return;
 576         }
 577
 578         bzero((char *)&frame, sizeof(frame));
 579
 580         frame.mii_phyaddr = sc->rl_phy_addr;
 581         frame.mii_regaddr = reg;
 582         frame.mii_data = data;
 583
 584         rl_mii_writereg(sc, &frame);
 585
 586         return;
 587 }
 588
 589 /*
 590  * Calculate CRC of a multicast group address, return the upper 6 bits.
 591  */
 592 static u_int8_t rl_calchash(addr)
 593         caddr_t                 addr;
 594 {
 595         u_int32_t               crc, carry;
 596         int                     i, j;
 597         u_int8_t                c;
 598
 599         /* Compute CRC for the address value. */
 600         crc = 0xFFFFFFFF; /* initial value */
 601
 602         for (i = 0; i < 6; i++) {
 603                 c = *(addr + i);
 604                 for (j = 0; j < 8; j++) {
 605                         carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
 606                         crc <<= 1;
 607                         c >>= 1;
 608                         if (carry)
 609                                 crc = (crc ^ 0x04c11db6) | carry;
 610                 }
 611         }
 612
 613         /* return the filter bit position */
 614         return(crc >> 26);
 615 }
 616
 617 /*
 618  * Program the 64-bit multicast hash filter.
 619  */
 620 static void rl_setmulti(sc)
 621         struct rl_softc         *sc;
 622 {
 623         struct ifnet            *ifp;
 624         int                     h = 0;
 625         u_int32_t               hashes[2] = { 0, 0 };
 626         struct ifmultiaddr      *ifma;
 627         u_int32_t               rxfilt;
 628         int                     mcnt = 0;
 629
 630         ifp = &sc->arpcom.ac_if;
 631
 632         rxfilt = CSR_READ_4(sc, RL_RXCFG);
 633
 634         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 635                 rxfilt |= RL_RXCFG_RX_MULTI;
 636                 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 637                 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
 638                 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
 639                 return;
 640         }
 641
 642         /* first, zot all the existing hash bits */
 643         CSR_WRITE_4(sc, RL_MAR0, 0);
 644         CSR_WRITE_4(sc, RL_MAR4, 0);
 645
 646         /* now program new ones */
 647         for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
 648                                 ifma = ifma->ifma_link.le_next) {
 649                 if (ifma->ifma_addr->sa_family != AF_LINK)
 650                         continue;
 651                 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 652                 if (h < 32)
 653                         hashes[0] |= (1 << h);
 654                 else
 655                         hashes[1] |= (1 << (h - 32));
 656                 mcnt++;
 657         }
 658
 659         if (mcnt)
 660                 rxfilt |= RL_RXCFG_RX_MULTI;
 661         else
 662                 rxfilt &= ~RL_RXCFG_RX_MULTI;
 663
 664         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 665         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
 666         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
 667
 668         return;
 669 }
 670
 671 /*
 672  * Initiate an autonegotiation session.
 673  */
 674 static void rl_autoneg_xmit(sc)
 675         struct rl_softc         *sc;
 676 {
 677         u_int16_t               phy_sts;
 678
 679         rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
 680         DELAY(500);
 681         while(rl_phy_readreg(sc, PHY_BMCR)
 682                         & PHY_BMCR_RESET);
 683
 684         phy_sts = rl_phy_readreg(sc, PHY_BMCR);
 685         phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
 686         rl_phy_writereg(sc, PHY_BMCR, phy_sts);
 687
 688         return;
 689 }
 690
 691 /*
 692  * Invoke autonegotiation on a PHY. Also used with the 8139 internal
 693  * transceiver.
 694  */
 695 static void rl_autoneg_mii(sc, flag, verbose)
 696         struct rl_softc         *sc;
 697         int                     flag;
 698         int                     verbose;
 699 {
 700         u_int16_t               phy_sts = 0, media, advert, ability;
 701         struct ifnet            *ifp;
 702         struct ifmedia          *ifm;
 703
 704         ifm = &sc->ifmedia;
 705         ifp = &sc->arpcom.ac_if;
 706
 707         /*
 708          * The 100baseT4 PHY sometimes has the 'autoneg supported'
 709          * bit cleared in the status register, but has the 'autoneg enabled'
 710          * bit set in the control register. This is a contradiction, and
 711          * I'm not sure how to handle it. If you want to force an attempt
 712          * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
 713          * and see what happens.
 714          */
 715 #ifndef FORCE_AUTONEG_TFOUR
 716         /*
 717          * First, see if autoneg is supported. If not, there's
 718          * no point in continuing.
 719          */
 720         phy_sts = rl_phy_readreg(sc, PHY_BMSR);
 721         if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
 722                 if (verbose)
 723                         printf("rl%d: autonegotiation not supported\n",
 724                                                         sc->rl_unit);
 725                 return;
 726         }
 727 #endif
 728
 729         switch (flag) {
 730         case RL_FLAG_FORCEDELAY:
 731                 /*
 732                  * XXX Never use this option anywhere but in the probe
 733                  * routine: making the kernel stop dead in its tracks
 734                  * for three whole seconds after we've gone multi-user
 735                  * is really bad manners.
 736                  */
 737                 rl_autoneg_xmit(sc);
 738                 DELAY(5000000);
 739                 break;
 740         case RL_FLAG_SCHEDDELAY:
 741                 /*
 742                  * Wait for the transmitter to go idle before starting
 743                  * an autoneg session, otherwise rl_start() may clobber
 744                  * our timeout, and we don't want to allow transmission
 745                  * during an autoneg session since that can screw it up.
 746                  */
 747                 if (sc->rl_cdata.rl_tx_cnt) {
 748                         sc->rl_want_auto = 1;
 749                         return;
 750                 }
 751                 rl_autoneg_xmit(sc);
 752                 ifp->if_timer = 5;
 753                 sc->rl_autoneg = 1;
 754                 sc->rl_want_auto = 0;
 755                 return;
 756                 break;
 757         case RL_FLAG_DELAYTIMEO:
 758                 ifp->if_timer = 0;
 759                 sc->rl_autoneg = 0;
 760                 break;
 761         default:
 762                 printf("rl%d: invalid autoneg flag: %d\n", sc->rl_unit, flag);
 763                 return;
 764         }
 765
 766         if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
 767                 if (verbose)
 768                         printf("rl%d: autoneg complete, ", sc->rl_unit);
 769                 phy_sts = rl_phy_readreg(sc, PHY_BMSR);
 770         } else {
 771                 if (verbose)
 772                         printf("rl%d: autoneg not complete, ", sc->rl_unit);
 773         }
 774
 775         media = rl_phy_readreg(sc, PHY_BMCR);
 776
 777         /* Link is good. Report modes and set duplex mode. */
 778         if (rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
 779                 if (verbose)
 780                         printf("link status good ");
 781                 advert = rl_phy_readreg(sc, PHY_ANAR);
 782                 ability = rl_phy_readreg(sc, PHY_LPAR);
 783
 784                 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
 785                         ifm->ifm_media = IFM_ETHER|IFM_100_T4;
 786                         media |= PHY_BMCR_SPEEDSEL;
 787                         media &= ~PHY_BMCR_DUPLEX;
 788                         printf("(100baseT4)\n");
 789                 } else if (advert & PHY_ANAR_100BTXFULL &&
 790                         ability & PHY_ANAR_100BTXFULL) {
 791                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
 792                         media |= PHY_BMCR_SPEEDSEL;
 793                         media |= PHY_BMCR_DUPLEX;
 794                         printf("(full-duplex, 100Mbps)\n");
 795                 } else if (advert & PHY_ANAR_100BTXHALF &&
 796                         ability & PHY_ANAR_100BTXHALF) {
 797                         ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
 798                         media |= PHY_BMCR_SPEEDSEL;
 799                         media &= ~PHY_BMCR_DUPLEX;
 800                         printf("(half-duplex, 100Mbps)\n");
 801                 } else if (advert & PHY_ANAR_10BTFULL &&
 802                         ability & PHY_ANAR_10BTFULL) {
 803                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
 804                         media &= ~PHY_BMCR_SPEEDSEL;
 805                         media |= PHY_BMCR_DUPLEX;
 806                         printf("(full-duplex, 10Mbps)\n");
 807                 } else {
 808                         ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
 809                         media &= ~PHY_BMCR_SPEEDSEL;
 810                         media &= ~PHY_BMCR_DUPLEX;
 811                         printf("(half-duplex, 10Mbps)\n");
 812                 }
 813
 814                 /* Set ASIC's duplex mode to match the PHY. */
 815                 rl_phy_writereg(sc, PHY_BMCR, media);
 816         } else {
 817                 if (verbose)
 818                         printf("no carrier\n");
 819         }
 820
 821         rl_init(sc);
 822
 823         if (sc->rl_tx_pend) {
 824                 sc->rl_autoneg = 0;
 825                 sc->rl_tx_pend = 0;
 826                 rl_start(ifp);
 827         }
 828
 829         return;
 830 }
 831
 832 static void rl_getmode_mii(sc)
 833         struct rl_softc         *sc;
 834 {
 835         u_int16_t               bmsr;
 836         struct ifnet            *ifp;
 837
 838         ifp = &sc->arpcom.ac_if;
 839
 840         bmsr = rl_phy_readreg(sc, PHY_BMSR);
 841         if (bootverbose)
 842                 printf("rl%d: PHY status word: %x\n", sc->rl_unit, bmsr);
 843
 844         /* fallback */
 845         sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
 846
 847         if (bmsr & PHY_BMSR_10BTHALF) {
 848                 if (bootverbose)
 849                         printf("rl%d: 10Mbps half-duplex mode supported\n",
 850                                                                 sc->rl_unit);
 851                 ifmedia_add(&sc->ifmedia,
 852                         IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
 853                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
 854         }
 855
 856         if (bmsr & PHY_BMSR_10BTFULL) {
 857                 if (bootverbose)
 858                         printf("rl%d: 10Mbps full-duplex mode supported\n",
 859                                                                 sc->rl_unit);
 860                 ifmedia_add(&sc->ifmedia,
 861                         IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
 862                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
 863         }
 864
 865         if (bmsr & PHY_BMSR_100BTXHALF) {
 866                 if (bootverbose)
 867                         printf("rl%d: 100Mbps half-duplex mode supported\n",
 868                                                                 sc->rl_unit);
 869                 ifp->if_baudrate = 100000000;
 870                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
 871                 ifmedia_add(&sc->ifmedia,
 872                         IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
 873                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
 874         }
 875
 876         if (bmsr & PHY_BMSR_100BTXFULL) {
 877                 if (bootverbose)
 878                         printf("rl%d: 100Mbps full-duplex mode supported\n",
 879                                                                 sc->rl_unit);
 880                 ifp->if_baudrate = 100000000;
 881                 ifmedia_add(&sc->ifmedia,
 882                         IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
 883                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
 884         }
 885
 886         /* Some also support 100BaseT4. */
 887         if (bmsr & PHY_BMSR_100BT4) {
 888                 if (bootverbose)
 889                         printf("rl%d: 100baseT4 mode supported\n", sc->rl_unit);
 890                 ifp->if_baudrate = 100000000;
 891                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
 892                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
 893 #ifdef FORCE_AUTONEG_TFOUR
 894                 if (bootverbose)
 895                         printf("rl%d: forcing on autoneg support for BT4\n",
 896                                                          sc->rl_unit);
 897                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
 898                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
 899 #endif
 900         }
 901
 902         if (bmsr & PHY_BMSR_CANAUTONEG) {
 903                 if (bootverbose)
 904                         printf("rl%d: autoneg supported\n", sc->rl_unit);
 905                 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 906                 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
 907         }
 908
 909         return;
 910 }
 911
 912 /*
 913  * Set speed and duplex mode.
 914  */
 915 static void rl_setmode_mii(sc, media)
 916         struct rl_softc         *sc;
 917         int                     media;
 918 {
 919         u_int16_t               bmcr;
 920
 921         printf("rl%d: selecting MII, ", sc->rl_unit);
 922
 923         bmcr = rl_phy_readreg(sc, PHY_BMCR);
 924
 925         bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
 926                         PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
 927
 928         if (IFM_SUBTYPE(media) == IFM_100_T4) {
 929                 printf("100Mbps/T4, half-duplex\n");
 930                 bmcr |= PHY_BMCR_SPEEDSEL;
 931                 bmcr &= ~PHY_BMCR_DUPLEX;
 932         }
 933
 934         if (IFM_SUBTYPE(media) == IFM_100_TX) {
 935                 printf("100Mbps, ");
 936                 bmcr |= PHY_BMCR_SPEEDSEL;
 937         }
 938
 939         if (IFM_SUBTYPE(media) == IFM_10_T) {
 940                 printf("10Mbps, ");
 941                 bmcr &= ~PHY_BMCR_SPEEDSEL;
 942         }
 943
 944         if ((media & IFM_GMASK) == IFM_FDX) {
 945                 printf("full duplex\n");
 946                 bmcr |= PHY_BMCR_DUPLEX;
 947         } else {
 948                 printf("half duplex\n");
 949                 bmcr &= ~PHY_BMCR_DUPLEX;
 950         }
 951
 952         rl_phy_writereg(sc, PHY_BMCR, bmcr);
 953
 954         return;
 955 }
 956
 957 static void rl_reset(sc)
 958         struct rl_softc         *sc;
 959 {
 960         register int            i;
 961
 962         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
 963
 964         for (i = 0; i < RL_TIMEOUT; i++) {
 965                 DELAY(10);
 966                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
 967                         break;
 968         }
 969         if (i == RL_TIMEOUT)
 970                 printf("rl%d: reset never completed!\n", sc->rl_unit);
 971
 972         return;
 973 }
 974
 975 /*
 976  * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
 977  * IDs against our list and return a device name if we find a match.
 978  */
 979 static const char *
 980 rl_probe(config_id, device_id)
 981         pcici_t                 config_id;
 982         pcidi_t                 device_id;
 983 {
 984         struct rl_type          *t;
 985
 986         t = rl_devs;
 987
 988         while(t->rl_name != NULL) {
 989                 if ((device_id & 0xFFFF) == t->rl_vid &&
 990                     ((device_id >> 16) & 0xFFFF) == t->rl_did) {
 991                         return(t->rl_name);
 992                 }
 993                 t++;
 994         }
 995
 996         return(NULL);
 997 }
 998
 999 /*
1000  * Attach the interface. Allocate softc structures, do ifmedia
1001  * setup and ethernet/BPF attach.
1002  */
1003 static void
1004 rl_attach(config_id, unit)
1005         pcici_t                 config_id;
1006         int                     unit;
1007 {
1008         int                     s, i;
1009 #ifndef RL_USEIOSPACE
1010         vm_offset_t             pbase, vbase;
1011 #endif
1012         u_char                  eaddr[ETHER_ADDR_LEN];
1013         u_int32_t               command;
1014         struct rl_softc         *sc;
1015         struct ifnet            *ifp;
1016         int                     media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1017         struct rl_type          *p;
1018         u_int16_t               phy_vid, phy_did, phy_sts;
1019         u_int16_t               rl_did = 0;
1020
1021         s = splimp();
1022
1023         sc = malloc(sizeof(struct rl_softc), M_DEVBUF, M_NOWAIT);
1024         if (sc == NULL) {
1025                 printf("rl%d: no memory for softc struct!\n", unit);
1026                 return;
1027         }
1028         bzero(sc, sizeof(struct rl_softc));
1029
1030         /*
1031          * Handle power management nonsense.
1032          */
1033
1034         command = pci_conf_read(config_id, RL_PCI_CAPID) & 0x000000FF;
1035         if (command == 0x01) {
1036
1037                 command = pci_conf_read(config_id, RL_PCI_PWRMGMTCTRL);
1038                 if (command & RL_PSTATE_MASK) {
1039                         u_int32_t               iobase, membase, irq;
1040
1041                         /* Save important PCI config data. */
1042                         iobase = pci_conf_read(config_id, RL_PCI_LOIO);
1043                         membase = pci_conf_read(config_id, RL_PCI_LOMEM);
1044                         irq = pci_conf_read(config_id, RL_PCI_INTLINE);
1045
1046                         /* Reset the power state. */
1047                         printf("rl%d: chip is is in D%d power mode "
1048                         "-- setting to D0\n", unit, command & RL_PSTATE_MASK);
1049                         command &= 0xFFFFFFFC;
1050                         pci_conf_write(config_id, RL_PCI_PWRMGMTCTRL, command);
1051
1052                         /* Restore PCI config data. */
1053                         pci_conf_write(config_id, RL_PCI_LOIO, iobase);
1054                         pci_conf_write(config_id, RL_PCI_LOMEM, membase);
1055                         pci_conf_write(config_id, RL_PCI_INTLINE, irq);
1056                 }
1057         }
1058
1059         /*
1060          * Map control/status registers.
1061          */
1062         command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1063         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1064         pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1065         command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1066
1067 #ifdef RL_USEIOSPACE
1068         if (!(command & PCIM_CMD_PORTEN)) {
1069                 printf("rl%d: failed to enable I/O ports!\n", unit);
1070                 free(sc, M_DEVBUF);
1071                 goto fail;
1072         }
1073
1074         if (!pci_map_port(config_id, RL_PCI_LOIO,
1075                                 (u_int16_t *)&(sc->rl_bhandle))) {
1076                 printf ("rl%d: couldn't map ports\n", unit);
1077                 goto fail;
1078         }
1079         sc->rl_btag = I386_BUS_SPACE_IO;
1080 #else
1081         if (!(command & PCIM_CMD_MEMEN)) {
1082                 printf("rl%d: failed to enable memory mapping!\n", unit);
1083                 goto fail;
1084         }
1085
1086         if (!pci_map_mem(config_id, RL_PCI_LOMEM, &vbase, &pbase)) {
1087                 printf ("rl%d: couldn't map memory\n", unit);
1088                 goto fail;
1089         }
1090         sc->rl_btag = I386_BUS_SPACE_MEM;
1091         sc->rl_bhandle = vbase;
1092 #endif
1093
1094         /* Allocate interrupt */
1095         if (!pci_map_int(config_id, rl_intr, sc, &net_imask)) {
1096                 printf("rl%d: couldn't map interrupt\n", unit);
1097                 goto fail;
1098         }
1099
1100         /* Reset the adapter. */
1101         rl_reset(sc);
1102
1103         /*
1104          * Get station address from the EEPROM.
1105          */
1106         rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
1107
1108         /*
1109          * A RealTek chip was detected. Inform the world.
1110          */
1111         printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1112
1113         sc->rl_unit = unit;
1114         bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1115
1116         /*
1117          * Now read the exact device type from the EEPROM to find
1118          * out if it's an 8129 or 8139.
1119          */
1120         rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1121
1122         if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030)
1123                 sc->rl_type = RL_8139;
1124         else if (rl_did == RT_DEVICEID_8129)
1125                 sc->rl_type = RL_8129;
1126         else {
1127                 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1128                 free(sc, M_DEVBUF);
1129                 goto fail;
1130         }
1131
1132         sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 16, M_DEVBUF,
1133                 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
1134
1135         if (sc->rl_cdata.rl_rx_buf == NULL) {
1136                 free(sc, M_DEVBUF);
1137                 printf("rl%d: no memory for list buffers!\n", unit);
1138                 goto fail;
1139         }
1140
1141         ifp = &sc->arpcom.ac_if;
1142         ifp->if_softc = sc;
1143         ifp->if_unit = unit;
1144         ifp->if_name = "rl";
1145         ifp->if_mtu = ETHERMTU;
1146         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1147         ifp->if_ioctl = rl_ioctl;
1148         ifp->if_output = ether_output;
1149         ifp->if_start = rl_start;
1150         ifp->if_watchdog = rl_watchdog;
1151         ifp->if_init = rl_init;
1152         ifp->if_baudrate = 10000000;
1153         ifp->if_snd.ifq_maxlen = RL_TX_LIST_CNT - 1;
1154
1155         if (sc->rl_type == RL_8129) {
1156                 if (bootverbose)
1157                         printf("rl%d: probing for a PHY\n", sc->rl_unit);
1158                 for (i = RL_PHYADDR_MIN; i < RL_PHYADDR_MAX + 1; i++) {
1159                         if (bootverbose)
1160                                 printf("rl%d: checking address: %d\n",
1161                                                         sc->rl_unit, i);
1162                         sc->rl_phy_addr = i;
1163                         rl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1164                         DELAY(500);
1165                         while(rl_phy_readreg(sc, PHY_BMCR)
1166                                         & PHY_BMCR_RESET);
1167                         if ((phy_sts = rl_phy_readreg(sc, PHY_BMSR)))
1168                                 break;
1169                 }
1170                 if (phy_sts) {
1171                         phy_vid = rl_phy_readreg(sc, PHY_VENID);
1172                         phy_did = rl_phy_readreg(sc, PHY_DEVID);
1173                         if (bootverbose)
1174                                 printf("rl%d: found PHY at address %d, ",
1175                                                 sc->rl_unit, sc->rl_phy_addr);
1176                         if (bootverbose)
1177                                 printf("vendor id: %x device id: %x\n",
1178                                         phy_vid, phy_did);
1179                         p = rl_phys;
1180                         while(p->rl_vid) {
1181                                 if (phy_vid == p->rl_vid &&
1182                                         (phy_did | 0x000F) == p->rl_did) {
1183                                         sc->rl_pinfo = p;
1184                                         break;
1185                                 }
1186                                 p++;
1187                         }
1188                         if (sc->rl_pinfo == NULL)
1189                                 sc->rl_pinfo = &rl_phys[PHY_UNKNOWN];
1190                         if (bootverbose)
1191                                 printf("rl%d: PHY type: %s\n",
1192                                         sc->rl_unit, sc->rl_pinfo->rl_name);
1193                 } else {
1194                         printf("rl%d: MII without any phy!\n", sc->rl_unit);
1195                 }
1196         }
1197
1198         /*
1199          * Do ifmedia setup.
1200          */
1201         ifmedia_init(&sc->ifmedia, 0, rl_ifmedia_upd, rl_ifmedia_sts);
1202
1203         rl_getmode_mii(sc);
1204
1205         /* Choose a default media. */
1206         media = IFM_ETHER|IFM_AUTO;
1207         ifmedia_set(&sc->ifmedia, media);
1208
1209         rl_autoneg_mii(sc, RL_FLAG_FORCEDELAY, 1);
1210
1211         /*
1212          * Call MI attach routines.
1213          */
1214         if_attach(ifp);
1215         ether_ifattach(ifp);
1216
1217 #if NBPFILTER > 0
1218         bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1219 #endif
1220         at_shutdown(rl_shutdown, sc, SHUTDOWN_POST_SYNC);
1221
1222 fail:
1223         splx(s);
1224         return;
1225 }
1226
1227 /*
1228  * Initialize the transmit descriptors.
1229  */
1230 static int rl_list_tx_init(sc)
1231         struct rl_softc         *sc;
1232 {
1233         struct rl_chain_data    *cd;
1234         int                     i;
1235
1236         cd = &sc->rl_cdata;
1237         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1238                 cd->rl_tx_chain[i].rl_desc = i * 4;
1239                 CSR_WRITE_4(sc, RL_TXADDR0 + cd->rl_tx_chain[i].rl_desc, 0);
1240                 CSR_WRITE_4(sc, RL_TXSTAT0 + cd->rl_tx_chain[i].rl_desc, 0);
1241                 if (i == (RL_TX_LIST_CNT - 1))
1242                         cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[0];
1243                 else
1244                         cd->rl_tx_chain[i].rl_next = &cd->rl_tx_chain[i + 1];
1245         }
1246
1247         sc->rl_cdata.rl_tx_cnt = 0;
1248         cd->rl_tx_cur = cd->rl_tx_free = &cd->rl_tx_chain[0];
1249
1250         return(0);
1251 }
1252
1253 /*
1254  * A frame has been uploaded: pass the resulting mbuf chain up to
1255  * the higher level protocols.
1256  *
1257  * You know there's something wrong with a PCI bus-master chip design
1258  * when you have to use m_devget().
1259  *
1260  * The receive operation is badly documented in the datasheet, so I'll
1261  * attempt to document it here. The driver provides a buffer area and
1262  * places its base address in the RX buffer start address register.
1263  * The chip then begins copying frames into the RX buffer. Each frame
1264  * is preceeded by a 32-bit RX status word which specifies the length
1265  * of the frame and certain other status bits. Each frame (starting with
1266  * the status word) is also 32-bit aligned. The frame length is in the
1267  * first 16 bits of the status word; the lower 15 bits correspond with
1268  * the 'rx status register' mentioned in the datasheet.
1269  */
1270 static void rl_rxeof(sc)
1271         struct rl_softc         *sc;
1272 {
1273         struct ether_header     *eh;
1274         struct mbuf             *m;
1275         struct ifnet            *ifp;
1276         int                     total_len = 0;
1277         u_int32_t               rxstat;
1278         caddr_t                 rxbufpos;
1279         int                     wrap = 0;
1280         u_int16_t               cur_rx;
1281         u_int16_t               limit;
1282         u_int16_t               rx_bytes = 0, max_bytes;
1283
1284         ifp = &sc->arpcom.ac_if;
1285
1286         cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1287
1288         /* Do not try to read past this point. */
1289         limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1290
1291         if (limit < cur_rx)
1292                 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1293         else
1294                 max_bytes = limit - cur_rx;
1295
1296         while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1297                 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1298                 rxstat = *(u_int32_t *)rxbufpos;
1299
1300                 /*
1301                  * Here's a totally undocumented fact for you. When the
1302                  * RealTek chip is in the process of copying a packet into
1303                  * RAM for you, the length will be 0xfff0. If you spot a
1304                  * packet header with this value, you need to stop. The
1305                  * datasheet makes absolutely no mention of this and
1306                  * RealTek should be shot for this.
1307                  */
1308                 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1309                         break;
1310
1311                 if (!(rxstat & RL_RXSTAT_RXOK)) {
1312                         ifp->if_ierrors++;
1313                         if (rxstat & (RL_RXSTAT_BADSYM|RL_RXSTAT_RUNT|
1314                                         RL_RXSTAT_GIANT|RL_RXSTAT_CRCERR|
1315                                         RL_RXSTAT_ALIGNERR)) {
1316                                 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB);
1317                                 CSR_WRITE_2(sc, RL_COMMAND, RL_CMD_TX_ENB|
1318                                                         RL_CMD_RX_ENB);
1319                                 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1320                                 CSR_WRITE_4(sc, RL_RXADDR,
1321                                         vtophys(sc->rl_cdata.rl_rx_buf));
1322                                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1323                                 cur_rx = 0;
1324                         }
1325                         break;
1326                 }
1327
1328                 /* No errors; receive the packet. */
1329                 total_len = rxstat >> 16;
1330                 rx_bytes += total_len + 4;
1331
1332                 /*
1333                  * XXX The RealTek chip includes the CRC with every
1334                  * received frame, and there's no way to turn this
1335                  * behavior off (at least, I can't find anything in
1336                  * the manual that explains how to do it) so we have
1337                  * to trim off the CRC manually.
1338                  */
1339                 total_len -= ETHER_CRC_LEN;
1340
1341                 /*
1342                  * Avoid trying to read more bytes than we know
1343                  * the chip has prepared for us.
1344                  */
1345                 if (rx_bytes > max_bytes)
1346                         break;
1347
1348                 rxbufpos = sc->rl_cdata.rl_rx_buf +
1349                         ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1350
1351                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1352                         rxbufpos = sc->rl_cdata.rl_rx_buf;
1353
1354                 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1355
1356                 if (total_len > wrap) {
1357                         m = m_devget(rxbufpos, wrap, 0, ifp, NULL);
1358                         if (m == NULL) {
1359                                 ifp->if_ierrors++;
1360                                 printf("rl%d: out of mbufs, tried to "
1361                                         "copy %d bytes\n", sc->rl_unit, wrap);
1362                         }
1363                         else
1364                                 m_copyback(m, wrap, total_len - wrap,
1365                                         sc->rl_cdata.rl_rx_buf);
1366                         cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1367                 } else {
1368                         m = m_devget(rxbufpos, total_len, 0, ifp, NULL);
1369                         if (m == NULL) {
1370                                 ifp->if_ierrors++;
1371                                 printf("rl%d: out of mbufs, tried to "
1372                                 "copy %d bytes\n", sc->rl_unit, total_len);
1373                         }
1374                         cur_rx += total_len + 4 + ETHER_CRC_LEN;
1375                 }
1376
1377                 /*
1378                  * Round up to 32-bit boundary.
1379                  */
1380                 cur_rx = (cur_rx + 3) & ~3;
1381                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1382
1383                 if (m == NULL)
1384                         continue;
1385
1386                 eh = mtod(m, struct ether_header *);
1387                 ifp->if_ipackets++;
1388
1389 #if NBPFILTER > 0
1390                 /*
1391                  * Handle BPF listeners. Let the BPF user see the packet, but
1392                  * don't pass it up to the ether_input() layer unless it's
1393                  * a broadcast packet, multicast packet, matches our ethernet
1394                  * address or the interface is in promiscuous mode.
1395                  */
1396                 if (ifp->if_bpf) {
1397                         bpf_mtap(ifp, m);
1398                         if (ifp->if_flags & IFF_PROMISC &&
1399                                 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1400                                                 ETHER_ADDR_LEN) &&
1401                                         (eh->ether_dhost[0] & 1) == 0)) {
1402                                 m_freem(m);
1403                                 continue;
1404                         }
1405                 }
1406 #endif
1407                 /* Remove header from mbuf and pass it on. */
1408                 m_adj(m, sizeof(struct ether_header));
1409                 ether_input(ifp, eh, m);
1410         }
1411
1412         return;
1413 }
1414
1415 /*
1416  * A frame was downloaded to the chip. It's safe for us to clean up
1417  * the list buffers.
1418  */
1419 static void rl_txeof(sc)
1420         struct rl_softc         *sc;
1421 {
1422         struct rl_chain         *cur_tx;
1423         struct ifnet            *ifp;
1424         u_int32_t               txstat;
1425
1426         ifp = &sc->arpcom.ac_if;
1427
1428         /* Clear the timeout timer. */
1429         ifp->if_timer = 0;
1430
1431         /*
1432          * Go through our tx list and free mbufs for those
1433          * frames that have been uploaded.
1434          */
1435         if (sc->rl_cdata.rl_tx_free == NULL)
1436                 return;
1437
1438         while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) {
1439                 cur_tx = sc->rl_cdata.rl_tx_free;
1440                 txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc);
1441
1442                 if (!(txstat & RL_TXSTAT_TX_OK))
1443                         break;
1444
1445                 if (txstat & RL_TXSTAT_COLLCNT)
1446                         ifp->if_collisions +=
1447                                         (txstat & RL_TXSTAT_COLLCNT) >> 24;
1448
1449                 sc->rl_cdata.rl_tx_free = cur_tx->rl_next;
1450
1451                 sc->rl_cdata.rl_tx_cnt--;
1452                 m_freem(cur_tx->rl_mbuf);
1453                 cur_tx->rl_mbuf = NULL;
1454                 ifp->if_opackets++;
1455         }
1456
1457         if (!sc->rl_cdata.rl_tx_cnt) {
1458                 ifp->if_flags &= ~IFF_OACTIVE;
1459                 if (sc->rl_want_auto)
1460                         rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1461         } else {
1462                 if (ifp->if_snd.ifq_head != NULL)
1463                         rl_start(ifp);
1464         }
1465
1466         return;
1467 }
1468
1469 /*
1470  * TX error handler.
1471  */
1472 static void rl_txeoc(sc)
1473         struct rl_softc         *sc;
1474 {
1475         u_int32_t               txstat;
1476         struct rl_chain         *cur_tx;
1477         struct ifnet            *ifp;
1478
1479         ifp = &sc->arpcom.ac_if;
1480
1481         if (sc->rl_cdata.rl_tx_free == NULL)
1482                 return;
1483
1484         while(sc->rl_cdata.rl_tx_free->rl_mbuf != NULL) {
1485                 cur_tx = sc->rl_cdata.rl_tx_free;
1486                 txstat = CSR_READ_4(sc, RL_TXSTAT0 + cur_tx->rl_desc);
1487
1488                 if (!(txstat & RL_TXSTAT_OWN))
1489                         break;
1490
1491                 if (!(txstat & RL_TXSTAT_TX_OK)) {
1492                         ifp->if_oerrors++;
1493                         if (txstat & RL_TXSTAT_COLLCNT)
1494                                 ifp->if_collisions +=
1495                                         (txstat & RL_TXSTAT_COLLCNT) >> 24;
1496                         CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc,
1497                                 vtophys(mtod(cur_tx->rl_mbuf, caddr_t)));
1498                         CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc,
1499                                 RL_TX_EARLYTHRESH |
1500                                         cur_tx->rl_mbuf->m_pkthdr.len);
1501                         break;
1502                 } else {
1503                         if (txstat & RL_TXSTAT_COLLCNT)
1504                                 ifp->if_collisions +=
1505                                         (txstat & RL_TXSTAT_COLLCNT) >> 24;
1506                         sc->rl_cdata.rl_tx_free = cur_tx->rl_next;
1507
1508                         sc->rl_cdata.rl_tx_cnt--;
1509                         m_freem(cur_tx->rl_mbuf);
1510                         cur_tx->rl_mbuf = NULL;
1511                         ifp->if_opackets++;
1512                 }
1513         }
1514
1515         return;
1516 }
1517
1518 static void rl_intr(arg)
1519         void                    *arg;
1520 {
1521         struct rl_softc         *sc;
1522         struct ifnet            *ifp;
1523         u_int16_t               status;
1524
1525         sc = arg;
1526         ifp = &sc->arpcom.ac_if;
1527
1528         /* Disable interrupts. */
1529         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1530
1531         for (;;) {
1532
1533                 status = CSR_READ_2(sc, RL_ISR);
1534                 if (status)
1535                         CSR_WRITE_2(sc, RL_ISR, status);
1536
1537                 if ((status & RL_INTRS) == 0)
1538                         break;
1539
1540                 if (status & RL_ISR_RX_OK)
1541                         rl_rxeof(sc);
1542
1543                 if (status & RL_ISR_RX_ERR)
1544                         rl_rxeof(sc);
1545
1546                 if (status & RL_ISR_TX_OK)
1547                         rl_txeof(sc);
1548
1549                 if (status & RL_ISR_TX_ERR)
1550                         rl_txeoc(sc);
1551
1552                 if (status & RL_ISR_SYSTEM_ERR) {
1553                         rl_reset(sc);
1554                         rl_init(sc);
1555                 }
1556
1557         }
1558
1559         /* Re-enable interrupts. */
1560         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1561
1562         if (ifp->if_snd.ifq_head != NULL) {
1563                 rl_start(ifp);
1564         }
1565
1566         return;
1567 }
1568
1569 /*
1570  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1571  * pointers to the fragment pointers.
1572  */
1573 static int rl_encap(sc, c, m_head)
1574         struct rl_softc         *sc;
1575         struct rl_chain         *c;
1576         struct mbuf             *m_head;
1577 {
1578         struct mbuf             *m;
1579         struct mbuf             *m_new = NULL;
1580
1581         /*
1582          * There are two possible encapsulation mechanisms
1583          * that we can use: an efficient one, and a very lossy
1584          * one. The efficient one only happens very rarely,
1585          * whereas the lossy one can and most likely will happen
1586          * all the time.
1587          * The efficient case happens if:
1588          * - the packet fits in a single mbuf
1589          * - the packet is 32-bit aligned within the mbuf data area
1590          * In this case, we can DMA from the mbuf directly.
1591          * The lossy case covers everything else. Bah.
1592          */
1593
1594         m = m_head;
1595
1596         MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1597         if (m_new == NULL) {
1598                 printf("rl%d: no memory for tx list", sc->rl_unit);
1599                 return(1);
1600         }
1601         if (m_head->m_pkthdr.len > MHLEN) {
1602                 MCLGET(m_new, M_DONTWAIT);
1603                 if (!(m_new->m_flags & M_EXT)) {
1604                         m_freem(m_new);
1605                         printf("rl%d: no memory for tx list",
1606                                         sc->rl_unit);
1607                         return(1);
1608                 }
1609         }
1610         m_copydata(m_head, 0, m_head->m_pkthdr.len,
1611                                 mtod(m_new, caddr_t));
1612         m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1613         m_freem(m_head);
1614         m_head = m_new;
1615
1616         /* Pad frames to at least 60 bytes. */
1617         if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1618                 m_head->m_pkthdr.len +=
1619                         (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1620                 m_head->m_len = m_head->m_pkthdr.len;
1621         }
1622
1623         c->rl_mbuf = m_head;
1624
1625         return(0);
1626 }
1627
1628 /*
1629  * Main transmit routine.
1630  */
1631
1632 static void rl_start(ifp)
1633         struct ifnet            *ifp;
1634 {
1635         struct rl_softc         *sc;
1636         struct mbuf             *m_head = NULL;
1637         struct rl_chain         *cur_tx = NULL;
1638
1639         sc = ifp->if_softc;
1640
1641         if (sc->rl_autoneg) {
1642                 sc->rl_tx_pend = 1;
1643                 return;
1644         }
1645
1646         /*
1647          * Check for an available queue slot. If there are none,
1648          * punt.
1649          */
1650         if (sc->rl_cdata.rl_tx_cur->rl_mbuf != NULL) {
1651                 ifp->if_flags |= IFF_OACTIVE;
1652                 return;
1653         }
1654
1655         while(sc->rl_cdata.rl_tx_cur->rl_mbuf == NULL) {
1656                 IF_DEQUEUE(&ifp->if_snd, m_head);
1657                 if (m_head == NULL)
1658                         break;
1659
1660
1661                 /* Pick a descriptor off the free list. */
1662                 cur_tx = sc->rl_cdata.rl_tx_cur;
1663                 sc->rl_cdata.rl_tx_cur = cur_tx->rl_next;
1664                 sc->rl_cdata.rl_tx_cnt++;
1665
1666                 /* Pack the data into the descriptor. */
1667                 rl_encap(sc, cur_tx, m_head);
1668
1669 #if NBPFILTER > 0
1670                 /*
1671                  * If there's a BPF listener, bounce a copy of this frame
1672                  * to him.
1673                  */
1674                 if (ifp->if_bpf)
1675                         bpf_mtap(ifp, cur_tx->rl_mbuf);
1676 #endif
1677                 /*
1678                  * Transmit the frame.
1679                  */
1680                 CSR_WRITE_4(sc, RL_TXADDR0 + cur_tx->rl_desc,
1681                                 vtophys(mtod(cur_tx->rl_mbuf, caddr_t)));
1682                 CSR_WRITE_4(sc, RL_TXSTAT0 + cur_tx->rl_desc,
1683                         RL_TX_EARLYTHRESH | cur_tx->rl_mbuf->m_pkthdr.len);
1684         }
1685
1686         /*
1687          * Set a timeout in case the chip goes out to lunch.
1688          */
1689         ifp->if_timer = 5;
1690
1691         return;
1692 }
1693
1694 static void rl_init(xsc)
1695         void                    *xsc;
1696 {
1697         struct rl_softc         *sc = xsc;
1698         struct ifnet            *ifp = &sc->arpcom.ac_if;
1699         int                     s, i;
1700         u_int32_t               rxcfg = 0;
1701         u_int16_t               phy_bmcr = 0;
1702
1703         if (sc->rl_autoneg)
1704                 return;
1705
1706         s = splimp();
1707
1708         /*
1709          * XXX Hack for the 8139: the built-in autoneg logic's state
1710          * gets reset by rl_init() when we don't want it to. Try
1711          * to preserve it. (For 8129 cards with real external PHYs,
1712          * the BMCR register doesn't change, but this doesn't hurt.)
1713          */
1714         if (sc->rl_type == RL_8139)
1715                 phy_bmcr = rl_phy_readreg(sc, PHY_BMCR);
1716
1717         /*
1718          * Cancel pending I/O and free all RX/TX buffers.
1719          */
1720         rl_stop(sc);
1721
1722         /* Init our MAC address */
1723         for (i = 0; i < ETHER_ADDR_LEN; i++) {
1724                 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1725         }
1726
1727         /* Init the RX buffer pointer register. */
1728         CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf));
1729
1730         /* Init TX descriptors. */
1731         rl_list_tx_init(sc);
1732
1733         /*
1734          * Enable transmit and receive.
1735          */
1736         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1737
1738         /*
1739          * Set the buffer size values.
1740          */
1741         CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1742
1743         /* Set the individual bit to receive frames for this host only. */
1744         rxcfg = CSR_READ_4(sc, RL_RXCFG);
1745         rxcfg |= RL_RXCFG_RX_INDIV;
1746
1747         /* If we want promiscuous mode, set the allframes bit. */
1748         if (ifp->if_flags & IFF_PROMISC) {
1749                 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1750                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1751         } else {
1752                 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1753                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1754         }
1755
1756         /*
1757          * Set capture broadcast bit to capture broadcast frames.
1758          */
1759         if (ifp->if_flags & IFF_BROADCAST) {
1760                 rxcfg |= RL_RXCFG_RX_BROAD;
1761                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1762         } else {
1763                 rxcfg &= ~RL_RXCFG_RX_BROAD;
1764                 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1765         }
1766
1767         /*
1768          * Program the multicast filter, if necessary.
1769          */
1770         rl_setmulti(sc);
1771
1772         /*
1773          * Enable interrupts.
1774          */
1775         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1776
1777         /* Start RX/TX process. */
1778         CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1779
1780         /* Enable receiver and transmitter. */
1781         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1782
1783         /* Restore state of BMCR */
1784         if (sc->rl_pinfo != NULL)
1785                 rl_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1786
1787         CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1788
1789         ifp->if_flags |= IFF_RUNNING;
1790         ifp->if_flags &= ~IFF_OACTIVE;
1791
1792         (void)splx(s);
1793
1794         return;
1795 }
1796
1797 /*
1798  * Set media options.
1799  */
1800 static int rl_ifmedia_upd(ifp)
1801         struct ifnet            *ifp;
1802 {
1803         struct rl_softc         *sc;
1804         struct ifmedia          *ifm;
1805
1806         sc = ifp->if_softc;
1807         ifm = &sc->ifmedia;
1808
1809         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1810                 return(EINVAL);
1811
1812         if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1813                 rl_autoneg_mii(sc, RL_FLAG_SCHEDDELAY, 1);
1814         else
1815                 rl_setmode_mii(sc, ifm->ifm_media);
1816
1817         return(0);
1818 }
1819
1820 /*
1821  * Report current media status.
1822  */
1823 static void rl_ifmedia_sts(ifp, ifmr)
1824         struct ifnet            *ifp;
1825         struct ifmediareq       *ifmr;
1826 {
1827         struct rl_softc         *sc;
1828         u_int16_t               advert = 0, ability = 0;
1829
1830         sc = ifp->if_softc;
1831
1832         if (!(rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1833                 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1834                         ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
1835                 else
1836                         ifmr->ifm_active = IFM_ETHER|IFM_10_T;
1837
1838                 if (rl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1839                         ifmr->ifm_active |= IFM_FDX;
1840                 else
1841                         ifmr->ifm_active |= IFM_HDX;
1842                 return;
1843         }
1844
1845         ability = rl_phy_readreg(sc, PHY_LPAR);
1846         advert = rl_phy_readreg(sc, PHY_ANAR);
1847         if (advert & PHY_ANAR_100BT4 &&
1848                 ability & PHY_ANAR_100BT4) {
1849                 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
1850         } else if (advert & PHY_ANAR_100BTXFULL &&
1851                 ability & PHY_ANAR_100BTXFULL) {
1852                 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
1853         } else if (advert & PHY_ANAR_100BTXHALF &&
1854                 ability & PHY_ANAR_100BTXHALF) {
1855                 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
1856         } else if (advert & PHY_ANAR_10BTFULL &&
1857                 ability & PHY_ANAR_10BTFULL) {
1858                 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
1859         } else if (advert & PHY_ANAR_10BTHALF &&
1860                 ability & PHY_ANAR_10BTHALF) {
1861                 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
1862         }
1863
1864         return;
1865 }
1866
1867 static int rl_ioctl(ifp, command, data)
1868         struct ifnet            *ifp;
1869         u_long                  command;
1870         caddr_t                 data;
1871 {
1872         struct rl_softc         *sc = ifp->if_softc;
1873         struct ifreq            *ifr = (struct ifreq *) data;
1874         int                     s, error = 0;
1875
1876         s = splimp();
1877
1878         switch(command) {
1879         case SIOCSIFADDR:
1880         case SIOCGIFADDR:
1881         case SIOCSIFMTU:
1882                 error = ether_ioctl(ifp, command, data);
1883                 break;
1884         case SIOCSIFFLAGS:
1885                 if (ifp->if_flags & IFF_UP) {
1886                         rl_init(sc);
1887                 } else {
1888                         if (ifp->if_flags & IFF_RUNNING)
1889                                 rl_stop(sc);
1890                 }
1891                 error = 0;
1892                 break;
1893         case SIOCADDMULTI:
1894         case SIOCDELMULTI:
1895                 rl_setmulti(sc);
1896                 error = 0;
1897                 break;
1898         case SIOCGIFMEDIA:
1899         case SIOCSIFMEDIA:
1900                 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1901                 break;
1902         default:
1903                 error = EINVAL;
1904                 break;
1905         }
1906
1907         (void)splx(s);
1908
1909         return(error);
1910 }
1911
1912 static void rl_watchdog(ifp)
1913         struct ifnet            *ifp;
1914 {
1915         struct rl_softc         *sc;
1916
1917         sc = ifp->if_softc;
1918
1919         if (sc->rl_autoneg) {
1920                 rl_autoneg_mii(sc, RL_FLAG_DELAYTIMEO, 1);
1921                 return;
1922         }
1923
1924         printf("rl%d: watchdog timeout\n", sc->rl_unit);
1925         ifp->if_oerrors++;
1926         if (!(rl_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1927                 printf("rl%d: no carrier - transceiver cable problem?\n",
1928                                                                 sc->rl_unit);
1929         rl_txeoc(sc);
1930         rl_txeof(sc);
1931         rl_rxeof(sc);
1932         rl_init(sc);
1933
1934         return;
1935 }
1936
1937 /*
1938  * Stop the adapter and free any mbufs allocated to the
1939  * RX and TX lists.
1940  */
1941 static void rl_stop(sc)
1942         struct rl_softc         *sc;
1943 {
1944         register int            i;
1945         struct ifnet            *ifp;
1946
1947         ifp = &sc->arpcom.ac_if;
1948         ifp->if_timer = 0;
1949
1950         CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1951         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1952
1953         /*
1954          * Free the TX list buffers.
1955          */
1956         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1957                 if (sc->rl_cdata.rl_tx_chain[i].rl_mbuf != NULL) {
1958                         m_freem(sc->rl_cdata.rl_tx_chain[i].rl_mbuf);
1959                         sc->rl_cdata.rl_tx_chain[i].rl_mbuf = NULL;
1960                         CSR_WRITE_4(sc, RL_TXADDR0 +
1961                         sc->rl_cdata.rl_tx_chain[i].rl_desc, 0x00000000);
1962                 }
1963         }
1964
1965         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1966
1967         return;
1968 }
1969
1970 /*
1971  * Stop all chip I/O so that the kernel's probe routines don't
1972  * get confused by errant DMAs when rebooting.
1973  */
1974 static void rl_shutdown(howto, arg)
1975         int                     howto;
1976         void                    *arg;
1977 {
1978         struct rl_softc         *sc = (struct rl_softc *)arg;
1979
1980         rl_stop(sc);
1981
1982         return;
1983 }
1984
1985
1986 static struct pci_device rl_device = {
1987         "rl",
1988         rl_probe,
1989         rl_attach,
1990         &rl_count,
1991         NULL
1992 };
1993 DATA_SET(pcidevice_set, rl_device);