2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
37 * Programming manual is available from:
38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Department of Electical Engineering
42 * Columbia University, New York City
46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
47 * controller designed with flexibility and reducing CPU load in mind.
48 * The Starfire offers high and low priority buffer queues, a
49 * producer/consumer index mechanism and several different buffer
50 * queue and completion queue descriptor types. Any one of a number
51 * of different driver designs can be used, depending on system and
52 * OS requirements. This driver makes use of type0 transmit frame
53 * descriptors (since BSD fragments packets across an mbuf chain)
54 * and two RX buffer queues prioritized on size (one queue for small
55 * frames that will fit into a single mbuf, another with full size
56 * mbuf clusters for everything else). The producer/consumer indexes
57 * and completion queues are also used.
59 * One downside to the Starfire has to do with alignment: buffer
60 * queues must be aligned on 256-byte boundaries, and receive buffers
61 * must be aligned on longword boundaries. The receive buffer alignment
62 * causes problems on the Alpha platform, where the packet payload
63 * should be longword aligned. There is no simple way around this.
65 * For receive filtering, the Starfire offers 16 perfect filter slots
66 * and a 512-bit hash table.
68 * The Starfire has no internal transceiver, relying instead on an
69 * external MII-based transceiver. Accessing registers on external
70 * PHYs is done through a special register map rather than with the
71 * usual bitbang MDIO method.
73 * Acesssing the registers on the Starfire is a little tricky. The
74 * Starfire has a 512K internal register space. When programmed for
75 * PCI memory mapped mode, the entire register space can be accessed
76 * directly. However in I/O space mode, only 256 bytes are directly
77 * mapped into PCI I/O space. The other registers can be accessed
78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
79 * registers inside the 256-byte I/O window.
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/sockio.h>
86 #include <sys/malloc.h>
87 #include <sys/kernel.h>
88 #include <sys/socket.h>
91 #include <net/if_arp.h>
92 #include <net/ethernet.h>
93 #include <net/if_dl.h>
94 #include <net/if_media.h>
98 #include <vm/vm.h> /* for vtophys */
99 #include <vm/pmap.h> /* for vtophys */
100 #include <machine/clock.h> /* for DELAY */
101 #include <machine/bus_pio.h>
102 #include <machine/bus_memio.h>
103 #include <machine/bus.h>
104 #include <machine/resource.h>
106 #include <sys/rman.h>
108 #include <dev/mii/mii.h>
109 #include <dev/mii/miivar.h>
111 /* "controller miibus0" required. See GENERIC if you get errors here. */
112 #include "miibus_if.h"
114 #include <pci/pcireg.h>
115 #include <pci/pcivar.h>
117 #define SF_USEIOSPACE
119 #include <pci/if_sfreg.h>
122 static const char rcsid[] =
126 static struct sf_type sf_devs[] = {
127 { AD_VENDORID, AD_DEVICEID_STARFIRE,
128 "Adaptec AIC-6915 10/100BaseTX" },
132 static int sf_probe __P((device_t));
133 static int sf_attach __P((device_t));
134 static int sf_detach __P((device_t));
135 static void sf_intr __P((void *));
136 static void sf_stats_update __P((void *));
137 static void sf_rxeof __P((struct sf_softc *));
138 static void sf_txeof __P((struct sf_softc *));
139 static int sf_encap __P((struct sf_softc *,
140 struct sf_tx_bufdesc_type0 *,
142 static void sf_start __P((struct ifnet *));
143 static int sf_ioctl __P((struct ifnet *, u_long, caddr_t));
144 static void sf_init __P((void *));
145 static void sf_stop __P((struct sf_softc *));
146 static void sf_watchdog __P((struct ifnet *));
147 static void sf_shutdown __P((device_t));
148 static int sf_ifmedia_upd __P((struct ifnet *));
149 static void sf_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
150 static void sf_reset __P((struct sf_softc *));
151 static int sf_init_rx_ring __P((struct sf_softc *));
152 static void sf_init_tx_ring __P((struct sf_softc *));
153 static int sf_newbuf __P((struct sf_softc *,
154 struct sf_rx_bufdesc_type0 *,
156 static void sf_setmulti __P((struct sf_softc *));
157 static int sf_setperf __P((struct sf_softc *, int, caddr_t));
158 static int sf_sethash __P((struct sf_softc *, caddr_t, int));
160 static int sf_setvlan __P((struct sf_softc *, int, u_int32_t));
163 static u_int8_t sf_read_eeprom __P((struct sf_softc *, int));
164 static u_int32_t sf_calchash __P((caddr_t));
166 static int sf_miibus_readreg __P((device_t, int, int));
167 static int sf_miibus_writereg __P((device_t, int, int, int));
168 static void sf_miibus_statchg __P((device_t));
170 static u_int32_t csr_read_4 __P((struct sf_softc *, int));
171 static void csr_write_4 __P((struct sf_softc *, int, u_int32_t));
174 #define SF_RES SYS_RES_IOPORT
175 #define SF_RID SF_PCI_LOIO
177 #define SF_RES SYS_RES_MEMORY
178 #define SF_RID SF_PCI_LOMEM
181 static device_method_t sf_methods[] = {
182 /* Device interface */
183 DEVMETHOD(device_probe, sf_probe),
184 DEVMETHOD(device_attach, sf_attach),
185 DEVMETHOD(device_detach, sf_detach),
186 DEVMETHOD(device_shutdown, sf_shutdown),
189 DEVMETHOD(bus_print_child, bus_generic_print_child),
190 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
193 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
194 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
195 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
200 static driver_t sf_driver = {
203 sizeof(struct sf_softc),
206 static devclass_t sf_devclass;
208 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
209 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
211 #define SF_SETBIT(sc, reg, x) \
212 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
214 #define SF_CLRBIT(sc, reg, x) \
215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
217 static u_int32_t csr_read_4(sc, reg)
224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
233 static u_int8_t sf_read_eeprom(sc, reg)
239 val = (csr_read_4(sc, SF_EEADDR_BASE +
240 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
245 static void csr_write_4(sc, reg, val)
251 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
252 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
254 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
259 static u_int32_t sf_calchash(addr)
262 u_int32_t crc, carry;
266 /* Compute CRC for the address value. */
267 crc = 0xFFFFFFFF; /* initial value */
269 for (i = 0; i < 6; i++) {
271 for (j = 0; j < 8; j++) {
272 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
276 crc = (crc ^ 0x04c11db6) | carry;
280 /* return the filter bit position */
281 return(crc >> 23 & 0x1FF);
285 * Copy the address 'mac' into the perfect RX filter entry at
286 * offset 'idx.' The perfect filter only has 16 entries so do
289 static int sf_setperf(sc, idx, mac)
296 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
302 p = (u_int16_t *)mac;
304 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
305 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
307 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
309 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
315 * Set the bit in the 512-bit hash table that corresponds to the
316 * specified mac address 'mac.' If 'prio' is nonzero, update the
317 * priority hash table instead of the filter hash table.
319 static int sf_sethash(sc, mac, prio)
329 h = sf_calchash(mac);
332 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
333 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
344 * Set a VLAN tag in the receive filter.
346 static int sf_setvlan(sc, idx, vlan)
351 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
354 csr_write_4(sc, SF_RXFILT_HASH_BASE +
355 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
361 static int sf_miibus_readreg(dev, phy, reg)
369 sc = device_get_softc(dev);
371 for (i = 0; i < SF_TIMEOUT; i++) {
372 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
373 if (val & SF_MII_DATAVALID)
380 if ((val & 0x0000FFFF) == 0xFFFF)
383 return(val & 0x0000FFFF);
386 static int sf_miibus_writereg(dev, phy, reg, val)
394 sc = device_get_softc(dev);
396 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
398 for (i = 0; i < SF_TIMEOUT; i++) {
399 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
400 if (!(busy & SF_MII_BUSY))
407 static void sf_miibus_statchg(dev)
411 struct mii_data *mii;
413 sc = device_get_softc(dev);
414 mii = device_get_softc(sc->sf_miibus);
416 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
417 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
419 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
425 static void sf_setmulti(sc)
430 struct ifmultiaddr *ifma;
431 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
433 ifp = &sc->arpcom.ac_if;
435 /* First zot all the existing filters. */
436 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
437 sf_setperf(sc, i, (char *)&dummy);
438 for (i = SF_RXFILT_HASH_BASE;
439 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
440 csr_write_4(sc, i, 0);
441 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
443 /* Now program new ones. */
444 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
445 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
448 /* First find the tail of the list. */
449 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
450 ifma = ifma->ifma_link.le_next) {
451 if (ifma->ifma_link.le_next == NULL)
454 /* Now traverse the list backwards. */
455 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
456 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
457 if (ifma->ifma_addr->sa_family != AF_LINK)
460 * Program the first 15 multicast groups
461 * into the perfect filter. For all others,
462 * use the hash table.
464 if (i < SF_RXFILT_PERFECT_CNT) {
466 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
472 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
482 static int sf_ifmedia_upd(ifp)
486 struct mii_data *mii;
489 mii = device_get_softc(sc->sf_miibus);
496 * Report current media status.
498 static void sf_ifmedia_sts(ifp, ifmr)
500 struct ifmediareq *ifmr;
503 struct mii_data *mii;
506 mii = device_get_softc(sc->sf_miibus);
509 ifmr->ifm_active = mii->mii_media_active;
510 ifmr->ifm_status = mii->mii_media_status;
515 static int sf_ioctl(ifp, command, data)
520 struct sf_softc *sc = ifp->if_softc;
521 struct ifreq *ifr = (struct ifreq *) data;
522 struct mii_data *mii;
531 error = ether_ioctl(ifp, command, data);
534 if (ifp->if_flags & IFF_UP) {
537 if (ifp->if_flags & IFF_RUNNING)
549 mii = device_get_softc(sc->sf_miibus);
550 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
562 static void sf_reset(sc)
567 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
568 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
570 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
572 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
574 for (i = 0; i < SF_TIMEOUT; i++) {
576 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
581 printf("sf%d: reset never completed!\n", sc->sf_unit);
583 /* Wait a little while for the chip to get its brains in order. */
589 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
590 * IDs against our list and return a device name if we find a match.
591 * We also check the subsystem ID so that we can identify exactly which
592 * NIC has been found, if possible.
594 static int sf_probe(dev)
601 while(t->sf_name != NULL) {
602 if ((pci_get_vendor(dev) == t->sf_vid) &&
603 (pci_get_device(dev) == t->sf_did)) {
604 switch((pci_read_config(dev,
605 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
606 case AD_SUBSYSID_62011_REV0:
607 case AD_SUBSYSID_62011_REV1:
609 "Adaptec ANA-62011 10/100BaseTX");
612 case AD_SUBSYSID_62022:
614 "Adaptec ANA-62022 10/100BaseTX");
617 case AD_SUBSYSID_62044_REV0:
618 case AD_SUBSYSID_62044_REV1:
620 "Adaptec ANA-62044 10/100BaseTX");
623 case AD_SUBSYSID_62020:
625 "Adaptec ANA-62020 10/100BaseFX");
628 case AD_SUBSYSID_69011:
630 "Adaptec ANA-69011 10/100BaseTX");
634 device_set_desc(dev, t->sf_name);
646 * Attach the interface. Allocate softc structures, do ifmedia
647 * setup and ethernet/BPF attach.
649 static int sf_attach(dev)
656 int unit, rid, error = 0;
660 sc = device_get_softc(dev);
661 unit = device_get_unit(dev);
662 bzero(sc, sizeof(struct sf_softc));
665 * Handle power management nonsense.
667 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
668 if (command == 0x01) {
670 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
671 if (command & SF_PSTATE_MASK) {
672 u_int32_t iobase, membase, irq;
674 /* Save important PCI config data. */
675 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
676 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
677 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
679 /* Reset the power state. */
680 printf("sf%d: chip is in D%d power mode "
681 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
682 command &= 0xFFFFFFFC;
683 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
685 /* Restore PCI config data. */
686 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
687 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
688 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
693 * Map control/status registers.
695 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
696 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
697 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4);
698 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
701 if (!(command & PCIM_CMD_PORTEN)) {
702 printf("sf%d: failed to enable I/O ports!\n", unit);
707 if (!(command & PCIM_CMD_MEMEN)) {
708 printf("sf%d: failed to enable memory mapping!\n", unit);
715 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid,
716 0, ~0, 1, RF_ACTIVE);
718 if (sc->sf_res == NULL) {
719 printf ("sf%d: couldn't map ports\n", unit);
724 sc->sf_btag = rman_get_bustag(sc->sf_res);
725 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
727 /* Allocate interrupt */
729 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
730 RF_SHAREABLE | RF_ACTIVE);
732 if (sc->sf_irq == NULL) {
733 printf("sf%d: couldn't map interrupt\n", unit);
734 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
739 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET,
740 sf_intr, sc, &sc->sf_intrhand);
743 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res);
744 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
745 printf("sf%d: couldn't set up irq\n", unit);
749 callout_handle_init(&sc->sf_stat_ch);
751 /* Reset the adapter. */
755 * Get station address from the EEPROM.
757 for (i = 0; i < ETHER_ADDR_LEN; i++)
758 sc->arpcom.ac_enaddr[i] =
759 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
762 * An Adaptec chip was detected. Inform the world.
764 printf("sf%d: Ethernet address: %6D\n", unit,
765 sc->arpcom.ac_enaddr, ":");
769 /* Allocate the descriptor queues. */
770 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
771 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
773 if (sc->sf_ldata == NULL) {
774 printf("sf%d: no memory for list buffers!\n", unit);
775 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
776 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
777 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
782 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
785 if (mii_phy_probe(dev, &sc->sf_miibus,
786 sf_ifmedia_upd, sf_ifmedia_sts)) {
787 printf("sf%d: MII without any phy!\n", sc->sf_unit);
788 free(sc->sf_ldata, M_DEVBUF);
789 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
790 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
791 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
796 ifp = &sc->arpcom.ac_if;
800 ifp->if_mtu = ETHERMTU;
801 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
802 ifp->if_ioctl = sf_ioctl;
803 ifp->if_output = ether_output;
804 ifp->if_start = sf_start;
805 ifp->if_watchdog = sf_watchdog;
806 ifp->if_init = sf_init;
807 ifp->if_baudrate = 10000000;
808 ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1;
811 * Call MI attach routines.
816 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
823 static int sf_detach(dev)
832 sc = device_get_softc(dev);
833 ifp = &sc->arpcom.ac_if;
838 bus_generic_detach(dev);
839 device_delete_child(dev, sc->sf_miibus);
841 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
842 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
843 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
845 free(sc->sf_ldata, M_DEVBUF);
852 static int sf_init_rx_ring(sc)
855 struct sf_list_data *ld;
860 bzero((char *)ld->sf_rx_dlist_big,
861 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
862 bzero((char *)ld->sf_rx_clist,
863 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
865 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
866 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
873 static void sf_init_tx_ring(sc)
876 struct sf_list_data *ld;
881 bzero((char *)ld->sf_tx_dlist,
882 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
883 bzero((char *)ld->sf_tx_clist,
884 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
886 for (i = 0; i < SF_TX_DLIST_CNT; i++)
887 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
888 for (i = 0; i < SF_TX_CLIST_CNT; i++)
889 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
891 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
897 static int sf_newbuf(sc, c, m)
899 struct sf_rx_bufdesc_type0 *c;
902 struct mbuf *m_new = NULL;
905 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
907 printf("sf%d: no memory for rx list -- "
908 "packet dropped!\n", sc->sf_unit);
912 MCLGET(m_new, M_DONTWAIT);
913 if (!(m_new->m_flags & M_EXT)) {
914 printf("sf%d: no memory for rx list -- "
915 "packet dropped!\n", sc->sf_unit);
919 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
922 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
923 m_new->m_data = m_new->m_ext.ext_buf;
926 m_adj(m_new, sizeof(u_int64_t));
929 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
936 * The starfire is programmed to use 'normal' mode for packet reception,
937 * which means we use the consumer/producer model for both the buffer
938 * descriptor queue and the completion descriptor queue. The only problem
939 * with this is that it involves a lot of register accesses: we have to
940 * read the RX completion consumer and producer indexes and the RX buffer
941 * producer index, plus the RX completion consumer and RX buffer producer
942 * indexes have to be updated. It would have been easier if Adaptec had
943 * put each index in a separate register, especially given that the damn
944 * NIC has a 512K register space.
946 * In spite of all the lovely features that Adaptec crammed into the 6915,
947 * it is marred by one truly stupid design flaw, which is that receive
948 * buffer addresses must be aligned on a longword boundary. This forces
949 * the packet payload to be unaligned, which is suboptimal on the x86 and
950 * completely unuseable on the Alpha. Our only recourse is to copy received
951 * packets into properly aligned buffers before handing them off.
954 static void sf_rxeof(sc)
957 struct ether_header *eh;
960 struct sf_rx_bufdesc_type0 *desc;
961 struct sf_rx_cmpdesc_type3 *cur_rx;
962 u_int32_t rxcons, rxprod;
963 int cmpprodidx, cmpconsidx, bufprodidx;
965 ifp = &sc->arpcom.ac_if;
967 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
968 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
969 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
970 cmpconsidx = SF_IDX_LO(rxcons);
971 bufprodidx = SF_IDX_LO(rxprod);
973 while (cmpconsidx != cmpprodidx) {
976 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
977 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
979 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
980 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
982 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
984 sf_newbuf(sc, desc, m);
988 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
989 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
990 sf_newbuf(sc, desc, m);
995 m_adj(m0, ETHER_ALIGN);
998 eh = mtod(m, struct ether_header *);
1003 if (ifp->if_flags & IFF_PROMISC &&
1004 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1005 ETHER_ADDR_LEN) && !(eh->ether_dhost[0] & 1))) {
1011 /* Remove header from mbuf and pass it on. */
1012 m_adj(m, sizeof(struct ether_header));
1013 ether_input(ifp, eh, m);
1017 csr_write_4(sc, SF_CQ_CONSIDX,
1018 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
1019 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1020 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
1026 * Read the transmit status from the completion queue and release
1027 * mbufs. Note that the buffer descriptor index in the completion
1028 * descriptor is an offset from the start of the transmit buffer
1029 * descriptor list in bytes. This is important because the manual
1030 * gives the impression that it should match the producer/consumer
1031 * index, which is the offset in 8 byte blocks.
1033 static void sf_txeof(sc)
1034 struct sf_softc *sc;
1036 int txcons, cmpprodidx, cmpconsidx;
1037 struct sf_tx_cmpdesc_type1 *cur_cmp;
1038 struct sf_tx_bufdesc_type0 *cur_tx;
1041 ifp = &sc->arpcom.ac_if;
1043 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1044 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1045 cmpconsidx = SF_IDX_HI(txcons);
1047 while (cmpconsidx != cmpprodidx) {
1048 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1049 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1050 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1052 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1058 if (cur_tx->sf_mbuf != NULL) {
1059 m_freem(cur_tx->sf_mbuf);
1060 cur_tx->sf_mbuf = NULL;
1065 ifp->if_flags &= ~IFF_OACTIVE;
1067 csr_write_4(sc, SF_CQ_CONSIDX,
1068 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1069 ((cmpconsidx << 16) & 0xFFFF0000));
1074 static void sf_intr(arg)
1077 struct sf_softc *sc;
1082 ifp = &sc->arpcom.ac_if;
1084 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
1087 /* Disable interrupts. */
1088 csr_write_4(sc, SF_IMR, 0x00000000);
1091 status = csr_read_4(sc, SF_ISR);
1093 csr_write_4(sc, SF_ISR, status);
1095 if (!(status & SF_INTRS))
1098 if (status & SF_ISR_RXDQ1_DMADONE)
1101 if (status & SF_ISR_TX_TXDONE)
1104 if (status & SF_ISR_ABNORMALINTR) {
1105 if (status & SF_ISR_STATSOFLOW) {
1106 untimeout(sf_stats_update, sc,
1108 sf_stats_update(sc);
1114 /* Re-enable interrupts. */
1115 csr_write_4(sc, SF_IMR, SF_INTRS);
1117 if (ifp->if_snd.ifq_head != NULL)
1123 static void sf_init(xsc)
1126 struct sf_softc *sc;
1128 struct mii_data *mii;
1134 ifp = &sc->arpcom.ac_if;
1135 mii = device_get_softc(sc->sf_miibus);
1140 /* Init all the receive filter registers */
1141 for (i = SF_RXFILT_PERFECT_BASE;
1142 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1143 csr_write_4(sc, i, 0);
1145 /* Empty stats counter registers. */
1146 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1147 csr_write_4(sc, SF_STATS_BASE +
1148 (i + sizeof(u_int32_t)), 0);
1150 /* Init our MAC address */
1151 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1152 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1153 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1155 if (sf_init_rx_ring(sc) == ENOBUFS) {
1156 printf("sf%d: initialization failed: no "
1157 "memory for rx buffers\n", sc->sf_unit);
1162 sf_init_tx_ring(sc);
1164 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1166 /* If we want promiscuous mode, set the allframes bit. */
1167 if (ifp->if_flags & IFF_PROMISC) {
1168 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1170 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1173 if (ifp->if_flags & IFF_BROADCAST) {
1174 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1176 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1179 /* Init the completion queue indexes */
1180 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1181 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1183 /* Init the RX completion queue */
1184 csr_write_4(sc, SF_RXCQ_CTL_1,
1185 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1186 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1188 /* Init RX DMA control. */
1189 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1191 /* Init the RX buffer descriptor queue. */
1192 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1193 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1194 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1195 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1197 /* Init the TX completion queue */
1198 csr_write_4(sc, SF_TXCQ_CTL,
1199 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1201 /* Init the TX buffer descriptor queue. */
1202 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1203 vtophys(sc->sf_ldata->sf_tx_dlist));
1204 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1205 csr_write_4(sc, SF_TXDQ_CTL,
1206 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1207 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1209 /* Enable autopadding of short TX frames. */
1210 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1212 /* Make sure the duplex mode is set correctly. */
1213 if ((mii->mii_media.ifm_media & IFM_GMASK) == IFM_FDX) {
1214 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
1216 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
1219 /* Enable interrupts. */
1220 csr_write_4(sc, SF_IMR, SF_INTRS);
1221 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1223 /* Enable the RX and TX engines. */
1224 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1225 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1229 ifp->if_flags |= IFF_RUNNING;
1230 ifp->if_flags &= ~IFF_OACTIVE;
1232 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1239 static int sf_encap(sc, c, m_head)
1240 struct sf_softc *sc;
1241 struct sf_tx_bufdesc_type0 *c;
1242 struct mbuf *m_head;
1245 struct sf_frag *f = NULL;
1250 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1251 if (m->m_len != 0) {
1252 if (frag == SF_MAXFRAGS)
1254 f = &c->sf_frags[frag];
1256 f->sf_pktlen = m_head->m_pkthdr.len;
1257 f->sf_fraglen = m->m_len;
1258 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1264 struct mbuf *m_new = NULL;
1266 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1267 if (m_new == NULL) {
1268 printf("sf%d: no memory for tx list", sc->sf_unit);
1272 if (m_head->m_pkthdr.len > MHLEN) {
1273 MCLGET(m_new, M_DONTWAIT);
1274 if (!(m_new->m_flags & M_EXT)) {
1276 printf("sf%d: no memory for tx list",
1281 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1282 mtod(m_new, caddr_t));
1283 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1286 f = &c->sf_frags[0];
1287 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1288 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1292 c->sf_mbuf = m_head;
1293 c->sf_id = SF_TX_BUFDESC_ID;
1294 c->sf_fragcnt = frag;
1302 static void sf_start(ifp)
1305 struct sf_softc *sc;
1306 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1307 struct mbuf *m_head = NULL;
1312 if (ifp->if_flags & IFF_OACTIVE)
1315 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1316 i = SF_IDX_HI(txprod) >> 4;
1318 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1319 IF_DEQUEUE(&ifp->if_snd, m_head);
1323 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1324 sf_encap(sc, cur_tx, m_head);
1327 * If there's a BPF listener, bounce a copy of this frame
1331 bpf_mtap(ifp, m_head);
1333 SF_INC(i, SF_TX_DLIST_CNT);
1335 if (sc->sf_tx_cnt == (SF_TX_DLIST_CNT - 2))
1343 csr_write_4(sc, SF_TXDQ_PRODIDX,
1344 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1345 ((i << 20) & 0xFFFF0000));
1352 static void sf_stop(sc)
1353 struct sf_softc *sc;
1358 ifp = &sc->arpcom.ac_if;
1360 untimeout(sf_stats_update, sc, sc->sf_stat_ch);
1362 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1363 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1364 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1365 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1366 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1367 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1368 csr_write_4(sc, SF_TXCQ_CTL, 0);
1369 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1370 csr_write_4(sc, SF_TXDQ_CTL, 0);
1373 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1374 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1375 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1376 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1380 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1381 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1382 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1383 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1387 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1393 * Note: it is important that this function not be interrupted. We
1394 * use a two-stage register access scheme: if we are interrupted in
1395 * between setting the indirect address register and reading from the
1396 * indirect data register, the contents of the address register could
1397 * be changed out from under us.
1399 static void sf_stats_update(xsc)
1402 struct sf_softc *sc;
1404 struct mii_data *mii;
1405 struct sf_stats stats;
1412 ifp = &sc->arpcom.ac_if;
1413 mii = device_get_softc(sc->sf_miibus);
1415 ptr = (u_int32_t *)&stats;
1416 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1417 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1418 (i + sizeof(u_int32_t)));
1420 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1421 csr_write_4(sc, SF_STATS_BASE +
1422 (i + sizeof(u_int32_t)), 0);
1424 ifp->if_collisions += stats.sf_tx_single_colls +
1425 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1429 sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
1436 static void sf_watchdog(ifp)
1439 struct sf_softc *sc;
1444 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1450 if (ifp->if_snd.ifq_head != NULL)
1456 static void sf_shutdown(dev)
1459 struct sf_softc *sc;
1461 sc = device_get_softc(dev);