2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
37 * available from http://www.sis.com.tw.
39 * This driver also supports the NatSemi DP83815. Datasheets are
40 * available from http://www.national.com.
42 * Written by Bill Paul <wpaul@ee.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
49 * simple TX and RX descriptors of 3 longwords in size. The receiver
50 * has a single perfect filter entry for the station address and a
51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
52 * transceiver while the 7016 requires an external transceiver chip.
53 * Both chips offer the standard bit-bang MII interface as well as
54 * an enchanced PHY interface which simplifies accessing MII registers.
56 * The only downside to this chipset is that RX descriptors must be
60 #include <sys/param.h>
61 #include <sys/systm.h>
62 #include <sys/sockio.h>
64 #include <sys/malloc.h>
65 #include <sys/kernel.h>
66 #include <sys/socket.h>
67 #include <sys/sysctl.h>
70 #include <net/if_arp.h>
71 #include <net/ethernet.h>
72 #include <net/if_dl.h>
73 #include <net/if_media.h>
74 #include <net/if_types.h>
75 #include <net/if_vlan_var.h>
79 #include <machine/bus_pio.h>
80 #include <machine/bus_memio.h>
81 #include <machine/bus.h>
82 #include <machine/resource.h>
86 #include <dev/mii/mii.h>
87 #include <dev/mii/miivar.h>
89 #include <pci/pcireg.h>
90 #include <pci/pcivar.h>
92 #define SIS_USEIOSPACE
94 #include <pci/if_sisreg.h>
96 MODULE_DEPEND(sis, miibus, 1, 1, 1);
98 /* "controller miibus0" required. See GENERIC if you get errors here. */
99 #include "miibus_if.h"
102 static const char rcsid[] =
107 * Various supported device vendors/types and their names.
109 static struct sis_type sis_devs[] = {
110 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
111 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
112 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP83815 10/100BaseTX" },
116 static int sis_probe (device_t);
117 static int sis_attach (device_t);
118 static int sis_detach (device_t);
120 static int sis_newbuf (struct sis_softc *,
121 struct sis_desc *, struct mbuf *);
122 static int sis_encap (struct sis_softc *,
123 struct mbuf *, u_int32_t *);
124 static void sis_rxeof (struct sis_softc *);
125 static void sis_rxeoc (struct sis_softc *);
126 static void sis_txeof (struct sis_softc *);
127 static void sis_intr (void *);
128 static void sis_tick (void *);
129 static void sis_start (struct ifnet *);
130 static int sis_ioctl (struct ifnet *, u_long, caddr_t);
131 static void sis_init (void *);
132 static void sis_stop (struct sis_softc *);
133 static void sis_watchdog (struct ifnet *);
134 static void sis_shutdown (device_t);
135 static int sis_ifmedia_upd (struct ifnet *);
136 static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *);
138 static u_int16_t sis_reverse (u_int16_t);
139 static void sis_delay (struct sis_softc *);
140 static void sis_eeprom_idle (struct sis_softc *);
141 static void sis_eeprom_putbyte (struct sis_softc *, int);
142 static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *);
143 static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int);
145 static void sis_read_cmos (struct sis_softc *, device_t, caddr_t,
147 static void sis_read_mac (struct sis_softc *, device_t, caddr_t);
148 static device_t sis_find_bridge (device_t);
151 static int sis_miibus_readreg (device_t, int, int);
152 static int sis_miibus_writereg (device_t, int, int, int);
153 static void sis_miibus_statchg (device_t);
155 static void sis_setmulti_sis (struct sis_softc *);
156 static void sis_setmulti_ns (struct sis_softc *);
157 static u_int32_t sis_crc (struct sis_softc *, caddr_t);
158 static void sis_reset (struct sis_softc *);
159 static int sis_list_rx_init (struct sis_softc *);
160 static int sis_list_tx_init (struct sis_softc *);
162 static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int);
163 static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int);
164 static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int);
165 #ifdef SIS_USEIOSPACE
166 #define SIS_RES SYS_RES_IOPORT
167 #define SIS_RID SIS_PCI_LOIO
169 #define SIS_RES SYS_RES_MEMORY
170 #define SIS_RID SIS_PCI_LOMEM
173 static device_method_t sis_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, sis_probe),
176 DEVMETHOD(device_attach, sis_attach),
177 DEVMETHOD(device_detach, sis_detach),
178 DEVMETHOD(device_shutdown, sis_shutdown),
181 DEVMETHOD(bus_print_child, bus_generic_print_child),
182 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
185 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
186 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
187 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
192 static driver_t sis_driver = {
195 sizeof(struct sis_softc)
198 static devclass_t sis_devclass;
201 static int sis_quick=1;
202 SYSCTL_INT(_hw, OID_AUTO, sis_quick, CTLFLAG_RW,
203 &sis_quick,0,"do not mdevget in sis driver");
206 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
207 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
209 #define SIS_SETBIT(sc, reg, x) \
210 CSR_WRITE_4(sc, reg, \
211 CSR_READ_4(sc, reg) | (x))
213 #define SIS_CLRBIT(sc, reg, x) \
214 CSR_WRITE_4(sc, reg, \
215 CSR_READ_4(sc, reg) & ~(x))
218 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
221 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
224 sis_dma_map_desc_next(arg, segs, nseg, error)
226 bus_dma_segment_t *segs;
232 r->sis_next = segs->ds_addr;
238 sis_dma_map_desc_ptr(arg, segs, nseg, error)
240 bus_dma_segment_t *segs;
246 r->sis_ptr = segs->ds_addr;
252 sis_dma_map_ring(arg, segs, nseg, error)
254 bus_dma_segment_t *segs;
266 * Routine to reverse the bits in a word. Stolen almost
267 * verbatim from /usr/games/fortune.
269 static u_int16_t sis_reverse(n)
272 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
273 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
274 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
275 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
280 static void sis_delay(sc)
281 struct sis_softc *sc;
285 for (idx = (300 / 33) + 1; idx > 0; idx--)
286 CSR_READ_4(sc, SIS_CSR);
291 static void sis_eeprom_idle(sc)
292 struct sis_softc *sc;
296 SIO_SET(SIS_EECTL_CSEL);
298 SIO_SET(SIS_EECTL_CLK);
301 for (i = 0; i < 25; i++) {
302 SIO_CLR(SIS_EECTL_CLK);
304 SIO_SET(SIS_EECTL_CLK);
308 SIO_CLR(SIS_EECTL_CLK);
310 SIO_CLR(SIS_EECTL_CSEL);
312 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
318 * Send a read command and address to the EEPROM, check for ACK.
320 static void sis_eeprom_putbyte(sc, addr)
321 struct sis_softc *sc;
326 d = addr | SIS_EECMD_READ;
329 * Feed in each bit and stobe the clock.
331 for (i = 0x400; i; i >>= 1) {
333 SIO_SET(SIS_EECTL_DIN);
335 SIO_CLR(SIS_EECTL_DIN);
338 SIO_SET(SIS_EECTL_CLK);
340 SIO_CLR(SIS_EECTL_CLK);
348 * Read a word of data stored in the EEPROM at address 'addr.'
350 static void sis_eeprom_getword(sc, addr, dest)
351 struct sis_softc *sc;
358 /* Force EEPROM to idle state. */
361 /* Enter EEPROM access mode. */
363 SIO_CLR(SIS_EECTL_CLK);
365 SIO_SET(SIS_EECTL_CSEL);
369 * Send address of word we want to read.
371 sis_eeprom_putbyte(sc, addr);
374 * Start reading bits from EEPROM.
376 for (i = 0x8000; i; i >>= 1) {
377 SIO_SET(SIS_EECTL_CLK);
379 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
382 SIO_CLR(SIS_EECTL_CLK);
386 /* Turn off EEPROM access mode. */
395 * Read a sequence of words from the EEPROM.
397 static void sis_read_eeprom(sc, dest, off, cnt, swap)
398 struct sis_softc *sc;
405 u_int16_t word = 0, *ptr;
407 for (i = 0; i < cnt; i++) {
408 sis_eeprom_getword(sc, off + i, &word);
409 ptr = (u_int16_t *)(dest + (i * 2));
420 static device_t sis_find_bridge(dev)
423 devclass_t pci_devclass;
424 device_t *pci_devices;
426 device_t *pci_children;
427 int pci_childcount = 0;
428 device_t *busp, *childp;
429 device_t child = NULL;
432 if ((pci_devclass = devclass_find("pci")) == NULL)
435 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
437 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
439 device_get_children(*busp, &pci_children, &pci_childcount);
440 for (j = 0, childp = pci_children;
441 j < pci_childcount; j++, childp++) {
442 if (pci_get_vendor(*childp) == SIS_VENDORID &&
443 pci_get_device(*childp) == 0x0008) {
451 free(pci_devices, M_TEMP);
452 free(pci_children, M_TEMP);
456 static void sis_read_cmos(sc, dev, dest, off, cnt)
457 struct sis_softc *sc;
466 bus_space_tag_t btag;
468 bridge = sis_find_bridge(dev);
471 reg = pci_read_config(bridge, 0x48, 1);
472 pci_write_config(bridge, 0x48, reg|0x40, 1);
475 btag = I386_BUS_SPACE_IO;
477 for (i = 0; i < cnt; i++) {
478 bus_space_write_1(btag, 0x0, 0x70, i + off);
479 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
482 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
486 static void sis_read_mac(sc, dev, dest)
487 struct sis_softc *sc;
491 u_int32_t filtsave, csrsave;
493 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
494 csrsave = CSR_READ_4(sc, SIS_CSR);
496 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
497 CSR_WRITE_4(sc, SIS_CSR, 0);
499 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
501 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
502 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
503 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
504 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
505 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
506 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
508 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
509 CSR_WRITE_4(sc, SIS_CSR, csrsave);
514 static int sis_miibus_readreg(dev, phy, reg)
518 struct sis_softc *sc;
521 sc = device_get_softc(dev);
523 if (sc->sis_type == SIS_TYPE_83815) {
527 * The NatSemi chip can take a while after
528 * a reset to come ready, during which the BMSR
529 * returns a value of 0. This is *never* supposed
530 * to happen: some of the BMSR bits are meant to
531 * be hardwired in the on position, and this can
532 * confuse the miibus code a bit during the probe
533 * and attach phase. So we make an effort to check
534 * for this condition and wait for it to clear.
536 if (!CSR_READ_4(sc, NS_BMSR))
538 val = CSR_READ_4(sc, NS_BMCR + (reg * 4));
542 if (sc->sis_type == SIS_TYPE_900 &&
543 sc->sis_rev < SIS_REV_635 && phy != 0)
546 CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
547 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
549 for (i = 0; i < SIS_TIMEOUT; i++) {
550 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
554 if (i == SIS_TIMEOUT) {
555 printf("sis%d: PHY failed to come ready\n", sc->sis_unit);
559 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
567 static int sis_miibus_writereg(dev, phy, reg, data)
571 struct sis_softc *sc;
574 sc = device_get_softc(dev);
576 if (sc->sis_type == SIS_TYPE_83815) {
579 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
583 if (sc->sis_type == SIS_TYPE_900 && phy != 0)
586 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
587 (reg << 6) | SIS_PHYOP_WRITE);
588 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
590 for (i = 0; i < SIS_TIMEOUT; i++) {
591 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
595 if (i == SIS_TIMEOUT)
596 printf("sis%d: PHY failed to come ready\n", sc->sis_unit);
601 static void sis_miibus_statchg(dev)
604 struct sis_softc *sc;
606 sc = device_get_softc(dev);
612 static u_int32_t sis_crc(sc, addr)
613 struct sis_softc *sc;
616 u_int32_t crc, carry;
620 /* Compute CRC for the address value. */
621 crc = 0xFFFFFFFF; /* initial value */
623 for (i = 0; i < 6; i++) {
625 for (j = 0; j < 8; j++) {
626 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
630 crc = (crc ^ 0x04c11db6) | carry;
635 * return the filter bit position
637 * The NatSemi chip has a 512-bit filter, which is
638 * different than the SiS, so we special-case it.
640 if (sc->sis_type == SIS_TYPE_83815)
641 return((crc >> 23) & 0x1FF);
643 return((crc >> 25) & 0x0000007F);
646 static void sis_setmulti_ns(sc)
647 struct sis_softc *sc;
650 struct ifmultiaddr *ifma;
651 u_int32_t h = 0, i, filtsave;
654 ifp = &sc->arpcom.ac_if;
656 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
657 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
658 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
663 * We have to explicitly enable the multicast hash table
664 * on the NatSemi chip if we want to use it, which we do.
666 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
667 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
669 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
671 /* first, zot all the existing hash bits */
672 for (i = 0; i < 32; i++) {
673 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
674 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
677 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
678 if (ifma->ifma_addr->sa_family != AF_LINK)
680 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
683 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
686 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
689 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
694 static void sis_setmulti_sis(sc)
695 struct sis_softc *sc;
698 struct ifmultiaddr *ifma;
699 u_int32_t h = 0, i, filtsave;
701 ifp = &sc->arpcom.ac_if;
703 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
704 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
708 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
710 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
712 /* first, zot all the existing hash bits */
713 for (i = 0; i < 8; i++) {
714 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + ((i * 16) >> 4)) << 16);
715 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
718 /* now program new ones */
719 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
720 if (ifma->ifma_addr->sa_family != AF_LINK)
722 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
723 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + (h >> 4)) << 16);
724 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << (h & 0xF)));
727 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
732 static void sis_reset(sc)
733 struct sis_softc *sc;
737 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
739 for (i = 0; i < SIS_TIMEOUT; i++) {
740 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
744 if (i == SIS_TIMEOUT)
745 printf("sis%d: reset never completed\n", sc->sis_unit);
747 /* Wait a little while for the chip to get its brains in order. */
751 * If this is a NetSemi chip, make sure to clear
754 if (sc->sis_type == SIS_TYPE_83815) {
755 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
756 CSR_WRITE_4(sc, NS_CLKRUN, 0);
763 * Probe for an SiS chip. Check the PCI vendor and device
764 * IDs against our list and return a device name if we find a match.
766 static int sis_probe(dev)
773 while(t->sis_name != NULL) {
774 if ((pci_get_vendor(dev) == t->sis_vid) &&
775 (pci_get_device(dev) == t->sis_did)) {
776 device_set_desc(dev, t->sis_name);
786 * Attach the interface. Allocate softc structures, do ifmedia
787 * setup and ethernet/BPF attach.
789 static int sis_attach(dev)
792 u_char eaddr[ETHER_ADDR_LEN];
794 struct sis_softc *sc;
796 int unit, error = 0, rid;
798 sc = device_get_softc(dev);
799 unit = device_get_unit(dev);
800 bzero(sc, sizeof(struct sis_softc));
802 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
805 if (pci_get_device(dev) == SIS_DEVICEID_900)
806 sc->sis_type = SIS_TYPE_900;
807 if (pci_get_device(dev) == SIS_DEVICEID_7016)
808 sc->sis_type = SIS_TYPE_7016;
809 if (pci_get_vendor(dev) == NS_VENDORID)
810 sc->sis_type = SIS_TYPE_83815;
812 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
815 * Handle power management nonsense.
817 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
818 u_int32_t iobase, membase, irq;
820 /* Save important PCI config data. */
821 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
822 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
823 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
825 /* Reset the power state. */
826 printf("sis%d: chip is in D%d power mode "
827 "-- setting to D0\n", unit,
828 pci_get_powerstate(dev));
829 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
831 /* Restore PCI config data. */
832 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
833 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
834 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
838 * Map control/status registers.
840 pci_enable_busmaster(dev);
841 pci_enable_io(dev, SYS_RES_IOPORT);
842 pci_enable_io(dev, SYS_RES_MEMORY);
843 command = pci_read_config(dev, PCIR_COMMAND, 4);
845 #ifdef SIS_USEIOSPACE
846 if (!(command & PCIM_CMD_PORTEN)) {
847 printf("sis%d: failed to enable I/O ports!\n", unit);
852 if (!(command & PCIM_CMD_MEMEN)) {
853 printf("sis%d: failed to enable memory mapping!\n", unit);
860 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid,
861 0, ~0, 1, RF_ACTIVE);
863 if (sc->sis_res == NULL) {
864 printf("sis%d: couldn't map ports/memory\n", unit);
869 sc->sis_btag = rman_get_bustag(sc->sis_res);
870 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
872 /* Allocate interrupt */
874 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
875 RF_SHAREABLE | RF_ACTIVE);
877 if (sc->sis_irq == NULL) {
878 printf("sis%d: couldn't map interrupt\n", unit);
879 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
884 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET,
885 sis_intr, sc, &sc->sis_intrhand);
888 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
889 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
890 printf("sis%d: couldn't set up irq\n", unit);
894 /* Reset the adapter. */
898 * Get station address from the EEPROM.
900 switch (pci_get_vendor(dev)) {
903 * Reading the MAC address out of the EEPROM on
904 * the NatSemi chip takes a bit more work than
905 * you'd expect. The address spans 4 16-bit words,
906 * with the first word containing only a single bit.
907 * You have to shift everything over one bit to
908 * get it aligned properly. Also, the bits are
909 * stored backwards (the LSB is really the MSB,
910 * and so on) so you have to reverse them in order
911 * to get the MAC address into the form we want.
912 * Why? Who the hell knows.
917 sis_read_eeprom(sc, (caddr_t)&tmp,
918 NS_EE_NODEADDR, 4, 0);
920 /* Shift everything over one bit. */
921 tmp[3] = tmp[3] >> 1;
922 tmp[3] |= tmp[2] << 15;
923 tmp[2] = tmp[2] >> 1;
924 tmp[2] |= tmp[1] << 15;
925 tmp[1] = tmp[1] >> 1;
926 tmp[1] |= tmp[0] << 15;
928 /* Now reverse all the bits. */
929 tmp[3] = sis_reverse(tmp[3]);
930 tmp[2] = sis_reverse(tmp[2]);
931 tmp[1] = sis_reverse(tmp[1]);
933 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
940 * If this is a SiS 630E chipset with an embedded
941 * SiS 900 controller, we have to read the MAC address
942 * from the APC CMOS RAM. Our method for doing this
943 * is very ugly since we have to reach out and grab
944 * ahold of hardware for which we cannot properly
945 * allocate resources. This code is only compiled on
946 * the i386 architecture since the SiS 630E chipset
947 * is for x86 motherboards only. Note that there are
948 * a lot of magic numbers in this hack. These are
949 * taken from SiS's Linux driver. I'd like to replace
950 * them with proper symbolic definitions, but that
951 * requires some datasheets that I don't have access
954 if (sc->sis_rev == SIS_REV_630S ||
955 sc->sis_rev == SIS_REV_630E ||
956 sc->sis_rev == SIS_REV_630EA1)
957 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
959 else if (sc->sis_rev == SIS_REV_635 ||
960 sc->sis_rev == SIS_REV_630ET)
961 sis_read_mac(sc, dev, (caddr_t)&eaddr);
964 sis_read_eeprom(sc, (caddr_t)&eaddr,
965 SIS_EE_NODEADDR, 3, 0);
970 * A SiS chip was detected. Inform the world.
972 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":");
975 callout_handle_init(&sc->sis_stat_ch);
976 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
979 * Allocate the parent bus DMA tag appropriate for PCI.
981 #define SIS_NSEG_NEW 32
982 error = bus_dma_tag_create(NULL, /* parent */
983 1, 0, /* alignment, boundary */
984 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
985 BUS_SPACE_MAXADDR, /* highaddr */
986 NULL, NULL, /* filter, filterarg */
987 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
988 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
989 BUS_DMA_ALLOCNOW, /* flags */
990 &sc->sis_parent_tag);
993 * Now allocate a tag for the DMA descriptor lists.
994 * All of our lists are allocated as a contiguous block
997 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
998 1, 0, /* alignment, boundary */
999 BUS_SPACE_MAXADDR, /* lowaddr */
1000 BUS_SPACE_MAXADDR, /* highaddr */
1001 NULL, NULL, /* filter, filterarg */
1002 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */
1003 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1005 &sc->sis_ldata.sis_rx_tag);
1007 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1008 1, 0, /* alignment, boundary */
1009 BUS_SPACE_MAXADDR, /* lowaddr */
1010 BUS_SPACE_MAXADDR, /* highaddr */
1011 NULL, NULL, /* filter, filterarg */
1012 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */
1013 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1015 &sc->sis_ldata.sis_tx_tag);
1017 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1018 1, 0, /* alignment, boundary */
1019 BUS_SPACE_MAXADDR, /* lowaddr */
1020 BUS_SPACE_MAXADDR, /* highaddr */
1021 NULL, NULL, /* filter, filterarg */
1022 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */
1023 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1028 * Now allocate a chunk of DMA-able memory based on the
1029 * tag we just created.
1031 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
1032 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT,
1033 &sc->sis_ldata.sis_tx_dmamap);
1036 printf("sis%d: no memory for list buffers!\n", unit);
1037 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1038 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1039 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1040 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1041 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1046 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
1047 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT,
1048 &sc->sis_ldata.sis_rx_dmamap);
1051 printf("sis%d: no memory for list buffers!\n", unit);
1052 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1053 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1054 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1055 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1056 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap);
1057 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1058 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1064 bzero(sc->sis_ldata.sis_tx_list, SIS_TX_LIST_SZ);
1065 bzero(sc->sis_ldata.sis_rx_list, SIS_RX_LIST_SZ);
1068 * Obtain the physical addresses of the RX and TX
1069 * rings which we'll need later in the init routine.
1071 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1072 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]),
1073 sizeof(struct sis_desc), sis_dma_map_ring,
1074 &sc->sis_cdata.sis_tx_paddr, 0);
1075 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1076 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]),
1077 sizeof(struct sis_desc), sis_dma_map_ring,
1078 &sc->sis_cdata.sis_rx_paddr, 0);
1080 ifp = &sc->arpcom.ac_if;
1082 ifp->if_unit = unit;
1083 ifp->if_name = "sis";
1084 ifp->if_mtu = ETHERMTU;
1085 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1086 ifp->if_ioctl = sis_ioctl;
1087 ifp->if_output = ether_output;
1088 ifp->if_start = sis_start;
1089 ifp->if_watchdog = sis_watchdog;
1090 ifp->if_init = sis_init;
1091 ifp->if_baudrate = 10000000;
1092 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1;
1097 if (mii_phy_probe(dev, &sc->sis_miibus,
1098 sis_ifmedia_upd, sis_ifmedia_sts)) {
1099 printf("sis%d: MII without any PHY!\n", sc->sis_unit);
1100 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1101 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1102 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1103 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1104 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap);
1105 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1106 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap);
1107 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1108 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1114 * Call MI attach routine.
1116 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1119 * Tell the upper layer(s) we support long frames.
1121 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1123 callout_handle_init(&sc->sis_stat_ch);
1129 mtx_destroy(&sc->sis_mtx);
1133 static int sis_detach(dev)
1136 struct sis_softc *sc;
1140 sc = device_get_softc(dev);
1142 ifp = &sc->arpcom.ac_if;
1146 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1148 bus_generic_detach(dev);
1149 device_delete_child(dev, sc->sis_miibus);
1151 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1152 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1153 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1155 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
1156 sc->sis_ldata.sis_rx_dmamap);
1157 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
1158 sc->sis_ldata.sis_tx_dmamap);
1159 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1160 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap);
1161 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1162 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap);
1163 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1164 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1165 bus_dma_tag_destroy(sc->sis_parent_tag);
1168 mtx_destroy(&sc->sis_mtx);
1174 * Initialize the transmit descriptors.
1176 static int sis_list_tx_init(sc)
1177 struct sis_softc *sc;
1179 struct sis_list_data *ld;
1180 struct sis_ring_data *cd;
1183 cd = &sc->sis_cdata;
1184 ld = &sc->sis_ldata;
1186 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1187 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1188 ld->sis_tx_list[i].sis_nextdesc =
1189 &ld->sis_tx_list[nexti];
1190 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1191 sc->sis_ldata.sis_tx_dmamap,
1192 &ld->sis_tx_list[nexti], sizeof(struct sis_desc),
1193 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0);
1194 ld->sis_tx_list[i].sis_mbuf = NULL;
1195 ld->sis_tx_list[i].sis_ptr = 0;
1196 ld->sis_tx_list[i].sis_ctl = 0;
1199 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1201 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag,
1202 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE);
1208 * Initialize the RX descriptors and allocate mbufs for them. Note that
1209 * we arrange the descriptors in a closed ring, so that the last descriptor
1210 * points back to the first.
1212 static int sis_list_rx_init(sc)
1213 struct sis_softc *sc;
1215 struct sis_list_data *ld;
1216 struct sis_ring_data *cd;
1219 ld = &sc->sis_ldata;
1220 cd = &sc->sis_cdata;
1222 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1223 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1225 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1226 ld->sis_rx_list[i].sis_nextdesc =
1227 &ld->sis_rx_list[nexti];
1228 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1229 sc->sis_ldata.sis_rx_dmamap,
1230 &ld->sis_rx_list[nexti],
1231 sizeof(struct sis_desc), sis_dma_map_desc_next,
1232 &ld->sis_rx_list[i], 0);
1235 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag,
1236 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE);
1238 cd->sis_rx_prod = 0;
1244 * Initialize an RX descriptor and attach an MBUF cluster.
1246 static int sis_newbuf(sc, c, m)
1247 struct sis_softc *sc;
1251 struct mbuf *m_new = NULL;
1257 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1261 MCLGET(m_new, M_DONTWAIT);
1262 if (!(m_new->m_flags & M_EXT)) {
1266 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1269 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1270 m_new->m_data = m_new->m_ext.ext_buf;
1273 m_adj(m_new, sizeof(u_int64_t));
1275 c->sis_mbuf = m_new;
1276 c->sis_ctl = SIS_RXLEN;
1278 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1279 bus_dmamap_load(sc->sis_tag, c->sis_map,
1280 mtod(m_new, void *), m_new->m_len,
1281 sis_dma_map_desc_ptr, c, 0);
1282 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
1288 * A frame has been uploaded: pass the resulting mbuf chain up to
1289 * the higher level protocols.
1291 static void sis_rxeof(sc)
1292 struct sis_softc *sc;
1294 struct ether_header *eh;
1297 struct sis_desc *cur_rx;
1298 int i, total_len = 0;
1301 ifp = &sc->arpcom.ac_if;
1302 i = sc->sis_cdata.sis_rx_prod;
1304 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1306 #ifdef DEVICE_POLLING
1307 if (ifp->if_ipending & IFF_POLLING) {
1308 if (sc->rxcycles <= 0)
1312 #endif /* DEVICE_POLLING */
1313 cur_rx = &sc->sis_ldata.sis_rx_list[i];
1314 rxstat = cur_rx->sis_rxstat;
1315 bus_dmamap_sync(sc->sis_tag,
1316 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE);
1317 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1318 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1319 m = cur_rx->sis_mbuf;
1320 cur_rx->sis_mbuf = NULL;
1321 total_len = SIS_RXBYTES(cur_rx);
1322 SIS_INC(i, SIS_RX_LIST_CNT);
1325 * If an error occurs, update stats, clear the
1326 * status word and leave the mbuf cluster in place:
1327 * it should simply get re-used next time this descriptor
1328 * comes up in the ring.
1330 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1332 if (rxstat & SIS_RXSTAT_COLL)
1333 ifp->if_collisions++;
1334 sis_newbuf(sc, cur_rx, m);
1338 /* No errors; receive the packet. */
1341 * On the x86 we do not have alignment problems, so try to
1342 * allocate a new buffer for the receive ring, and pass up
1343 * the one where the packet is already, saving the expensive
1344 * copy done in m_devget().
1345 * If we are on an architecture with alignment problems, or
1346 * if the allocation fails, then use m_devget and leave the
1347 * existing buffer in the receive ring.
1349 if (sis_quick && sis_newbuf(sc, cur_rx, NULL) == 0) {
1350 m->m_pkthdr.rcvif = ifp;
1351 m->m_pkthdr.len = m->m_len = total_len;
1356 m0 = m_devget(mtod(m, char *), total_len,
1357 ETHER_ALIGN, ifp, NULL);
1358 sis_newbuf(sc, cur_rx, m);
1367 eh = mtod(m, struct ether_header *);
1369 /* Remove header from mbuf and pass it on. */
1370 m_adj(m, sizeof(struct ether_header));
1371 ether_input(ifp, eh, m);
1374 sc->sis_cdata.sis_rx_prod = i;
1380 struct sis_softc *sc;
1388 * A frame was downloaded to the chip. It's safe for us to clean up
1392 static void sis_txeof(sc)
1393 struct sis_softc *sc;
1395 struct sis_desc *cur_tx = NULL;
1399 ifp = &sc->arpcom.ac_if;
1401 /* Clear the timeout timer. */
1405 * Go through our tx list and free mbufs for those
1406 * frames that have been transmitted.
1408 idx = sc->sis_cdata.sis_tx_cons;
1409 while (idx != sc->sis_cdata.sis_tx_prod) {
1410 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1412 if (SIS_OWNDESC(cur_tx))
1415 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) {
1416 sc->sis_cdata.sis_tx_cnt--;
1417 SIS_INC(idx, SIS_TX_LIST_CNT);
1421 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1423 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1424 ifp->if_collisions++;
1425 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1426 ifp->if_collisions++;
1429 ifp->if_collisions +=
1430 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1433 if (cur_tx->sis_mbuf != NULL) {
1434 m_freem(cur_tx->sis_mbuf);
1435 cur_tx->sis_mbuf = NULL;
1436 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1437 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1440 sc->sis_cdata.sis_tx_cnt--;
1441 SIS_INC(idx, SIS_TX_LIST_CNT);
1445 sc->sis_cdata.sis_tx_cons = idx;
1448 ifp->if_flags &= ~IFF_OACTIVE;
1453 static void sis_tick(xsc)
1456 struct sis_softc *sc;
1457 struct mii_data *mii;
1462 ifp = &sc->arpcom.ac_if;
1464 mii = device_get_softc(sc->sis_miibus);
1467 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE &&
1468 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1470 if (ifp->if_snd.ifq_head != NULL)
1474 sc->sis_stat_ch = timeout(sis_tick, sc, hz);
1481 #ifdef DEVICE_POLLING
1482 static poll_handler_t sis_poll;
1485 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1487 struct sis_softc *sc = ifp->if_softc;
1490 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1491 CSR_WRITE_4(sc, SIS_IER, 1);
1496 * On the sis, reading the status register also clears it.
1497 * So before returning to intr mode we must make sure that all
1498 * possible pending sources of interrupts have been served.
1499 * In practice this means run to completion the *eof routines,
1500 * and then call the interrupt routine
1502 sc->rxcycles = count;
1505 if (ifp->if_snd.ifq_head != NULL)
1508 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1511 /* Reading the ISR register clears all interrupts. */
1512 status = CSR_READ_4(sc, SIS_ISR);
1514 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1517 if (status & (SIS_ISR_RX_IDLE))
1518 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1520 if (status & SIS_ISR_SYSERR) {
1529 #endif /* DEVICE_POLLING */
1531 static void sis_intr(arg)
1534 struct sis_softc *sc;
1539 ifp = &sc->arpcom.ac_if;
1542 #ifdef DEVICE_POLLING
1543 if (ifp->if_ipending & IFF_POLLING)
1545 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */
1546 CSR_WRITE_4(sc, SIS_IER, 0);
1549 #endif /* DEVICE_POLLING */
1551 /* Supress unwanted interrupts */
1552 if (!(ifp->if_flags & IFF_UP)) {
1557 /* Disable interrupts. */
1558 CSR_WRITE_4(sc, SIS_IER, 0);
1561 /* Reading the ISR register clears all interrupts. */
1562 status = CSR_READ_4(sc, SIS_ISR);
1564 if ((status & SIS_INTRS) == 0)
1568 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1569 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1572 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE))
1575 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1578 if (status & (SIS_ISR_RX_IDLE))
1579 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1581 if (status & SIS_ISR_SYSERR) {
1587 /* Re-enable interrupts. */
1588 CSR_WRITE_4(sc, SIS_IER, 1);
1590 if (ifp->if_snd.ifq_head != NULL)
1599 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1600 * pointers to the fragment pointers.
1602 static int sis_encap(sc, m_head, txidx)
1603 struct sis_softc *sc;
1604 struct mbuf *m_head;
1607 struct sis_desc *f = NULL;
1609 int frag, cur, cnt = 0;
1612 * Start packing the mbufs in this chain into
1613 * the fragment pointers. Stop when we run out
1614 * of fragments or hit the end of the mbuf chain.
1617 cur = frag = *txidx;
1619 for (m = m_head; m != NULL; m = m->m_next) {
1620 if (m->m_len != 0) {
1621 if ((SIS_TX_LIST_CNT -
1622 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1624 f = &sc->sis_ldata.sis_tx_list[frag];
1625 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1626 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1627 bus_dmamap_load(sc->sis_tag, f->sis_map,
1628 mtod(m, void *), m->m_len,
1629 sis_dma_map_desc_ptr, f, 0);
1630 bus_dmamap_sync(sc->sis_tag,
1631 f->sis_map, BUS_DMASYNC_PREREAD);
1633 f->sis_ctl |= SIS_CMDSTS_OWN;
1635 SIS_INC(frag, SIS_TX_LIST_CNT);
1643 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head;
1644 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1645 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1646 sc->sis_cdata.sis_tx_cnt += cnt;
1653 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1654 * to the mbuf data regions directly in the transmit lists. We also save a
1655 * copy of the pointers since the transmit list fragment pointers are
1656 * physical addresses.
1659 static void sis_start(ifp)
1662 struct sis_softc *sc;
1663 struct mbuf *m_head = NULL;
1669 if (!sc->sis_link) {
1674 idx = sc->sis_cdata.sis_tx_prod;
1676 if (ifp->if_flags & IFF_OACTIVE) {
1681 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
1682 IF_DEQUEUE(&ifp->if_snd, m_head);
1686 if (sis_encap(sc, m_head, &idx)) {
1687 IF_PREPEND(&ifp->if_snd, m_head);
1688 ifp->if_flags |= IFF_OACTIVE;
1693 * If there's a BPF listener, bounce a copy of this frame
1697 bpf_mtap(ifp, m_head);
1702 sc->sis_cdata.sis_tx_prod = idx;
1703 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1706 * Set a timeout in case the chip goes out to lunch.
1715 static void sis_init(xsc)
1718 struct sis_softc *sc = xsc;
1719 struct ifnet *ifp = &sc->arpcom.ac_if;
1720 struct mii_data *mii;
1725 * Cancel pending I/O and free all RX/TX buffers.
1729 mii = device_get_softc(sc->sis_miibus);
1731 /* Set MAC address */
1732 if (sc->sis_type == SIS_TYPE_83815) {
1733 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1734 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1735 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1736 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1737 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1738 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1739 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1740 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1741 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1743 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1744 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1745 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1746 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1747 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1748 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1749 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1750 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1751 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1754 /* Init circular RX list. */
1755 if (sis_list_rx_init(sc) == ENOBUFS) {
1756 printf("sis%d: initialization failed: no "
1757 "memory for rx buffers\n", sc->sis_unit);
1764 * Init tx descriptors.
1766 sis_list_tx_init(sc);
1769 * For the NatSemi chip, we have to explicitly enable the
1770 * reception of ARP frames, as well as turn on the 'perfect
1771 * match' filter where we store the station address, otherwise
1772 * we won't receive unicasts meant for this host.
1774 if (sc->sis_type == SIS_TYPE_83815) {
1775 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1776 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1779 /* If we want promiscuous mode, set the allframes bit. */
1780 if (ifp->if_flags & IFF_PROMISC) {
1781 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1783 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1787 * Set the capture broadcast bit to capture broadcast frames.
1789 if (ifp->if_flags & IFF_BROADCAST) {
1790 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1792 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1796 * Load the multicast filter.
1798 if (sc->sis_type == SIS_TYPE_83815)
1799 sis_setmulti_ns(sc);
1801 sis_setmulti_sis(sc);
1803 /* Turn the receive filter on */
1804 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1807 * Load the address of the RX and TX lists.
1809 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
1810 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
1812 /* Set RX configuration */
1813 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG);
1815 /* Accept Long Packets for VLAN support */
1816 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1818 /* Set TX configuration */
1819 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
1820 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1822 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1825 /* Set full/half duplex mode. */
1826 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1827 SIS_SETBIT(sc, SIS_TX_CFG,
1828 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1829 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1831 SIS_CLRBIT(sc, SIS_TX_CFG,
1832 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1833 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1837 * Enable interrupts.
1839 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1840 #ifdef DEVICE_POLLING
1842 * ... only enable interrupts if we are not polling, make sure
1843 * they are off otherwise.
1845 if (ifp->if_ipending & IFF_POLLING)
1846 CSR_WRITE_4(sc, SIS_IER, 0);
1848 #endif /* DEVICE_POLLING */
1849 CSR_WRITE_4(sc, SIS_IER, 1);
1851 /* Enable receiver and transmitter. */
1852 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
1853 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1860 * Page 75 of the DP83815 manual recommends the
1861 * following register settings "for optimum
1862 * performance." Note however that at least three
1863 * of the registers are listed as "reserved" in
1864 * the register map, so who knows what they do.
1866 if (sc->sis_type == SIS_TYPE_83815) {
1867 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1868 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1869 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1870 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1871 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1874 ifp->if_flags |= IFF_RUNNING;
1875 ifp->if_flags &= ~IFF_OACTIVE;
1877 sc->sis_stat_ch = timeout(sis_tick, sc, hz);
1885 * Set media options.
1887 static int sis_ifmedia_upd(ifp)
1890 struct sis_softc *sc;
1891 struct mii_data *mii;
1895 mii = device_get_softc(sc->sis_miibus);
1897 if (mii->mii_instance) {
1898 struct mii_softc *miisc;
1899 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1900 mii_phy_reset(miisc);
1908 * Report current media status.
1910 static void sis_ifmedia_sts(ifp, ifmr)
1912 struct ifmediareq *ifmr;
1914 struct sis_softc *sc;
1915 struct mii_data *mii;
1919 mii = device_get_softc(sc->sis_miibus);
1921 ifmr->ifm_active = mii->mii_media_active;
1922 ifmr->ifm_status = mii->mii_media_status;
1927 static int sis_ioctl(ifp, command, data)
1932 struct sis_softc *sc = ifp->if_softc;
1933 struct ifreq *ifr = (struct ifreq *) data;
1934 struct mii_data *mii;
1941 error = ether_ioctl(ifp, command, data);
1944 if (ifp->if_flags & IFF_UP) {
1947 if (ifp->if_flags & IFF_RUNNING)
1955 if (sc->sis_type == SIS_TYPE_83815)
1956 sis_setmulti_ns(sc);
1958 sis_setmulti_sis(sc);
1964 mii = device_get_softc(sc->sis_miibus);
1966 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1977 static void sis_watchdog(ifp)
1980 struct sis_softc *sc;
1987 printf("sis%d: watchdog timeout\n", sc->sis_unit);
1993 if (ifp->if_snd.ifq_head != NULL)
2002 * Stop the adapter and free any mbufs allocated to the
2005 static void sis_stop(sc)
2006 struct sis_softc *sc;
2012 ifp = &sc->arpcom.ac_if;
2015 untimeout(sis_tick, sc, sc->sis_stat_ch);
2017 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2018 #ifdef DEVICE_POLLING
2019 ether_poll_deregister(ifp);
2021 CSR_WRITE_4(sc, SIS_IER, 0);
2022 CSR_WRITE_4(sc, SIS_IMR, 0);
2023 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2025 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2026 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2031 * Free data in the RX lists.
2033 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2034 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
2035 bus_dmamap_unload(sc->sis_tag,
2036 sc->sis_ldata.sis_rx_list[i].sis_map);
2037 bus_dmamap_destroy(sc->sis_tag,
2038 sc->sis_ldata.sis_rx_list[i].sis_map);
2039 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
2040 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
2043 bzero(sc->sis_ldata.sis_rx_list,
2044 sizeof(sc->sis_ldata.sis_rx_list));
2047 * Free the TX list buffers.
2049 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2050 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
2051 bus_dmamap_unload(sc->sis_tag,
2052 sc->sis_ldata.sis_tx_list[i].sis_map);
2053 bus_dmamap_destroy(sc->sis_tag,
2054 sc->sis_ldata.sis_tx_list[i].sis_map);
2055 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
2056 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
2060 bzero(sc->sis_ldata.sis_tx_list,
2061 sizeof(sc->sis_ldata.sis_tx_list));
2069 * Stop all chip I/O so that the kernel's probe routines don't
2070 * get confused by errant DMAs when rebooting.
2072 static void sis_shutdown(dev)
2075 struct sis_softc *sc;
2077 sc = device_get_softc(dev);