2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
35 * available from http://www.sis.com.tw.
37 * This driver also supports the NatSemi DP83815. Datasheets are
38 * available from http://www.national.com.
40 * Written by Bill Paul <wpaul@ee.columbia.edu>
41 * Electrical Engineering Department
42 * Columbia University, New York City
46 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
47 * simple TX and RX descriptors of 3 longwords in size. The receiver
48 * has a single perfect filter entry for the station address and a
49 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
50 * transceiver while the 7016 requires an external transceiver chip.
51 * Both chips offer the standard bit-bang MII interface as well as
52 * an enchanced PHY interface which simplifies accessing MII registers.
54 * The only downside to this chipset is that RX descriptors must be
58 #include <sys/cdefs.h>
59 __FBSDID("$FreeBSD$");
61 #include <sys/param.h>
62 #include <sys/systm.h>
63 #include <sys/sockio.h>
65 #include <sys/malloc.h>
66 #include <sys/kernel.h>
67 #include <sys/socket.h>
68 #include <sys/sysctl.h>
71 #include <net/if_arp.h>
72 #include <net/ethernet.h>
73 #include <net/if_dl.h>
74 #include <net/if_media.h>
75 #include <net/if_types.h>
76 #include <net/if_vlan_var.h>
80 #include <machine/bus_pio.h>
81 #include <machine/bus_memio.h>
82 #include <machine/bus.h>
83 #include <machine/resource.h>
87 #include <dev/mii/mii.h>
88 #include <dev/mii/miivar.h>
90 #include <dev/pci/pcireg.h>
91 #include <dev/pci/pcivar.h>
93 #define SIS_USEIOSPACE
95 #include <pci/if_sisreg.h>
97 MODULE_DEPEND(sis, pci, 1, 1, 1);
98 MODULE_DEPEND(sis, ether, 1, 1, 1);
99 MODULE_DEPEND(sis, miibus, 1, 1, 1);
101 /* "controller miibus0" required. See GENERIC if you get errors here. */
102 #include "miibus_if.h"
105 * Various supported device vendors/types and their names.
107 static struct sis_type sis_devs[] = {
108 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
109 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
110 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
114 static int sis_probe (device_t);
115 static int sis_attach (device_t);
116 static int sis_detach (device_t);
118 static int sis_newbuf (struct sis_softc *,
119 struct sis_desc *, struct mbuf *);
120 static int sis_encap (struct sis_softc *,
121 struct mbuf **, u_int32_t *);
122 static void sis_rxeof (struct sis_softc *);
123 static void sis_rxeoc (struct sis_softc *);
124 static void sis_txeof (struct sis_softc *);
125 static void sis_intr (void *);
126 static void sis_tick (void *);
127 static void sis_start (struct ifnet *);
128 static int sis_ioctl (struct ifnet *, u_long, caddr_t);
129 static void sis_init (void *);
130 static void sis_stop (struct sis_softc *);
131 static void sis_watchdog (struct ifnet *);
132 static void sis_shutdown (device_t);
133 static int sis_ifmedia_upd (struct ifnet *);
134 static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *);
136 static u_int16_t sis_reverse (u_int16_t);
137 static void sis_delay (struct sis_softc *);
138 static void sis_eeprom_idle (struct sis_softc *);
139 static void sis_eeprom_putbyte (struct sis_softc *, int);
140 static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *);
141 static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int);
143 static void sis_read_cmos (struct sis_softc *, device_t, caddr_t,
145 static void sis_read_mac (struct sis_softc *, device_t, caddr_t);
146 static device_t sis_find_bridge (device_t);
149 static void sis_mii_sync (struct sis_softc *);
150 static void sis_mii_send (struct sis_softc *, u_int32_t, int);
151 static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *);
152 static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *);
153 static int sis_miibus_readreg (device_t, int, int);
154 static int sis_miibus_writereg (device_t, int, int, int);
155 static void sis_miibus_statchg (device_t);
157 static void sis_setmulti_sis (struct sis_softc *);
158 static void sis_setmulti_ns (struct sis_softc *);
159 static u_int32_t sis_crc (struct sis_softc *, caddr_t);
160 static void sis_reset (struct sis_softc *);
161 static int sis_list_rx_init (struct sis_softc *);
162 static int sis_list_tx_init (struct sis_softc *);
164 static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int);
165 static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int);
166 static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int);
167 #ifdef SIS_USEIOSPACE
168 #define SIS_RES SYS_RES_IOPORT
169 #define SIS_RID SIS_PCI_LOIO
171 #define SIS_RES SYS_RES_MEMORY
172 #define SIS_RID SIS_PCI_LOMEM
175 static device_method_t sis_methods[] = {
176 /* Device interface */
177 DEVMETHOD(device_probe, sis_probe),
178 DEVMETHOD(device_attach, sis_attach),
179 DEVMETHOD(device_detach, sis_detach),
180 DEVMETHOD(device_shutdown, sis_shutdown),
183 DEVMETHOD(bus_print_child, bus_generic_print_child),
184 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
187 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
188 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
189 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
194 static driver_t sis_driver = {
197 sizeof(struct sis_softc)
200 static devclass_t sis_devclass;
202 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
203 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
205 #define SIS_SETBIT(sc, reg, x) \
206 CSR_WRITE_4(sc, reg, \
207 CSR_READ_4(sc, reg) | (x))
209 #define SIS_CLRBIT(sc, reg, x) \
210 CSR_WRITE_4(sc, reg, \
211 CSR_READ_4(sc, reg) & ~(x))
214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
217 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
220 sis_dma_map_desc_next(arg, segs, nseg, error)
222 bus_dma_segment_t *segs;
228 r->sis_next = segs->ds_addr;
234 sis_dma_map_desc_ptr(arg, segs, nseg, error)
236 bus_dma_segment_t *segs;
242 r->sis_ptr = segs->ds_addr;
248 sis_dma_map_ring(arg, segs, nseg, error)
250 bus_dma_segment_t *segs;
262 * Routine to reverse the bits in a word. Stolen almost
263 * verbatim from /usr/games/fortune.
269 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
270 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
271 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
272 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
279 struct sis_softc *sc;
283 for (idx = (300 / 33) + 1; idx > 0; idx--)
284 CSR_READ_4(sc, SIS_CSR);
291 struct sis_softc *sc;
295 SIO_SET(SIS_EECTL_CSEL);
297 SIO_SET(SIS_EECTL_CLK);
300 for (i = 0; i < 25; i++) {
301 SIO_CLR(SIS_EECTL_CLK);
303 SIO_SET(SIS_EECTL_CLK);
307 SIO_CLR(SIS_EECTL_CLK);
309 SIO_CLR(SIS_EECTL_CSEL);
311 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
317 * Send a read command and address to the EEPROM, check for ACK.
320 sis_eeprom_putbyte(sc, addr)
321 struct sis_softc *sc;
326 d = addr | SIS_EECMD_READ;
329 * Feed in each bit and stobe the clock.
331 for (i = 0x400; i; i >>= 1) {
333 SIO_SET(SIS_EECTL_DIN);
335 SIO_CLR(SIS_EECTL_DIN);
338 SIO_SET(SIS_EECTL_CLK);
340 SIO_CLR(SIS_EECTL_CLK);
348 * Read a word of data stored in the EEPROM at address 'addr.'
351 sis_eeprom_getword(sc, addr, dest)
352 struct sis_softc *sc;
359 /* Force EEPROM to idle state. */
362 /* Enter EEPROM access mode. */
364 SIO_CLR(SIS_EECTL_CLK);
366 SIO_SET(SIS_EECTL_CSEL);
370 * Send address of word we want to read.
372 sis_eeprom_putbyte(sc, addr);
375 * Start reading bits from EEPROM.
377 for (i = 0x8000; i; i >>= 1) {
378 SIO_SET(SIS_EECTL_CLK);
380 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
383 SIO_CLR(SIS_EECTL_CLK);
387 /* Turn off EEPROM access mode. */
396 * Read a sequence of words from the EEPROM.
399 sis_read_eeprom(sc, dest, off, cnt, swap)
400 struct sis_softc *sc;
407 u_int16_t word = 0, *ptr;
409 for (i = 0; i < cnt; i++) {
410 sis_eeprom_getword(sc, off + i, &word);
411 ptr = (u_int16_t *)(dest + (i * 2));
426 devclass_t pci_devclass;
427 device_t *pci_devices;
429 device_t *pci_children;
430 int pci_childcount = 0;
431 device_t *busp, *childp;
432 device_t child = NULL;
435 if ((pci_devclass = devclass_find("pci")) == NULL)
438 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
440 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
442 device_get_children(*busp, &pci_children, &pci_childcount);
443 for (j = 0, childp = pci_children;
444 j < pci_childcount; j++, childp++) {
445 if (pci_get_vendor(*childp) == SIS_VENDORID &&
446 pci_get_device(*childp) == 0x0008) {
454 free(pci_devices, M_TEMP);
455 free(pci_children, M_TEMP);
460 sis_read_cmos(sc, dev, dest, off, cnt)
461 struct sis_softc *sc;
470 bus_space_tag_t btag;
472 bridge = sis_find_bridge(dev);
475 reg = pci_read_config(bridge, 0x48, 1);
476 pci_write_config(bridge, 0x48, reg|0x40, 1);
479 btag = I386_BUS_SPACE_IO;
481 for (i = 0; i < cnt; i++) {
482 bus_space_write_1(btag, 0x0, 0x70, i + off);
483 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
486 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
491 sis_read_mac(sc, dev, dest)
492 struct sis_softc *sc;
496 u_int32_t filtsave, csrsave;
498 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
499 csrsave = CSR_READ_4(sc, SIS_CSR);
501 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
502 CSR_WRITE_4(sc, SIS_CSR, 0);
504 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
506 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
507 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
508 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
509 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
510 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
511 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
513 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
514 CSR_WRITE_4(sc, SIS_CSR, csrsave);
520 * Sync the PHYs by setting data bit and strobing the clock 32 times.
522 static void sis_mii_sync(sc)
523 struct sis_softc *sc;
527 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
529 for (i = 0; i < 32; i++) {
530 SIO_SET(SIS_MII_CLK);
532 SIO_CLR(SIS_MII_CLK);
540 * Clock a series of bits through the MII.
542 static void sis_mii_send(sc, bits, cnt)
543 struct sis_softc *sc;
549 SIO_CLR(SIS_MII_CLK);
551 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
553 SIO_SET(SIS_MII_DATA);
555 SIO_CLR(SIS_MII_DATA);
558 SIO_CLR(SIS_MII_CLK);
560 SIO_SET(SIS_MII_CLK);
565 * Read an PHY register through the MII.
567 static int sis_mii_readreg(sc, frame)
568 struct sis_softc *sc;
569 struct sis_mii_frame *frame;
577 * Set up frame for RX.
579 frame->mii_stdelim = SIS_MII_STARTDELIM;
580 frame->mii_opcode = SIS_MII_READOP;
581 frame->mii_turnaround = 0;
587 SIO_SET(SIS_MII_DIR);
592 * Send command/address info.
594 sis_mii_send(sc, frame->mii_stdelim, 2);
595 sis_mii_send(sc, frame->mii_opcode, 2);
596 sis_mii_send(sc, frame->mii_phyaddr, 5);
597 sis_mii_send(sc, frame->mii_regaddr, 5);
600 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
602 SIO_SET(SIS_MII_CLK);
606 SIO_CLR(SIS_MII_DIR);
609 SIO_CLR(SIS_MII_CLK);
611 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
612 SIO_SET(SIS_MII_CLK);
616 * Now try reading data bits. If the ack failed, we still
617 * need to clock through 16 cycles to keep the PHY(s) in sync.
620 for(i = 0; i < 16; i++) {
621 SIO_CLR(SIS_MII_CLK);
623 SIO_SET(SIS_MII_CLK);
629 for (i = 0x8000; i; i >>= 1) {
630 SIO_CLR(SIS_MII_CLK);
633 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
634 frame->mii_data |= i;
637 SIO_SET(SIS_MII_CLK);
643 SIO_CLR(SIS_MII_CLK);
645 SIO_SET(SIS_MII_CLK);
656 * Write to a PHY register through the MII.
658 static int sis_mii_writereg(sc, frame)
659 struct sis_softc *sc;
660 struct sis_mii_frame *frame;
667 * Set up frame for TX.
670 frame->mii_stdelim = SIS_MII_STARTDELIM;
671 frame->mii_opcode = SIS_MII_WRITEOP;
672 frame->mii_turnaround = SIS_MII_TURNAROUND;
675 * Turn on data output.
677 SIO_SET(SIS_MII_DIR);
681 sis_mii_send(sc, frame->mii_stdelim, 2);
682 sis_mii_send(sc, frame->mii_opcode, 2);
683 sis_mii_send(sc, frame->mii_phyaddr, 5);
684 sis_mii_send(sc, frame->mii_regaddr, 5);
685 sis_mii_send(sc, frame->mii_turnaround, 2);
686 sis_mii_send(sc, frame->mii_data, 16);
689 SIO_SET(SIS_MII_CLK);
691 SIO_CLR(SIS_MII_CLK);
697 SIO_CLR(SIS_MII_DIR);
705 sis_miibus_readreg(dev, phy, reg)
709 struct sis_softc *sc;
710 struct sis_mii_frame frame;
712 sc = device_get_softc(dev);
714 if (sc->sis_type == SIS_TYPE_83815) {
718 * The NatSemi chip can take a while after
719 * a reset to come ready, during which the BMSR
720 * returns a value of 0. This is *never* supposed
721 * to happen: some of the BMSR bits are meant to
722 * be hardwired in the on position, and this can
723 * confuse the miibus code a bit during the probe
724 * and attach phase. So we make an effort to check
725 * for this condition and wait for it to clear.
727 if (!CSR_READ_4(sc, NS_BMSR))
729 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
733 * Chipsets < SIS_635 seem not to be able to read/write
734 * through mdio. Use the enhanced PHY access register
737 if (sc->sis_type == SIS_TYPE_900 &&
738 sc->sis_rev < SIS_REV_635) {
744 CSR_WRITE_4(sc, SIS_PHYCTL,
745 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
746 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
748 for (i = 0; i < SIS_TIMEOUT; i++) {
749 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
753 if (i == SIS_TIMEOUT) {
754 printf("sis%d: PHY failed to come ready\n",
759 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
766 bzero((char *)&frame, sizeof(frame));
768 frame.mii_phyaddr = phy;
769 frame.mii_regaddr = reg;
770 sis_mii_readreg(sc, &frame);
772 return(frame.mii_data);
777 sis_miibus_writereg(dev, phy, reg, data)
781 struct sis_softc *sc;
782 struct sis_mii_frame frame;
784 sc = device_get_softc(dev);
786 if (sc->sis_type == SIS_TYPE_83815) {
789 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
794 * Chipsets < SIS_635 seem not to be able to read/write
795 * through mdio. Use the enhanced PHY access register
798 if (sc->sis_type == SIS_TYPE_900 &&
799 sc->sis_rev < SIS_REV_635) {
805 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
806 (reg << 6) | SIS_PHYOP_WRITE);
807 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
809 for (i = 0; i < SIS_TIMEOUT; i++) {
810 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
814 if (i == SIS_TIMEOUT)
815 printf("sis%d: PHY failed to come ready\n",
818 bzero((char *)&frame, sizeof(frame));
820 frame.mii_phyaddr = phy;
821 frame.mii_regaddr = reg;
822 frame.mii_data = data;
823 sis_mii_writereg(sc, &frame);
829 sis_miibus_statchg(dev)
832 struct sis_softc *sc;
834 sc = device_get_softc(dev);
842 struct sis_softc *sc;
845 u_int32_t crc, carry;
849 /* Compute CRC for the address value. */
850 crc = 0xFFFFFFFF; /* initial value */
852 for (i = 0; i < 6; i++) {
854 for (j = 0; j < 8; j++) {
855 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
859 crc = (crc ^ 0x04c11db6) | carry;
864 * return the filter bit position
866 * The NatSemi chip has a 512-bit filter, which is
867 * different than the SiS, so we special-case it.
869 if (sc->sis_type == SIS_TYPE_83815)
871 else if (sc->sis_rev >= SIS_REV_635 ||
872 sc->sis_rev == SIS_REV_900B)
880 struct sis_softc *sc;
883 struct ifmultiaddr *ifma;
884 u_int32_t h = 0, i, filtsave;
887 ifp = &sc->arpcom.ac_if;
889 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
890 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
891 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
896 * We have to explicitly enable the multicast hash table
897 * on the NatSemi chip if we want to use it, which we do.
899 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
900 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
902 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
904 /* first, zot all the existing hash bits */
905 for (i = 0; i < 32; i++) {
906 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
907 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
910 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
911 if (ifma->ifma_addr->sa_family != AF_LINK)
913 h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
916 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
919 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
922 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
929 struct sis_softc *sc;
932 struct ifmultiaddr *ifma;
933 u_int32_t h, i, n, ctl;
934 u_int16_t hashes[16];
936 ifp = &sc->arpcom.ac_if;
938 /* hash table size */
939 if (sc->sis_rev >= SIS_REV_635 ||
940 sc->sis_rev == SIS_REV_900B)
945 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
947 if (ifp->if_flags & IFF_BROADCAST)
948 ctl |= SIS_RXFILTCTL_BROAD;
950 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
951 ctl |= SIS_RXFILTCTL_ALLMULTI;
952 if (ifp->if_flags & IFF_PROMISC)
953 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
954 for (i = 0; i < n; i++)
957 for (i = 0; i < n; i++)
960 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
961 if (ifma->ifma_addr->sa_family != AF_LINK)
964 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
965 hashes[h >> 4] |= 1 << (h & 0xf);
969 ctl |= SIS_RXFILTCTL_ALLMULTI;
970 for (i = 0; i < n; i++)
975 for (i = 0; i < n; i++) {
976 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
977 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
980 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
985 struct sis_softc *sc;
989 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
991 for (i = 0; i < SIS_TIMEOUT; i++) {
992 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
996 if (i == SIS_TIMEOUT)
997 printf("sis%d: reset never completed\n", sc->sis_unit);
999 /* Wait a little while for the chip to get its brains in order. */
1003 * If this is a NetSemi chip, make sure to clear
1006 if (sc->sis_type == SIS_TYPE_83815) {
1007 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
1008 CSR_WRITE_4(sc, NS_CLKRUN, 0);
1015 * Probe for an SiS chip. Check the PCI vendor and device
1016 * IDs against our list and return a device name if we find a match.
1026 while(t->sis_name != NULL) {
1027 if ((pci_get_vendor(dev) == t->sis_vid) &&
1028 (pci_get_device(dev) == t->sis_did)) {
1029 device_set_desc(dev, t->sis_name);
1039 * Attach the interface. Allocate softc structures, do ifmedia
1040 * setup and ethernet/BPF attach.
1046 u_char eaddr[ETHER_ADDR_LEN];
1047 struct sis_softc *sc;
1049 int unit, error = 0, rid, waittime = 0;
1052 sc = device_get_softc(dev);
1053 unit = device_get_unit(dev);
1057 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1058 MTX_DEF | MTX_RECURSE);
1060 if (pci_get_device(dev) == SIS_DEVICEID_900)
1061 sc->sis_type = SIS_TYPE_900;
1062 if (pci_get_device(dev) == SIS_DEVICEID_7016)
1063 sc->sis_type = SIS_TYPE_7016;
1064 if (pci_get_vendor(dev) == NS_VENDORID)
1065 sc->sis_type = SIS_TYPE_83815;
1067 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
1068 #ifndef BURN_BRIDGES
1070 * Handle power management nonsense.
1072 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1073 u_int32_t iobase, membase, irq;
1075 /* Save important PCI config data. */
1076 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
1077 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
1078 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
1080 /* Reset the power state. */
1081 printf("sis%d: chip is in D%d power mode "
1082 "-- setting to D0\n", unit,
1083 pci_get_powerstate(dev));
1084 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1086 /* Restore PCI config data. */
1087 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
1088 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
1089 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
1093 * Map control/status registers.
1095 pci_enable_busmaster(dev);
1098 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid,
1099 0, ~0, 1, RF_ACTIVE);
1101 if (sc->sis_res == NULL) {
1102 printf("sis%d: couldn't map ports/memory\n", unit);
1107 sc->sis_btag = rman_get_bustag(sc->sis_res);
1108 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1110 /* Allocate interrupt */
1112 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1113 RF_SHAREABLE | RF_ACTIVE);
1115 if (sc->sis_irq == NULL) {
1116 printf("sis%d: couldn't map interrupt\n", unit);
1121 /* Reset the adapter. */
1124 if (sc->sis_type == SIS_TYPE_900 &&
1125 (sc->sis_rev == SIS_REV_635 ||
1126 sc->sis_rev == SIS_REV_900B)) {
1127 SIO_SET(SIS_CFG_RND_CNT);
1128 SIO_SET(SIS_CFG_PERR_DETECT);
1132 * Get station address from the EEPROM.
1134 switch (pci_get_vendor(dev)) {
1136 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
1138 /* We can't update the device description, so spew */
1139 if (sc->sis_srr == NS_SRR_15C)
1140 device_printf(dev, "Silicon Revision: DP83815C\n");
1141 else if (sc->sis_srr == NS_SRR_15D)
1142 device_printf(dev, "Silicon Revision: DP83815D\n");
1143 else if (sc->sis_srr == NS_SRR_16A)
1144 device_printf(dev, "Silicon Revision: DP83816A\n");
1146 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
1149 * Reading the MAC address out of the EEPROM on
1150 * the NatSemi chip takes a bit more work than
1151 * you'd expect. The address spans 4 16-bit words,
1152 * with the first word containing only a single bit.
1153 * You have to shift everything over one bit to
1154 * get it aligned properly. Also, the bits are
1155 * stored backwards (the LSB is really the MSB,
1156 * and so on) so you have to reverse them in order
1157 * to get the MAC address into the form we want.
1158 * Why? Who the hell knows.
1163 sis_read_eeprom(sc, (caddr_t)&tmp,
1164 NS_EE_NODEADDR, 4, 0);
1166 /* Shift everything over one bit. */
1167 tmp[3] = tmp[3] >> 1;
1168 tmp[3] |= tmp[2] << 15;
1169 tmp[2] = tmp[2] >> 1;
1170 tmp[2] |= tmp[1] << 15;
1171 tmp[1] = tmp[1] >> 1;
1172 tmp[1] |= tmp[0] << 15;
1174 /* Now reverse all the bits. */
1175 tmp[3] = sis_reverse(tmp[3]);
1176 tmp[2] = sis_reverse(tmp[2]);
1177 tmp[1] = sis_reverse(tmp[1]);
1179 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1186 * If this is a SiS 630E chipset with an embedded
1187 * SiS 900 controller, we have to read the MAC address
1188 * from the APC CMOS RAM. Our method for doing this
1189 * is very ugly since we have to reach out and grab
1190 * ahold of hardware for which we cannot properly
1191 * allocate resources. This code is only compiled on
1192 * the i386 architecture since the SiS 630E chipset
1193 * is for x86 motherboards only. Note that there are
1194 * a lot of magic numbers in this hack. These are
1195 * taken from SiS's Linux driver. I'd like to replace
1196 * them with proper symbolic definitions, but that
1197 * requires some datasheets that I don't have access
1200 if (sc->sis_rev == SIS_REV_630S ||
1201 sc->sis_rev == SIS_REV_630E ||
1202 sc->sis_rev == SIS_REV_630EA1)
1203 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1205 else if (sc->sis_rev == SIS_REV_635 ||
1206 sc->sis_rev == SIS_REV_630ET)
1207 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1208 else if (sc->sis_rev == SIS_REV_96x) {
1209 /* Allow to read EEPROM from LAN. It is shared
1210 * between a 1394 controller and the NIC and each
1211 * time we access it, we need to set SIS_EECMD_REQ.
1213 SIO_SET(SIS_EECMD_REQ);
1214 for (waittime = 0; waittime < SIS_TIMEOUT;
1216 /* Force EEPROM to idle state. */
1217 sis_eeprom_idle(sc);
1218 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1219 sis_read_eeprom(sc, (caddr_t)&eaddr,
1220 SIS_EE_NODEADDR, 3, 0);
1226 * Set SIS_EECTL_CLK to high, so a other master
1227 * can operate on the i2c bus.
1229 SIO_SET(SIS_EECTL_CLK);
1230 /* Refuse EEPROM access by LAN */
1231 SIO_SET(SIS_EECMD_DONE);
1234 sis_read_eeprom(sc, (caddr_t)&eaddr,
1235 SIS_EE_NODEADDR, 3, 0);
1240 * A SiS chip was detected. Inform the world.
1242 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":");
1244 sc->sis_unit = unit;
1245 callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE);
1246 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1249 * Allocate the parent bus DMA tag appropriate for PCI.
1251 #define SIS_NSEG_NEW 32
1252 error = bus_dma_tag_create(NULL, /* parent */
1253 1, 0, /* alignment, boundary */
1254 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1255 BUS_SPACE_MAXADDR, /* highaddr */
1256 NULL, NULL, /* filter, filterarg */
1257 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1258 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1259 BUS_DMA_ALLOCNOW, /* flags */
1260 NULL, NULL, /* lockfunc, lockarg */
1261 &sc->sis_parent_tag);
1266 * Now allocate a tag for the DMA descriptor lists and a chunk
1267 * of DMA-able memory based on the tag. Also obtain the physical
1268 * addresses of the RX and TX ring, which we'll need later.
1269 * All of our lists are allocated as a contiguous block
1272 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1273 1, 0, /* alignment, boundary */
1274 BUS_SPACE_MAXADDR, /* lowaddr */
1275 BUS_SPACE_MAXADDR, /* highaddr */
1276 NULL, NULL, /* filter, filterarg */
1277 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */
1278 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1280 busdma_lock_mutex, /* lockfunc */
1281 &Giant, /* lockarg */
1282 &sc->sis_ldata.sis_rx_tag);
1286 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
1287 (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1288 &sc->sis_ldata.sis_rx_dmamap);
1291 printf("sis%d: no memory for rx list buffers!\n", unit);
1292 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1293 sc->sis_ldata.sis_rx_tag = NULL;
1297 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1298 sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]),
1299 sizeof(struct sis_desc), sis_dma_map_ring,
1300 &sc->sis_cdata.sis_rx_paddr, 0);
1303 printf("sis%d: cannot get address of the rx ring!\n", unit);
1304 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1305 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap);
1306 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1307 sc->sis_ldata.sis_rx_tag = NULL;
1311 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1312 1, 0, /* alignment, boundary */
1313 BUS_SPACE_MAXADDR, /* lowaddr */
1314 BUS_SPACE_MAXADDR, /* highaddr */
1315 NULL, NULL, /* filter, filterarg */
1316 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */
1317 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1319 busdma_lock_mutex, /* lockfunc */
1320 &Giant, /* lockarg */
1321 &sc->sis_ldata.sis_tx_tag);
1325 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
1326 (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1327 &sc->sis_ldata.sis_tx_dmamap);
1330 printf("sis%d: no memory for tx list buffers!\n", unit);
1331 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1332 sc->sis_ldata.sis_tx_tag = NULL;
1336 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1337 sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]),
1338 sizeof(struct sis_desc), sis_dma_map_ring,
1339 &sc->sis_cdata.sis_tx_paddr, 0);
1342 printf("sis%d: cannot get address of the tx ring!\n", unit);
1343 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1344 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap);
1345 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1346 sc->sis_ldata.sis_tx_tag = NULL;
1350 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1351 1, 0, /* alignment, boundary */
1352 BUS_SPACE_MAXADDR, /* lowaddr */
1353 BUS_SPACE_MAXADDR, /* highaddr */
1354 NULL, NULL, /* filter, filterarg */
1355 MCLBYTES, 1, /* maxsize,nsegments */
1356 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1358 busdma_lock_mutex, /* lockfunc */
1359 &Giant, /* lockarg */
1365 * Obtain the physical addresses of the RX and TX
1366 * rings which we'll need later in the init routine.
1369 ifp = &sc->arpcom.ac_if;
1371 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1372 ifp->if_mtu = ETHERMTU;
1373 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1374 ifp->if_ioctl = sis_ioctl;
1375 ifp->if_output = ether_output;
1376 ifp->if_start = sis_start;
1377 ifp->if_watchdog = sis_watchdog;
1378 ifp->if_init = sis_init;
1379 ifp->if_baudrate = 10000000;
1380 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1;
1385 if (mii_phy_probe(dev, &sc->sis_miibus,
1386 sis_ifmedia_upd, sis_ifmedia_sts)) {
1387 printf("sis%d: MII without any PHY!\n", sc->sis_unit);
1393 * Call MI attach routine.
1395 ether_ifattach(ifp, eaddr);
1398 * Tell the upper layer(s) we support long frames.
1400 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1401 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1403 /* Hook interrupt last to avoid having to lock softc */
1404 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE,
1405 sis_intr, sc, &sc->sis_intrhand);
1408 printf("sis%d: couldn't set up irq\n", unit);
1409 ether_ifdetach(ifp);
1421 * Shutdown hardware and free up resources. This can be called any
1422 * time after the mutex has been initialized. It is called in both
1423 * the error case in attach and the normal detach case so it needs
1424 * to be careful about only freeing resources that have actually been
1431 struct sis_softc *sc;
1434 sc = device_get_softc(dev);
1435 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1437 ifp = &sc->arpcom.ac_if;
1439 /* These should only be active if attach succeeded. */
1440 if (device_is_attached(dev)) {
1443 ether_ifdetach(ifp);
1446 device_delete_child(dev, sc->sis_miibus);
1447 bus_generic_detach(dev);
1449 if (sc->sis_intrhand)
1450 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1452 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1454 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1456 if (sc->sis_ldata.sis_rx_tag) {
1457 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
1458 sc->sis_ldata.sis_rx_dmamap);
1459 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1460 sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap);
1461 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1463 if (sc->sis_ldata.sis_tx_tag) {
1464 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
1465 sc->sis_ldata.sis_tx_dmamap);
1466 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1467 sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap);
1468 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1470 if (sc->sis_parent_tag)
1471 bus_dma_tag_destroy(sc->sis_parent_tag);
1473 bus_dma_tag_destroy(sc->sis_tag);
1476 mtx_destroy(&sc->sis_mtx);
1482 * Initialize the transmit descriptors.
1485 sis_list_tx_init(sc)
1486 struct sis_softc *sc;
1488 struct sis_list_data *ld;
1489 struct sis_ring_data *cd;
1492 cd = &sc->sis_cdata;
1493 ld = &sc->sis_ldata;
1495 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1496 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1497 ld->sis_tx_list[i].sis_nextdesc =
1498 &ld->sis_tx_list[nexti];
1499 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1500 sc->sis_ldata.sis_tx_dmamap,
1501 &ld->sis_tx_list[nexti], sizeof(struct sis_desc),
1502 sis_dma_map_desc_next, &ld->sis_tx_list[i], 0);
1503 ld->sis_tx_list[i].sis_mbuf = NULL;
1504 ld->sis_tx_list[i].sis_ptr = 0;
1505 ld->sis_tx_list[i].sis_ctl = 0;
1508 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1510 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag,
1511 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE);
1517 * Initialize the RX descriptors and allocate mbufs for them. Note that
1518 * we arrange the descriptors in a closed ring, so that the last descriptor
1519 * points back to the first.
1522 sis_list_rx_init(sc)
1523 struct sis_softc *sc;
1525 struct sis_list_data *ld;
1526 struct sis_ring_data *cd;
1529 ld = &sc->sis_ldata;
1530 cd = &sc->sis_cdata;
1532 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1533 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1535 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1536 ld->sis_rx_list[i].sis_nextdesc =
1537 &ld->sis_rx_list[nexti];
1538 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1539 sc->sis_ldata.sis_rx_dmamap,
1540 &ld->sis_rx_list[nexti],
1541 sizeof(struct sis_desc), sis_dma_map_desc_next,
1542 &ld->sis_rx_list[i], 0);
1545 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag,
1546 sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE);
1548 cd->sis_rx_prod = 0;
1554 * Initialize an RX descriptor and attach an MBUF cluster.
1557 sis_newbuf(sc, c, m)
1558 struct sis_softc *sc;
1567 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1571 m->m_data = m->m_ext.ext_buf;
1574 c->sis_ctl = SIS_RXLEN;
1576 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1577 bus_dmamap_load(sc->sis_tag, c->sis_map,
1578 mtod(m, void *), MCLBYTES,
1579 sis_dma_map_desc_ptr, c, 0);
1580 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
1586 * A frame has been uploaded: pass the resulting mbuf chain up to
1587 * the higher level protocols.
1591 struct sis_softc *sc;
1595 struct sis_desc *cur_rx;
1596 int i, total_len = 0;
1599 ifp = &sc->arpcom.ac_if;
1600 i = sc->sis_cdata.sis_rx_prod;
1602 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1604 #ifdef DEVICE_POLLING
1605 if (ifp->if_flags & IFF_POLLING) {
1606 if (sc->rxcycles <= 0)
1610 #endif /* DEVICE_POLLING */
1611 cur_rx = &sc->sis_ldata.sis_rx_list[i];
1612 rxstat = cur_rx->sis_rxstat;
1613 bus_dmamap_sync(sc->sis_tag,
1614 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE);
1615 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1616 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1617 m = cur_rx->sis_mbuf;
1618 cur_rx->sis_mbuf = NULL;
1619 total_len = SIS_RXBYTES(cur_rx);
1620 SIS_INC(i, SIS_RX_LIST_CNT);
1623 * If an error occurs, update stats, clear the
1624 * status word and leave the mbuf cluster in place:
1625 * it should simply get re-used next time this descriptor
1626 * comes up in the ring.
1628 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1630 if (rxstat & SIS_RXSTAT_COLL)
1631 ifp->if_collisions++;
1632 sis_newbuf(sc, cur_rx, m);
1636 /* No errors; receive the packet. */
1639 * On the x86 we do not have alignment problems, so try to
1640 * allocate a new buffer for the receive ring, and pass up
1641 * the one where the packet is already, saving the expensive
1642 * copy done in m_devget().
1643 * If we are on an architecture with alignment problems, or
1644 * if the allocation fails, then use m_devget and leave the
1645 * existing buffer in the receive ring.
1647 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1648 m->m_pkthdr.len = m->m_len = total_len;
1653 m0 = m_devget(mtod(m, char *), total_len,
1654 ETHER_ALIGN, ifp, NULL);
1655 sis_newbuf(sc, cur_rx, m);
1664 m->m_pkthdr.rcvif = ifp;
1666 (*ifp->if_input)(ifp, m);
1669 sc->sis_cdata.sis_rx_prod = i;
1676 struct sis_softc *sc;
1684 * A frame was downloaded to the chip. It's safe for us to clean up
1690 struct sis_softc *sc;
1695 ifp = &sc->arpcom.ac_if;
1698 * Go through our tx list and free mbufs for those
1699 * frames that have been transmitted.
1701 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1702 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1703 struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1705 if (SIS_OWNDESC(cur_tx))
1708 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1711 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1713 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1714 ifp->if_collisions++;
1715 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1716 ifp->if_collisions++;
1719 ifp->if_collisions +=
1720 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1723 if (cur_tx->sis_mbuf != NULL) {
1724 m_freem(cur_tx->sis_mbuf);
1725 cur_tx->sis_mbuf = NULL;
1726 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1727 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1731 if (idx != sc->sis_cdata.sis_tx_cons) {
1732 /* we freed up some buffers */
1733 sc->sis_cdata.sis_tx_cons = idx;
1734 ifp->if_flags &= ~IFF_OACTIVE;
1737 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
1746 struct sis_softc *sc;
1747 struct mii_data *mii;
1753 ifp = &sc->arpcom.ac_if;
1755 mii = device_get_softc(sc->sis_miibus);
1758 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE &&
1759 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1761 if (ifp->if_snd.ifq_head != NULL)
1765 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1772 #ifdef DEVICE_POLLING
1773 static poll_handler_t sis_poll;
1776 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1778 struct sis_softc *sc = ifp->if_softc;
1781 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1782 CSR_WRITE_4(sc, SIS_IER, 1);
1787 * On the sis, reading the status register also clears it.
1788 * So before returning to intr mode we must make sure that all
1789 * possible pending sources of interrupts have been served.
1790 * In practice this means run to completion the *eof routines,
1791 * and then call the interrupt routine
1793 sc->rxcycles = count;
1796 if (ifp->if_snd.ifq_head != NULL)
1799 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1802 /* Reading the ISR register clears all interrupts. */
1803 status = CSR_READ_4(sc, SIS_ISR);
1805 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1808 if (status & (SIS_ISR_RX_IDLE))
1809 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1811 if (status & SIS_ISR_SYSERR) {
1820 #endif /* DEVICE_POLLING */
1826 struct sis_softc *sc;
1831 ifp = &sc->arpcom.ac_if;
1834 #ifdef DEVICE_POLLING
1835 if (ifp->if_flags & IFF_POLLING)
1837 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */
1838 CSR_WRITE_4(sc, SIS_IER, 0);
1841 #endif /* DEVICE_POLLING */
1843 /* Supress unwanted interrupts */
1844 if (!(ifp->if_flags & IFF_UP)) {
1849 /* Disable interrupts. */
1850 CSR_WRITE_4(sc, SIS_IER, 0);
1853 /* Reading the ISR register clears all interrupts. */
1854 status = CSR_READ_4(sc, SIS_ISR);
1856 if ((status & SIS_INTRS) == 0)
1860 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1861 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1864 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE))
1867 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1870 if (status & (SIS_ISR_RX_IDLE))
1871 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1873 if (status & SIS_ISR_SYSERR) {
1879 /* Re-enable interrupts. */
1880 CSR_WRITE_4(sc, SIS_IER, 1);
1882 if (ifp->if_snd.ifq_head != NULL)
1891 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1892 * pointers to the fragment pointers.
1895 sis_encap(sc, m_head, txidx)
1896 struct sis_softc *sc;
1897 struct mbuf **m_head;
1900 struct sis_desc *f = NULL;
1902 int frag, cur, cnt = 0, chainlen = 0;
1905 * If there's no way we can send any packets, return now.
1907 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2)
1911 * Count the number of frags in this chain to see if
1912 * we need to m_defrag. Since the descriptor list is shared
1913 * by all packets, we'll m_defrag long chains so that they
1914 * do not use up the entire list, even if they would fit.
1917 for (m = *m_head; m != NULL; m = m->m_next)
1920 if ((chainlen > SIS_TX_LIST_CNT / 4) ||
1921 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) {
1922 m = m_defrag(*m_head, M_DONTWAIT);
1929 * Start packing the mbufs in this chain into
1930 * the fragment pointers. Stop when we run out
1931 * of fragments or hit the end of the mbuf chain.
1933 cur = frag = *txidx;
1935 for (m = *m_head; m != NULL; m = m->m_next) {
1936 if (m->m_len != 0) {
1937 if ((SIS_TX_LIST_CNT -
1938 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1940 f = &sc->sis_ldata.sis_tx_list[frag];
1941 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1942 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1943 bus_dmamap_load(sc->sis_tag, f->sis_map,
1944 mtod(m, void *), m->m_len,
1945 sis_dma_map_desc_ptr, f, 0);
1946 bus_dmamap_sync(sc->sis_tag,
1947 f->sis_map, BUS_DMASYNC_PREREAD);
1949 f->sis_ctl |= SIS_CMDSTS_OWN;
1951 SIS_INC(frag, SIS_TX_LIST_CNT);
1959 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = *m_head;
1960 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1961 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1962 sc->sis_cdata.sis_tx_cnt += cnt;
1969 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1970 * to the mbuf data regions directly in the transmit lists. We also save a
1971 * copy of the pointers since the transmit list fragment pointers are
1972 * physical addresses.
1979 struct sis_softc *sc;
1980 struct mbuf *m_head = NULL;
1986 if (!sc->sis_link) {
1991 idx = sc->sis_cdata.sis_tx_prod;
1993 if (ifp->if_flags & IFF_OACTIVE) {
1998 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
1999 IF_DEQUEUE(&ifp->if_snd, m_head);
2003 if (sis_encap(sc, &m_head, &idx)) {
2004 IF_PREPEND(&ifp->if_snd, m_head);
2005 ifp->if_flags |= IFF_OACTIVE;
2010 * If there's a BPF listener, bounce a copy of this frame
2013 BPF_MTAP(ifp, m_head);
2018 sc->sis_cdata.sis_tx_prod = idx;
2019 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
2022 * Set a timeout in case the chip goes out to lunch.
2035 struct sis_softc *sc = xsc;
2036 struct ifnet *ifp = &sc->arpcom.ac_if;
2037 struct mii_data *mii;
2042 * Cancel pending I/O and free all RX/TX buffers.
2047 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
2049 * Configure 400usec of interrupt holdoff. This is based
2050 * on emperical tests on a Soekris 4801.
2052 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
2056 mii = device_get_softc(sc->sis_miibus);
2058 /* Set MAC address */
2059 if (sc->sis_type == SIS_TYPE_83815) {
2060 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
2061 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
2062 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
2063 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
2064 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
2065 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
2066 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
2067 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
2068 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
2070 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
2071 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
2072 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
2073 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
2074 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
2075 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
2076 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
2077 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
2078 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
2081 /* Init circular RX list. */
2082 if (sis_list_rx_init(sc) == ENOBUFS) {
2083 printf("sis%d: initialization failed: no "
2084 "memory for rx buffers\n", sc->sis_unit);
2091 * Init tx descriptors.
2093 sis_list_tx_init(sc);
2096 * For the NatSemi chip, we have to explicitly enable the
2097 * reception of ARP frames, as well as turn on the 'perfect
2098 * match' filter where we store the station address, otherwise
2099 * we won't receive unicasts meant for this host.
2101 if (sc->sis_type == SIS_TYPE_83815) {
2102 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
2103 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
2106 /* If we want promiscuous mode, set the allframes bit. */
2107 if (ifp->if_flags & IFF_PROMISC) {
2108 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
2110 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
2114 * Set the capture broadcast bit to capture broadcast frames.
2116 if (ifp->if_flags & IFF_BROADCAST) {
2117 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
2119 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
2123 * Load the multicast filter.
2125 if (sc->sis_type == SIS_TYPE_83815)
2126 sis_setmulti_ns(sc);
2128 sis_setmulti_sis(sc);
2130 /* Turn the receive filter on */
2131 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
2134 * Load the address of the RX and TX lists.
2136 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
2137 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
2139 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
2140 * the PCI bus. When this bit is set, the Max DMA Burst Size
2141 * for TX/RX DMA should be no larger than 16 double words.
2143 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
2144 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
2146 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
2150 /* Accept Long Packets for VLAN support */
2151 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
2153 /* Set TX configuration */
2154 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
2155 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
2157 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
2160 /* Set full/half duplex mode. */
2161 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
2162 SIS_SETBIT(sc, SIS_TX_CFG,
2163 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
2164 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
2166 SIS_CLRBIT(sc, SIS_TX_CFG,
2167 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
2168 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
2171 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
2172 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2176 * Some DP83815s experience problems when used with short
2177 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This
2178 * sequence adjusts the DSP's signal attenuation to fix the
2181 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2183 reg = CSR_READ_4(sc, NS_PHY_DSPCFG);
2184 CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000);
2186 reg = CSR_READ_4(sc, NS_PHY_TDATA);
2187 if ((reg & 0x0080) == 0 || (reg & 0xff) >= 0xd8) {
2188 device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg);
2189 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
2190 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
2192 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2196 * Enable interrupts.
2198 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2199 #ifdef DEVICE_POLLING
2201 * ... only enable interrupts if we are not polling, make sure
2202 * they are off otherwise.
2204 if (ifp->if_flags & IFF_POLLING)
2205 CSR_WRITE_4(sc, SIS_IER, 0);
2207 #endif /* DEVICE_POLLING */
2208 CSR_WRITE_4(sc, SIS_IER, 1);
2210 /* Enable receiver and transmitter. */
2211 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2212 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2219 * Page 75 of the DP83815 manual recommends the
2220 * following register settings "for optimum
2221 * performance." Note however that at least three
2222 * of the registers are listed as "reserved" in
2223 * the register map, so who knows what they do.
2225 if (sc->sis_type == SIS_TYPE_83815) {
2226 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2227 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2228 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2229 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2230 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2233 ifp->if_flags |= IFF_RUNNING;
2234 ifp->if_flags &= ~IFF_OACTIVE;
2237 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2245 * Set media options.
2248 sis_ifmedia_upd(ifp)
2251 struct sis_softc *sc;
2252 struct mii_data *mii;
2256 mii = device_get_softc(sc->sis_miibus);
2258 if (mii->mii_instance) {
2259 struct mii_softc *miisc;
2260 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2261 mii_phy_reset(miisc);
2269 * Report current media status.
2272 sis_ifmedia_sts(ifp, ifmr)
2274 struct ifmediareq *ifmr;
2276 struct sis_softc *sc;
2277 struct mii_data *mii;
2281 mii = device_get_softc(sc->sis_miibus);
2283 ifmr->ifm_active = mii->mii_media_active;
2284 ifmr->ifm_status = mii->mii_media_status;
2290 sis_ioctl(ifp, command, data)
2295 struct sis_softc *sc = ifp->if_softc;
2296 struct ifreq *ifr = (struct ifreq *) data;
2297 struct mii_data *mii;
2302 if (ifp->if_flags & IFF_UP) {
2305 if (ifp->if_flags & IFF_RUNNING)
2313 if (sc->sis_type == SIS_TYPE_83815)
2314 sis_setmulti_ns(sc);
2316 sis_setmulti_sis(sc);
2322 mii = device_get_softc(sc->sis_miibus);
2324 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2328 error = ether_ioctl(ifp, command, data);
2339 struct sis_softc *sc;
2346 printf("sis%d: watchdog timeout\n", sc->sis_unit);
2352 if (ifp->if_snd.ifq_head != NULL)
2361 * Stop the adapter and free any mbufs allocated to the
2366 struct sis_softc *sc;
2372 ifp = &sc->arpcom.ac_if;
2375 callout_stop(&sc->sis_stat_ch);
2377 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2378 #ifdef DEVICE_POLLING
2379 ether_poll_deregister(ifp);
2381 CSR_WRITE_4(sc, SIS_IER, 0);
2382 CSR_WRITE_4(sc, SIS_IMR, 0);
2383 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2385 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2386 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2391 * Free data in the RX lists.
2393 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2394 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
2395 bus_dmamap_unload(sc->sis_tag,
2396 sc->sis_ldata.sis_rx_list[i].sis_map);
2397 bus_dmamap_destroy(sc->sis_tag,
2398 sc->sis_ldata.sis_rx_list[i].sis_map);
2399 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
2400 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
2403 bzero(sc->sis_ldata.sis_rx_list,
2404 sizeof(sc->sis_ldata.sis_rx_list));
2407 * Free the TX list buffers.
2409 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2410 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
2411 bus_dmamap_unload(sc->sis_tag,
2412 sc->sis_ldata.sis_tx_list[i].sis_map);
2413 bus_dmamap_destroy(sc->sis_tag,
2414 sc->sis_ldata.sis_tx_list[i].sis_map);
2415 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
2416 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
2420 bzero(sc->sis_ldata.sis_tx_list,
2421 sizeof(sc->sis_ldata.sis_tx_list));
2429 * Stop all chip I/O so that the kernel's probe routines don't
2430 * get confused by errant DMAs when rebooting.
2436 struct sis_softc *sc;
2438 sc = device_get_softc(dev);