2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
3 * Copyright (c) 1997, 1998, 1999
4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
39 * available from http://www.sis.com.tw.
41 * This driver also supports the NatSemi DP83815. Datasheets are
42 * available from http://www.national.com.
44 * Written by Bill Paul <wpaul@ee.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #ifdef HAVE_KERNEL_OPTION_HEADERS
62 #include "opt_device_polling.h"
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/sockio.h>
69 #include <sys/malloc.h>
70 #include <sys/kernel.h>
71 #include <sys/module.h>
72 #include <sys/socket.h>
73 #include <sys/sysctl.h>
76 #include <net/if_arp.h>
77 #include <net/ethernet.h>
78 #include <net/if_dl.h>
79 #include <net/if_media.h>
80 #include <net/if_types.h>
81 #include <net/if_vlan_var.h>
85 #include <machine/bus.h>
86 #include <machine/resource.h>
90 #include <dev/mii/mii.h>
91 #include <dev/mii/miivar.h>
93 #include <dev/pci/pcireg.h>
94 #include <dev/pci/pcivar.h>
96 #define SIS_USEIOSPACE
98 #include <pci/if_sisreg.h>
100 MODULE_DEPEND(sis, pci, 1, 1, 1);
101 MODULE_DEPEND(sis, ether, 1, 1, 1);
102 MODULE_DEPEND(sis, miibus, 1, 1, 1);
104 /* "device miibus" required. See GENERIC if you get errors here. */
105 #include "miibus_if.h"
107 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
108 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
109 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
112 * register space access macros
114 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
116 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
118 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
121 * Various supported device vendors/types and their names.
123 static struct sis_type sis_devs[] = {
124 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
125 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
126 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
130 static int sis_detach(device_t);
131 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
132 static int sis_ifmedia_upd(struct ifnet *);
133 static void sis_init(void *);
134 static void sis_initl(struct sis_softc *);
135 static void sis_intr(void *);
136 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
137 static int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *);
138 static void sis_start(struct ifnet *);
139 static void sis_startl(struct ifnet *);
140 static void sis_stop(struct sis_softc *);
141 static void sis_watchdog(struct ifnet *);
144 static struct resource_spec sis_res_spec[] = {
145 #ifdef SIS_USEIOSPACE
146 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
148 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
150 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
154 #define SIS_SETBIT(sc, reg, x) \
155 CSR_WRITE_4(sc, reg, \
156 CSR_READ_4(sc, reg) | (x))
158 #define SIS_CLRBIT(sc, reg, x) \
159 CSR_WRITE_4(sc, reg, \
160 CSR_READ_4(sc, reg) & ~(x))
163 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
166 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
169 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
174 r->sis_next = segs->ds_addr;
178 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
183 r->sis_ptr = segs->ds_addr;
187 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
196 * Routine to reverse the bits in a word. Stolen almost
197 * verbatim from /usr/games/fortune.
200 sis_reverse(uint16_t n)
202 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
203 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
204 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
205 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
211 sis_delay(struct sis_softc *sc)
215 for (idx = (300 / 33) + 1; idx > 0; idx--)
216 CSR_READ_4(sc, SIS_CSR);
220 sis_eeprom_idle(struct sis_softc *sc)
224 SIO_SET(SIS_EECTL_CSEL);
226 SIO_SET(SIS_EECTL_CLK);
229 for (i = 0; i < 25; i++) {
230 SIO_CLR(SIS_EECTL_CLK);
232 SIO_SET(SIS_EECTL_CLK);
236 SIO_CLR(SIS_EECTL_CLK);
238 SIO_CLR(SIS_EECTL_CSEL);
240 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
244 * Send a read command and address to the EEPROM, check for ACK.
247 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
251 d = addr | SIS_EECMD_READ;
254 * Feed in each bit and stobe the clock.
256 for (i = 0x400; i; i >>= 1) {
258 SIO_SET(SIS_EECTL_DIN);
260 SIO_CLR(SIS_EECTL_DIN);
263 SIO_SET(SIS_EECTL_CLK);
265 SIO_CLR(SIS_EECTL_CLK);
271 * Read a word of data stored in the EEPROM at address 'addr.'
274 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
279 /* Force EEPROM to idle state. */
282 /* Enter EEPROM access mode. */
284 SIO_CLR(SIS_EECTL_CLK);
286 SIO_SET(SIS_EECTL_CSEL);
290 * Send address of word we want to read.
292 sis_eeprom_putbyte(sc, addr);
295 * Start reading bits from EEPROM.
297 for (i = 0x8000; i; i >>= 1) {
298 SIO_SET(SIS_EECTL_CLK);
300 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
303 SIO_CLR(SIS_EECTL_CLK);
307 /* Turn off EEPROM access mode. */
314 * Read a sequence of words from the EEPROM.
317 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
320 u_int16_t word = 0, *ptr;
322 for (i = 0; i < cnt; i++) {
323 sis_eeprom_getword(sc, off + i, &word);
324 ptr = (u_int16_t *)(dest + (i * 2));
332 #if defined(__i386__) || defined(__amd64__)
334 sis_find_bridge(device_t dev)
336 devclass_t pci_devclass;
337 device_t *pci_devices;
339 device_t *pci_children;
340 int pci_childcount = 0;
341 device_t *busp, *childp;
342 device_t child = NULL;
345 if ((pci_devclass = devclass_find("pci")) == NULL)
348 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
350 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
352 device_get_children(*busp, &pci_children, &pci_childcount);
353 for (j = 0, childp = pci_children;
354 j < pci_childcount; j++, childp++) {
355 if (pci_get_vendor(*childp) == SIS_VENDORID &&
356 pci_get_device(*childp) == 0x0008) {
364 free(pci_devices, M_TEMP);
365 free(pci_children, M_TEMP);
370 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
375 bus_space_tag_t btag;
377 bridge = sis_find_bridge(dev);
380 reg = pci_read_config(bridge, 0x48, 1);
381 pci_write_config(bridge, 0x48, reg|0x40, 1);
384 #if defined(__i386__)
385 btag = I386_BUS_SPACE_IO;
386 #elif defined(__amd64__)
387 btag = AMD64_BUS_SPACE_IO;
390 for (i = 0; i < cnt; i++) {
391 bus_space_write_1(btag, 0x0, 0x70, i + off);
392 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
395 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
400 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
402 u_int32_t filtsave, csrsave;
404 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
405 csrsave = CSR_READ_4(sc, SIS_CSR);
407 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
408 CSR_WRITE_4(sc, SIS_CSR, 0);
410 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
412 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
413 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
414 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
415 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
416 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
417 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
419 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
420 CSR_WRITE_4(sc, SIS_CSR, csrsave);
426 * Sync the PHYs by setting data bit and strobing the clock 32 times.
429 sis_mii_sync(struct sis_softc *sc)
433 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
435 for (i = 0; i < 32; i++) {
436 SIO_SET(SIS_MII_CLK);
438 SIO_CLR(SIS_MII_CLK);
444 * Clock a series of bits through the MII.
447 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
451 SIO_CLR(SIS_MII_CLK);
453 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
455 SIO_SET(SIS_MII_DATA);
457 SIO_CLR(SIS_MII_DATA);
460 SIO_CLR(SIS_MII_CLK);
462 SIO_SET(SIS_MII_CLK);
467 * Read an PHY register through the MII.
470 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
475 * Set up frame for RX.
477 frame->mii_stdelim = SIS_MII_STARTDELIM;
478 frame->mii_opcode = SIS_MII_READOP;
479 frame->mii_turnaround = 0;
485 SIO_SET(SIS_MII_DIR);
490 * Send command/address info.
492 sis_mii_send(sc, frame->mii_stdelim, 2);
493 sis_mii_send(sc, frame->mii_opcode, 2);
494 sis_mii_send(sc, frame->mii_phyaddr, 5);
495 sis_mii_send(sc, frame->mii_regaddr, 5);
498 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
500 SIO_SET(SIS_MII_CLK);
504 SIO_CLR(SIS_MII_DIR);
507 SIO_CLR(SIS_MII_CLK);
509 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
510 SIO_SET(SIS_MII_CLK);
514 * Now try reading data bits. If the ack failed, we still
515 * need to clock through 16 cycles to keep the PHY(s) in sync.
518 for(i = 0; i < 16; i++) {
519 SIO_CLR(SIS_MII_CLK);
521 SIO_SET(SIS_MII_CLK);
527 for (i = 0x8000; i; i >>= 1) {
528 SIO_CLR(SIS_MII_CLK);
531 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
532 frame->mii_data |= i;
535 SIO_SET(SIS_MII_CLK);
541 SIO_CLR(SIS_MII_CLK);
543 SIO_SET(SIS_MII_CLK);
552 * Write to a PHY register through the MII.
555 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
559 * Set up frame for TX.
562 frame->mii_stdelim = SIS_MII_STARTDELIM;
563 frame->mii_opcode = SIS_MII_WRITEOP;
564 frame->mii_turnaround = SIS_MII_TURNAROUND;
567 * Turn on data output.
569 SIO_SET(SIS_MII_DIR);
573 sis_mii_send(sc, frame->mii_stdelim, 2);
574 sis_mii_send(sc, frame->mii_opcode, 2);
575 sis_mii_send(sc, frame->mii_phyaddr, 5);
576 sis_mii_send(sc, frame->mii_regaddr, 5);
577 sis_mii_send(sc, frame->mii_turnaround, 2);
578 sis_mii_send(sc, frame->mii_data, 16);
581 SIO_SET(SIS_MII_CLK);
583 SIO_CLR(SIS_MII_CLK);
589 SIO_CLR(SIS_MII_DIR);
595 sis_miibus_readreg(device_t dev, int phy, int reg)
597 struct sis_softc *sc;
598 struct sis_mii_frame frame;
600 sc = device_get_softc(dev);
602 if (sc->sis_type == SIS_TYPE_83815) {
606 * The NatSemi chip can take a while after
607 * a reset to come ready, during which the BMSR
608 * returns a value of 0. This is *never* supposed
609 * to happen: some of the BMSR bits are meant to
610 * be hardwired in the on position, and this can
611 * confuse the miibus code a bit during the probe
612 * and attach phase. So we make an effort to check
613 * for this condition and wait for it to clear.
615 if (!CSR_READ_4(sc, NS_BMSR))
617 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
621 * Chipsets < SIS_635 seem not to be able to read/write
622 * through mdio. Use the enhanced PHY access register
625 if (sc->sis_type == SIS_TYPE_900 &&
626 sc->sis_rev < SIS_REV_635) {
632 CSR_WRITE_4(sc, SIS_PHYCTL,
633 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
634 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
636 for (i = 0; i < SIS_TIMEOUT; i++) {
637 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
641 if (i == SIS_TIMEOUT) {
642 if_printf(sc->sis_ifp, "PHY failed to come ready\n");
646 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
653 bzero((char *)&frame, sizeof(frame));
655 frame.mii_phyaddr = phy;
656 frame.mii_regaddr = reg;
657 sis_mii_readreg(sc, &frame);
659 return(frame.mii_data);
664 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
666 struct sis_softc *sc;
667 struct sis_mii_frame frame;
669 sc = device_get_softc(dev);
671 if (sc->sis_type == SIS_TYPE_83815) {
674 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
679 * Chipsets < SIS_635 seem not to be able to read/write
680 * through mdio. Use the enhanced PHY access register
683 if (sc->sis_type == SIS_TYPE_900 &&
684 sc->sis_rev < SIS_REV_635) {
690 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
691 (reg << 6) | SIS_PHYOP_WRITE);
692 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
694 for (i = 0; i < SIS_TIMEOUT; i++) {
695 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
699 if (i == SIS_TIMEOUT)
700 if_printf(sc->sis_ifp, "PHY failed to come ready\n");
702 bzero((char *)&frame, sizeof(frame));
704 frame.mii_phyaddr = phy;
705 frame.mii_regaddr = reg;
706 frame.mii_data = data;
707 sis_mii_writereg(sc, &frame);
713 sis_miibus_statchg(device_t dev)
715 struct sis_softc *sc;
717 sc = device_get_softc(dev);
723 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
727 /* Compute CRC for the address value. */
728 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
731 * return the filter bit position
733 * The NatSemi chip has a 512-bit filter, which is
734 * different than the SiS, so we special-case it.
736 if (sc->sis_type == SIS_TYPE_83815)
738 else if (sc->sis_rev >= SIS_REV_635 ||
739 sc->sis_rev == SIS_REV_900B)
746 sis_setmulti_ns(struct sis_softc *sc)
749 struct ifmultiaddr *ifma;
750 u_int32_t h = 0, i, filtsave;
755 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
756 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
757 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
762 * We have to explicitly enable the multicast hash table
763 * on the NatSemi chip if we want to use it, which we do.
765 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
766 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
768 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
770 /* first, zot all the existing hash bits */
771 for (i = 0; i < 32; i++) {
772 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
773 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
777 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
778 if (ifma->ifma_addr->sa_family != AF_LINK)
781 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
784 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
787 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
791 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
797 sis_setmulti_sis(struct sis_softc *sc)
800 struct ifmultiaddr *ifma;
801 u_int32_t h, i, n, ctl;
802 u_int16_t hashes[16];
806 /* hash table size */
807 if (sc->sis_rev >= SIS_REV_635 ||
808 sc->sis_rev == SIS_REV_900B)
813 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
815 if (ifp->if_flags & IFF_BROADCAST)
816 ctl |= SIS_RXFILTCTL_BROAD;
818 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
819 ctl |= SIS_RXFILTCTL_ALLMULTI;
820 if (ifp->if_flags & IFF_PROMISC)
821 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
822 for (i = 0; i < n; i++)
825 for (i = 0; i < n; i++)
829 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
830 if (ifma->ifma_addr->sa_family != AF_LINK)
833 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
834 hashes[h >> 4] |= 1 << (h & 0xf);
839 ctl |= SIS_RXFILTCTL_ALLMULTI;
840 for (i = 0; i < n; i++)
845 for (i = 0; i < n; i++) {
846 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
847 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
850 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
854 sis_reset(struct sis_softc *sc)
858 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
860 for (i = 0; i < SIS_TIMEOUT; i++) {
861 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
865 if (i == SIS_TIMEOUT)
866 if_printf(sc->sis_ifp, "reset never completed\n");
868 /* Wait a little while for the chip to get its brains in order. */
872 * If this is a NetSemi chip, make sure to clear
875 if (sc->sis_type == SIS_TYPE_83815) {
876 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
877 CSR_WRITE_4(sc, NS_CLKRUN, 0);
884 * Probe for an SiS chip. Check the PCI vendor and device
885 * IDs against our list and return a device name if we find a match.
888 sis_probe(device_t dev)
894 while(t->sis_name != NULL) {
895 if ((pci_get_vendor(dev) == t->sis_vid) &&
896 (pci_get_device(dev) == t->sis_did)) {
897 device_set_desc(dev, t->sis_name);
898 return (BUS_PROBE_DEFAULT);
907 * Attach the interface. Allocate softc structures, do ifmedia
908 * setup and ethernet/BPF attach.
911 sis_attach(device_t dev)
913 u_char eaddr[ETHER_ADDR_LEN];
914 struct sis_softc *sc;
916 int error = 0, waittime = 0;
919 sc = device_get_softc(dev);
923 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
925 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
927 if (pci_get_device(dev) == SIS_DEVICEID_900)
928 sc->sis_type = SIS_TYPE_900;
929 if (pci_get_device(dev) == SIS_DEVICEID_7016)
930 sc->sis_type = SIS_TYPE_7016;
931 if (pci_get_vendor(dev) == NS_VENDORID)
932 sc->sis_type = SIS_TYPE_83815;
934 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
936 * Map control/status registers.
938 pci_enable_busmaster(dev);
940 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
942 device_printf(dev, "couldn't allocate resources\n");
946 /* Reset the adapter. */
949 if (sc->sis_type == SIS_TYPE_900 &&
950 (sc->sis_rev == SIS_REV_635 ||
951 sc->sis_rev == SIS_REV_900B)) {
952 SIO_SET(SIS_CFG_RND_CNT);
953 SIO_SET(SIS_CFG_PERR_DETECT);
957 * Get station address from the EEPROM.
959 switch (pci_get_vendor(dev)) {
961 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
963 /* We can't update the device description, so spew */
964 if (sc->sis_srr == NS_SRR_15C)
965 device_printf(dev, "Silicon Revision: DP83815C\n");
966 else if (sc->sis_srr == NS_SRR_15D)
967 device_printf(dev, "Silicon Revision: DP83815D\n");
968 else if (sc->sis_srr == NS_SRR_16A)
969 device_printf(dev, "Silicon Revision: DP83816A\n");
971 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
974 * Reading the MAC address out of the EEPROM on
975 * the NatSemi chip takes a bit more work than
976 * you'd expect. The address spans 4 16-bit words,
977 * with the first word containing only a single bit.
978 * You have to shift everything over one bit to
979 * get it aligned properly. Also, the bits are
980 * stored backwards (the LSB is really the MSB,
981 * and so on) so you have to reverse them in order
982 * to get the MAC address into the form we want.
983 * Why? Who the hell knows.
988 sis_read_eeprom(sc, (caddr_t)&tmp,
989 NS_EE_NODEADDR, 4, 0);
991 /* Shift everything over one bit. */
992 tmp[3] = tmp[3] >> 1;
993 tmp[3] |= tmp[2] << 15;
994 tmp[2] = tmp[2] >> 1;
995 tmp[2] |= tmp[1] << 15;
996 tmp[1] = tmp[1] >> 1;
997 tmp[1] |= tmp[0] << 15;
999 /* Now reverse all the bits. */
1000 tmp[3] = sis_reverse(tmp[3]);
1001 tmp[2] = sis_reverse(tmp[2]);
1002 tmp[1] = sis_reverse(tmp[1]);
1004 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1009 #if defined(__i386__) || defined(__amd64__)
1011 * If this is a SiS 630E chipset with an embedded
1012 * SiS 900 controller, we have to read the MAC address
1013 * from the APC CMOS RAM. Our method for doing this
1014 * is very ugly since we have to reach out and grab
1015 * ahold of hardware for which we cannot properly
1016 * allocate resources. This code is only compiled on
1017 * the i386 architecture since the SiS 630E chipset
1018 * is for x86 motherboards only. Note that there are
1019 * a lot of magic numbers in this hack. These are
1020 * taken from SiS's Linux driver. I'd like to replace
1021 * them with proper symbolic definitions, but that
1022 * requires some datasheets that I don't have access
1025 if (sc->sis_rev == SIS_REV_630S ||
1026 sc->sis_rev == SIS_REV_630E ||
1027 sc->sis_rev == SIS_REV_630EA1)
1028 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1030 else if (sc->sis_rev == SIS_REV_635 ||
1031 sc->sis_rev == SIS_REV_630ET)
1032 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1033 else if (sc->sis_rev == SIS_REV_96x) {
1034 /* Allow to read EEPROM from LAN. It is shared
1035 * between a 1394 controller and the NIC and each
1036 * time we access it, we need to set SIS_EECMD_REQ.
1038 SIO_SET(SIS_EECMD_REQ);
1039 for (waittime = 0; waittime < SIS_TIMEOUT;
1041 /* Force EEPROM to idle state. */
1042 sis_eeprom_idle(sc);
1043 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1044 sis_read_eeprom(sc, (caddr_t)&eaddr,
1045 SIS_EE_NODEADDR, 3, 0);
1051 * Set SIS_EECTL_CLK to high, so a other master
1052 * can operate on the i2c bus.
1054 SIO_SET(SIS_EECTL_CLK);
1055 /* Refuse EEPROM access by LAN */
1056 SIO_SET(SIS_EECMD_DONE);
1059 sis_read_eeprom(sc, (caddr_t)&eaddr,
1060 SIS_EE_NODEADDR, 3, 0);
1065 * Allocate the parent bus DMA tag appropriate for PCI.
1067 #define SIS_NSEG_NEW 32
1068 error = bus_dma_tag_create(NULL, /* parent */
1069 1, 0, /* alignment, boundary */
1070 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1071 BUS_SPACE_MAXADDR, /* highaddr */
1072 NULL, NULL, /* filter, filterarg */
1073 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1074 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1075 BUS_DMA_ALLOCNOW, /* flags */
1076 NULL, NULL, /* lockfunc, lockarg */
1077 &sc->sis_parent_tag);
1082 * Now allocate a tag for the DMA descriptor lists and a chunk
1083 * of DMA-able memory based on the tag. Also obtain the physical
1084 * addresses of the RX and TX ring, which we'll need later.
1085 * All of our lists are allocated as a contiguous block
1088 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1089 1, 0, /* alignment, boundary */
1090 BUS_SPACE_MAXADDR, /* lowaddr */
1091 BUS_SPACE_MAXADDR, /* highaddr */
1092 NULL, NULL, /* filter, filterarg */
1093 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */
1094 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1096 busdma_lock_mutex, /* lockfunc */
1097 &Giant, /* lockarg */
1102 error = bus_dmamem_alloc(sc->sis_rx_tag,
1103 (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1104 &sc->sis_rx_dmamap);
1107 device_printf(dev, "no memory for rx list buffers!\n");
1108 bus_dma_tag_destroy(sc->sis_rx_tag);
1109 sc->sis_rx_tag = NULL;
1113 error = bus_dmamap_load(sc->sis_rx_tag,
1114 sc->sis_rx_dmamap, &(sc->sis_rx_list[0]),
1115 sizeof(struct sis_desc), sis_dma_map_ring,
1116 &sc->sis_rx_paddr, 0);
1119 device_printf(dev, "cannot get address of the rx ring!\n");
1120 bus_dmamem_free(sc->sis_rx_tag,
1121 sc->sis_rx_list, sc->sis_rx_dmamap);
1122 bus_dma_tag_destroy(sc->sis_rx_tag);
1123 sc->sis_rx_tag = NULL;
1127 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1128 1, 0, /* alignment, boundary */
1129 BUS_SPACE_MAXADDR, /* lowaddr */
1130 BUS_SPACE_MAXADDR, /* highaddr */
1131 NULL, NULL, /* filter, filterarg */
1132 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */
1133 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1135 busdma_lock_mutex, /* lockfunc */
1136 &Giant, /* lockarg */
1141 error = bus_dmamem_alloc(sc->sis_tx_tag,
1142 (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1143 &sc->sis_tx_dmamap);
1146 device_printf(dev, "no memory for tx list buffers!\n");
1147 bus_dma_tag_destroy(sc->sis_tx_tag);
1148 sc->sis_tx_tag = NULL;
1152 error = bus_dmamap_load(sc->sis_tx_tag,
1153 sc->sis_tx_dmamap, &(sc->sis_tx_list[0]),
1154 sizeof(struct sis_desc), sis_dma_map_ring,
1155 &sc->sis_tx_paddr, 0);
1158 device_printf(dev, "cannot get address of the tx ring!\n");
1159 bus_dmamem_free(sc->sis_tx_tag,
1160 sc->sis_tx_list, sc->sis_tx_dmamap);
1161 bus_dma_tag_destroy(sc->sis_tx_tag);
1162 sc->sis_tx_tag = NULL;
1166 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1167 1, 0, /* alignment, boundary */
1168 BUS_SPACE_MAXADDR, /* lowaddr */
1169 BUS_SPACE_MAXADDR, /* highaddr */
1170 NULL, NULL, /* filter, filterarg */
1171 MCLBYTES, 1, /* maxsize,nsegments */
1172 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1174 busdma_lock_mutex, /* lockfunc */
1175 &Giant, /* lockarg */
1181 * Obtain the physical addresses of the RX and TX
1182 * rings which we'll need later in the init routine.
1185 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1187 device_printf(dev, "can not if_alloc()\n");
1192 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1193 ifp->if_mtu = ETHERMTU;
1194 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1195 ifp->if_ioctl = sis_ioctl;
1196 ifp->if_start = sis_start;
1197 ifp->if_watchdog = sis_watchdog;
1198 ifp->if_init = sis_init;
1199 ifp->if_baudrate = 10000000;
1200 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1201 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
1202 IFQ_SET_READY(&ifp->if_snd);
1207 if (mii_phy_probe(dev, &sc->sis_miibus,
1208 sis_ifmedia_upd, sis_ifmedia_sts)) {
1209 device_printf(dev, "MII without any PHY!\n");
1215 * Call MI attach routine.
1217 ether_ifattach(ifp, eaddr);
1220 * Tell the upper layer(s) we support long frames.
1222 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1223 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1224 ifp->if_capenable = ifp->if_capabilities;
1225 #ifdef DEVICE_POLLING
1226 ifp->if_capabilities |= IFCAP_POLLING;
1229 /* Hook interrupt last to avoid having to lock softc */
1230 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1231 sis_intr, sc, &sc->sis_intrhand);
1234 device_printf(dev, "couldn't set up irq\n");
1235 ether_ifdetach(ifp);
1247 * Shutdown hardware and free up resources. This can be called any
1248 * time after the mutex has been initialized. It is called in both
1249 * the error case in attach and the normal detach case so it needs
1250 * to be careful about only freeing resources that have actually been
1254 sis_detach(device_t dev)
1256 struct sis_softc *sc;
1259 sc = device_get_softc(dev);
1260 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1263 #ifdef DEVICE_POLLING
1264 if (ifp->if_capenable & IFCAP_POLLING)
1265 ether_poll_deregister(ifp);
1268 /* These should only be active if attach succeeded. */
1269 if (device_is_attached(dev)) {
1274 callout_drain(&sc->sis_stat_ch);
1275 ether_ifdetach(ifp);
1278 device_delete_child(dev, sc->sis_miibus);
1279 bus_generic_detach(dev);
1281 if (sc->sis_intrhand)
1282 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
1283 bus_release_resources(dev, sis_res_spec, sc->sis_res);
1288 if (sc->sis_rx_tag) {
1289 bus_dmamap_unload(sc->sis_rx_tag,
1291 bus_dmamem_free(sc->sis_rx_tag,
1292 sc->sis_rx_list, sc->sis_rx_dmamap);
1293 bus_dma_tag_destroy(sc->sis_rx_tag);
1295 if (sc->sis_tx_tag) {
1296 bus_dmamap_unload(sc->sis_tx_tag,
1298 bus_dmamem_free(sc->sis_tx_tag,
1299 sc->sis_tx_list, sc->sis_tx_dmamap);
1300 bus_dma_tag_destroy(sc->sis_tx_tag);
1302 if (sc->sis_parent_tag)
1303 bus_dma_tag_destroy(sc->sis_parent_tag);
1305 bus_dma_tag_destroy(sc->sis_tag);
1307 mtx_destroy(&sc->sis_mtx);
1313 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1314 * we arrange the descriptors in a closed ring, so that the last descriptor
1315 * points back to the first.
1318 sis_ring_init(struct sis_softc *sc)
1321 struct sis_desc *dp;
1323 dp = &sc->sis_tx_list[0];
1324 for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) {
1325 if (i == (SIS_TX_LIST_CNT - 1))
1326 dp->sis_nextdesc = &sc->sis_tx_list[0];
1328 dp->sis_nextdesc = dp + 1;
1329 bus_dmamap_load(sc->sis_tx_tag,
1331 dp->sis_nextdesc, sizeof(struct sis_desc),
1332 sis_dma_map_desc_next, dp, 0);
1333 dp->sis_mbuf = NULL;
1338 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1340 bus_dmamap_sync(sc->sis_tx_tag,
1341 sc->sis_tx_dmamap, BUS_DMASYNC_PREWRITE);
1343 dp = &sc->sis_rx_list[0];
1344 for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) {
1345 error = sis_newbuf(sc, dp, NULL);
1348 if (i == (SIS_RX_LIST_CNT - 1))
1349 dp->sis_nextdesc = &sc->sis_rx_list[0];
1351 dp->sis_nextdesc = dp + 1;
1352 bus_dmamap_load(sc->sis_rx_tag,
1354 dp->sis_nextdesc, sizeof(struct sis_desc),
1355 sis_dma_map_desc_next, dp, 0);
1358 bus_dmamap_sync(sc->sis_rx_tag,
1359 sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE);
1361 sc->sis_rx_pdsc = &sc->sis_rx_list[0];
1367 * Initialize an RX descriptor and attach an MBUF cluster.
1370 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
1377 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1381 m->m_data = m->m_ext.ext_buf;
1384 c->sis_ctl = SIS_RXLEN;
1386 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1387 bus_dmamap_load(sc->sis_tag, c->sis_map,
1388 mtod(m, void *), MCLBYTES,
1389 sis_dma_map_desc_ptr, c, 0);
1390 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD);
1396 * A frame has been uploaded: pass the resulting mbuf chain up to
1397 * the higher level protocols.
1400 sis_rxeof(struct sis_softc *sc)
1404 struct sis_desc *cur_rx;
1408 SIS_LOCK_ASSERT(sc);
1412 for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx);
1413 cur_rx = cur_rx->sis_nextdesc) {
1415 #ifdef DEVICE_POLLING
1416 if (ifp->if_capenable & IFCAP_POLLING) {
1417 if (sc->rxcycles <= 0)
1422 rxstat = cur_rx->sis_rxstat;
1423 bus_dmamap_sync(sc->sis_tag,
1424 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE);
1425 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1426 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1427 m = cur_rx->sis_mbuf;
1428 cur_rx->sis_mbuf = NULL;
1429 total_len = SIS_RXBYTES(cur_rx);
1432 * If an error occurs, update stats, clear the
1433 * status word and leave the mbuf cluster in place:
1434 * it should simply get re-used next time this descriptor
1435 * comes up in the ring.
1437 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1439 if (rxstat & SIS_RXSTAT_COLL)
1440 ifp->if_collisions++;
1441 sis_newbuf(sc, cur_rx, m);
1445 /* No errors; receive the packet. */
1446 #if defined(__i386__) || defined(__amd64__)
1448 * On the x86 we do not have alignment problems, so try to
1449 * allocate a new buffer for the receive ring, and pass up
1450 * the one where the packet is already, saving the expensive
1451 * copy done in m_devget().
1452 * If we are on an architecture with alignment problems, or
1453 * if the allocation fails, then use m_devget and leave the
1454 * existing buffer in the receive ring.
1456 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1457 m->m_pkthdr.len = m->m_len = total_len;
1462 m0 = m_devget(mtod(m, char *), total_len,
1463 ETHER_ALIGN, ifp, NULL);
1464 sis_newbuf(sc, cur_rx, m);
1473 m->m_pkthdr.rcvif = ifp;
1476 (*ifp->if_input)(ifp, m);
1480 sc->sis_rx_pdsc = cur_rx;
1484 sis_rxeoc(struct sis_softc *sc)
1487 SIS_LOCK_ASSERT(sc);
1493 * A frame was downloaded to the chip. It's safe for us to clean up
1498 sis_txeof(struct sis_softc *sc)
1503 SIS_LOCK_ASSERT(sc);
1507 * Go through our tx list and free mbufs for those
1508 * frames that have been transmitted.
1510 for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0;
1511 sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1512 struct sis_desc *cur_tx = &sc->sis_tx_list[idx];
1514 if (SIS_OWNDESC(cur_tx))
1517 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1520 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1522 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1523 ifp->if_collisions++;
1524 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1525 ifp->if_collisions++;
1528 ifp->if_collisions +=
1529 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1532 if (cur_tx->sis_mbuf != NULL) {
1533 m_freem(cur_tx->sis_mbuf);
1534 cur_tx->sis_mbuf = NULL;
1535 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1536 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1540 if (idx != sc->sis_tx_cons) {
1541 /* we freed up some buffers */
1542 sc->sis_tx_cons = idx;
1543 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1546 ifp->if_timer = (sc->sis_tx_cnt == 0) ? 0 : 5;
1554 struct sis_softc *sc;
1555 struct mii_data *mii;
1559 SIS_LOCK_ASSERT(sc);
1563 mii = device_get_softc(sc->sis_miibus);
1566 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE &&
1567 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1569 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1573 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1577 #ifdef DEVICE_POLLING
1578 static poll_handler_t sis_poll;
1581 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1583 struct sis_softc *sc = ifp->if_softc;
1586 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1592 * On the sis, reading the status register also clears it.
1593 * So before returning to intr mode we must make sure that all
1594 * possible pending sources of interrupts have been served.
1595 * In practice this means run to completion the *eof routines,
1596 * and then call the interrupt routine
1598 sc->rxcycles = count;
1601 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1604 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1607 /* Reading the ISR register clears all interrupts. */
1608 status = CSR_READ_4(sc, SIS_ISR);
1610 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1613 if (status & (SIS_ISR_RX_IDLE))
1614 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1616 if (status & SIS_ISR_SYSERR) {
1624 #endif /* DEVICE_POLLING */
1629 struct sis_softc *sc;
1636 if (sc->sis_stopped) /* Most likely shared interrupt */
1640 #ifdef DEVICE_POLLING
1641 if (ifp->if_capenable & IFCAP_POLLING) {
1647 /* Disable interrupts. */
1648 CSR_WRITE_4(sc, SIS_IER, 0);
1651 SIS_LOCK_ASSERT(sc);
1652 /* Reading the ISR register clears all interrupts. */
1653 status = CSR_READ_4(sc, SIS_ISR);
1655 if ((status & SIS_INTRS) == 0)
1659 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1660 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1663 if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE))
1666 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1669 if (status & (SIS_ISR_RX_IDLE))
1670 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1672 if (status & SIS_ISR_SYSERR) {
1678 /* Re-enable interrupts. */
1679 CSR_WRITE_4(sc, SIS_IER, 1);
1681 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1688 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1689 * pointers to the fragment pointers.
1692 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1694 struct sis_desc *f = NULL;
1696 int frag, cur, cnt = 0, chainlen = 0;
1699 * If there's no way we can send any packets, return now.
1701 if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2)
1705 * Count the number of frags in this chain to see if
1706 * we need to m_defrag. Since the descriptor list is shared
1707 * by all packets, we'll m_defrag long chains so that they
1708 * do not use up the entire list, even if they would fit.
1711 for (m = *m_head; m != NULL; m = m->m_next)
1714 if ((chainlen > SIS_TX_LIST_CNT / 4) ||
1715 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) {
1716 m = m_defrag(*m_head, M_DONTWAIT);
1723 * Start packing the mbufs in this chain into
1724 * the fragment pointers. Stop when we run out
1725 * of fragments or hit the end of the mbuf chain.
1727 cur = frag = *txidx;
1729 for (m = *m_head; m != NULL; m = m->m_next) {
1730 if (m->m_len != 0) {
1731 if ((SIS_TX_LIST_CNT -
1732 (sc->sis_tx_cnt + cnt)) < 2)
1734 f = &sc->sis_tx_list[frag];
1735 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1736 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1737 bus_dmamap_load(sc->sis_tag, f->sis_map,
1738 mtod(m, void *), m->m_len,
1739 sis_dma_map_desc_ptr, f, 0);
1740 bus_dmamap_sync(sc->sis_tag,
1741 f->sis_map, BUS_DMASYNC_PREREAD);
1743 f->sis_ctl |= SIS_CMDSTS_OWN;
1745 SIS_INC(frag, SIS_TX_LIST_CNT);
1753 sc->sis_tx_list[cur].sis_mbuf = *m_head;
1754 sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1755 sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1756 sc->sis_tx_cnt += cnt;
1763 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1764 * to the mbuf data regions directly in the transmit lists. We also save a
1765 * copy of the pointers since the transmit list fragment pointers are
1766 * physical addresses.
1770 sis_start(struct ifnet *ifp)
1772 struct sis_softc *sc;
1781 sis_startl(struct ifnet *ifp)
1783 struct sis_softc *sc;
1784 struct mbuf *m_head = NULL;
1785 u_int32_t idx, queued = 0;
1789 SIS_LOCK_ASSERT(sc);
1794 idx = sc->sis_tx_prod;
1796 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1799 while(sc->sis_tx_list[idx].sis_mbuf == NULL) {
1800 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1804 if (sis_encap(sc, &m_head, &idx)) {
1805 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1806 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1813 * If there's a BPF listener, bounce a copy of this frame
1816 BPF_MTAP(ifp, m_head);
1822 sc->sis_tx_prod = idx;
1823 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1826 * Set a timeout in case the chip goes out to lunch.
1835 struct sis_softc *sc = xsc;
1843 sis_initl(struct sis_softc *sc)
1845 struct ifnet *ifp = sc->sis_ifp;
1846 struct mii_data *mii;
1848 SIS_LOCK_ASSERT(sc);
1851 * Cancel pending I/O and free all RX/TX buffers.
1854 sc->sis_stopped = 0;
1857 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
1859 * Configure 400usec of interrupt holdoff. This is based
1860 * on emperical tests on a Soekris 4801.
1862 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
1866 mii = device_get_softc(sc->sis_miibus);
1868 /* Set MAC address */
1869 if (sc->sis_type == SIS_TYPE_83815) {
1870 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1871 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1872 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]);
1873 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1874 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1875 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]);
1876 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1877 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1878 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]);
1880 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1881 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1882 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]);
1883 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1884 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1885 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]);
1886 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1887 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1888 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]);
1891 /* Init circular TX/RX lists. */
1892 if (sis_ring_init(sc) != 0) {
1894 "initialization failed: no memory for rx buffers\n");
1900 * Short Cable Receive Errors (MP21.E)
1901 * also: Page 78 of the DP83815 data sheet (september 2002 version)
1902 * recommends the following register settings "for optimum
1903 * performance." for rev 15C. The driver from NS also sets
1904 * the PHY_CR register for later versions.
1906 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
1907 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1908 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1909 if (sc->sis_srr == NS_SRR_15C) {
1910 /* set val for c2 */
1911 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1913 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1914 /* rais SD off, from 4 to c */
1915 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1917 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
1922 * For the NatSemi chip, we have to explicitly enable the
1923 * reception of ARP frames, as well as turn on the 'perfect
1924 * match' filter where we store the station address, otherwise
1925 * we won't receive unicasts meant for this host.
1927 if (sc->sis_type == SIS_TYPE_83815) {
1928 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1929 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1932 /* If we want promiscuous mode, set the allframes bit. */
1933 if (ifp->if_flags & IFF_PROMISC) {
1934 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1936 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1940 * Set the capture broadcast bit to capture broadcast frames.
1942 if (ifp->if_flags & IFF_BROADCAST) {
1943 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1945 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1949 * Load the multicast filter.
1951 if (sc->sis_type == SIS_TYPE_83815)
1952 sis_setmulti_ns(sc);
1954 sis_setmulti_sis(sc);
1956 /* Turn the receive filter on */
1957 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1960 * Load the address of the RX and TX lists.
1962 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr);
1963 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr);
1965 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1966 * the PCI bus. When this bit is set, the Max DMA Burst Size
1967 * for TX/RX DMA should be no larger than 16 double words.
1969 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
1970 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1972 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1975 /* Accept Long Packets for VLAN support */
1976 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1978 /* Set TX configuration */
1979 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
1980 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1982 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1985 /* Set full/half duplex mode. */
1986 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1987 SIS_SETBIT(sc, SIS_TX_CFG,
1988 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1989 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1991 SIS_CLRBIT(sc, SIS_TX_CFG,
1992 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1993 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1996 if (sc->sis_type == SIS_TYPE_83816) {
1998 * MPII03.D: Half Duplex Excessive Collisions.
1999 * Also page 49 in 83816 manual
2001 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
2004 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
2005 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2009 * Short Cable Receive Errors (MP21.E)
2011 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2012 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
2013 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
2015 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
2016 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
2017 device_printf(sc->sis_self,
2018 "Applying short cable fix (reg=%x)\n", reg);
2019 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
2020 reg = CSR_READ_4(sc, NS_PHY_DSPCFG);
2021 SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20);
2023 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2027 * Enable interrupts.
2029 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2030 #ifdef DEVICE_POLLING
2032 * ... only enable interrupts if we are not polling, make sure
2033 * they are off otherwise.
2035 if (ifp->if_capenable & IFCAP_POLLING)
2036 CSR_WRITE_4(sc, SIS_IER, 0);
2039 CSR_WRITE_4(sc, SIS_IER, 1);
2041 /* Enable receiver and transmitter. */
2042 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2043 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2049 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2050 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2053 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2057 * Set media options.
2060 sis_ifmedia_upd(struct ifnet *ifp)
2062 struct sis_softc *sc;
2063 struct mii_data *mii;
2068 mii = device_get_softc(sc->sis_miibus);
2070 if (mii->mii_instance) {
2071 struct mii_softc *miisc;
2072 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2073 mii_phy_reset(miisc);
2082 * Report current media status.
2085 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2087 struct sis_softc *sc;
2088 struct mii_data *mii;
2093 mii = device_get_softc(sc->sis_miibus);
2096 ifmr->ifm_active = mii->mii_media_active;
2097 ifmr->ifm_status = mii->mii_media_status;
2101 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2103 struct sis_softc *sc = ifp->if_softc;
2104 struct ifreq *ifr = (struct ifreq *) data;
2105 struct mii_data *mii;
2111 if (ifp->if_flags & IFF_UP) {
2113 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2122 if (sc->sis_type == SIS_TYPE_83815)
2123 sis_setmulti_ns(sc);
2125 sis_setmulti_sis(sc);
2131 mii = device_get_softc(sc->sis_miibus);
2132 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2135 /* ok, disable interrupts */
2136 #ifdef DEVICE_POLLING
2137 if (ifr->ifr_reqcap & IFCAP_POLLING &&
2138 !(ifp->if_capenable & IFCAP_POLLING)) {
2139 error = ether_poll_register(sis_poll, ifp);
2143 /* Disable interrupts */
2144 CSR_WRITE_4(sc, SIS_IER, 0);
2145 ifp->if_capenable |= IFCAP_POLLING;
2150 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
2151 ifp->if_capenable & IFCAP_POLLING) {
2152 error = ether_poll_deregister(ifp);
2153 /* Enable interrupts. */
2155 CSR_WRITE_4(sc, SIS_IER, 1);
2156 ifp->if_capenable &= ~IFCAP_POLLING;
2160 #endif /* DEVICE_POLLING */
2163 error = ether_ioctl(ifp, command, data);
2171 sis_watchdog(struct ifnet *ifp)
2173 struct sis_softc *sc;
2178 if (sc->sis_stopped) {
2184 if_printf(ifp, "watchdog timeout\n");
2190 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2197 * Stop the adapter and free any mbufs allocated to the
2201 sis_stop(struct sis_softc *sc)
2205 struct sis_desc *dp;
2207 if (sc->sis_stopped)
2209 SIS_LOCK_ASSERT(sc);
2213 callout_stop(&sc->sis_stat_ch);
2215 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2216 CSR_WRITE_4(sc, SIS_IER, 0);
2217 CSR_WRITE_4(sc, SIS_IMR, 0);
2218 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2219 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2221 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2222 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2227 * Free data in the RX lists.
2229 dp = &sc->sis_rx_list[0];
2230 for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) {
2231 if (dp->sis_mbuf == NULL)
2233 bus_dmamap_unload(sc->sis_tag, dp->sis_map);
2234 bus_dmamap_destroy(sc->sis_tag, dp->sis_map);
2235 m_freem(dp->sis_mbuf);
2236 dp->sis_mbuf = NULL;
2238 bzero(sc->sis_rx_list, SIS_RX_LIST_SZ);
2241 * Free the TX list buffers.
2243 dp = &sc->sis_tx_list[0];
2244 for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) {
2245 if (dp->sis_mbuf == NULL)
2247 bus_dmamap_unload(sc->sis_tag, dp->sis_map);
2248 bus_dmamap_destroy(sc->sis_tag, dp->sis_map);
2249 m_freem(dp->sis_mbuf);
2250 dp->sis_mbuf = NULL;
2253 bzero(sc->sis_tx_list, SIS_TX_LIST_SZ);
2255 sc->sis_stopped = 1;
2259 * Stop all chip I/O so that the kernel's probe routines don't
2260 * get confused by errant DMAs when rebooting.
2263 sis_shutdown(device_t dev)
2265 struct sis_softc *sc;
2267 sc = device_get_softc(dev);
2274 static device_method_t sis_methods[] = {
2275 /* Device interface */
2276 DEVMETHOD(device_probe, sis_probe),
2277 DEVMETHOD(device_attach, sis_attach),
2278 DEVMETHOD(device_detach, sis_detach),
2279 DEVMETHOD(device_shutdown, sis_shutdown),
2282 DEVMETHOD(bus_print_child, bus_generic_print_child),
2283 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
2286 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2287 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2288 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2293 static driver_t sis_driver = {
2296 sizeof(struct sis_softc)
2299 static devclass_t sis_devclass;
2301 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
2302 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);