2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
37 * the SK-984x series adapters, both single port and dual port.
39 * The XaQti XMAC II datasheet,
40 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
41 * The SysKonnect GEnesis manual, http://www.syskonnect.com
43 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
44 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
45 * convenience to others until Vitesse corrects this problem:
47 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
49 * Written by Bill Paul <wpaul@ee.columbia.edu>
50 * Department of Electrical Engineering
51 * Columbia University, New York City
55 * The SysKonnect gigabit ethernet adapters consist of two main
56 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
57 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
58 * components and a PHY while the GEnesis controller provides a PCI
59 * interface with DMA support. Each card may have between 512K and
60 * 2MB of SRAM on board depending on the configuration.
62 * The SysKonnect GEnesis controller can have either one or two XMAC
63 * chips connected to it, allowing single or dual port NIC configurations.
64 * SysKonnect has the distinction of being the only vendor on the market
65 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
66 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
67 * XMAC registers. This driver takes advantage of these features to allow
68 * both XMACs to operate as independent interfaces.
71 #include <sys/param.h>
72 #include <sys/systm.h>
73 #include <sys/sockio.h>
75 #include <sys/malloc.h>
76 #include <sys/kernel.h>
77 #include <sys/socket.h>
78 #include <sys/queue.h>
81 #include <net/if_arp.h>
82 #include <net/ethernet.h>
83 #include <net/if_dl.h>
84 #include <net/if_media.h>
88 #include <vm/vm.h> /* for vtophys */
89 #include <vm/pmap.h> /* for vtophys */
90 #include <machine/bus_pio.h>
91 #include <machine/bus_memio.h>
92 #include <machine/bus.h>
93 #include <machine/resource.h>
97 #include <dev/mii/mii.h>
98 #include <dev/mii/miivar.h>
99 #include <dev/mii/brgphyreg.h>
101 #include <pci/pcireg.h>
102 #include <pci/pcivar.h>
104 #define SK_USEIOSPACE
106 #include <pci/if_skreg.h>
107 #include <pci/xmaciireg.h>
109 MODULE_DEPEND(sk, miibus, 1, 1, 1);
111 /* "controller miibus0" required. See GENERIC if you get errors here. */
112 #include "miibus_if.h"
115 static const char rcsid[] =
119 static struct sk_type sk_devs[] = {
120 { SK_VENDORID, SK_DEVICEID_GE, "SysKonnect Gigabit Ethernet" },
124 static int sk_probe (device_t);
125 static int sk_attach (device_t);
126 static int sk_detach (device_t);
127 static int sk_detach_xmac (device_t);
128 static int sk_probe_xmac (device_t);
129 static int sk_attach_xmac (device_t);
130 static void sk_tick (void *);
131 static void sk_intr (void *);
132 static void sk_intr_xmac (struct sk_if_softc *);
133 static void sk_intr_bcom (struct sk_if_softc *);
134 static void sk_rxeof (struct sk_if_softc *);
135 static void sk_txeof (struct sk_if_softc *);
136 static int sk_encap (struct sk_if_softc *, struct mbuf *,
138 static void sk_start (struct ifnet *);
139 static int sk_ioctl (struct ifnet *, u_long, caddr_t);
140 static void sk_init (void *);
141 static void sk_init_xmac (struct sk_if_softc *);
142 static void sk_stop (struct sk_if_softc *);
143 static void sk_watchdog (struct ifnet *);
144 static void sk_shutdown (device_t);
145 static int sk_ifmedia_upd (struct ifnet *);
146 static void sk_ifmedia_sts (struct ifnet *, struct ifmediareq *);
147 static void sk_reset (struct sk_softc *);
148 static int sk_newbuf (struct sk_if_softc *,
149 struct sk_chain *, struct mbuf *);
150 static int sk_alloc_jumbo_mem (struct sk_if_softc *);
151 static void *sk_jalloc (struct sk_if_softc *);
152 static void sk_jfree (caddr_t, void *);
153 static int sk_init_rx_ring (struct sk_if_softc *);
154 static void sk_init_tx_ring (struct sk_if_softc *);
155 static u_int32_t sk_win_read_4 (struct sk_softc *, int);
156 static u_int16_t sk_win_read_2 (struct sk_softc *, int);
157 static u_int8_t sk_win_read_1 (struct sk_softc *, int);
158 static void sk_win_write_4 (struct sk_softc *, int, u_int32_t);
159 static void sk_win_write_2 (struct sk_softc *, int, u_int32_t);
160 static void sk_win_write_1 (struct sk_softc *, int, u_int32_t);
161 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int);
162 static void sk_vpd_read_res (struct sk_softc *, struct vpd_res *, int);
163 static void sk_vpd_read (struct sk_softc *);
165 static int sk_miibus_readreg (device_t, int, int);
166 static int sk_miibus_writereg (device_t, int, int, int);
167 static void sk_miibus_statchg (device_t);
169 static u_int32_t sk_calchash (caddr_t);
170 static void sk_setfilt (struct sk_if_softc *, caddr_t, int);
171 static void sk_setmulti (struct sk_if_softc *);
174 #define SK_RES SYS_RES_IOPORT
175 #define SK_RID SK_PCI_LOIO
177 #define SK_RES SYS_RES_MEMORY
178 #define SK_RID SK_PCI_LOMEM
182 * Note that we have newbus methods for both the GEnesis controller
183 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
184 * the miibus code is a child of the XMACs. We need to do it this way
185 * so that the miibus drivers can access the PHY registers on the
186 * right PHY. It's not quite what I had in mind, but it's the only
187 * design that achieves the desired effect.
189 static device_method_t skc_methods[] = {
190 /* Device interface */
191 DEVMETHOD(device_probe, sk_probe),
192 DEVMETHOD(device_attach, sk_attach),
193 DEVMETHOD(device_detach, sk_detach),
194 DEVMETHOD(device_shutdown, sk_shutdown),
197 DEVMETHOD(bus_print_child, bus_generic_print_child),
198 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
203 static driver_t skc_driver = {
206 sizeof(struct sk_softc)
209 static devclass_t skc_devclass;
211 static device_method_t sk_methods[] = {
212 /* Device interface */
213 DEVMETHOD(device_probe, sk_probe_xmac),
214 DEVMETHOD(device_attach, sk_attach_xmac),
215 DEVMETHOD(device_detach, sk_detach_xmac),
216 DEVMETHOD(device_shutdown, bus_generic_shutdown),
219 DEVMETHOD(bus_print_child, bus_generic_print_child),
220 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
223 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
224 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
225 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
230 static driver_t sk_driver = {
233 sizeof(struct sk_if_softc)
236 static devclass_t sk_devclass;
238 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
239 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, 0, 0);
240 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
242 #define SK_SETBIT(sc, reg, x) \
243 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
245 #define SK_CLRBIT(sc, reg, x) \
246 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
248 #define SK_WIN_SETBIT_4(sc, reg, x) \
249 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
251 #define SK_WIN_CLRBIT_4(sc, reg, x) \
252 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
254 #define SK_WIN_SETBIT_2(sc, reg, x) \
255 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
257 #define SK_WIN_CLRBIT_2(sc, reg, x) \
258 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
260 static u_int32_t sk_win_read_4(sc, reg)
264 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
265 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
268 static u_int16_t sk_win_read_2(sc, reg)
272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
273 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
276 static u_int8_t sk_win_read_1(sc, reg)
280 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
281 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
284 static void sk_win_write_4(sc, reg, val)
289 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
290 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
294 static void sk_win_write_2(sc, reg, val)
299 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
300 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), (u_int32_t)val);
304 static void sk_win_write_1(sc, reg, val)
309 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
310 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
315 * The VPD EEPROM contains Vital Product Data, as suggested in
316 * the PCI 2.1 specification. The VPD data is separared into areas
317 * denoted by resource IDs. The SysKonnect VPD contains an ID string
318 * resource (the name of the adapter), a read-only area resource
319 * containing various key/data fields and a read/write area which
320 * can be used to store asset management information or log messages.
321 * We read the ID string and read-only into buffers attached to
322 * the controller softc structure for later use. At the moment,
323 * we only use the ID string during sk_attach().
325 static u_int8_t sk_vpd_readbyte(sc, addr)
331 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
332 for (i = 0; i < SK_TIMEOUT; i++) {
334 if (sk_win_read_2(sc,
335 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
342 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
345 static void sk_vpd_read_res(sc, res, addr)
353 ptr = (u_int8_t *)res;
354 for (i = 0; i < sizeof(struct vpd_res); i++)
355 ptr[i] = sk_vpd_readbyte(sc, i + addr);
360 static void sk_vpd_read(sc)
366 if (sc->sk_vpd_prodname != NULL)
367 free(sc->sk_vpd_prodname, M_DEVBUF);
368 if (sc->sk_vpd_readonly != NULL)
369 free(sc->sk_vpd_readonly, M_DEVBUF);
370 sc->sk_vpd_prodname = NULL;
371 sc->sk_vpd_readonly = NULL;
373 sk_vpd_read_res(sc, &res, pos);
375 if (res.vr_id != VPD_RES_ID) {
376 printf("skc%d: bad VPD resource id: expected %x got %x\n",
377 sc->sk_unit, VPD_RES_ID, res.vr_id);
382 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
383 for (i = 0; i < res.vr_len; i++)
384 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
385 sc->sk_vpd_prodname[i] = '\0';
388 sk_vpd_read_res(sc, &res, pos);
390 if (res.vr_id != VPD_RES_READ) {
391 printf("skc%d: bad VPD resource id: expected %x got %x\n",
392 sc->sk_unit, VPD_RES_READ, res.vr_id);
397 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
398 for (i = 0; i < res.vr_len + 1; i++)
399 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
404 static int sk_miibus_readreg(dev, phy, reg)
408 struct sk_if_softc *sc_if;
411 sc_if = device_get_softc(dev);
413 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
418 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
419 SK_XM_READ_2(sc_if, XM_PHY_DATA);
420 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
421 for (i = 0; i < SK_TIMEOUT; i++) {
423 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
424 XM_MMUCMD_PHYDATARDY)
428 if (i == SK_TIMEOUT) {
429 printf("sk%d: phy failed to come ready\n",
435 i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
440 static int sk_miibus_writereg(dev, phy, reg, val)
444 struct sk_if_softc *sc_if;
447 sc_if = device_get_softc(dev);
450 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
451 for (i = 0; i < SK_TIMEOUT; i++) {
452 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
456 if (i == SK_TIMEOUT) {
457 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
461 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
462 for (i = 0; i < SK_TIMEOUT; i++) {
464 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
471 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
476 static void sk_miibus_statchg(dev)
479 struct sk_if_softc *sc_if;
480 struct mii_data *mii;
482 sc_if = device_get_softc(dev);
483 mii = device_get_softc(sc_if->sk_miibus);
486 * If this is a GMII PHY, manually set the XMAC's
487 * duplex mode accordingly.
489 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
490 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
491 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
493 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
501 #define SK_POLY 0xEDB88320
504 static u_int32_t sk_calchash(addr)
507 u_int32_t idx, bit, data, crc;
509 /* Compute CRC for the address value. */
510 crc = 0xFFFFFFFF; /* initial value */
512 for (idx = 0; idx < 6; idx++) {
513 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
514 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? SK_POLY : 0);
517 return (~crc & ((1 << SK_BITS) - 1));
520 static void sk_setfilt(sc_if, addr, slot)
521 struct sk_if_softc *sc_if;
527 base = XM_RXFILT_ENTRY(slot);
529 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
530 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
531 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
536 static void sk_setmulti(sc_if)
537 struct sk_if_softc *sc_if;
540 u_int32_t hashes[2] = { 0, 0 };
542 struct ifmultiaddr *ifma;
543 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
545 ifp = &sc_if->arpcom.ac_if;
547 /* First, zot all the existing filters. */
548 for (i = 1; i < XM_RXFILT_MAX; i++)
549 sk_setfilt(sc_if, (caddr_t)&dummy, i);
550 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
551 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
553 /* Now program new ones. */
554 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
555 hashes[0] = 0xFFFFFFFF;
556 hashes[1] = 0xFFFFFFFF;
559 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
560 if (ifma->ifma_addr->sa_family != AF_LINK)
563 * Program the first XM_RXFILT_MAX multicast groups
564 * into the perfect filter. For all others,
565 * use the hash table.
567 if (i < XM_RXFILT_MAX) {
569 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
575 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
577 hashes[0] |= (1 << h);
579 hashes[1] |= (1 << (h - 32));
583 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
584 XM_MODE_RX_USE_PERFECT);
585 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
586 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
591 static int sk_init_rx_ring(sc_if)
592 struct sk_if_softc *sc_if;
594 struct sk_chain_data *cd;
595 struct sk_ring_data *rd;
598 cd = &sc_if->sk_cdata;
599 rd = sc_if->sk_rdata;
601 bzero((char *)rd->sk_rx_ring,
602 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
604 for (i = 0; i < SK_RX_RING_CNT; i++) {
605 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
606 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
608 if (i == (SK_RX_RING_CNT - 1)) {
609 cd->sk_rx_chain[i].sk_next =
611 rd->sk_rx_ring[i].sk_next =
612 vtophys(&rd->sk_rx_ring[0]);
614 cd->sk_rx_chain[i].sk_next =
615 &cd->sk_rx_chain[i + 1];
616 rd->sk_rx_ring[i].sk_next =
617 vtophys(&rd->sk_rx_ring[i + 1]);
621 sc_if->sk_cdata.sk_rx_prod = 0;
622 sc_if->sk_cdata.sk_rx_cons = 0;
627 static void sk_init_tx_ring(sc_if)
628 struct sk_if_softc *sc_if;
630 struct sk_chain_data *cd;
631 struct sk_ring_data *rd;
634 cd = &sc_if->sk_cdata;
635 rd = sc_if->sk_rdata;
637 bzero((char *)sc_if->sk_rdata->sk_tx_ring,
638 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
640 for (i = 0; i < SK_TX_RING_CNT; i++) {
641 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
642 if (i == (SK_TX_RING_CNT - 1)) {
643 cd->sk_tx_chain[i].sk_next =
645 rd->sk_tx_ring[i].sk_next =
646 vtophys(&rd->sk_tx_ring[0]);
648 cd->sk_tx_chain[i].sk_next =
649 &cd->sk_tx_chain[i + 1];
650 rd->sk_tx_ring[i].sk_next =
651 vtophys(&rd->sk_tx_ring[i + 1]);
655 sc_if->sk_cdata.sk_tx_prod = 0;
656 sc_if->sk_cdata.sk_tx_cons = 0;
657 sc_if->sk_cdata.sk_tx_cnt = 0;
662 static int sk_newbuf(sc_if, c, m)
663 struct sk_if_softc *sc_if;
667 struct mbuf *m_new = NULL;
668 struct sk_rx_desc *r;
673 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
677 /* Allocate the jumbo buffer */
678 buf = sk_jalloc(sc_if);
682 printf("sk%d: jumbo allocation failed "
683 "-- packet dropped!\n", sc_if->sk_unit);
688 /* Attach the buffer to the mbuf */
689 MEXTADD(m_new, buf, SK_JLEN, sk_jfree,
690 (struct sk_if_softc *)sc_if, 0, EXT_NET_DRV);
691 m_new->m_data = (void *)buf;
692 m_new->m_pkthdr.len = m_new->m_len = SK_JLEN;
695 * We're re-using a previously allocated mbuf;
696 * be sure to re-init pointers and lengths to
700 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
701 m_new->m_data = m_new->m_ext.ext_buf;
705 * Adjust alignment so packet payload begins on a
706 * longword boundary. Mandatory for Alpha, useful on
709 m_adj(m_new, ETHER_ALIGN);
713 r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
714 r->sk_ctl = m_new->m_len | SK_RXSTAT;
720 * Allocate jumbo buffer storage. The SysKonnect adapters support
721 * "jumbograms" (9K frames), although SysKonnect doesn't currently
722 * use them in their drivers. In order for us to use them, we need
723 * large 9K receive buffers, however standard mbuf clusters are only
724 * 2048 bytes in size. Consequently, we need to allocate and manage
725 * our own jumbo buffer pool. Fortunately, this does not require an
726 * excessive amount of additional code.
728 static int sk_alloc_jumbo_mem(sc_if)
729 struct sk_if_softc *sc_if;
733 struct sk_jpool_entry *entry;
735 /* Grab a big chunk o' storage. */
736 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
737 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
739 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
740 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
744 SLIST_INIT(&sc_if->sk_jfree_listhead);
745 SLIST_INIT(&sc_if->sk_jinuse_listhead);
748 * Now divide it up into 9K pieces and save the addresses
751 ptr = sc_if->sk_cdata.sk_jumbo_buf;
752 for (i = 0; i < SK_JSLOTS; i++) {
753 sc_if->sk_cdata.sk_jslots[i] = ptr;
755 entry = malloc(sizeof(struct sk_jpool_entry),
758 free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF);
759 sc_if->sk_cdata.sk_jumbo_buf = NULL;
760 printf("sk%d: no memory for jumbo "
761 "buffer queue!\n", sc_if->sk_unit);
765 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
766 entry, jpool_entries);
773 * Allocate a jumbo buffer.
775 static void *sk_jalloc(sc_if)
776 struct sk_if_softc *sc_if;
778 struct sk_jpool_entry *entry;
780 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
784 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
789 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
790 SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
791 return(sc_if->sk_cdata.sk_jslots[entry->slot]);
795 * Release a jumbo buffer.
797 static void sk_jfree(buf, args)
801 struct sk_if_softc *sc_if;
803 struct sk_jpool_entry *entry;
805 /* Extract the softc struct pointer. */
806 sc_if = (struct sk_if_softc *)args;
809 panic("sk_jfree: didn't get softc pointer!");
811 /* calculate the slot this buffer belongs to */
812 i = ((vm_offset_t)buf
813 - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
815 if ((i < 0) || (i >= SK_JSLOTS))
816 panic("sk_jfree: asked to free buffer that we don't manage!");
818 entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
820 panic("sk_jfree: buffer not in use!");
822 SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead, jpool_entries);
823 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jpool_entries);
831 static int sk_ifmedia_upd(ifp)
834 struct sk_if_softc *sc_if;
835 struct mii_data *mii;
837 sc_if = ifp->if_softc;
838 mii = device_get_softc(sc_if->sk_miibus);
846 * Report current media status.
848 static void sk_ifmedia_sts(ifp, ifmr)
850 struct ifmediareq *ifmr;
852 struct sk_if_softc *sc_if;
853 struct mii_data *mii;
855 sc_if = ifp->if_softc;
856 mii = device_get_softc(sc_if->sk_miibus);
859 ifmr->ifm_active = mii->mii_media_active;
860 ifmr->ifm_status = mii->mii_media_status;
865 static int sk_ioctl(ifp, command, data)
870 struct sk_if_softc *sc_if = ifp->if_softc;
871 struct ifreq *ifr = (struct ifreq *) data;
873 struct mii_data *mii;
880 error = ether_ioctl(ifp, command, data);
883 if (ifr->ifr_mtu > SK_JUMBO_MTU)
886 ifp->if_mtu = ifr->ifr_mtu;
891 if (ifp->if_flags & IFF_UP) {
892 if (ifp->if_flags & IFF_RUNNING &&
893 ifp->if_flags & IFF_PROMISC &&
894 !(sc_if->sk_if_flags & IFF_PROMISC)) {
895 SK_XM_SETBIT_4(sc_if, XM_MODE,
898 } else if (ifp->if_flags & IFF_RUNNING &&
899 !(ifp->if_flags & IFF_PROMISC) &&
900 sc_if->sk_if_flags & IFF_PROMISC) {
901 SK_XM_CLRBIT_4(sc_if, XM_MODE,
907 if (ifp->if_flags & IFF_RUNNING)
910 sc_if->sk_if_flags = ifp->if_flags;
920 mii = device_get_softc(sc_if->sk_miibus);
921 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
934 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
935 * IDs against our list and return a device name if we find a match.
937 static int sk_probe(dev)
944 while(t->sk_name != NULL) {
945 if ((pci_get_vendor(dev) == t->sk_vid) &&
946 (pci_get_device(dev) == t->sk_did)) {
947 device_set_desc(dev, t->sk_name);
957 * Force the GEnesis into reset, then bring it out of reset.
959 static void sk_reset(sc)
962 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_RESET);
963 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_RESET);
965 CSR_WRITE_4(sc, SK_CSR, SK_CSR_SW_UNRESET);
966 CSR_WRITE_4(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
968 /* Configure packet arbiter */
969 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
970 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
971 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
972 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
973 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
975 /* Enable RAM interface */
976 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
979 * Configure interrupt moderation. The moderation timer
980 * defers interrupts specified in the interrupt moderation
981 * timer mask based on the timeout specified in the interrupt
982 * moderation timer init register. Each bit in the timer
983 * register represents 18.825ns, so to specify a timeout in
984 * microseconds, we have to multiply by 54.
986 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
987 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
988 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
989 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
994 static int sk_probe_xmac(dev)
998 * Not much to do here. We always know there will be
999 * at least one XMAC present, and if there are two,
1000 * sk_attach() will create a second device instance
1003 device_set_desc(dev, "XaQti Corp. XMAC II");
1009 * Each XMAC chip is attached as a separate logical IP interface.
1010 * Single port cards will have only one logical interface of course.
1012 static int sk_attach_xmac(dev)
1015 struct sk_softc *sc;
1016 struct sk_if_softc *sc_if;
1023 sc_if = device_get_softc(dev);
1024 sc = device_get_softc(device_get_parent(dev));
1026 port = *(int *)device_get_ivars(dev);
1027 free(device_get_ivars(dev), M_DEVBUF);
1028 device_set_ivars(dev, NULL);
1029 sc_if->sk_dev = dev;
1031 bzero((char *)sc_if, sizeof(struct sk_if_softc));
1033 sc_if->sk_dev = dev;
1034 sc_if->sk_unit = device_get_unit(dev);
1035 sc_if->sk_port = port;
1036 sc_if->sk_softc = sc;
1037 sc->sk_if[port] = sc_if;
1038 if (port == SK_PORT_A)
1039 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1040 if (port == SK_PORT_B)
1041 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1044 * Get station address for this interface. Note that
1045 * dual port cards actually come with three station
1046 * addresses: one for each port, plus an extra. The
1047 * extra one is used by the SysKonnect driver software
1048 * as a 'virtual' station address for when both ports
1049 * are operating in failover mode. Currently we don't
1050 * use this extra address.
1052 for (i = 0; i < ETHER_ADDR_LEN; i++)
1053 sc_if->arpcom.ac_enaddr[i] =
1054 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1056 printf("sk%d: Ethernet address: %6D\n",
1057 sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":");
1060 * Set up RAM buffer addresses. The NIC will have a certain
1061 * amount of SRAM on it, somewhere between 512K and 2MB. We
1062 * need to divide this up a) between the transmitter and
1063 * receiver and b) between the two XMACs, if this is a
1064 * dual port NIC. Our algotithm is to divide up the memory
1065 * evenly so that everyone gets a fair share.
1067 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1068 u_int32_t chunk, val;
1070 chunk = sc->sk_ramsize / 2;
1071 val = sc->sk_rboff / sizeof(u_int64_t);
1072 sc_if->sk_rx_ramstart = val;
1073 val += (chunk / sizeof(u_int64_t));
1074 sc_if->sk_rx_ramend = val - 1;
1075 sc_if->sk_tx_ramstart = val;
1076 val += (chunk / sizeof(u_int64_t));
1077 sc_if->sk_tx_ramend = val - 1;
1079 u_int32_t chunk, val;
1081 chunk = sc->sk_ramsize / 4;
1082 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1084 sc_if->sk_rx_ramstart = val;
1085 val += (chunk / sizeof(u_int64_t));
1086 sc_if->sk_rx_ramend = val - 1;
1087 sc_if->sk_tx_ramstart = val;
1088 val += (chunk / sizeof(u_int64_t));
1089 sc_if->sk_tx_ramend = val - 1;
1092 /* Read and save PHY type and set PHY address */
1093 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1094 switch(sc_if->sk_phytype) {
1095 case SK_PHYTYPE_XMAC:
1096 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1098 case SK_PHYTYPE_BCOM:
1099 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1102 printf("skc%d: unsupported PHY type: %d\n",
1103 sc->sk_unit, sc_if->sk_phytype);
1108 /* Allocate the descriptor queues. */
1109 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1110 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1112 if (sc_if->sk_rdata == NULL) {
1113 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1114 sc->sk_if[port] = NULL;
1119 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1121 /* Try to allocate memory for jumbo buffers. */
1122 if (sk_alloc_jumbo_mem(sc_if)) {
1123 printf("sk%d: jumbo buffer allocation failed\n",
1125 contigfree(sc_if->sk_rdata,
1126 sizeof(struct sk_ring_data), M_DEVBUF);
1127 sc->sk_if[port] = NULL;
1132 ifp = &sc_if->arpcom.ac_if;
1133 ifp->if_softc = sc_if;
1134 ifp->if_unit = sc_if->sk_unit;
1135 ifp->if_name = "sk";
1136 ifp->if_mtu = ETHERMTU;
1137 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1138 ifp->if_ioctl = sk_ioctl;
1139 ifp->if_output = ether_output;
1140 ifp->if_start = sk_start;
1141 ifp->if_watchdog = sk_watchdog;
1142 ifp->if_init = sk_init;
1143 ifp->if_baudrate = 1000000000;
1144 ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1;
1147 * Call MI attach routine.
1149 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1150 callout_handle_init(&sc_if->sk_tick_ch);
1155 sk_init_xmac(sc_if);
1156 if (mii_phy_probe(dev, &sc_if->sk_miibus,
1157 sk_ifmedia_upd, sk_ifmedia_sts)) {
1158 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1159 contigfree(sc_if->sk_rdata,
1160 sizeof(struct sk_ring_data), M_DEVBUF);
1161 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1172 * Attach the interface. Allocate softc structures, do ifmedia
1173 * setup and ethernet/BPF attach.
1175 static int sk_attach(dev)
1179 struct sk_softc *sc;
1180 int unit, error = 0, rid, *port;
1182 sc = device_get_softc(dev);
1183 unit = device_get_unit(dev);
1184 bzero(sc, sizeof(struct sk_softc));
1186 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
1190 * Handle power management nonsense.
1192 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1193 u_int32_t iobase, membase, irq;
1195 /* Save important PCI config data. */
1196 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1197 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1198 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1200 /* Reset the power state. */
1201 printf("skc%d: chip is in D%d power mode "
1202 "-- setting to D0\n", unit,
1203 pci_get_powerstate(dev));
1204 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1206 /* Restore PCI config data. */
1207 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1208 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1209 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1213 * Map control/status registers.
1215 pci_enable_busmaster(dev);
1216 pci_enable_io(dev, SYS_RES_IOPORT);
1217 pci_enable_io(dev, SYS_RES_MEMORY);
1218 command = pci_read_config(dev, PCIR_COMMAND, 4);
1220 #ifdef SK_USEIOSPACE
1221 if (!(command & PCIM_CMD_PORTEN)) {
1222 printf("skc%d: failed to enable I/O ports!\n", unit);
1227 if (!(command & PCIM_CMD_MEMEN)) {
1228 printf("skc%d: failed to enable memory mapping!\n", unit);
1235 sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid,
1236 0, ~0, 1, RF_ACTIVE);
1238 if (sc->sk_res == NULL) {
1239 printf("sk%d: couldn't map ports/memory\n", unit);
1244 sc->sk_btag = rman_get_bustag(sc->sk_res);
1245 sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1247 /* Allocate interrupt */
1249 sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1250 RF_SHAREABLE | RF_ACTIVE);
1252 if (sc->sk_irq == NULL) {
1253 printf("skc%d: couldn't map interrupt\n", unit);
1254 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1259 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1260 sk_intr, sc, &sc->sk_intrhand);
1263 printf("skc%d: couldn't set up irq\n", unit);
1264 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1265 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1269 /* Reset the adapter. */
1274 /* Read and save vital product data from EEPROM. */
1277 /* Read and save RAM size and RAMbuffer offset */
1278 switch(sk_win_read_1(sc, SK_EPROM0)) {
1279 case SK_RAMSIZE_512K_64:
1280 sc->sk_ramsize = 0x80000;
1281 sc->sk_rboff = SK_RBOFF_0;
1283 case SK_RAMSIZE_1024K_64:
1284 sc->sk_ramsize = 0x100000;
1285 sc->sk_rboff = SK_RBOFF_80000;
1287 case SK_RAMSIZE_1024K_128:
1288 sc->sk_ramsize = 0x100000;
1289 sc->sk_rboff = SK_RBOFF_0;
1291 case SK_RAMSIZE_2048K_128:
1292 sc->sk_ramsize = 0x200000;
1293 sc->sk_rboff = SK_RBOFF_0;
1296 printf("skc%d: unknown ram size: %d\n",
1297 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1298 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1299 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1300 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1306 /* Read and save physical media type */
1307 switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1308 case SK_PMD_1000BASESX:
1309 sc->sk_pmd = IFM_1000_SX;
1311 case SK_PMD_1000BASELX:
1312 sc->sk_pmd = IFM_1000_LX;
1314 case SK_PMD_1000BASECX:
1315 sc->sk_pmd = IFM_1000_CX;
1317 case SK_PMD_1000BASETX:
1318 sc->sk_pmd = IFM_1000_TX;
1321 printf("skc%d: unknown media type: 0x%x\n",
1322 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1323 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1324 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1325 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1330 /* Announce the product name. */
1331 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1332 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1333 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1335 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1337 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1338 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1339 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1341 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1344 /* Turn on the 'driver is loaded' LED. */
1345 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1347 bus_generic_attach(dev);
1353 mtx_destroy(&sc->sk_mtx);
1357 static int sk_detach_xmac(dev)
1360 struct sk_softc *sc;
1361 struct sk_if_softc *sc_if;
1364 sc = device_get_softc(device_get_parent(dev));
1365 sc_if = device_get_softc(dev);
1368 ifp = &sc_if->arpcom.ac_if;
1370 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1371 bus_generic_detach(dev);
1372 if (sc_if->sk_miibus != NULL)
1373 device_delete_child(dev, sc_if->sk_miibus);
1374 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1375 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1376 SK_IF_UNLOCK(sc_if);
1381 static int sk_detach(dev)
1384 struct sk_softc *sc;
1386 sc = device_get_softc(dev);
1389 bus_generic_detach(dev);
1390 if (sc->sk_devs[SK_PORT_A] != NULL)
1391 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1392 if (sc->sk_devs[SK_PORT_B] != NULL)
1393 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1395 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1396 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1397 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1400 mtx_destroy(&sc->sk_mtx);
1405 static int sk_encap(sc_if, m_head, txidx)
1406 struct sk_if_softc *sc_if;
1407 struct mbuf *m_head;
1410 struct sk_tx_desc *f = NULL;
1412 u_int32_t frag, cur, cnt = 0;
1415 cur = frag = *txidx;
1418 * Start packing the mbufs in this chain into
1419 * the fragment pointers. Stop when we run out
1420 * of fragments or hit the end of the mbuf chain.
1422 for (m = m_head; m != NULL; m = m->m_next) {
1423 if (m->m_len != 0) {
1424 if ((SK_TX_RING_CNT -
1425 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1427 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1428 f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1429 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1431 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1433 f->sk_ctl |= SK_TXCTL_OWN;
1435 SK_INC(frag, SK_TX_RING_CNT);
1443 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1444 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1445 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1446 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1447 sc_if->sk_cdata.sk_tx_cnt += cnt;
1454 static void sk_start(ifp)
1457 struct sk_softc *sc;
1458 struct sk_if_softc *sc_if;
1459 struct mbuf *m_head = NULL;
1462 sc_if = ifp->if_softc;
1463 sc = sc_if->sk_softc;
1467 idx = sc_if->sk_cdata.sk_tx_prod;
1469 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1470 IF_DEQUEUE(&ifp->if_snd, m_head);
1475 * Pack the data into the transmit ring. If we
1476 * don't have room, set the OACTIVE flag and wait
1477 * for the NIC to drain the ring.
1479 if (sk_encap(sc_if, m_head, &idx)) {
1480 IF_PREPEND(&ifp->if_snd, m_head);
1481 ifp->if_flags |= IFF_OACTIVE;
1486 * If there's a BPF listener, bounce a copy of this frame
1490 bpf_mtap(ifp, m_head);
1494 sc_if->sk_cdata.sk_tx_prod = idx;
1495 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1497 /* Set a timeout in case the chip goes out to lunch. */
1499 SK_IF_UNLOCK(sc_if);
1505 static void sk_watchdog(ifp)
1508 struct sk_if_softc *sc_if;
1510 sc_if = ifp->if_softc;
1512 printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1518 static void sk_shutdown(dev)
1521 struct sk_softc *sc;
1523 sc = device_get_softc(dev);
1526 /* Turn off the 'driver is loaded' LED. */
1527 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1530 * Reset the GEnesis controller. Doing this should also
1531 * assert the resets on the attached XMAC(s).
1539 static void sk_rxeof(sc_if)
1540 struct sk_if_softc *sc_if;
1542 struct ether_header *eh;
1545 struct sk_chain *cur_rx;
1550 ifp = &sc_if->arpcom.ac_if;
1551 i = sc_if->sk_cdata.sk_rx_prod;
1552 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1554 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1556 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1557 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1558 m = cur_rx->sk_mbuf;
1559 cur_rx->sk_mbuf = NULL;
1560 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1561 SK_INC(i, SK_RX_RING_CNT);
1563 if (rxstat & XM_RXSTAT_ERRFRAME) {
1565 sk_newbuf(sc_if, cur_rx, m);
1570 * Try to allocate a new jumbo buffer. If that
1571 * fails, copy the packet to mbufs and put the
1572 * jumbo buffer back in the ring so it can be
1573 * re-used. If allocating mbufs fails, then we
1574 * have to drop the packet.
1576 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1578 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
1580 sk_newbuf(sc_if, cur_rx, m);
1582 printf("sk%d: no receive buffers "
1583 "available -- packet dropped!\n",
1590 m->m_pkthdr.rcvif = ifp;
1591 m->m_pkthdr.len = m->m_len = total_len;
1595 eh = mtod(m, struct ether_header *);
1597 /* Remove header from mbuf and pass it on. */
1598 m_adj(m, sizeof(struct ether_header));
1599 ether_input(ifp, eh, m);
1602 sc_if->sk_cdata.sk_rx_prod = i;
1607 static void sk_txeof(sc_if)
1608 struct sk_if_softc *sc_if;
1610 struct sk_tx_desc *cur_tx = NULL;
1614 ifp = &sc_if->arpcom.ac_if;
1617 * Go through our tx ring and free mbufs for those
1618 * frames that have been sent.
1620 idx = sc_if->sk_cdata.sk_tx_cons;
1621 while(idx != sc_if->sk_cdata.sk_tx_prod) {
1622 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1623 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
1625 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
1627 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
1628 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
1629 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
1631 sc_if->sk_cdata.sk_tx_cnt--;
1632 SK_INC(idx, SK_TX_RING_CNT);
1636 sc_if->sk_cdata.sk_tx_cons = idx;
1639 ifp->if_flags &= ~IFF_OACTIVE;
1644 static void sk_tick(xsc_if)
1647 struct sk_if_softc *sc_if;
1648 struct mii_data *mii;
1654 ifp = &sc_if->arpcom.ac_if;
1655 mii = device_get_softc(sc_if->sk_miibus);
1657 if (!(ifp->if_flags & IFF_UP)) {
1658 SK_IF_UNLOCK(sc_if);
1662 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1663 sk_intr_bcom(sc_if);
1664 SK_IF_UNLOCK(sc_if);
1669 * According to SysKonnect, the correct way to verify that
1670 * the link has come back up is to poll bit 0 of the GPIO
1671 * register three times. This pin has the signal from the
1672 * link_sync pin connected to it; if we read the same link
1673 * state 3 times in a row, we know the link is up.
1675 for (i = 0; i < 3; i++) {
1676 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
1681 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1682 SK_IF_UNLOCK(sc_if);
1686 /* Turn the GP0 interrupt back on. */
1687 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1688 SK_XM_READ_2(sc_if, XM_ISR);
1690 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
1692 SK_IF_UNLOCK(sc_if);
1696 static void sk_intr_bcom(sc_if)
1697 struct sk_if_softc *sc_if;
1699 struct sk_softc *sc;
1700 struct mii_data *mii;
1704 sc = sc_if->sk_softc;
1705 mii = device_get_softc(sc_if->sk_miibus);
1706 ifp = &sc_if->arpcom.ac_if;
1708 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1711 * Read the PHY interrupt register to make sure
1712 * we clear any pending interrupts.
1714 status = sk_miibus_readreg(sc_if->sk_dev,
1715 SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
1717 if (!(ifp->if_flags & IFF_RUNNING)) {
1718 sk_init_xmac(sc_if);
1722 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
1724 lstat = sk_miibus_readreg(sc_if->sk_dev,
1725 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS);
1727 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
1729 /* Turn off the link LED. */
1730 SK_IF_WRITE_1(sc_if, 0,
1731 SK_LINKLED1_CTL, SK_LINKLED_OFF);
1733 } else if (status & BRGPHY_ISR_LNK_CHG) {
1734 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM,
1735 BRGPHY_MII_IMR, 0xFF00);
1738 /* Turn on the link LED. */
1739 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
1740 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
1741 SK_LINKLED_BLINK_OFF);
1744 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1748 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1753 static void sk_intr_xmac(sc_if)
1754 struct sk_if_softc *sc_if;
1756 struct sk_softc *sc;
1758 struct mii_data *mii;
1760 sc = sc_if->sk_softc;
1761 mii = device_get_softc(sc_if->sk_miibus);
1762 status = SK_XM_READ_2(sc_if, XM_ISR);
1765 * Link has gone down. Start MII tick timeout to
1766 * watch for link resync.
1768 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
1769 if (status & XM_ISR_GP0_SET) {
1770 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1771 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1774 if (status & XM_ISR_AUTONEG_DONE) {
1775 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
1779 if (status & XM_IMR_TX_UNDERRUN)
1780 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
1782 if (status & XM_IMR_RX_OVERRUN)
1783 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
1785 status = SK_XM_READ_2(sc_if, XM_ISR);
1790 static void sk_intr(xsc)
1793 struct sk_softc *sc = xsc;
1794 struct sk_if_softc *sc_if0 = NULL, *sc_if1 = NULL;
1795 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
1800 sc_if0 = sc->sk_if[SK_PORT_A];
1801 sc_if1 = sc->sk_if[SK_PORT_B];
1804 ifp0 = &sc_if0->arpcom.ac_if;
1806 ifp1 = &sc_if1->arpcom.ac_if;
1809 status = CSR_READ_4(sc, SK_ISSR);
1810 if (!(status & sc->sk_intrmask))
1813 /* Handle receive interrupts first. */
1814 if (status & SK_ISR_RX1_EOF) {
1816 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
1817 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1819 if (status & SK_ISR_RX2_EOF) {
1821 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
1822 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1825 /* Then transmit interrupts. */
1826 if (status & SK_ISR_TX1_S_EOF) {
1828 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
1829 SK_TXBMU_CLR_IRQ_EOF);
1831 if (status & SK_ISR_TX2_S_EOF) {
1833 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
1834 SK_TXBMU_CLR_IRQ_EOF);
1837 /* Then MAC interrupts. */
1838 if (status & SK_ISR_MAC1 &&
1839 ifp0->if_flags & IFF_RUNNING)
1840 sk_intr_xmac(sc_if0);
1842 if (status & SK_ISR_MAC2 &&
1843 ifp1->if_flags & IFF_RUNNING)
1844 sk_intr_xmac(sc_if1);
1846 if (status & SK_ISR_EXTERNAL_REG) {
1848 sk_intr_bcom(sc_if0);
1850 sk_intr_bcom(sc_if1);
1854 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
1856 if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL)
1858 if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL)
1866 static void sk_init_xmac(sc_if)
1867 struct sk_if_softc *sc_if;
1869 struct sk_softc *sc;
1871 struct sk_bcom_hack bhack[] = {
1872 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
1873 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
1874 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1877 sc = sc_if->sk_softc;
1878 ifp = &sc_if->arpcom.ac_if;
1880 /* Unreset the XMAC. */
1881 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
1884 /* Reset the XMAC's internal state. */
1885 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
1887 /* Save the XMAC II revision */
1888 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
1891 * Perform additional initialization for external PHYs,
1892 * namely for the 1000baseTX cards that use the XMAC's
1895 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1899 /* Take PHY out of reset. */
1900 val = sk_win_read_4(sc, SK_GPIO);
1901 if (sc_if->sk_port == SK_PORT_A)
1902 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
1904 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
1905 sk_win_write_4(sc, SK_GPIO, val);
1907 /* Enable GMII mode on the XMAC. */
1908 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
1910 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM,
1911 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
1913 sk_miibus_writereg(sc_if->sk_dev, SK_PHYADDR_BCOM,
1914 BRGPHY_MII_IMR, 0xFFF0);
1917 * Early versions of the BCM5400 apparently have
1918 * a bug that requires them to have their reserved
1919 * registers initialized to some magic values. I don't
1920 * know what the numbers do, I'm just the messenger.
1922 if (sk_miibus_readreg(sc_if->sk_dev,
1923 SK_PHYADDR_BCOM, 0x03) == 0x6041) {
1924 while(bhack[i].reg) {
1925 sk_miibus_writereg(sc_if->sk_dev,
1926 SK_PHYADDR_BCOM, bhack[i].reg,
1933 /* Set station address */
1934 SK_XM_WRITE_2(sc_if, XM_PAR0,
1935 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]));
1936 SK_XM_WRITE_2(sc_if, XM_PAR1,
1937 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]));
1938 SK_XM_WRITE_2(sc_if, XM_PAR2,
1939 *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]));
1940 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
1942 if (ifp->if_flags & IFF_PROMISC) {
1943 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
1945 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
1948 if (ifp->if_flags & IFF_BROADCAST) {
1949 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
1951 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
1954 /* We don't need the FCS appended to the packet. */
1955 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
1957 /* We want short frames padded to 60 bytes. */
1958 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
1961 * Enable the reception of all error frames. This is is
1962 * a necessary evil due to the design of the XMAC. The
1963 * XMAC's receive FIFO is only 8K in size, however jumbo
1964 * frames can be up to 9000 bytes in length. When bad
1965 * frame filtering is enabled, the XMAC's RX FIFO operates
1966 * in 'store and forward' mode. For this to work, the
1967 * entire frame has to fit into the FIFO, but that means
1968 * that jumbo frames larger than 8192 bytes will be
1969 * truncated. Disabling all bad frame filtering causes
1970 * the RX FIFO to operate in streaming mode, in which
1971 * case the XMAC will start transfering frames out of the
1972 * RX FIFO as soon as the FIFO threshold is reached.
1974 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
1975 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
1976 XM_MODE_RX_INRANGELEN);
1978 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1979 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
1981 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
1984 * Bump up the transmit threshold. This helps hold off transmit
1985 * underruns when we're blasting traffic from both ports at once.
1987 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
1989 /* Set multicast filter */
1992 /* Clear and enable interrupts */
1993 SK_XM_READ_2(sc_if, XM_ISR);
1994 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1995 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
1997 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
1999 /* Configure MAC arbiter */
2000 switch(sc_if->sk_xmac_rev) {
2001 case XM_XMAC_REV_B2:
2002 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2003 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2004 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2005 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2006 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2007 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2008 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2009 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2010 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2012 case XM_XMAC_REV_C1:
2013 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2014 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2015 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2016 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2017 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2018 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2019 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2020 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2021 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2026 sk_win_write_2(sc, SK_MACARB_CTL,
2027 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2035 * Note that to properly initialize any part of the GEnesis chip,
2036 * you first have to take it out of reset mode.
2038 static void sk_init(xsc)
2041 struct sk_if_softc *sc_if = xsc;
2042 struct sk_softc *sc;
2044 struct mii_data *mii;
2048 ifp = &sc_if->arpcom.ac_if;
2049 sc = sc_if->sk_softc;
2050 mii = device_get_softc(sc_if->sk_miibus);
2052 /* Cancel pending I/O and free all RX/TX buffers. */
2055 /* Configure LINK_SYNC LED */
2056 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2057 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_ON);
2059 /* Configure RX LED */
2060 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_START);
2062 /* Configure TX LED */
2063 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_TXLEDCTL_COUNTER_START);
2065 /* Configure I2C registers */
2067 /* Configure XMAC(s) */
2068 sk_init_xmac(sc_if);
2071 /* Configure MAC FIFOs */
2072 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2073 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2074 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2076 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2077 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2078 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2080 /* Configure transmit arbiter(s) */
2081 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2082 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2084 /* Configure RAMbuffers */
2085 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2086 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2087 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2088 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2089 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2090 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2092 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2093 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2094 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2095 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2096 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2097 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2098 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2100 /* Configure BMUs */
2101 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2102 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2103 vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2104 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2106 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2107 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2108 vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2109 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2111 /* Init descriptors */
2112 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2113 printf("sk%d: initialization failed: no "
2114 "memory for rx buffers\n", sc_if->sk_unit);
2116 SK_IF_UNLOCK(sc_if);
2119 sk_init_tx_ring(sc_if);
2121 /* Configure interrupt handling */
2122 CSR_READ_4(sc, SK_ISSR);
2123 if (sc_if->sk_port == SK_PORT_A)
2124 sc->sk_intrmask |= SK_INTRS1;
2126 sc->sk_intrmask |= SK_INTRS2;
2128 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2130 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2133 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2135 /* Enable XMACs TX and RX state machines */
2136 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2137 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2139 ifp->if_flags |= IFF_RUNNING;
2140 ifp->if_flags &= ~IFF_OACTIVE;
2142 SK_IF_UNLOCK(sc_if);
2147 static void sk_stop(sc_if)
2148 struct sk_if_softc *sc_if;
2151 struct sk_softc *sc;
2155 sc = sc_if->sk_softc;
2156 ifp = &sc_if->arpcom.ac_if;
2158 untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2160 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2163 /* Put PHY back into reset. */
2164 val = sk_win_read_4(sc, SK_GPIO);
2165 if (sc_if->sk_port == SK_PORT_A) {
2166 val |= SK_GPIO_DIR0;
2167 val &= ~SK_GPIO_DAT0;
2169 val |= SK_GPIO_DIR2;
2170 val &= ~SK_GPIO_DAT2;
2172 sk_win_write_4(sc, SK_GPIO, val);
2175 /* Turn off various components of this interface. */
2176 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2177 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2178 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2179 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2180 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2181 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2182 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2183 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2184 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2185 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2186 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2187 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2189 /* Disable interrupts */
2190 if (sc_if->sk_port == SK_PORT_A)
2191 sc->sk_intrmask &= ~SK_INTRS1;
2193 sc->sk_intrmask &= ~SK_INTRS2;
2194 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2196 SK_XM_READ_2(sc_if, XM_ISR);
2197 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2199 /* Free RX and TX mbufs still in the queues. */
2200 for (i = 0; i < SK_RX_RING_CNT; i++) {
2201 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2202 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2203 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2207 for (i = 0; i < SK_TX_RING_CNT; i++) {
2208 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2209 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2210 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2214 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2215 SK_IF_UNLOCK(sc_if);