2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
44 #include <net/if_arp.h>
45 #include <net/ethernet.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
51 #include <vm/vm.h> /* for vtophys */
52 #include <vm/pmap.h> /* for vtophys */
53 #include <machine/bus_memio.h>
54 #include <machine/bus_pio.h>
55 #include <machine/bus.h>
56 #include <machine/resource.h>
60 #include <dev/mii/mii.h>
61 #include <dev/mii/miivar.h>
63 #include <pci/pcireg.h>
64 #include <pci/pcivar.h>
66 /* "controller miibus0" required. See GENERIC if you get errors here. */
67 #include "miibus_if.h"
69 #define STE_USEIOSPACE
71 #include <pci/if_stereg.h>
73 MODULE_DEPEND(ste, miibus, 1, 1, 1);
76 static const char rcsid[] =
81 * Various supported device vendors/types and their names.
83 static struct ste_type ste_devs[] = {
84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
85 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" },
89 static int ste_probe __P((device_t));
90 static int ste_attach __P((device_t));
91 static int ste_detach __P((device_t));
92 static void ste_init __P((void *));
93 static void ste_intr __P((void *));
94 static void ste_rxeof __P((struct ste_softc *));
95 static void ste_txeoc __P((struct ste_softc *));
96 static void ste_txeof __P((struct ste_softc *));
97 static void ste_stats_update __P((void *));
98 static void ste_stop __P((struct ste_softc *));
99 static void ste_reset __P((struct ste_softc *));
100 static int ste_ioctl __P((struct ifnet *, u_long, caddr_t));
101 static int ste_encap __P((struct ste_softc *, struct ste_chain *,
103 static void ste_start __P((struct ifnet *));
104 static void ste_watchdog __P((struct ifnet *));
105 static void ste_shutdown __P((device_t));
106 static int ste_newbuf __P((struct ste_softc *,
107 struct ste_chain_onefrag *,
109 static int ste_ifmedia_upd __P((struct ifnet *));
110 static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
112 static void ste_mii_sync __P((struct ste_softc *));
113 static void ste_mii_send __P((struct ste_softc *, u_int32_t, int));
114 static int ste_mii_readreg __P((struct ste_softc *,
115 struct ste_mii_frame *));
116 static int ste_mii_writereg __P((struct ste_softc *,
117 struct ste_mii_frame *));
118 static int ste_miibus_readreg __P((device_t, int, int));
119 static int ste_miibus_writereg __P((device_t, int, int, int));
120 static void ste_miibus_statchg __P((device_t));
122 static int ste_eeprom_wait __P((struct ste_softc *));
123 static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int,
125 static void ste_wait __P((struct ste_softc *));
126 static u_int8_t ste_calchash __P((caddr_t));
127 static void ste_setmulti __P((struct ste_softc *));
128 static int ste_init_rx_list __P((struct ste_softc *));
129 static void ste_init_tx_list __P((struct ste_softc *));
131 #ifdef STE_USEIOSPACE
132 #define STE_RES SYS_RES_IOPORT
133 #define STE_RID STE_PCI_LOIO
135 #define STE_RES SYS_RES_MEMORY
136 #define STE_RID STE_PCI_LOMEM
139 static device_method_t ste_methods[] = {
140 /* Device interface */
141 DEVMETHOD(device_probe, ste_probe),
142 DEVMETHOD(device_attach, ste_attach),
143 DEVMETHOD(device_detach, ste_detach),
144 DEVMETHOD(device_shutdown, ste_shutdown),
147 DEVMETHOD(bus_print_child, bus_generic_print_child),
148 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
151 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
152 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
153 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
158 static driver_t ste_driver = {
161 sizeof(struct ste_softc)
164 static devclass_t ste_devclass;
166 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0);
167 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
169 #define STE_SETBIT4(sc, reg, x) \
170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
172 #define STE_CLRBIT4(sc, reg, x) \
173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
175 #define STE_SETBIT2(sc, reg, x) \
176 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
178 #define STE_CLRBIT2(sc, reg, x) \
179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
181 #define STE_SETBIT1(sc, reg, x) \
182 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
184 #define STE_CLRBIT1(sc, reg, x) \
185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
188 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
189 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
192 * Sync the PHYs by setting data bit and strobing the clock 32 times.
194 static void ste_mii_sync(sc)
195 struct ste_softc *sc;
199 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
201 for (i = 0; i < 32; i++) {
202 MII_SET(STE_PHYCTL_MCLK);
204 MII_CLR(STE_PHYCTL_MCLK);
212 * Clock a series of bits through the MII.
214 static void ste_mii_send(sc, bits, cnt)
215 struct ste_softc *sc;
221 MII_CLR(STE_PHYCTL_MCLK);
223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
225 MII_SET(STE_PHYCTL_MDATA);
227 MII_CLR(STE_PHYCTL_MDATA);
230 MII_CLR(STE_PHYCTL_MCLK);
232 MII_SET(STE_PHYCTL_MCLK);
237 * Read an PHY register through the MII.
239 static int ste_mii_readreg(sc, frame)
240 struct ste_softc *sc;
241 struct ste_mii_frame *frame;
249 * Set up frame for RX.
251 frame->mii_stdelim = STE_MII_STARTDELIM;
252 frame->mii_opcode = STE_MII_READOP;
253 frame->mii_turnaround = 0;
256 CSR_WRITE_2(sc, STE_PHYCTL, 0);
260 MII_SET(STE_PHYCTL_MDIR);
265 * Send command/address info.
267 ste_mii_send(sc, frame->mii_stdelim, 2);
268 ste_mii_send(sc, frame->mii_opcode, 2);
269 ste_mii_send(sc, frame->mii_phyaddr, 5);
270 ste_mii_send(sc, frame->mii_regaddr, 5);
273 MII_CLR(STE_PHYCTL_MDIR);
276 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
278 MII_SET(STE_PHYCTL_MCLK);
282 MII_CLR(STE_PHYCTL_MCLK);
284 MII_SET(STE_PHYCTL_MCLK);
286 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
289 * Now try reading data bits. If the ack failed, we still
290 * need to clock through 16 cycles to keep the PHY(s) in sync.
293 for(i = 0; i < 16; i++) {
294 MII_CLR(STE_PHYCTL_MCLK);
296 MII_SET(STE_PHYCTL_MCLK);
302 for (i = 0x8000; i; i >>= 1) {
303 MII_CLR(STE_PHYCTL_MCLK);
306 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
307 frame->mii_data |= i;
310 MII_SET(STE_PHYCTL_MCLK);
316 MII_CLR(STE_PHYCTL_MCLK);
318 MII_SET(STE_PHYCTL_MCLK);
329 * Write to a PHY register through the MII.
331 static int ste_mii_writereg(sc, frame)
332 struct ste_softc *sc;
333 struct ste_mii_frame *frame;
339 * Set up frame for TX.
342 frame->mii_stdelim = STE_MII_STARTDELIM;
343 frame->mii_opcode = STE_MII_WRITEOP;
344 frame->mii_turnaround = STE_MII_TURNAROUND;
347 * Turn on data output.
349 MII_SET(STE_PHYCTL_MDIR);
353 ste_mii_send(sc, frame->mii_stdelim, 2);
354 ste_mii_send(sc, frame->mii_opcode, 2);
355 ste_mii_send(sc, frame->mii_phyaddr, 5);
356 ste_mii_send(sc, frame->mii_regaddr, 5);
357 ste_mii_send(sc, frame->mii_turnaround, 2);
358 ste_mii_send(sc, frame->mii_data, 16);
361 MII_SET(STE_PHYCTL_MCLK);
363 MII_CLR(STE_PHYCTL_MCLK);
369 MII_CLR(STE_PHYCTL_MDIR);
376 static int ste_miibus_readreg(dev, phy, reg)
380 struct ste_softc *sc;
381 struct ste_mii_frame frame;
383 sc = device_get_softc(dev);
385 bzero((char *)&frame, sizeof(frame));
387 frame.mii_phyaddr = phy;
388 frame.mii_regaddr = reg;
389 ste_mii_readreg(sc, &frame);
391 return(frame.mii_data);
394 static int ste_miibus_writereg(dev, phy, reg, data)
398 struct ste_softc *sc;
399 struct ste_mii_frame frame;
401 sc = device_get_softc(dev);
402 bzero((char *)&frame, sizeof(frame));
404 frame.mii_phyaddr = phy;
405 frame.mii_regaddr = reg;
406 frame.mii_data = data;
408 ste_mii_writereg(sc, &frame);
413 static void ste_miibus_statchg(dev)
416 struct ste_softc *sc;
417 struct mii_data *mii;
419 sc = device_get_softc(dev);
421 mii = device_get_softc(sc->ste_miibus);
423 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
424 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
426 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
433 static int ste_ifmedia_upd(ifp)
436 struct ste_softc *sc;
437 struct mii_data *mii;
440 mii = device_get_softc(sc->ste_miibus);
442 if (mii->mii_instance) {
443 struct mii_softc *miisc;
444 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
445 mii_phy_reset(miisc);
452 static void ste_ifmedia_sts(ifp, ifmr)
454 struct ifmediareq *ifmr;
456 struct ste_softc *sc;
457 struct mii_data *mii;
460 mii = device_get_softc(sc->ste_miibus);
463 ifmr->ifm_active = mii->mii_media_active;
464 ifmr->ifm_status = mii->mii_media_status;
469 static void ste_wait(sc)
470 struct ste_softc *sc;
474 for (i = 0; i < STE_TIMEOUT; i++) {
475 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
479 if (i == STE_TIMEOUT)
480 printf("ste%d: command never completed!\n", sc->ste_unit);
486 * The EEPROM is slow: give it time to come ready after issuing
489 static int ste_eeprom_wait(sc)
490 struct ste_softc *sc;
496 for (i = 0; i < 100; i++) {
497 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
504 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit);
512 * Read a sequence of words from the EEPROM. Note that ethernet address
513 * data is stored in the EEPROM in network byte order.
515 static int ste_read_eeprom(sc, dest, off, cnt, swap)
516 struct ste_softc *sc;
523 u_int16_t word = 0, *ptr;
525 if (ste_eeprom_wait(sc))
528 for (i = 0; i < cnt; i++) {
529 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
530 err = ste_eeprom_wait(sc);
533 word = CSR_READ_2(sc, STE_EEPROM_DATA);
534 ptr = (u_int16_t *)(dest + (i * 2));
544 static u_int8_t ste_calchash(addr)
548 u_int32_t crc, carry;
552 /* Compute CRC for the address value. */
553 crc = 0xFFFFFFFF; /* initial value */
555 for (i = 0; i < 6; i++) {
557 for (j = 0; j < 8; j++) {
558 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
562 crc = (crc ^ 0x04c11db6) | carry;
566 /* return the filter bit position */
567 return(crc & 0x0000003F);
570 static void ste_setmulti(sc)
571 struct ste_softc *sc;
575 u_int32_t hashes[2] = { 0, 0 };
576 struct ifmultiaddr *ifma;
578 ifp = &sc->arpcom.ac_if;
579 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
580 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
581 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
585 /* first, zot all the existing hash bits */
586 CSR_WRITE_4(sc, STE_MAR0, 0);
587 CSR_WRITE_4(sc, STE_MAR1, 0);
589 /* now program new ones */
590 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
591 if (ifma->ifma_addr->sa_family != AF_LINK)
593 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
595 hashes[0] |= (1 << h);
597 hashes[1] |= (1 << (h - 32));
600 CSR_WRITE_4(sc, STE_MAR0, hashes[0]);
601 CSR_WRITE_4(sc, STE_MAR1, hashes[1]);
602 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
603 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
608 static void ste_intr(xsc)
611 struct ste_softc *sc;
617 ifp = &sc->arpcom.ac_if;
619 /* See if this is really our interrupt. */
620 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) {
626 status = CSR_READ_2(sc, STE_ISR_ACK);
628 if (!(status & STE_INTRS))
631 if (status & STE_ISR_RX_DMADONE)
634 if (status & STE_ISR_TX_DMADONE)
637 if (status & STE_ISR_TX_DONE)
640 if (status & STE_ISR_STATS_OFLOW) {
641 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
642 ste_stats_update(sc);
645 if (status & STE_ISR_HOSTERR) {
651 /* Re-enable interrupts */
652 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
654 if (ifp->if_snd.ifq_head != NULL)
663 * A frame has been uploaded: pass the resulting mbuf chain up to
664 * the higher level protocols.
666 static void ste_rxeof(sc)
667 struct ste_softc *sc;
669 struct ether_header *eh;
672 struct ste_chain_onefrag *cur_rx;
676 ifp = &sc->arpcom.ac_if;
680 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) {
681 cur_rx = sc->ste_cdata.ste_rx_head;
682 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
685 * If an error occurs, update stats, clear the
686 * status word and leave the mbuf cluster in place:
687 * it should simply get re-used next time this descriptor
688 * comes up in the ring.
690 if (rxstat & STE_RXSTAT_FRAME_ERR) {
692 cur_rx->ste_ptr->ste_status = 0;
697 * If there error bit was not set, the upload complete
698 * bit should be set which means we have a valid packet.
699 * If not, something truly strange has happened.
701 if (!(rxstat & STE_RXSTAT_DMADONE)) {
702 printf("ste%d: bad receive status -- packet dropped",
705 cur_rx->ste_ptr->ste_status = 0;
709 /* No errors; receive the packet. */
710 m = cur_rx->ste_mbuf;
711 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
714 * Try to conjure up a new mbuf cluster. If that
715 * fails, it means we have an out of memory condition and
716 * should leave the buffer in place and continue. This will
717 * result in a lost packet, but there's little else we
718 * can do in this situation.
720 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
722 cur_rx->ste_ptr->ste_status = 0;
727 eh = mtod(m, struct ether_header *);
728 m->m_pkthdr.rcvif = ifp;
729 m->m_pkthdr.len = m->m_len = total_len;
731 /* Remove header from mbuf and pass it on. */
732 m_adj(m, sizeof(struct ether_header));
733 ether_input(ifp, eh, m);
737 * Handle the 'end of channel' condition. When the upload
738 * engine hits the end of the RX ring, it will stall. This
739 * is our cue to flush the RX ring, reload the uplist pointer
740 * register and unstall the engine.
741 * XXX This is actually a little goofy. With the ThunderLAN
742 * chip, you get an interrupt when the receiver hits the end
743 * of the receive ring, which tells you exactly when you
744 * you need to reload the ring pointer. Here we have to
745 * fake it. I'm mad at myself for not being clever enough
746 * to avoid the use of a goto here.
748 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 ||
749 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) {
750 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
752 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
753 vtophys(&sc->ste_ldata->ste_rx_list[0]));
754 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0];
755 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
762 static void ste_txeoc(sc)
763 struct ste_softc *sc;
768 ifp = &sc->arpcom.ac_if;
770 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
771 STE_TXSTATUS_TXDONE) {
772 if (txstat & STE_TXSTATUS_UNDERRUN ||
773 txstat & STE_TXSTATUS_EXCESSCOLLS ||
774 txstat & STE_TXSTATUS_RECLAIMERR) {
776 printf("ste%d: transmission error: %x\n",
777 sc->ste_unit, txstat);
782 if (txstat & STE_TXSTATUS_UNDERRUN &&
783 sc->ste_tx_thresh < STE_PACKET_SIZE) {
784 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
785 printf("ste%d: tx underrun, increasing tx"
786 " start threshold to %d bytes\n",
787 sc->ste_unit, sc->ste_tx_thresh);
789 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
790 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
791 (STE_PACKET_SIZE >> 4));
794 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
800 static void ste_txeof(sc)
801 struct ste_softc *sc;
803 struct ste_chain *cur_tx = NULL;
807 ifp = &sc->arpcom.ac_if;
809 idx = sc->ste_cdata.ste_tx_cons;
810 while(idx != sc->ste_cdata.ste_tx_prod) {
811 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
813 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
816 if (cur_tx->ste_mbuf != NULL) {
817 m_freem(cur_tx->ste_mbuf);
818 cur_tx->ste_mbuf = NULL;
823 sc->ste_cdata.ste_tx_cnt--;
824 STE_INC(idx, STE_TX_LIST_CNT);
828 sc->ste_cdata.ste_tx_cons = idx;
831 ifp->if_flags &= ~IFF_OACTIVE;
836 static void ste_stats_update(xsc)
839 struct ste_softc *sc;
840 struct ste_stats stats;
842 struct mii_data *mii;
849 ifp = &sc->arpcom.ac_if;
850 mii = device_get_softc(sc->ste_miibus);
852 p = (u_int8_t *)&stats;
854 for (i = 0; i < sizeof(stats); i++) {
855 *p = CSR_READ_1(sc, STE_STATS + i);
859 ifp->if_collisions += stats.ste_single_colls +
860 stats.ste_multi_colls + stats.ste_late_colls;
865 if (mii->mii_media_status & IFM_ACTIVE &&
866 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
868 if (ifp->if_snd.ifq_head != NULL)
872 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
880 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
881 * IDs against our list and return a device name if we find a match.
883 static int ste_probe(dev)
890 while(t->ste_name != NULL) {
891 if ((pci_get_vendor(dev) == t->ste_vid) &&
892 (pci_get_device(dev) == t->ste_did)) {
893 device_set_desc(dev, t->ste_name);
903 * Attach the interface. Allocate softc structures, do ifmedia
904 * setup and ethernet/BPF attach.
906 static int ste_attach(dev)
910 struct ste_softc *sc;
912 int unit, error = 0, rid;
914 sc = device_get_softc(dev);
915 unit = device_get_unit(dev);
916 bzero(sc, sizeof(struct ste_softc));
918 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
922 * Handle power management nonsense.
924 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF;
925 if (command == 0x01) {
927 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4);
928 if (command & STE_PSTATE_MASK) {
929 u_int32_t iobase, membase, irq;
931 /* Save important PCI config data. */
932 iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
933 membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
934 irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
936 /* Reset the power state. */
937 printf("ste%d: chip is in D%d power mode "
938 "-- setting to D0\n", unit, command & STE_PSTATE_MASK);
939 command &= 0xFFFFFFFC;
940 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4);
942 /* Restore PCI config data. */
943 pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
944 pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
945 pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
950 * Map control/status registers.
952 command = pci_read_config(dev, PCIR_COMMAND, 4);
953 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
954 pci_write_config(dev, PCIR_COMMAND, command, 4);
955 command = pci_read_config(dev, PCIR_COMMAND, 4);
957 #ifdef STE_USEIOSPACE
958 if (!(command & PCIM_CMD_PORTEN)) {
959 printf("ste%d: failed to enable I/O ports!\n", unit);
964 if (!(command & PCIM_CMD_MEMEN)) {
965 printf("ste%d: failed to enable memory mapping!\n", unit);
972 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid,
973 0, ~0, 1, RF_ACTIVE);
975 if (sc->ste_res == NULL) {
976 printf ("ste%d: couldn't map ports/memory\n", unit);
981 sc->ste_btag = rman_get_bustag(sc->ste_res);
982 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
985 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
986 RF_SHAREABLE | RF_ACTIVE);
988 if (sc->ste_irq == NULL) {
989 printf("ste%d: couldn't map interrupt\n", unit);
990 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
995 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET,
996 ste_intr, sc, &sc->ste_intrhand);
999 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1000 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1001 printf("ste%d: couldn't set up irq\n", unit);
1005 callout_handle_init(&sc->ste_stat_ch);
1007 /* Reset the adapter. */
1011 * Get station address from the EEPROM.
1013 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1014 STE_EEADDR_NODE0, 3, 0)) {
1015 printf("ste%d: failed to read station address\n", unit);
1016 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1017 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1018 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1024 * A Sundance chip was detected. Inform the world.
1026 printf("ste%d: Ethernet address: %6D\n", unit,
1027 sc->arpcom.ac_enaddr, ":");
1029 sc->ste_unit = unit;
1031 /* Allocate the descriptor queues. */
1032 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1033 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1035 if (sc->ste_ldata == NULL) {
1036 printf("ste%d: no memory for list buffers!\n", unit);
1037 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1038 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1039 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1044 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1047 if (mii_phy_probe(dev, &sc->ste_miibus,
1048 ste_ifmedia_upd, ste_ifmedia_sts)) {
1049 printf("ste%d: MII without any phy!\n", sc->ste_unit);
1050 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1051 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1052 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1053 contigfree(sc->ste_ldata,
1054 sizeof(struct ste_list_data), M_DEVBUF);
1059 ifp = &sc->arpcom.ac_if;
1061 ifp->if_unit = unit;
1062 ifp->if_name = "ste";
1063 ifp->if_mtu = ETHERMTU;
1064 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1065 ifp->if_ioctl = ste_ioctl;
1066 ifp->if_output = ether_output;
1067 ifp->if_start = ste_start;
1068 ifp->if_watchdog = ste_watchdog;
1069 ifp->if_init = ste_init;
1070 ifp->if_baudrate = 10000000;
1071 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1;
1074 * Call MI attach routine.
1076 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1082 mtx_destroy(&sc->ste_mtx);
1086 static int ste_detach(dev)
1089 struct ste_softc *sc;
1092 sc = device_get_softc(dev);
1094 ifp = &sc->arpcom.ac_if;
1097 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1099 bus_generic_detach(dev);
1100 device_delete_child(dev, sc->ste_miibus);
1102 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1103 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1104 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1106 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF);
1109 mtx_destroy(&sc->ste_mtx);
1114 static int ste_newbuf(sc, c, m)
1115 struct ste_softc *sc;
1116 struct ste_chain_onefrag *c;
1119 struct mbuf *m_new = NULL;
1122 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1123 if (m_new == NULL) {
1124 printf("ste%d: no memory for rx list -- "
1125 "packet dropped\n", sc->ste_unit);
1128 MCLGET(m_new, M_DONTWAIT);
1129 if (!(m_new->m_flags & M_EXT)) {
1130 printf("ste%d: no memory for rx list -- "
1131 "packet dropped\n", sc->ste_unit);
1135 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1138 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1139 m_new->m_data = m_new->m_ext.ext_buf;
1142 m_adj(m_new, ETHER_ALIGN);
1144 c->ste_mbuf = m_new;
1145 c->ste_ptr->ste_status = 0;
1146 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1147 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST;
1152 static int ste_init_rx_list(sc)
1153 struct ste_softc *sc;
1155 struct ste_chain_data *cd;
1156 struct ste_list_data *ld;
1159 cd = &sc->ste_cdata;
1162 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1163 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1164 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1166 if (i == (STE_RX_LIST_CNT - 1)) {
1167 cd->ste_rx_chain[i].ste_next =
1168 &cd->ste_rx_chain[0];
1169 ld->ste_rx_list[i].ste_next =
1170 vtophys(&ld->ste_rx_list[0]);
1172 cd->ste_rx_chain[i].ste_next =
1173 &cd->ste_rx_chain[i + 1];
1174 ld->ste_rx_list[i].ste_next =
1175 vtophys(&ld->ste_rx_list[i + 1]);
1180 cd->ste_rx_head = &cd->ste_rx_chain[0];
1185 static void ste_init_tx_list(sc)
1186 struct ste_softc *sc;
1188 struct ste_chain_data *cd;
1189 struct ste_list_data *ld;
1192 cd = &sc->ste_cdata;
1194 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1195 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1196 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1197 if (i == (STE_TX_LIST_CNT - 1))
1198 cd->ste_tx_chain[i].ste_next =
1199 &cd->ste_tx_chain[0];
1201 cd->ste_tx_chain[i].ste_next =
1202 &cd->ste_tx_chain[i + 1];
1204 cd->ste_tx_chain[i].ste_prev =
1205 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1];
1207 cd->ste_tx_chain[i].ste_prev =
1208 &cd->ste_tx_chain[i - 1];
1212 bzero((char *)ld->ste_tx_list,
1213 sizeof(struct ste_desc) * STE_TX_LIST_CNT);
1215 cd->ste_tx_prod = 0;
1216 cd->ste_tx_cons = 0;
1222 static void ste_init(xsc)
1225 struct ste_softc *sc;
1228 struct mii_data *mii;
1232 ifp = &sc->arpcom.ac_if;
1233 mii = device_get_softc(sc->ste_miibus);
1237 /* Init our MAC address */
1238 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1239 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1243 if (ste_init_rx_list(sc) == ENOBUFS) {
1244 printf("ste%d: initialization failed: no "
1245 "memory for RX buffers\n", sc->ste_unit);
1251 /* Init TX descriptors */
1252 ste_init_tx_list(sc);
1254 /* Set the TX freethresh value */
1255 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1257 /* Set the TX start threshold for best performance. */
1258 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1260 /* Set the TX reclaim threshold. */
1261 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1263 /* Set up the RX filter. */
1264 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1266 /* If we want promiscuous mode, set the allframes bit. */
1267 if (ifp->if_flags & IFF_PROMISC) {
1268 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1270 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1273 /* Set capture broadcast bit to accept broadcast frames. */
1274 if (ifp->if_flags & IFF_BROADCAST) {
1275 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1277 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1282 /* Load the address of the RX list. */
1283 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1285 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1286 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1287 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1288 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1290 /* Set TX polling interval */
1291 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1293 /* Load address of the TX list */
1294 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1296 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1297 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1298 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1299 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1302 /* Enable receiver and transmitter */
1303 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1304 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1305 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1307 /* Enable stats counters. */
1308 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1310 /* Enable interrupts. */
1311 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1312 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1314 ste_ifmedia_upd(ifp);
1316 ifp->if_flags |= IFF_RUNNING;
1317 ifp->if_flags &= ~IFF_OACTIVE;
1319 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
1325 static void ste_stop(sc)
1326 struct ste_softc *sc;
1332 ifp = &sc->arpcom.ac_if;
1334 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
1336 CSR_WRITE_2(sc, STE_IMR, 0);
1337 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1338 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1340 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1341 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1346 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1347 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1348 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1349 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1353 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1354 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1355 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1356 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1360 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1366 static void ste_reset(sc)
1367 struct ste_softc *sc;
1371 STE_SETBIT4(sc, STE_ASICCTL,
1372 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1373 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1374 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1375 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1376 STE_ASICCTL_EXTRESET_RESET);
1380 for (i = 0; i < STE_TIMEOUT; i++) {
1381 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1385 if (i == STE_TIMEOUT)
1386 printf("ste%d: global reset never completed\n", sc->ste_unit);
1391 static int ste_ioctl(ifp, command, data)
1396 struct ste_softc *sc;
1398 struct mii_data *mii;
1403 ifr = (struct ifreq *)data;
1409 error = ether_ioctl(ifp, command, data);
1412 if (ifp->if_flags & IFF_UP) {
1413 if (ifp->if_flags & IFF_RUNNING &&
1414 ifp->if_flags & IFF_PROMISC &&
1415 !(sc->ste_if_flags & IFF_PROMISC)) {
1416 STE_SETBIT1(sc, STE_RX_MODE,
1417 STE_RXMODE_PROMISC);
1418 } else if (ifp->if_flags & IFF_RUNNING &&
1419 !(ifp->if_flags & IFF_PROMISC) &&
1420 sc->ste_if_flags & IFF_PROMISC) {
1421 STE_CLRBIT1(sc, STE_RX_MODE,
1422 STE_RXMODE_PROMISC);
1423 } else if (!(ifp->if_flags & IFF_RUNNING)) {
1424 sc->ste_tx_thresh = STE_MIN_FRAMELEN;
1428 if (ifp->if_flags & IFF_RUNNING)
1431 sc->ste_if_flags = ifp->if_flags;
1441 mii = device_get_softc(sc->ste_miibus);
1442 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1454 static int ste_encap(sc, c, m_head)
1455 struct ste_softc *sc;
1456 struct ste_chain *c;
1457 struct mbuf *m_head;
1460 struct ste_frag *f = NULL;
1469 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1470 if (m->m_len != 0) {
1471 if (frag == STE_MAXFRAGS)
1473 total_len += m->m_len;
1474 f = &c->ste_ptr->ste_frags[frag];
1475 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1476 f->ste_len = m->m_len;
1481 c->ste_mbuf = m_head;
1482 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1483 c->ste_ptr->ste_ctl = total_len;
1488 static void ste_start(ifp)
1491 struct ste_softc *sc;
1492 struct mbuf *m_head = NULL;
1493 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1499 if (!sc->ste_link) {
1504 if (ifp->if_flags & IFF_OACTIVE) {
1509 idx = sc->ste_cdata.ste_tx_prod;
1510 start_tx = &sc->ste_cdata.ste_tx_chain[idx];
1512 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1514 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) {
1515 ifp->if_flags |= IFF_OACTIVE;
1519 IF_DEQUEUE(&ifp->if_snd, m_head);
1523 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1525 ste_encap(sc, cur_tx, m_head);
1528 prev->ste_ptr->ste_next = cur_tx->ste_phys;
1532 * If there's a BPF listener, bounce a copy of this frame
1536 bpf_mtap(ifp, cur_tx->ste_mbuf);
1538 STE_INC(idx, STE_TX_LIST_CNT);
1539 sc->ste_cdata.ste_tx_cnt++;
1542 if (cur_tx == NULL) {
1547 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR;
1549 /* Start transmission */
1550 sc->ste_cdata.ste_tx_prod = idx;
1551 start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys;
1559 static void ste_watchdog(ifp)
1562 struct ste_softc *sc;
1568 printf("ste%d: watchdog timeout\n", sc->ste_unit);
1576 if (ifp->if_snd.ifq_head != NULL)
1583 static void ste_shutdown(dev)
1586 struct ste_softc *sc;
1588 sc = device_get_softc(dev);