2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/sockio.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
43 #include <sys/socket.h>
44 #include <sys/sysctl.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/if_vlan_var.h>
55 #include <vm/vm.h> /* for vtophys */
56 #include <vm/pmap.h> /* for vtophys */
57 #include <machine/bus_memio.h>
58 #include <machine/bus_pio.h>
59 #include <machine/bus.h>
60 #include <machine/resource.h>
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
67 #include <dev/pci/pcireg.h>
68 #include <dev/pci/pcivar.h>
70 /* "controller miibus0" required. See GENERIC if you get errors here. */
71 #include "miibus_if.h"
73 #define STE_USEIOSPACE
75 #include <pci/if_stereg.h>
77 MODULE_DEPEND(ste, pci, 1, 1, 1);
78 MODULE_DEPEND(ste, ether, 1, 1, 1);
79 MODULE_DEPEND(ste, miibus, 1, 1, 1);
82 * Various supported device vendors/types and their names.
84 static struct ste_type ste_devs[] = {
85 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
86 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
90 static int ste_probe (device_t);
91 static int ste_attach (device_t);
92 static int ste_detach (device_t);
93 static void ste_init (void *);
94 static void ste_intr (void *);
95 static void ste_rxeoc (struct ste_softc *);
96 static void ste_rxeof (struct ste_softc *);
97 static void ste_txeoc (struct ste_softc *);
98 static void ste_txeof (struct ste_softc *);
99 static void ste_stats_update (void *);
100 static void ste_stop (struct ste_softc *);
101 static void ste_reset (struct ste_softc *);
102 static int ste_ioctl (struct ifnet *, u_long, caddr_t);
103 static int ste_encap (struct ste_softc *, struct ste_chain *,
105 static void ste_start (struct ifnet *);
106 static void ste_watchdog (struct ifnet *);
107 static void ste_shutdown (device_t);
108 static int ste_newbuf (struct ste_softc *,
109 struct ste_chain_onefrag *,
111 static int ste_ifmedia_upd (struct ifnet *);
112 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *);
114 static void ste_mii_sync (struct ste_softc *);
115 static void ste_mii_send (struct ste_softc *, u_int32_t, int);
116 static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *);
117 static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *);
118 static int ste_miibus_readreg (device_t, int, int);
119 static int ste_miibus_writereg (device_t, int, int, int);
120 static void ste_miibus_statchg (device_t);
122 static int ste_eeprom_wait (struct ste_softc *);
123 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int);
124 static void ste_wait (struct ste_softc *);
125 static u_int8_t ste_calchash (caddr_t);
126 static void ste_setmulti (struct ste_softc *);
127 static int ste_init_rx_list (struct ste_softc *);
128 static void ste_init_tx_list (struct ste_softc *);
130 #ifdef STE_USEIOSPACE
131 #define STE_RES SYS_RES_IOPORT
132 #define STE_RID STE_PCI_LOIO
134 #define STE_RES SYS_RES_MEMORY
135 #define STE_RID STE_PCI_LOMEM
138 static device_method_t ste_methods[] = {
139 /* Device interface */
140 DEVMETHOD(device_probe, ste_probe),
141 DEVMETHOD(device_attach, ste_attach),
142 DEVMETHOD(device_detach, ste_detach),
143 DEVMETHOD(device_shutdown, ste_shutdown),
146 DEVMETHOD(bus_print_child, bus_generic_print_child),
147 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
150 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
151 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
152 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
157 static driver_t ste_driver = {
160 sizeof(struct ste_softc)
163 static devclass_t ste_devclass;
165 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
166 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
168 SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters");
170 static int ste_rxsyncs;
171 SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, "");
173 #define STE_SETBIT4(sc, reg, x) \
174 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
176 #define STE_CLRBIT4(sc, reg, x) \
177 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
179 #define STE_SETBIT2(sc, reg, x) \
180 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
182 #define STE_CLRBIT2(sc, reg, x) \
183 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
185 #define STE_SETBIT1(sc, reg, x) \
186 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
188 #define STE_CLRBIT1(sc, reg, x) \
189 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
192 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
193 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
196 * Sync the PHYs by setting data bit and strobing the clock 32 times.
200 struct ste_softc *sc;
204 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
206 for (i = 0; i < 32; i++) {
207 MII_SET(STE_PHYCTL_MCLK);
209 MII_CLR(STE_PHYCTL_MCLK);
217 * Clock a series of bits through the MII.
220 ste_mii_send(sc, bits, cnt)
221 struct ste_softc *sc;
227 MII_CLR(STE_PHYCTL_MCLK);
229 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
231 MII_SET(STE_PHYCTL_MDATA);
233 MII_CLR(STE_PHYCTL_MDATA);
236 MII_CLR(STE_PHYCTL_MCLK);
238 MII_SET(STE_PHYCTL_MCLK);
243 * Read an PHY register through the MII.
246 ste_mii_readreg(sc, frame)
247 struct ste_softc *sc;
248 struct ste_mii_frame *frame;
256 * Set up frame for RX.
258 frame->mii_stdelim = STE_MII_STARTDELIM;
259 frame->mii_opcode = STE_MII_READOP;
260 frame->mii_turnaround = 0;
263 CSR_WRITE_2(sc, STE_PHYCTL, 0);
267 MII_SET(STE_PHYCTL_MDIR);
272 * Send command/address info.
274 ste_mii_send(sc, frame->mii_stdelim, 2);
275 ste_mii_send(sc, frame->mii_opcode, 2);
276 ste_mii_send(sc, frame->mii_phyaddr, 5);
277 ste_mii_send(sc, frame->mii_regaddr, 5);
280 MII_CLR(STE_PHYCTL_MDIR);
283 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
285 MII_SET(STE_PHYCTL_MCLK);
289 MII_CLR(STE_PHYCTL_MCLK);
291 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
292 MII_SET(STE_PHYCTL_MCLK);
296 * Now try reading data bits. If the ack failed, we still
297 * need to clock through 16 cycles to keep the PHY(s) in sync.
300 for(i = 0; i < 16; i++) {
301 MII_CLR(STE_PHYCTL_MCLK);
303 MII_SET(STE_PHYCTL_MCLK);
309 for (i = 0x8000; i; i >>= 1) {
310 MII_CLR(STE_PHYCTL_MCLK);
313 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
314 frame->mii_data |= i;
317 MII_SET(STE_PHYCTL_MCLK);
323 MII_CLR(STE_PHYCTL_MCLK);
325 MII_SET(STE_PHYCTL_MCLK);
336 * Write to a PHY register through the MII.
339 ste_mii_writereg(sc, frame)
340 struct ste_softc *sc;
341 struct ste_mii_frame *frame;
347 * Set up frame for TX.
350 frame->mii_stdelim = STE_MII_STARTDELIM;
351 frame->mii_opcode = STE_MII_WRITEOP;
352 frame->mii_turnaround = STE_MII_TURNAROUND;
355 * Turn on data output.
357 MII_SET(STE_PHYCTL_MDIR);
361 ste_mii_send(sc, frame->mii_stdelim, 2);
362 ste_mii_send(sc, frame->mii_opcode, 2);
363 ste_mii_send(sc, frame->mii_phyaddr, 5);
364 ste_mii_send(sc, frame->mii_regaddr, 5);
365 ste_mii_send(sc, frame->mii_turnaround, 2);
366 ste_mii_send(sc, frame->mii_data, 16);
369 MII_SET(STE_PHYCTL_MCLK);
371 MII_CLR(STE_PHYCTL_MCLK);
377 MII_CLR(STE_PHYCTL_MDIR);
385 ste_miibus_readreg(dev, phy, reg)
389 struct ste_softc *sc;
390 struct ste_mii_frame frame;
392 sc = device_get_softc(dev);
394 if ( sc->ste_one_phy && phy != 0 )
397 bzero((char *)&frame, sizeof(frame));
399 frame.mii_phyaddr = phy;
400 frame.mii_regaddr = reg;
401 ste_mii_readreg(sc, &frame);
403 return(frame.mii_data);
407 ste_miibus_writereg(dev, phy, reg, data)
411 struct ste_softc *sc;
412 struct ste_mii_frame frame;
414 sc = device_get_softc(dev);
415 bzero((char *)&frame, sizeof(frame));
417 frame.mii_phyaddr = phy;
418 frame.mii_regaddr = reg;
419 frame.mii_data = data;
421 ste_mii_writereg(sc, &frame);
427 ste_miibus_statchg(dev)
430 struct ste_softc *sc;
431 struct mii_data *mii;
433 sc = device_get_softc(dev);
435 mii = device_get_softc(sc->ste_miibus);
437 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
438 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
440 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
451 struct ste_softc *sc;
452 struct mii_data *mii;
455 mii = device_get_softc(sc->ste_miibus);
457 if (mii->mii_instance) {
458 struct mii_softc *miisc;
459 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
460 mii_phy_reset(miisc);
468 ste_ifmedia_sts(ifp, ifmr)
470 struct ifmediareq *ifmr;
472 struct ste_softc *sc;
473 struct mii_data *mii;
476 mii = device_get_softc(sc->ste_miibus);
479 ifmr->ifm_active = mii->mii_media_active;
480 ifmr->ifm_status = mii->mii_media_status;
487 struct ste_softc *sc;
491 for (i = 0; i < STE_TIMEOUT; i++) {
492 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
496 if (i == STE_TIMEOUT)
497 printf("ste%d: command never completed!\n", sc->ste_unit);
503 * The EEPROM is slow: give it time to come ready after issuing
508 struct ste_softc *sc;
514 for (i = 0; i < 100; i++) {
515 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
522 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit);
530 * Read a sequence of words from the EEPROM. Note that ethernet address
531 * data is stored in the EEPROM in network byte order.
534 ste_read_eeprom(sc, dest, off, cnt, swap)
535 struct ste_softc *sc;
542 u_int16_t word = 0, *ptr;
544 if (ste_eeprom_wait(sc))
547 for (i = 0; i < cnt; i++) {
548 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
549 err = ste_eeprom_wait(sc);
552 word = CSR_READ_2(sc, STE_EEPROM_DATA);
553 ptr = (u_int16_t *)(dest + (i * 2));
568 u_int32_t crc, carry;
572 /* Compute CRC for the address value. */
573 crc = 0xFFFFFFFF; /* initial value */
575 for (i = 0; i < 6; i++) {
577 for (j = 0; j < 8; j++) {
578 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
582 crc = (crc ^ 0x04c11db6) | carry;
586 /* return the filter bit position */
587 return(crc & 0x0000003F);
592 struct ste_softc *sc;
596 u_int32_t hashes[2] = { 0, 0 };
597 struct ifmultiaddr *ifma;
599 ifp = &sc->arpcom.ac_if;
600 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
601 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
602 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
606 /* first, zot all the existing hash bits */
607 CSR_WRITE_2(sc, STE_MAR0, 0);
608 CSR_WRITE_2(sc, STE_MAR1, 0);
609 CSR_WRITE_2(sc, STE_MAR2, 0);
610 CSR_WRITE_2(sc, STE_MAR3, 0);
612 /* now program new ones */
613 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
614 if (ifma->ifma_addr->sa_family != AF_LINK)
616 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
618 hashes[0] |= (1 << h);
620 hashes[1] |= (1 << (h - 32));
623 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
624 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
625 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
626 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
627 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
628 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
633 #ifdef DEVICE_POLLING
634 static poll_handler_t ste_poll;
637 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
639 struct ste_softc *sc = ifp->if_softc;
642 if (!(ifp->if_capenable & IFCAP_POLLING)) {
643 ether_poll_deregister(ifp);
644 cmd = POLL_DEREGISTER;
646 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
647 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
651 sc->rxcycles = count;
652 if (cmd == POLL_AND_CHECK_STATUS)
656 if (ifp->if_snd.ifq_head != NULL)
659 if (cmd == POLL_AND_CHECK_STATUS) {
662 status = CSR_READ_2(sc, STE_ISR_ACK);
664 if (status & STE_ISR_TX_DONE)
667 if (status & STE_ISR_STATS_OFLOW) {
668 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
669 ste_stats_update(sc);
672 if (status & STE_ISR_LINKEVENT)
673 mii_pollstat(device_get_softc(sc->ste_miibus));
675 if (status & STE_ISR_HOSTERR) {
683 #endif /* DEVICE_POLLING */
689 struct ste_softc *sc;
695 ifp = &sc->arpcom.ac_if;
697 #ifdef DEVICE_POLLING
698 if (ifp->if_flags & IFF_POLLING)
700 if ((ifp->if_capenable & IFCAP_POLLING) &&
701 ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */
702 CSR_WRITE_2(sc, STE_IMR, 0);
706 #endif /* DEVICE_POLLING */
708 /* See if this is really our interrupt. */
709 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) {
715 status = CSR_READ_2(sc, STE_ISR_ACK);
717 if (!(status & STE_INTRS))
720 if (status & STE_ISR_RX_DMADONE) {
725 if (status & STE_ISR_TX_DMADONE)
728 if (status & STE_ISR_TX_DONE)
731 if (status & STE_ISR_STATS_OFLOW) {
732 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
733 ste_stats_update(sc);
736 if (status & STE_ISR_LINKEVENT)
737 mii_pollstat(device_get_softc(sc->ste_miibus));
740 if (status & STE_ISR_HOSTERR) {
746 /* Re-enable interrupts */
747 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
749 if (ifp->if_snd.ifq_head != NULL)
752 #ifdef DEVICE_POLLING
754 #endif /* DEVICE_POLLING */
761 ste_rxeoc(struct ste_softc *sc)
763 struct ste_chain_onefrag *cur_rx;
767 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
768 cur_rx = sc->ste_cdata.ste_rx_head;
770 cur_rx = cur_rx->ste_next;
771 /* If the ring is empty, just return. */
772 if (cur_rx == sc->ste_cdata.ste_rx_head)
774 } while (cur_rx->ste_ptr->ste_status == 0);
775 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
776 /* We've fallen behind the chip: catch it. */
777 sc->ste_cdata.ste_rx_head = cur_rx;
784 * A frame has been uploaded: pass the resulting mbuf chain up to
785 * the higher level protocols.
789 struct ste_softc *sc;
793 struct ste_chain_onefrag *cur_rx;
794 int total_len = 0, count=0;
799 ifp = &sc->arpcom.ac_if;
801 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
802 & STE_RXSTAT_DMADONE) {
803 #ifdef DEVICE_POLLING
804 if (ifp->if_flags & IFF_POLLING) {
805 if (sc->rxcycles <= 0)
809 #endif /* DEVICE_POLLING */
810 if ((STE_RX_LIST_CNT - count) < 3) {
814 cur_rx = sc->ste_cdata.ste_rx_head;
815 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
818 * If an error occurs, update stats, clear the
819 * status word and leave the mbuf cluster in place:
820 * it should simply get re-used next time this descriptor
821 * comes up in the ring.
823 if (rxstat & STE_RXSTAT_FRAME_ERR) {
825 cur_rx->ste_ptr->ste_status = 0;
830 * If there error bit was not set, the upload complete
831 * bit should be set which means we have a valid packet.
832 * If not, something truly strange has happened.
834 if (!(rxstat & STE_RXSTAT_DMADONE)) {
835 printf("ste%d: bad receive status -- packet dropped\n",
838 cur_rx->ste_ptr->ste_status = 0;
842 /* No errors; receive the packet. */
843 m = cur_rx->ste_mbuf;
844 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
847 * Try to conjure up a new mbuf cluster. If that
848 * fails, it means we have an out of memory condition and
849 * should leave the buffer in place and continue. This will
850 * result in a lost packet, but there's little else we
851 * can do in this situation.
853 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
855 cur_rx->ste_ptr->ste_status = 0;
859 m->m_pkthdr.rcvif = ifp;
860 m->m_pkthdr.len = m->m_len = total_len;
864 (*ifp->if_input)(ifp, m);
867 cur_rx->ste_ptr->ste_status = 0;
876 struct ste_softc *sc;
881 ifp = &sc->arpcom.ac_if;
883 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
884 STE_TXSTATUS_TXDONE) {
885 if (txstat & STE_TXSTATUS_UNDERRUN ||
886 txstat & STE_TXSTATUS_EXCESSCOLLS ||
887 txstat & STE_TXSTATUS_RECLAIMERR) {
889 printf("ste%d: transmission error: %x\n",
890 sc->ste_unit, txstat);
895 if (txstat & STE_TXSTATUS_UNDERRUN &&
896 sc->ste_tx_thresh < STE_PACKET_SIZE) {
897 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
898 printf("ste%d: tx underrun, increasing tx"
899 " start threshold to %d bytes\n",
900 sc->ste_unit, sc->ste_tx_thresh);
902 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
903 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
904 (STE_PACKET_SIZE >> 4));
907 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
915 struct ste_softc *sc;
917 struct ste_chain *cur_tx;
921 ifp = &sc->arpcom.ac_if;
923 idx = sc->ste_cdata.ste_tx_cons;
924 while(idx != sc->ste_cdata.ste_tx_prod) {
925 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
927 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
930 m_freem(cur_tx->ste_mbuf);
931 cur_tx->ste_mbuf = NULL;
932 ifp->if_flags &= ~IFF_OACTIVE;
935 STE_INC(idx, STE_TX_LIST_CNT);
938 sc->ste_cdata.ste_tx_cons = idx;
939 if (idx == sc->ste_cdata.ste_tx_prod)
944 ste_stats_update(xsc)
947 struct ste_softc *sc;
949 struct mii_data *mii;
954 ifp = &sc->arpcom.ac_if;
955 mii = device_get_softc(sc->ste_miibus);
957 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
958 + CSR_READ_1(sc, STE_MULTI_COLLS)
959 + CSR_READ_1(sc, STE_SINGLE_COLLS);
963 if (mii->mii_media_status & IFM_ACTIVE &&
964 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
967 * we don't get a call-back on re-init so do it
968 * otherwise we get stuck in the wrong link state
970 ste_miibus_statchg(sc->ste_dev);
971 if (ifp->if_snd.ifq_head != NULL)
976 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
984 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
985 * IDs against our list and return a device name if we find a match.
995 while(t->ste_name != NULL) {
996 if ((pci_get_vendor(dev) == t->ste_vid) &&
997 (pci_get_device(dev) == t->ste_did)) {
998 device_set_desc(dev, t->ste_name);
1008 * Attach the interface. Allocate softc structures, do ifmedia
1009 * setup and ethernet/BPF attach.
1015 struct ste_softc *sc;
1017 int unit, error = 0, rid;
1019 sc = device_get_softc(dev);
1020 unit = device_get_unit(dev);
1024 * Only use one PHY since this chip reports multiple
1025 * Note on the DFE-550 the PHY is at 1 on the DFE-580
1026 * it is at 0 & 1. It is rev 0x12.
1028 if (pci_get_vendor(dev) == DL_VENDORID &&
1029 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
1030 pci_get_revid(dev) == 0x12 )
1031 sc->ste_one_phy = 1;
1033 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1034 MTX_DEF | MTX_RECURSE);
1035 #ifndef BURN_BRIDGES
1037 * Handle power management nonsense.
1039 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1040 u_int32_t iobase, membase, irq;
1042 /* Save important PCI config data. */
1043 iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
1044 membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
1045 irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
1047 /* Reset the power state. */
1048 printf("ste%d: chip is in D%d power mode "
1049 "-- setting to D0\n", unit,
1050 pci_get_powerstate(dev));
1051 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1053 /* Restore PCI config data. */
1054 pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
1055 pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
1056 pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
1060 * Map control/status registers.
1062 pci_enable_busmaster(dev);
1065 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE);
1067 if (sc->ste_res == NULL) {
1068 printf ("ste%d: couldn't map ports/memory\n", unit);
1073 sc->ste_btag = rman_get_bustag(sc->ste_res);
1074 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
1076 /* Allocate interrupt */
1078 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1079 RF_SHAREABLE | RF_ACTIVE);
1081 if (sc->ste_irq == NULL) {
1082 printf("ste%d: couldn't map interrupt\n", unit);
1087 callout_handle_init(&sc->ste_stat_ch);
1089 /* Reset the adapter. */
1093 * Get station address from the EEPROM.
1095 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1096 STE_EEADDR_NODE0, 3, 0)) {
1097 printf("ste%d: failed to read station address\n", unit);
1102 sc->ste_unit = unit;
1104 /* Allocate the descriptor queues. */
1105 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1106 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1108 if (sc->ste_ldata == NULL) {
1109 printf("ste%d: no memory for list buffers!\n", unit);
1114 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1117 if (mii_phy_probe(dev, &sc->ste_miibus,
1118 ste_ifmedia_upd, ste_ifmedia_sts)) {
1119 printf("ste%d: MII without any phy!\n", sc->ste_unit);
1124 ifp = &sc->arpcom.ac_if;
1126 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1127 ifp->if_mtu = ETHERMTU;
1128 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1129 ifp->if_ioctl = ste_ioctl;
1130 ifp->if_start = ste_start;
1131 ifp->if_watchdog = ste_watchdog;
1132 ifp->if_init = ste_init;
1133 ifp->if_baudrate = 10000000;
1134 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1;
1136 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1139 * Call MI attach routine.
1141 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1144 * Tell the upper layer(s) we support long frames.
1146 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1147 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1148 #ifdef DEVICE_POLLING
1149 ifp->if_capabilities |= IFCAP_POLLING;
1151 ifp->if_capenable = ifp->if_capabilities;
1153 /* Hook interrupt last to avoid having to lock softc */
1154 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET,
1155 ste_intr, sc, &sc->ste_intrhand);
1158 printf("ste%d: couldn't set up irq\n", unit);
1159 ether_ifdetach(ifp);
1171 * Shutdown hardware and free up resources. This can be called any
1172 * time after the mutex has been initialized. It is called in both
1173 * the error case in attach and the normal detach case so it needs
1174 * to be careful about only freeing resources that have actually been
1181 struct ste_softc *sc;
1184 sc = device_get_softc(dev);
1185 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1187 ifp = &sc->arpcom.ac_if;
1189 /* These should only be active if attach succeeded */
1190 if (device_is_attached(dev)) {
1192 ether_ifdetach(ifp);
1195 device_delete_child(dev, sc->ste_miibus);
1196 bus_generic_detach(dev);
1198 if (sc->ste_intrhand)
1199 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1201 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1203 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1205 if (sc->ste_ldata) {
1206 contigfree(sc->ste_ldata, sizeof(struct ste_list_data),
1211 mtx_destroy(&sc->ste_mtx);
1217 ste_newbuf(sc, c, m)
1218 struct ste_softc *sc;
1219 struct ste_chain_onefrag *c;
1222 struct mbuf *m_new = NULL;
1225 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1228 MCLGET(m_new, M_DONTWAIT);
1229 if (!(m_new->m_flags & M_EXT)) {
1233 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1236 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1237 m_new->m_data = m_new->m_ext.ext_buf;
1240 m_adj(m_new, ETHER_ALIGN);
1242 c->ste_mbuf = m_new;
1243 c->ste_ptr->ste_status = 0;
1244 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1245 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST;
1251 ste_init_rx_list(sc)
1252 struct ste_softc *sc;
1254 struct ste_chain_data *cd;
1255 struct ste_list_data *ld;
1258 cd = &sc->ste_cdata;
1261 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1262 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1263 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1265 if (i == (STE_RX_LIST_CNT - 1)) {
1266 cd->ste_rx_chain[i].ste_next =
1267 &cd->ste_rx_chain[0];
1268 ld->ste_rx_list[i].ste_next =
1269 vtophys(&ld->ste_rx_list[0]);
1271 cd->ste_rx_chain[i].ste_next =
1272 &cd->ste_rx_chain[i + 1];
1273 ld->ste_rx_list[i].ste_next =
1274 vtophys(&ld->ste_rx_list[i + 1]);
1276 ld->ste_rx_list[i].ste_status = 0;
1279 cd->ste_rx_head = &cd->ste_rx_chain[0];
1285 ste_init_tx_list(sc)
1286 struct ste_softc *sc;
1288 struct ste_chain_data *cd;
1289 struct ste_list_data *ld;
1292 cd = &sc->ste_cdata;
1294 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1295 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1296 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1297 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1298 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1299 if (i == (STE_TX_LIST_CNT - 1))
1300 cd->ste_tx_chain[i].ste_next =
1301 &cd->ste_tx_chain[0];
1303 cd->ste_tx_chain[i].ste_next =
1304 &cd->ste_tx_chain[i + 1];
1307 cd->ste_tx_prod = 0;
1308 cd->ste_tx_cons = 0;
1317 struct ste_softc *sc;
1323 ifp = &sc->arpcom.ac_if;
1327 /* Init our MAC address */
1328 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1329 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1333 if (ste_init_rx_list(sc) == ENOBUFS) {
1334 printf("ste%d: initialization failed: no "
1335 "memory for RX buffers\n", sc->ste_unit);
1341 /* Set RX polling interval */
1342 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1344 /* Init TX descriptors */
1345 ste_init_tx_list(sc);
1347 /* Set the TX freethresh value */
1348 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1350 /* Set the TX start threshold for best performance. */
1351 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1353 /* Set the TX reclaim threshold. */
1354 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1356 /* Set up the RX filter. */
1357 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1359 /* If we want promiscuous mode, set the allframes bit. */
1360 if (ifp->if_flags & IFF_PROMISC) {
1361 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1363 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1366 /* Set capture broadcast bit to accept broadcast frames. */
1367 if (ifp->if_flags & IFF_BROADCAST) {
1368 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1370 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1375 /* Load the address of the RX list. */
1376 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1378 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1379 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1380 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1381 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1383 /* Set TX polling interval (defer until we TX first packet */
1384 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1386 /* Load address of the TX list */
1387 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1389 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1390 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1391 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1393 sc->ste_tx_prev = NULL;
1395 /* Enable receiver and transmitter */
1396 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1397 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1398 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1399 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1401 /* Enable stats counters. */
1402 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1404 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1405 #ifdef DEVICE_POLLING
1406 /* Disable interrupts if we are polling. */
1407 if (ifp->if_flags & IFF_POLLING)
1408 CSR_WRITE_2(sc, STE_IMR, 0);
1410 #endif /* DEVICE_POLLING */
1411 /* Enable interrupts. */
1412 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1414 /* Accept VLAN length packets */
1415 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1417 ste_ifmedia_upd(ifp);
1419 ifp->if_flags |= IFF_RUNNING;
1420 ifp->if_flags &= ~IFF_OACTIVE;
1422 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
1430 struct ste_softc *sc;
1436 ifp = &sc->arpcom.ac_if;
1438 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
1439 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1440 #ifdef DEVICE_POLLING
1441 ether_poll_deregister(ifp);
1442 #endif /* DEVICE_POLLING */
1444 CSR_WRITE_2(sc, STE_IMR, 0);
1445 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1446 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1447 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1448 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1449 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1452 * Try really hard to stop the RX engine or under heavy RX
1453 * data chip will write into de-allocated memory.
1459 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1460 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1461 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1462 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1466 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1467 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1468 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1469 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1473 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1481 struct ste_softc *sc;
1485 STE_SETBIT4(sc, STE_ASICCTL,
1486 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1487 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1488 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1489 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1490 STE_ASICCTL_EXTRESET_RESET);
1494 for (i = 0; i < STE_TIMEOUT; i++) {
1495 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1499 if (i == STE_TIMEOUT)
1500 printf("ste%d: global reset never completed\n", sc->ste_unit);
1506 ste_ioctl(ifp, command, data)
1511 struct ste_softc *sc;
1513 struct mii_data *mii;
1518 ifr = (struct ifreq *)data;
1522 if (ifp->if_flags & IFF_UP) {
1523 if (ifp->if_flags & IFF_RUNNING &&
1524 ifp->if_flags & IFF_PROMISC &&
1525 !(sc->ste_if_flags & IFF_PROMISC)) {
1526 STE_SETBIT1(sc, STE_RX_MODE,
1527 STE_RXMODE_PROMISC);
1528 } else if (ifp->if_flags & IFF_RUNNING &&
1529 !(ifp->if_flags & IFF_PROMISC) &&
1530 sc->ste_if_flags & IFF_PROMISC) {
1531 STE_CLRBIT1(sc, STE_RX_MODE,
1532 STE_RXMODE_PROMISC);
1534 if (ifp->if_flags & IFF_RUNNING &&
1535 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI)
1537 if (!(ifp->if_flags & IFF_RUNNING)) {
1538 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1542 if (ifp->if_flags & IFF_RUNNING)
1545 sc->ste_if_flags = ifp->if_flags;
1555 mii = device_get_softc(sc->ste_miibus);
1556 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1559 ifp->if_capenable &= ~IFCAP_POLLING;
1560 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING;
1563 error = ether_ioctl(ifp, command, data);
1573 ste_encap(sc, c, m_head)
1574 struct ste_softc *sc;
1575 struct ste_chain *c;
1576 struct mbuf *m_head;
1579 struct ste_frag *f = NULL;
1587 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1588 if (m->m_len != 0) {
1589 if (frag == STE_MAXFRAGS)
1591 f = &d->ste_frags[frag];
1592 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1593 f->ste_len = m->m_len;
1602 * We ran out of segments. We have to recopy this
1603 * mbuf chain first. Bail out if we can't get the
1606 mn = m_defrag(m_head, M_DONTWAIT);
1615 c->ste_mbuf = m_head;
1616 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1626 struct ste_softc *sc;
1627 struct mbuf *m_head = NULL;
1628 struct ste_chain *cur_tx;
1634 if (!sc->ste_link) {
1639 if (ifp->if_flags & IFF_OACTIVE) {
1644 idx = sc->ste_cdata.ste_tx_prod;
1646 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1648 * We cannot re-use the last (free) descriptor;
1649 * the chip may not have read its ste_next yet.
1651 if (STE_NEXT(idx, STE_TX_LIST_CNT) ==
1652 sc->ste_cdata.ste_tx_cons) {
1653 ifp->if_flags |= IFF_OACTIVE;
1657 IF_DEQUEUE(&ifp->if_snd, m_head);
1661 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1663 if (ste_encap(sc, cur_tx, m_head) != 0)
1666 cur_tx->ste_ptr->ste_next = 0;
1668 if (sc->ste_tx_prev == NULL) {
1669 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1670 /* Load address of the TX list */
1671 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1674 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1675 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1677 /* Set TX polling interval to start TX engine */
1678 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1680 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1683 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1684 sc->ste_tx_prev->ste_ptr->ste_next
1688 sc->ste_tx_prev = cur_tx;
1691 * If there's a BPF listener, bounce a copy of this frame
1694 BPF_MTAP(ifp, cur_tx->ste_mbuf);
1696 STE_INC(idx, STE_TX_LIST_CNT);
1699 sc->ste_cdata.ste_tx_prod = idx;
1710 struct ste_softc *sc;
1716 printf("ste%d: watchdog timeout\n", sc->ste_unit);
1725 if (ifp->if_snd.ifq_head != NULL)
1736 struct ste_softc *sc;
1738 sc = device_get_softc(dev);