2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/sockio.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
46 #include <net/if_arp.h>
47 #include <net/ethernet.h>
48 #include <net/if_dl.h>
49 #include <net/if_media.h>
50 #include <net/if_vlan_var.h>
54 #include <vm/vm.h> /* for vtophys */
55 #include <vm/pmap.h> /* for vtophys */
56 #include <machine/bus_memio.h>
57 #include <machine/bus_pio.h>
58 #include <machine/bus.h>
59 #include <machine/resource.h>
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
69 /* "controller miibus0" required. See GENERIC if you get errors here. */
70 #include "miibus_if.h"
72 #define STE_USEIOSPACE
74 #include <pci/if_stereg.h>
76 MODULE_DEPEND(ste, pci, 1, 1, 1);
77 MODULE_DEPEND(ste, ether, 1, 1, 1);
78 MODULE_DEPEND(ste, miibus, 1, 1, 1);
81 * Various supported device vendors/types and their names.
83 static struct ste_type ste_devs[] = {
84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
85 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" },
89 static int ste_probe (device_t);
90 static int ste_attach (device_t);
91 static int ste_detach (device_t);
92 static void ste_init (void *);
93 static void ste_intr (void *);
94 static void ste_rxeoc (struct ste_softc *);
95 static void ste_rxeof (struct ste_softc *);
96 static void ste_txeoc (struct ste_softc *);
97 static void ste_txeof (struct ste_softc *);
98 static void ste_stats_update (void *);
99 static void ste_stop (struct ste_softc *);
100 static void ste_reset (struct ste_softc *);
101 static int ste_ioctl (struct ifnet *, u_long, caddr_t);
102 static int ste_encap (struct ste_softc *, struct ste_chain *,
104 static void ste_start (struct ifnet *);
105 static void ste_watchdog (struct ifnet *);
106 static void ste_shutdown (device_t);
107 static int ste_newbuf (struct ste_softc *,
108 struct ste_chain_onefrag *,
110 static int ste_ifmedia_upd (struct ifnet *);
111 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *);
113 static void ste_mii_sync (struct ste_softc *);
114 static void ste_mii_send (struct ste_softc *, u_int32_t, int);
115 static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *);
116 static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *);
117 static int ste_miibus_readreg (device_t, int, int);
118 static int ste_miibus_writereg (device_t, int, int, int);
119 static void ste_miibus_statchg (device_t);
121 static int ste_eeprom_wait (struct ste_softc *);
122 static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int);
123 static void ste_wait (struct ste_softc *);
124 static u_int8_t ste_calchash (caddr_t);
125 static void ste_setmulti (struct ste_softc *);
126 static int ste_init_rx_list (struct ste_softc *);
127 static void ste_init_tx_list (struct ste_softc *);
129 #ifdef STE_USEIOSPACE
130 #define STE_RES SYS_RES_IOPORT
131 #define STE_RID STE_PCI_LOIO
133 #define STE_RES SYS_RES_MEMORY
134 #define STE_RID STE_PCI_LOMEM
137 static device_method_t ste_methods[] = {
138 /* Device interface */
139 DEVMETHOD(device_probe, ste_probe),
140 DEVMETHOD(device_attach, ste_attach),
141 DEVMETHOD(device_detach, ste_detach),
142 DEVMETHOD(device_shutdown, ste_shutdown),
145 DEVMETHOD(bus_print_child, bus_generic_print_child),
146 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
149 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
150 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
151 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
156 static driver_t ste_driver = {
159 sizeof(struct ste_softc)
162 static devclass_t ste_devclass;
164 DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0);
165 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
167 SYSCTL_NODE(_hw, OID_AUTO, ste, CTLFLAG_RD, 0, "if_ste parameters");
169 static int ste_rxsyncs;
170 SYSCTL_INT(_hw_ste, OID_AUTO, rxsyncs, CTLFLAG_RW, &ste_rxsyncs, 0, "");
172 #define STE_SETBIT4(sc, reg, x) \
173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
175 #define STE_CLRBIT4(sc, reg, x) \
176 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
178 #define STE_SETBIT2(sc, reg, x) \
179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
181 #define STE_CLRBIT2(sc, reg, x) \
182 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
184 #define STE_SETBIT1(sc, reg, x) \
185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
187 #define STE_CLRBIT1(sc, reg, x) \
188 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
191 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
192 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
195 * Sync the PHYs by setting data bit and strobing the clock 32 times.
199 struct ste_softc *sc;
203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
205 for (i = 0; i < 32; i++) {
206 MII_SET(STE_PHYCTL_MCLK);
208 MII_CLR(STE_PHYCTL_MCLK);
216 * Clock a series of bits through the MII.
219 ste_mii_send(sc, bits, cnt)
220 struct ste_softc *sc;
226 MII_CLR(STE_PHYCTL_MCLK);
228 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
230 MII_SET(STE_PHYCTL_MDATA);
232 MII_CLR(STE_PHYCTL_MDATA);
235 MII_CLR(STE_PHYCTL_MCLK);
237 MII_SET(STE_PHYCTL_MCLK);
242 * Read an PHY register through the MII.
245 ste_mii_readreg(sc, frame)
246 struct ste_softc *sc;
247 struct ste_mii_frame *frame;
255 * Set up frame for RX.
257 frame->mii_stdelim = STE_MII_STARTDELIM;
258 frame->mii_opcode = STE_MII_READOP;
259 frame->mii_turnaround = 0;
262 CSR_WRITE_2(sc, STE_PHYCTL, 0);
266 MII_SET(STE_PHYCTL_MDIR);
271 * Send command/address info.
273 ste_mii_send(sc, frame->mii_stdelim, 2);
274 ste_mii_send(sc, frame->mii_opcode, 2);
275 ste_mii_send(sc, frame->mii_phyaddr, 5);
276 ste_mii_send(sc, frame->mii_regaddr, 5);
279 MII_CLR(STE_PHYCTL_MDIR);
282 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
284 MII_SET(STE_PHYCTL_MCLK);
288 MII_CLR(STE_PHYCTL_MCLK);
290 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
291 MII_SET(STE_PHYCTL_MCLK);
295 * Now try reading data bits. If the ack failed, we still
296 * need to clock through 16 cycles to keep the PHY(s) in sync.
299 for(i = 0; i < 16; i++) {
300 MII_CLR(STE_PHYCTL_MCLK);
302 MII_SET(STE_PHYCTL_MCLK);
308 for (i = 0x8000; i; i >>= 1) {
309 MII_CLR(STE_PHYCTL_MCLK);
312 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
313 frame->mii_data |= i;
316 MII_SET(STE_PHYCTL_MCLK);
322 MII_CLR(STE_PHYCTL_MCLK);
324 MII_SET(STE_PHYCTL_MCLK);
335 * Write to a PHY register through the MII.
338 ste_mii_writereg(sc, frame)
339 struct ste_softc *sc;
340 struct ste_mii_frame *frame;
346 * Set up frame for TX.
349 frame->mii_stdelim = STE_MII_STARTDELIM;
350 frame->mii_opcode = STE_MII_WRITEOP;
351 frame->mii_turnaround = STE_MII_TURNAROUND;
354 * Turn on data output.
356 MII_SET(STE_PHYCTL_MDIR);
360 ste_mii_send(sc, frame->mii_stdelim, 2);
361 ste_mii_send(sc, frame->mii_opcode, 2);
362 ste_mii_send(sc, frame->mii_phyaddr, 5);
363 ste_mii_send(sc, frame->mii_regaddr, 5);
364 ste_mii_send(sc, frame->mii_turnaround, 2);
365 ste_mii_send(sc, frame->mii_data, 16);
368 MII_SET(STE_PHYCTL_MCLK);
370 MII_CLR(STE_PHYCTL_MCLK);
376 MII_CLR(STE_PHYCTL_MDIR);
384 ste_miibus_readreg(dev, phy, reg)
388 struct ste_softc *sc;
389 struct ste_mii_frame frame;
391 sc = device_get_softc(dev);
393 if ( sc->ste_one_phy && phy != 0 )
396 bzero((char *)&frame, sizeof(frame));
398 frame.mii_phyaddr = phy;
399 frame.mii_regaddr = reg;
400 ste_mii_readreg(sc, &frame);
402 return(frame.mii_data);
406 ste_miibus_writereg(dev, phy, reg, data)
410 struct ste_softc *sc;
411 struct ste_mii_frame frame;
413 sc = device_get_softc(dev);
414 bzero((char *)&frame, sizeof(frame));
416 frame.mii_phyaddr = phy;
417 frame.mii_regaddr = reg;
418 frame.mii_data = data;
420 ste_mii_writereg(sc, &frame);
426 ste_miibus_statchg(dev)
429 struct ste_softc *sc;
430 struct mii_data *mii;
432 sc = device_get_softc(dev);
434 mii = device_get_softc(sc->ste_miibus);
436 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
437 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
439 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
450 struct ste_softc *sc;
451 struct mii_data *mii;
454 mii = device_get_softc(sc->ste_miibus);
456 if (mii->mii_instance) {
457 struct mii_softc *miisc;
458 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
459 mii_phy_reset(miisc);
467 ste_ifmedia_sts(ifp, ifmr)
469 struct ifmediareq *ifmr;
471 struct ste_softc *sc;
472 struct mii_data *mii;
475 mii = device_get_softc(sc->ste_miibus);
478 ifmr->ifm_active = mii->mii_media_active;
479 ifmr->ifm_status = mii->mii_media_status;
486 struct ste_softc *sc;
490 for (i = 0; i < STE_TIMEOUT; i++) {
491 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
495 if (i == STE_TIMEOUT)
496 printf("ste%d: command never completed!\n", sc->ste_unit);
502 * The EEPROM is slow: give it time to come ready after issuing
507 struct ste_softc *sc;
513 for (i = 0; i < 100; i++) {
514 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
521 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit);
529 * Read a sequence of words from the EEPROM. Note that ethernet address
530 * data is stored in the EEPROM in network byte order.
533 ste_read_eeprom(sc, dest, off, cnt, swap)
534 struct ste_softc *sc;
541 u_int16_t word = 0, *ptr;
543 if (ste_eeprom_wait(sc))
546 for (i = 0; i < cnt; i++) {
547 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
548 err = ste_eeprom_wait(sc);
551 word = CSR_READ_2(sc, STE_EEPROM_DATA);
552 ptr = (u_int16_t *)(dest + (i * 2));
567 u_int32_t crc, carry;
571 /* Compute CRC for the address value. */
572 crc = 0xFFFFFFFF; /* initial value */
574 for (i = 0; i < 6; i++) {
576 for (j = 0; j < 8; j++) {
577 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
581 crc = (crc ^ 0x04c11db6) | carry;
585 /* return the filter bit position */
586 return(crc & 0x0000003F);
591 struct ste_softc *sc;
595 u_int32_t hashes[2] = { 0, 0 };
596 struct ifmultiaddr *ifma;
598 ifp = &sc->arpcom.ac_if;
599 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
600 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
601 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
605 /* first, zot all the existing hash bits */
606 CSR_WRITE_2(sc, STE_MAR0, 0);
607 CSR_WRITE_2(sc, STE_MAR1, 0);
608 CSR_WRITE_2(sc, STE_MAR2, 0);
609 CSR_WRITE_2(sc, STE_MAR3, 0);
611 /* now program new ones */
612 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
613 if (ifma->ifma_addr->sa_family != AF_LINK)
615 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
617 hashes[0] |= (1 << h);
619 hashes[1] |= (1 << (h - 32));
622 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
623 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
624 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
625 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
626 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
627 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
632 #ifdef DEVICE_POLLING
633 static poll_handler_t ste_poll;
636 ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
638 struct ste_softc *sc = ifp->if_softc;
641 if (!(ifp->if_capenable & IFCAP_POLLING)) {
642 ether_poll_deregister(ifp);
643 cmd = POLL_DEREGISTER;
645 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
646 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
650 sc->rxcycles = count;
651 if (cmd == POLL_AND_CHECK_STATUS)
655 if (ifp->if_snd.ifq_head != NULL)
658 if (cmd == POLL_AND_CHECK_STATUS) {
661 status = CSR_READ_2(sc, STE_ISR_ACK);
663 if (status & STE_ISR_TX_DONE)
666 if (status & STE_ISR_STATS_OFLOW) {
667 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
668 ste_stats_update(sc);
671 if (status & STE_ISR_LINKEVENT)
672 mii_pollstat(device_get_softc(sc->ste_miibus));
674 if (status & STE_ISR_HOSTERR) {
682 #endif /* DEVICE_POLLING */
688 struct ste_softc *sc;
694 ifp = &sc->arpcom.ac_if;
696 #ifdef DEVICE_POLLING
697 if (ifp->if_flags & IFF_POLLING)
699 if ((ifp->if_capenable & IFCAP_POLLING) &&
700 ether_poll_register(ste_poll, ifp)) { /* ok, disable interrupts */
701 CSR_WRITE_2(sc, STE_IMR, 0);
705 #endif /* DEVICE_POLLING */
707 /* See if this is really our interrupt. */
708 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) {
714 status = CSR_READ_2(sc, STE_ISR_ACK);
716 if (!(status & STE_INTRS))
719 if (status & STE_ISR_RX_DMADONE) {
724 if (status & STE_ISR_TX_DMADONE)
727 if (status & STE_ISR_TX_DONE)
730 if (status & STE_ISR_STATS_OFLOW) {
731 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
732 ste_stats_update(sc);
735 if (status & STE_ISR_LINKEVENT)
736 mii_pollstat(device_get_softc(sc->ste_miibus));
739 if (status & STE_ISR_HOSTERR) {
745 /* Re-enable interrupts */
746 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
748 if (ifp->if_snd.ifq_head != NULL)
751 #ifdef DEVICE_POLLING
753 #endif /* DEVICE_POLLING */
760 ste_rxeoc(struct ste_softc *sc)
762 struct ste_chain_onefrag *cur_rx;
766 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
767 cur_rx = sc->ste_cdata.ste_rx_head;
769 cur_rx = cur_rx->ste_next;
770 /* If the ring is empty, just return. */
771 if (cur_rx == sc->ste_cdata.ste_rx_head)
773 } while (cur_rx->ste_ptr->ste_status == 0);
774 if (sc->ste_cdata.ste_rx_head->ste_ptr->ste_status == 0) {
775 /* We've fallen behind the chip: catch it. */
776 sc->ste_cdata.ste_rx_head = cur_rx;
783 * A frame has been uploaded: pass the resulting mbuf chain up to
784 * the higher level protocols.
788 struct ste_softc *sc;
792 struct ste_chain_onefrag *cur_rx;
793 int total_len = 0, count=0;
798 ifp = &sc->arpcom.ac_if;
800 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
801 & STE_RXSTAT_DMADONE) {
802 #ifdef DEVICE_POLLING
803 if (ifp->if_flags & IFF_POLLING) {
804 if (sc->rxcycles <= 0)
808 #endif /* DEVICE_POLLING */
809 if ((STE_RX_LIST_CNT - count) < 3) {
813 cur_rx = sc->ste_cdata.ste_rx_head;
814 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
817 * If an error occurs, update stats, clear the
818 * status word and leave the mbuf cluster in place:
819 * it should simply get re-used next time this descriptor
820 * comes up in the ring.
822 if (rxstat & STE_RXSTAT_FRAME_ERR) {
824 cur_rx->ste_ptr->ste_status = 0;
829 * If there error bit was not set, the upload complete
830 * bit should be set which means we have a valid packet.
831 * If not, something truly strange has happened.
833 if (!(rxstat & STE_RXSTAT_DMADONE)) {
834 printf("ste%d: bad receive status -- packet dropped\n",
837 cur_rx->ste_ptr->ste_status = 0;
841 /* No errors; receive the packet. */
842 m = cur_rx->ste_mbuf;
843 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
846 * Try to conjure up a new mbuf cluster. If that
847 * fails, it means we have an out of memory condition and
848 * should leave the buffer in place and continue. This will
849 * result in a lost packet, but there's little else we
850 * can do in this situation.
852 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
854 cur_rx->ste_ptr->ste_status = 0;
858 m->m_pkthdr.rcvif = ifp;
859 m->m_pkthdr.len = m->m_len = total_len;
863 (*ifp->if_input)(ifp, m);
866 cur_rx->ste_ptr->ste_status = 0;
875 struct ste_softc *sc;
880 ifp = &sc->arpcom.ac_if;
882 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
883 STE_TXSTATUS_TXDONE) {
884 if (txstat & STE_TXSTATUS_UNDERRUN ||
885 txstat & STE_TXSTATUS_EXCESSCOLLS ||
886 txstat & STE_TXSTATUS_RECLAIMERR) {
888 printf("ste%d: transmission error: %x\n",
889 sc->ste_unit, txstat);
894 if (txstat & STE_TXSTATUS_UNDERRUN &&
895 sc->ste_tx_thresh < STE_PACKET_SIZE) {
896 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
897 printf("ste%d: tx underrun, increasing tx"
898 " start threshold to %d bytes\n",
899 sc->ste_unit, sc->ste_tx_thresh);
901 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
902 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
903 (STE_PACKET_SIZE >> 4));
906 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
914 struct ste_softc *sc;
916 struct ste_chain *cur_tx;
920 ifp = &sc->arpcom.ac_if;
922 idx = sc->ste_cdata.ste_tx_cons;
923 while(idx != sc->ste_cdata.ste_tx_prod) {
924 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
926 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
929 m_freem(cur_tx->ste_mbuf);
930 cur_tx->ste_mbuf = NULL;
931 ifp->if_flags &= ~IFF_OACTIVE;
934 STE_INC(idx, STE_TX_LIST_CNT);
937 sc->ste_cdata.ste_tx_cons = idx;
938 if (idx == sc->ste_cdata.ste_tx_prod)
943 ste_stats_update(xsc)
946 struct ste_softc *sc;
948 struct mii_data *mii;
953 ifp = &sc->arpcom.ac_if;
954 mii = device_get_softc(sc->ste_miibus);
956 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
957 + CSR_READ_1(sc, STE_MULTI_COLLS)
958 + CSR_READ_1(sc, STE_SINGLE_COLLS);
962 if (mii->mii_media_status & IFM_ACTIVE &&
963 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
966 * we don't get a call-back on re-init so do it
967 * otherwise we get stuck in the wrong link state
969 ste_miibus_statchg(sc->ste_dev);
970 if (ifp->if_snd.ifq_head != NULL)
975 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
983 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
984 * IDs against our list and return a device name if we find a match.
994 while(t->ste_name != NULL) {
995 if ((pci_get_vendor(dev) == t->ste_vid) &&
996 (pci_get_device(dev) == t->ste_did)) {
997 device_set_desc(dev, t->ste_name);
1007 * Attach the interface. Allocate softc structures, do ifmedia
1008 * setup and ethernet/BPF attach.
1014 struct ste_softc *sc;
1016 int unit, error = 0, rid;
1018 sc = device_get_softc(dev);
1019 unit = device_get_unit(dev);
1023 * Only use one PHY since this chip reports multiple
1024 * Note on the DFE-550 the PHY is at 1 on the DFE-580
1025 * it is at 0 & 1. It is rev 0x12.
1027 if (pci_get_vendor(dev) == DL_VENDORID &&
1028 pci_get_device(dev) == DL_DEVICEID_DL10050 &&
1029 pci_get_revid(dev) == 0x12 )
1030 sc->ste_one_phy = 1;
1032 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1033 MTX_DEF | MTX_RECURSE);
1034 #ifndef BURN_BRIDGES
1036 * Handle power management nonsense.
1038 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1039 u_int32_t iobase, membase, irq;
1041 /* Save important PCI config data. */
1042 iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
1043 membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
1044 irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
1046 /* Reset the power state. */
1047 printf("ste%d: chip is in D%d power mode "
1048 "-- setting to D0\n", unit,
1049 pci_get_powerstate(dev));
1050 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1052 /* Restore PCI config data. */
1053 pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
1054 pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
1055 pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
1059 * Map control/status registers.
1061 pci_enable_busmaster(dev);
1064 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE);
1066 if (sc->ste_res == NULL) {
1067 printf ("ste%d: couldn't map ports/memory\n", unit);
1072 sc->ste_btag = rman_get_bustag(sc->ste_res);
1073 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
1075 /* Allocate interrupt */
1077 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1078 RF_SHAREABLE | RF_ACTIVE);
1080 if (sc->ste_irq == NULL) {
1081 printf("ste%d: couldn't map interrupt\n", unit);
1086 callout_handle_init(&sc->ste_stat_ch);
1088 /* Reset the adapter. */
1092 * Get station address from the EEPROM.
1094 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1095 STE_EEADDR_NODE0, 3, 0)) {
1096 printf("ste%d: failed to read station address\n", unit);
1101 sc->ste_unit = unit;
1103 /* Allocate the descriptor queues. */
1104 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1105 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1107 if (sc->ste_ldata == NULL) {
1108 printf("ste%d: no memory for list buffers!\n", unit);
1113 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1116 if (mii_phy_probe(dev, &sc->ste_miibus,
1117 ste_ifmedia_upd, ste_ifmedia_sts)) {
1118 printf("ste%d: MII without any phy!\n", sc->ste_unit);
1123 ifp = &sc->arpcom.ac_if;
1125 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1126 ifp->if_mtu = ETHERMTU;
1127 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1128 ifp->if_ioctl = ste_ioctl;
1129 ifp->if_start = ste_start;
1130 ifp->if_watchdog = ste_watchdog;
1131 ifp->if_init = ste_init;
1132 ifp->if_baudrate = 10000000;
1133 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1;
1135 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1138 * Call MI attach routine.
1140 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1143 * Tell the upper layer(s) we support long frames.
1145 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1146 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1147 #ifdef DEVICE_POLLING
1148 ifp->if_capabilities |= IFCAP_POLLING;
1150 ifp->if_capenable = ifp->if_capabilities;
1152 /* Hook interrupt last to avoid having to lock softc */
1153 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET,
1154 ste_intr, sc, &sc->ste_intrhand);
1157 printf("ste%d: couldn't set up irq\n", unit);
1158 ether_ifdetach(ifp);
1170 * Shutdown hardware and free up resources. This can be called any
1171 * time after the mutex has been initialized. It is called in both
1172 * the error case in attach and the normal detach case so it needs
1173 * to be careful about only freeing resources that have actually been
1180 struct ste_softc *sc;
1183 sc = device_get_softc(dev);
1184 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized"));
1186 ifp = &sc->arpcom.ac_if;
1188 /* These should only be active if attach succeeded */
1189 if (device_is_attached(dev)) {
1191 ether_ifdetach(ifp);
1194 device_delete_child(dev, sc->ste_miibus);
1195 bus_generic_detach(dev);
1197 if (sc->ste_intrhand)
1198 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1200 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1202 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1204 if (sc->ste_ldata) {
1205 contigfree(sc->ste_ldata, sizeof(struct ste_list_data),
1210 mtx_destroy(&sc->ste_mtx);
1216 ste_newbuf(sc, c, m)
1217 struct ste_softc *sc;
1218 struct ste_chain_onefrag *c;
1221 struct mbuf *m_new = NULL;
1224 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1227 MCLGET(m_new, M_DONTWAIT);
1228 if (!(m_new->m_flags & M_EXT)) {
1232 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1235 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1236 m_new->m_data = m_new->m_ext.ext_buf;
1239 m_adj(m_new, ETHER_ALIGN);
1241 c->ste_mbuf = m_new;
1242 c->ste_ptr->ste_status = 0;
1243 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1244 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST;
1250 ste_init_rx_list(sc)
1251 struct ste_softc *sc;
1253 struct ste_chain_data *cd;
1254 struct ste_list_data *ld;
1257 cd = &sc->ste_cdata;
1260 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1261 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1262 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1264 if (i == (STE_RX_LIST_CNT - 1)) {
1265 cd->ste_rx_chain[i].ste_next =
1266 &cd->ste_rx_chain[0];
1267 ld->ste_rx_list[i].ste_next =
1268 vtophys(&ld->ste_rx_list[0]);
1270 cd->ste_rx_chain[i].ste_next =
1271 &cd->ste_rx_chain[i + 1];
1272 ld->ste_rx_list[i].ste_next =
1273 vtophys(&ld->ste_rx_list[i + 1]);
1275 ld->ste_rx_list[i].ste_status = 0;
1278 cd->ste_rx_head = &cd->ste_rx_chain[0];
1284 ste_init_tx_list(sc)
1285 struct ste_softc *sc;
1287 struct ste_chain_data *cd;
1288 struct ste_list_data *ld;
1291 cd = &sc->ste_cdata;
1293 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1294 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1295 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1296 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1297 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1298 if (i == (STE_TX_LIST_CNT - 1))
1299 cd->ste_tx_chain[i].ste_next =
1300 &cd->ste_tx_chain[0];
1302 cd->ste_tx_chain[i].ste_next =
1303 &cd->ste_tx_chain[i + 1];
1306 cd->ste_tx_prod = 0;
1307 cd->ste_tx_cons = 0;
1316 struct ste_softc *sc;
1322 ifp = &sc->arpcom.ac_if;
1326 /* Init our MAC address */
1327 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1328 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1332 if (ste_init_rx_list(sc) == ENOBUFS) {
1333 printf("ste%d: initialization failed: no "
1334 "memory for RX buffers\n", sc->ste_unit);
1340 /* Set RX polling interval */
1341 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1343 /* Init TX descriptors */
1344 ste_init_tx_list(sc);
1346 /* Set the TX freethresh value */
1347 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1349 /* Set the TX start threshold for best performance. */
1350 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1352 /* Set the TX reclaim threshold. */
1353 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1355 /* Set up the RX filter. */
1356 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1358 /* If we want promiscuous mode, set the allframes bit. */
1359 if (ifp->if_flags & IFF_PROMISC) {
1360 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1362 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1365 /* Set capture broadcast bit to accept broadcast frames. */
1366 if (ifp->if_flags & IFF_BROADCAST) {
1367 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1369 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1374 /* Load the address of the RX list. */
1375 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1377 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1378 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1379 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1380 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1382 /* Set TX polling interval (defer until we TX first packet */
1383 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1385 /* Load address of the TX list */
1386 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1388 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1389 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1390 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1392 sc->ste_tx_prev = NULL;
1394 /* Enable receiver and transmitter */
1395 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1396 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1397 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1398 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1400 /* Enable stats counters. */
1401 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1403 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1404 #ifdef DEVICE_POLLING
1405 /* Disable interrupts if we are polling. */
1406 if (ifp->if_flags & IFF_POLLING)
1407 CSR_WRITE_2(sc, STE_IMR, 0);
1409 #endif /* DEVICE_POLLING */
1410 /* Enable interrupts. */
1411 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1413 /* Accept VLAN length packets */
1414 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
1416 ste_ifmedia_upd(ifp);
1418 ifp->if_flags |= IFF_RUNNING;
1419 ifp->if_flags &= ~IFF_OACTIVE;
1421 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
1429 struct ste_softc *sc;
1435 ifp = &sc->arpcom.ac_if;
1437 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
1438 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1439 #ifdef DEVICE_POLLING
1440 ether_poll_deregister(ifp);
1441 #endif /* DEVICE_POLLING */
1443 CSR_WRITE_2(sc, STE_IMR, 0);
1444 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1445 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1446 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1447 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1448 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1451 * Try really hard to stop the RX engine or under heavy RX
1452 * data chip will write into de-allocated memory.
1458 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1459 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1460 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1461 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1465 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1466 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1467 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1468 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1472 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1480 struct ste_softc *sc;
1484 STE_SETBIT4(sc, STE_ASICCTL,
1485 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1486 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1487 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1488 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1489 STE_ASICCTL_EXTRESET_RESET);
1493 for (i = 0; i < STE_TIMEOUT; i++) {
1494 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1498 if (i == STE_TIMEOUT)
1499 printf("ste%d: global reset never completed\n", sc->ste_unit);
1505 ste_ioctl(ifp, command, data)
1510 struct ste_softc *sc;
1512 struct mii_data *mii;
1517 ifr = (struct ifreq *)data;
1521 if (ifp->if_flags & IFF_UP) {
1522 if (ifp->if_flags & IFF_RUNNING &&
1523 ifp->if_flags & IFF_PROMISC &&
1524 !(sc->ste_if_flags & IFF_PROMISC)) {
1525 STE_SETBIT1(sc, STE_RX_MODE,
1526 STE_RXMODE_PROMISC);
1527 } else if (ifp->if_flags & IFF_RUNNING &&
1528 !(ifp->if_flags & IFF_PROMISC) &&
1529 sc->ste_if_flags & IFF_PROMISC) {
1530 STE_CLRBIT1(sc, STE_RX_MODE,
1531 STE_RXMODE_PROMISC);
1533 if (ifp->if_flags & IFF_RUNNING &&
1534 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI)
1536 if (!(ifp->if_flags & IFF_RUNNING)) {
1537 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1541 if (ifp->if_flags & IFF_RUNNING)
1544 sc->ste_if_flags = ifp->if_flags;
1554 mii = device_get_softc(sc->ste_miibus);
1555 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1558 ifp->if_capenable = ifr->ifr_reqcap;
1561 error = ether_ioctl(ifp, command, data);
1571 ste_encap(sc, c, m_head)
1572 struct ste_softc *sc;
1573 struct ste_chain *c;
1574 struct mbuf *m_head;
1577 struct ste_frag *f = NULL;
1585 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1586 if (m->m_len != 0) {
1587 if (frag == STE_MAXFRAGS)
1589 f = &d->ste_frags[frag];
1590 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1591 f->ste_len = m->m_len;
1600 * We ran out of segments. We have to recopy this
1601 * mbuf chain first. Bail out if we can't get the
1604 mn = m_defrag(m_head, M_DONTWAIT);
1613 c->ste_mbuf = m_head;
1614 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1624 struct ste_softc *sc;
1625 struct mbuf *m_head = NULL;
1626 struct ste_chain *cur_tx;
1632 if (!sc->ste_link) {
1637 if (ifp->if_flags & IFF_OACTIVE) {
1642 idx = sc->ste_cdata.ste_tx_prod;
1644 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1646 * We cannot re-use the last (free) descriptor;
1647 * the chip may not have read its ste_next yet.
1649 if (STE_NEXT(idx, STE_TX_LIST_CNT) ==
1650 sc->ste_cdata.ste_tx_cons) {
1651 ifp->if_flags |= IFF_OACTIVE;
1655 IF_DEQUEUE(&ifp->if_snd, m_head);
1659 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1661 if (ste_encap(sc, cur_tx, m_head) != 0)
1664 cur_tx->ste_ptr->ste_next = 0;
1666 if (sc->ste_tx_prev == NULL) {
1667 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1668 /* Load address of the TX list */
1669 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1672 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1673 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1675 /* Set TX polling interval to start TX engine */
1676 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1678 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1681 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1682 sc->ste_tx_prev->ste_ptr->ste_next
1686 sc->ste_tx_prev = cur_tx;
1689 * If there's a BPF listener, bounce a copy of this frame
1692 BPF_MTAP(ifp, cur_tx->ste_mbuf);
1694 STE_INC(idx, STE_TX_LIST_CNT);
1697 sc->ste_cdata.ste_tx_prod = idx;
1708 struct ste_softc *sc;
1714 printf("ste%d: watchdog timeout\n", sc->ste_unit);
1723 if (ifp->if_snd.ifq_head != NULL)
1734 struct ste_softc *sc;
1736 sc = device_get_softc(dev);