2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35 * Manuals, sample driver and firmware source kits are available
36 * from http://www.alteon.com/support/openkits.
38 * Written by Bill Paul <wpaul@ctr.columbia.edu>
39 * Electrical Engineering Department
40 * Columbia University, New York City
44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48 * filtering and jumbo (9014 byte) frames. The hardware is largely
49 * controlled by firmware, which must be loaded into the NIC during
52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53 * revision, which supports new features such as extended commands,
54 * extended jumbo receive ring desciptors and a mini receive ring.
56 * Alteon Networks is to be commended for releasing such a vast amount
57 * of development material for the Tigon NIC without requiring an NDA
58 * (although they really should have done it a long time ago). With
59 * any luck, the other vendors will finally wise up and follow Alteon's
62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63 * this driver by #including it as a C header file. This bloats the
64 * driver somewhat, but it's the easiest method considering that the
65 * driver code and firmware code need to be kept in sync. The source
66 * for the firmware is not provided with the FreeBSD distribution since
67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
69 * The following people deserve special thanks:
70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
72 * - Raymond Lee of Netgear, for providing a pair of Netgear
73 * GA620 Tigon 2 boards for testing
74 * - Ulf Zimmermann, for bringing the GA260 to my attention and
75 * convincing me to write this driver.
76 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/socket.h>
92 #include <sys/queue.h>
96 #include <net/if_arp.h>
97 #include <net/ethernet.h>
98 #include <net/if_dl.h>
99 #include <net/if_media.h>
100 #include <net/if_types.h>
101 #include <net/if_vlan_var.h>
105 #include <netinet/in_systm.h>
106 #include <netinet/in.h>
107 #include <netinet/ip.h>
109 #include <vm/vm.h> /* for vtophys */
110 #include <vm/pmap.h> /* for vtophys */
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 /* #define TI_PRIVATE_JUMBOS */
118 #if !defined(TI_PRIVATE_JUMBOS)
119 #include <sys/sockio.h>
121 #include <sys/lock.h>
122 #include <sys/sf_buf.h>
123 #include <vm/vm_extern.h>
125 #include <vm/vm_map.h>
126 #include <vm/vm_map.h>
127 #include <vm/vm_param.h>
128 #include <vm/vm_pageout.h>
129 #include <sys/vmmeter.h>
130 #include <vm/vm_page.h>
131 #include <vm/vm_object.h>
132 #include <vm/vm_kern.h>
133 #include <sys/proc.h>
134 #endif /* !TI_PRIVATE_JUMBOS */
136 #include <dev/pci/pcireg.h>
137 #include <dev/pci/pcivar.h>
139 #include <sys/tiio.h>
140 #include <pci/if_tireg.h>
141 #include <pci/ti_fw.h>
142 #include <pci/ti_fw2.h>
144 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
146 * We can only turn on header splitting if we're using extended receive
149 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS)
150 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive"
151 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */
153 struct ti_softc *tis[8];
162 * Various supported device vendors/types and their names.
165 static struct ti_type ti_devs[] = {
166 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
167 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
168 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
169 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
170 { TC_VENDORID, TC_DEVICEID_3C985,
171 "3Com 3c985-SX Gigabit Ethernet" },
172 { NG_VENDORID, NG_DEVICEID_GA620,
173 "Netgear GA620 1000baseSX Gigabit Ethernet" },
174 { NG_VENDORID, NG_DEVICEID_GA620T,
175 "Netgear GA620 1000baseT Gigabit Ethernet" },
176 { SGI_VENDORID, SGI_DEVICEID_TIGON,
177 "Silicon Graphics Gigabit Ethernet" },
178 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
179 "Farallon PN9000SX Gigabit Ethernet" },
184 static d_open_t ti_open;
185 static d_close_t ti_close;
186 static d_ioctl_t ti_ioctl2;
188 static struct cdevsw ti_cdevsw = {
189 .d_version = D_VERSION,
190 .d_flags = D_NEEDGIANT,
193 .d_ioctl = ti_ioctl2,
197 static int ti_probe(device_t);
198 static int ti_attach(device_t);
199 static int ti_detach(device_t);
200 static void ti_txeof(struct ti_softc *);
201 static void ti_rxeof(struct ti_softc *);
203 static void ti_stats_update(struct ti_softc *);
204 static int ti_encap(struct ti_softc *, struct mbuf *, u_int32_t *);
206 static void ti_intr(void *);
207 static void ti_start(struct ifnet *);
208 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
209 static void ti_init(void *);
210 static void ti_init2(struct ti_softc *);
211 static void ti_stop(struct ti_softc *);
212 static void ti_watchdog(struct ifnet *);
213 static void ti_shutdown(device_t);
214 static int ti_ifmedia_upd(struct ifnet *);
215 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
217 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int);
218 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *);
219 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
221 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
222 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
223 static void ti_setmulti(struct ti_softc *);
225 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t);
226 static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int);
227 static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t,
229 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
230 static void ti_loadfw(struct ti_softc *);
231 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
232 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
233 static void ti_handle_events(struct ti_softc *);
234 #ifdef TI_PRIVATE_JUMBOS
235 static int ti_alloc_jumbo_mem(struct ti_softc *);
236 static void *ti_jalloc(struct ti_softc *);
237 static void ti_jfree(void *, void *);
238 #endif /* TI_PRIVATE_JUMBOS */
239 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
240 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
241 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
242 static int ti_init_rx_ring_std(struct ti_softc *);
243 static void ti_free_rx_ring_std(struct ti_softc *);
244 static int ti_init_rx_ring_jumbo(struct ti_softc *);
245 static void ti_free_rx_ring_jumbo(struct ti_softc *);
246 static int ti_init_rx_ring_mini(struct ti_softc *);
247 static void ti_free_rx_ring_mini(struct ti_softc *);
248 static void ti_free_tx_ring(struct ti_softc *);
249 static int ti_init_tx_ring(struct ti_softc *);
251 static int ti_64bitslot_war(struct ti_softc *);
252 static int ti_chipinit(struct ti_softc *);
253 static int ti_gibinit(struct ti_softc *);
255 #ifdef TI_JUMBO_HDRSPLIT
256 static __inline void ti_hdr_split (struct mbuf *top, int hdr_len,
257 int pkt_len, int idx);
258 #endif /* TI_JUMBO_HDRSPLIT */
260 static device_method_t ti_methods[] = {
261 /* Device interface */
262 DEVMETHOD(device_probe, ti_probe),
263 DEVMETHOD(device_attach, ti_attach),
264 DEVMETHOD(device_detach, ti_detach),
265 DEVMETHOD(device_shutdown, ti_shutdown),
269 static driver_t ti_driver = {
272 sizeof(struct ti_softc)
275 static devclass_t ti_devclass;
277 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
278 MODULE_DEPEND(ti, pci, 1, 1, 1);
279 MODULE_DEPEND(ti, ether, 1, 1, 1);
282 * Send an instruction or address to the EEPROM, check for ACK.
284 static u_int32_t ti_eeprom_putbyte(sc, byte)
288 register int i, ack = 0;
291 * Make sure we're in TX mode.
293 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
296 * Feed in each bit and stobe the clock.
298 for (i = 0x80; i; i >>= 1) {
300 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
313 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
318 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
319 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
326 * Read a byte of data stored in the EEPROM at address 'addr.'
327 * We have to send two address bytes since the EEPROM can hold
328 * more than 256 bytes of data.
330 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
341 * Send write control code to EEPROM.
343 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
344 if_printf(sc->ti_ifp,
345 "failed to send write command, status: %x\n",
346 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
351 * Send first byte of address of byte we want to read.
353 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
354 if_printf(sc->ti_ifp, "failed to send address, status: %x\n",
355 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
359 * Send second byte address of byte we want to read.
361 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
362 if_printf(sc->ti_ifp, "failed to send address, status: %x\n",
363 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
370 * Send read control code to EEPROM.
372 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
373 if_printf(sc->ti_ifp,
374 "failed to send read command, status: %x\n",
375 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
380 * Start reading bits from EEPROM.
382 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
383 for (i = 0x80; i; i >>= 1) {
384 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
386 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
388 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
395 * No ACK generated for read, so just return byte.
404 * Read a sequence of bytes from the EEPROM.
407 ti_read_eeprom(sc, dest, off, cnt)
416 for (i = 0; i < cnt; i++) {
417 err = ti_eeprom_getbyte(sc, off + i, &byte);
423 return (err ? 1 : 0);
427 * NIC memory access function. Can be used to either clear a section
428 * of NIC local memory or (if buf is non-NULL) copy data into it.
431 ti_mem(sc, addr, len, buf)
436 int segptr, segsize, cnt;
437 caddr_t ti_winbase, ptr;
441 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
448 segsize = TI_WINLEN - (segptr % TI_WINLEN);
449 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
451 bzero((char *)ti_winbase + (segptr &
452 (TI_WINLEN - 1)), segsize);
454 bcopy((char *)ptr, (char *)ti_winbase +
455 (segptr & (TI_WINLEN - 1)), segsize);
464 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata)
466 u_int32_t tigon_addr, len;
468 int useraddr, readdata;
470 int segptr, segsize, cnt;
473 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN];
478 * At the moment, we don't handle non-aligned cases, we just bail.
479 * If this proves to be a problem, it will be fixed.
482 && (tigon_addr & 0x3)) {
483 if_printf(sc->ti_ifp, "ti_copy_mem: tigon address %#x isn't "
484 "word-aligned\n", tigon_addr);
485 if_printf(sc->ti_ifp, "ti_copy_mem: unaligned writes aren't "
490 segptr = tigon_addr & ~0x3;
491 segresid = tigon_addr - segptr;
494 * This is the non-aligned amount left over that we'll need to
499 /* Add in the left over amount at the front of the buffer */
504 * If resid + segresid is >= 4, add multiples of 4 to the count and
505 * decrease the residual by that much.
508 resid -= resid & ~0x3;
515 * Make sure we aren't interrupted while we're changing the window
521 * Save the old window base value.
523 origwin = CSR_READ_4(sc, TI_WINBASE);
526 bus_size_t ti_offset;
531 segsize = TI_WINLEN - (segptr % TI_WINLEN);
532 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
534 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
538 bus_space_read_region_4(sc->ti_btag,
539 sc->ti_bhandle, ti_offset,
540 (u_int32_t *)tmparray,
544 * Yeah, this is a little on the kludgy
545 * side, but at least this code is only
546 * used for debugging.
548 ti_bcopy_swap(tmparray, tmparray2, segsize,
552 copyout(&tmparray2[segresid], ptr,
556 copyout(tmparray2, ptr, segsize);
560 ti_bcopy_swap(tmparray, tmparray2,
561 segsize, TI_SWAP_NTOH);
562 bcopy(&tmparray2[segresid], ptr,
566 ti_bcopy_swap(tmparray, ptr, segsize,
572 copyin(ptr, tmparray2, segsize);
573 ti_bcopy_swap(tmparray2, tmparray, segsize,
576 ti_bcopy_swap(ptr, tmparray, segsize,
579 bus_space_write_region_4(sc->ti_btag,
580 sc->ti_bhandle, ti_offset,
581 (u_int32_t *)tmparray,
590 * Handle leftover, non-word-aligned bytes.
593 u_int32_t tmpval, tmpval2;
594 bus_size_t ti_offset;
597 * Set the segment pointer.
599 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
601 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
604 * First, grab whatever is in our source/destination.
605 * We'll obviously need this for reads, but also for
606 * writes, since we'll be doing read/modify/write.
608 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
609 ti_offset, &tmpval, 1);
612 * Next, translate this from little-endian to big-endian
613 * (at least on i386 boxes).
615 tmpval2 = ntohl(tmpval);
619 * If we're reading, just copy the leftover number
620 * of bytes from the host byte order buffer to
624 copyout(&tmpval2, ptr, resid);
626 bcopy(&tmpval2, ptr, resid);
629 * If we're writing, first copy the bytes to be
630 * written into the network byte order buffer,
631 * leaving the rest of the buffer with whatever was
632 * originally in there. Then, swap the bytes
633 * around into host order and write them out.
635 * XXX KDM the read side of this has been verified
636 * to work, but the write side of it has not been
637 * verified. So user beware.
640 copyin(ptr, &tmpval2, resid);
642 bcopy(ptr, &tmpval2, resid);
644 tmpval = htonl(tmpval2);
646 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
647 ti_offset, &tmpval, 1);
651 CSR_WRITE_4(sc, TI_WINBASE, origwin);
659 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu)
661 u_int32_t tigon_addr, len;
663 int useraddr, readdata;
668 u_int32_t tmpval, tmpval2;
672 * At the moment, we don't handle non-aligned cases, we just bail.
673 * If this proves to be a problem, it will be fixed.
675 if (tigon_addr & 0x3) {
676 if_printf(sc->ti_ifp, "ti_copy_scratch: tigon address %#x "
677 "isn't word-aligned\n", tigon_addr);
682 if_printf(sc->ti_ifp, "ti_copy_scratch: transfer length %d "
683 "isn't word-aligned\n", len);
694 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
697 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
699 tmpval = ntohl(tmpval2);
702 * Note: I've used this debugging interface
703 * extensively with Alteon's 12.3.15 firmware,
704 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
706 * When you compile the firmware without
707 * optimization, which is necessary sometimes in
708 * order to properly step through it, you sometimes
709 * read out a bogus value of 0xc0017c instead of
710 * whatever was supposed to be in that scratchpad
711 * location. That value is on the stack somewhere,
712 * but I've never been able to figure out what was
713 * causing the problem.
715 * The address seems to pop up in random places,
716 * often not in the same place on two subsequent
719 * In any case, the underlying data doesn't seem
720 * to be affected, just the value read out.
725 if (tmpval2 == 0xc0017c)
726 if_printf(sc->ti_ifp, "found 0xc0017c at %#x "
727 "(tmpval2)\n", segptr);
729 if (tmpval == 0xc0017c)
730 if_printf(sc->ti_ifp, "found 0xc0017c at %#x "
731 "(tmpval)\n", segptr);
734 copyout(&tmpval, ptr, 4);
736 bcopy(&tmpval, ptr, 4);
739 copyin(ptr, &tmpval2, 4);
741 bcopy(ptr, &tmpval2, 4);
743 tmpval = htonl(tmpval2);
745 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
759 ti_bcopy_swap(src, dst, len, swap_type)
763 ti_swap_type swap_type;
765 const u_int8_t *tmpsrc;
770 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n",
780 if (swap_type == TI_SWAP_NTOH)
781 *(u_int32_t *)tmpdst =
782 ntohl(*(const u_int32_t *)tmpsrc);
784 *(u_int32_t *)tmpdst =
785 htonl(*(const u_int32_t *)tmpsrc);
796 * Load firmware image into the NIC. Check that the firmware revision
797 * is acceptable and see if we want the firmware for the Tigon 1 or
804 switch (sc->ti_hwrev) {
806 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
807 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
808 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
809 if_printf(sc->ti_ifp, "firmware revision mismatch; "
810 "want %d.%d.%d, got %d.%d.%d\n",
811 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
812 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
813 tigonFwReleaseMinor, tigonFwReleaseFix);
816 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
817 (caddr_t)tigonFwText);
818 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
819 (caddr_t)tigonFwData);
820 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
821 (caddr_t)tigonFwRodata);
822 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
823 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
824 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
826 case TI_HWREV_TIGON_II:
827 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
828 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
829 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
830 if_printf(sc->ti_ifp, "firmware revision mismatch; "
831 "want %d.%d.%d, got %d.%d.%d\n",
832 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
833 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
834 tigon2FwReleaseMinor, tigon2FwReleaseFix);
837 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
838 (caddr_t)tigon2FwText);
839 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
840 (caddr_t)tigon2FwData);
841 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
842 (caddr_t)tigon2FwRodata);
843 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
844 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
845 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
848 if_printf(sc->ti_ifp,
849 "can't load firmware: unknown hardware rev\n");
855 * Send the NIC a command via the command ring.
860 struct ti_cmd_desc *cmd;
864 if (sc->ti_rdata->ti_cmd_ring == NULL)
867 index = sc->ti_cmd_saved_prodidx;
868 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
869 TI_INC(index, TI_CMD_RING_CNT);
870 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
871 sc->ti_cmd_saved_prodidx = index;
875 * Send the NIC an extended command. The 'len' parameter specifies the
876 * number of command slots to include after the initial command.
879 ti_cmd_ext(sc, cmd, arg, len)
881 struct ti_cmd_desc *cmd;
888 if (sc->ti_rdata->ti_cmd_ring == NULL)
891 index = sc->ti_cmd_saved_prodidx;
892 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
893 TI_INC(index, TI_CMD_RING_CNT);
894 for (i = 0; i < len; i++) {
895 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
896 *(u_int32_t *)(&arg[i * 4]));
897 TI_INC(index, TI_CMD_RING_CNT);
899 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
900 sc->ti_cmd_saved_prodidx = index;
904 * Handle events that have triggered interrupts.
910 struct ti_event_desc *e;
912 if (sc->ti_rdata->ti_event_ring == NULL)
915 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
916 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
917 switch (e->ti_event) {
918 case TI_EV_LINKSTAT_CHANGED:
919 sc->ti_linkstat = e->ti_code;
920 if (e->ti_code == TI_EV_CODE_LINK_UP)
921 if_printf(sc->ti_ifp, "10/100 link up\n");
922 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
923 if_printf(sc->ti_ifp, "gigabit link up\n");
924 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
925 if_printf(sc->ti_ifp, "link down\n");
928 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
929 if_printf(sc->ti_ifp, "invalid command\n");
930 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
931 if_printf(sc->ti_ifp, "unknown command\n");
932 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
933 if_printf(sc->ti_ifp, "bad config data\n");
935 case TI_EV_FIRMWARE_UP:
938 case TI_EV_STATS_UPDATED:
941 case TI_EV_RESET_JUMBO_RING:
942 case TI_EV_MCAST_UPDATED:
946 if_printf(sc->ti_ifp, "unknown event: %d\n",
950 /* Advance the consumer index. */
951 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
952 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
956 #ifdef TI_PRIVATE_JUMBOS
959 * Memory management for the jumbo receive ring is a pain in the
960 * butt. We need to allocate at least 9018 bytes of space per frame,
961 * _and_ it has to be contiguous (unless you use the extended
962 * jumbo descriptor format). Using malloc() all the time won't
963 * work: malloc() allocates memory in powers of two, which means we
964 * would end up wasting a considerable amount of space by allocating
965 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
966 * to do our own memory management.
968 * The driver needs to allocate a contiguous chunk of memory at boot
969 * time. We then chop this up ourselves into 9K pieces and use them
970 * as external mbuf storage.
972 * One issue here is how much memory to allocate. The jumbo ring has
973 * 256 slots in it, but at 9K per slot than can consume over 2MB of
974 * RAM. This is a bit much, especially considering we also need
975 * RAM for the standard ring and mini ring (on the Tigon 2). To
976 * save space, we only actually allocate enough memory for 64 slots
977 * by default, which works out to between 500 and 600K. This can
978 * be tuned by changing a #define in if_tireg.h.
982 ti_alloc_jumbo_mem(sc)
987 struct ti_jpool_entry *entry;
989 /* Grab a big chunk o' storage. */
990 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
991 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
993 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
994 if_printf(sc->ti_ifp, "no memory for jumbo buffers!\n");
998 SLIST_INIT(&sc->ti_jfree_listhead);
999 SLIST_INIT(&sc->ti_jinuse_listhead);
1002 * Now divide it up into 9K pieces and save the addresses
1005 ptr = sc->ti_cdata.ti_jumbo_buf;
1006 for (i = 0; i < TI_JSLOTS; i++) {
1007 sc->ti_cdata.ti_jslots[i] = ptr;
1009 entry = malloc(sizeof(struct ti_jpool_entry),
1010 M_DEVBUF, M_NOWAIT);
1011 if (entry == NULL) {
1012 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
1014 sc->ti_cdata.ti_jumbo_buf = NULL;
1015 if_printf(sc->ti_ifp, "no memory for jumbo "
1020 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1027 * Allocate a jumbo buffer.
1029 static void *ti_jalloc(sc)
1030 struct ti_softc *sc;
1032 struct ti_jpool_entry *entry;
1034 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
1036 if (entry == NULL) {
1037 if_printf(sc->ti_ifp, "no free jumbo buffers\n");
1041 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
1042 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
1043 return (sc->ti_cdata.ti_jslots[entry->slot]);
1047 * Release a jumbo buffer.
1054 struct ti_softc *sc;
1056 struct ti_jpool_entry *entry;
1058 /* Extract the softc struct pointer. */
1059 sc = (struct ti_softc *)args;
1062 panic("ti_jfree: didn't get softc pointer!");
1064 /* calculate the slot this buffer belongs to */
1065 i = ((vm_offset_t)buf
1066 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
1068 if ((i < 0) || (i >= TI_JSLOTS))
1069 panic("ti_jfree: asked to free buffer that we don't manage!");
1071 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
1073 panic("ti_jfree: buffer not in use!");
1075 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
1076 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
1079 #endif /* TI_PRIVATE_JUMBOS */
1082 * Intialize a standard receive ring descriptor.
1085 ti_newbuf_std(sc, i, m)
1086 struct ti_softc *sc;
1090 struct mbuf *m_new = NULL;
1091 struct ti_rx_desc *r;
1094 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1098 MCLGET(m_new, M_DONTWAIT);
1099 if (!(m_new->m_flags & M_EXT)) {
1103 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1106 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1107 m_new->m_data = m_new->m_ext.ext_buf;
1110 m_adj(m_new, ETHER_ALIGN);
1111 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
1112 r = &sc->ti_rdata->ti_rx_std_ring[i];
1113 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1114 r->ti_type = TI_BDTYPE_RECV_BD;
1116 if (sc->ti_ifp->if_hwassist)
1117 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1118 r->ti_len = m_new->m_len;
1125 * Intialize a mini receive ring descriptor. This only applies to
1129 ti_newbuf_mini(sc, i, m)
1130 struct ti_softc *sc;
1134 struct mbuf *m_new = NULL;
1135 struct ti_rx_desc *r;
1138 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1139 if (m_new == NULL) {
1142 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1145 m_new->m_data = m_new->m_pktdat;
1146 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
1149 m_adj(m_new, ETHER_ALIGN);
1150 r = &sc->ti_rdata->ti_rx_mini_ring[i];
1151 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
1152 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1153 r->ti_type = TI_BDTYPE_RECV_BD;
1154 r->ti_flags = TI_BDFLAG_MINI_RING;
1155 if (sc->ti_ifp->if_hwassist)
1156 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1157 r->ti_len = m_new->m_len;
1163 #ifdef TI_PRIVATE_JUMBOS
1166 * Initialize a jumbo receive ring descriptor. This allocates
1167 * a jumbo buffer from the pool managed internally by the driver.
1170 ti_newbuf_jumbo(sc, i, m)
1171 struct ti_softc *sc;
1175 struct mbuf *m_new = NULL;
1176 struct ti_rx_desc *r;
1179 caddr_t *buf = NULL;
1181 /* Allocate the mbuf. */
1182 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1183 if (m_new == NULL) {
1187 /* Allocate the jumbo buffer */
1188 buf = ti_jalloc(sc);
1191 if_printf(sc->ti_ifp, "jumbo allocation failed "
1192 "-- packet dropped!\n");
1196 /* Attach the buffer to the mbuf. */
1197 m_new->m_data = (void *) buf;
1198 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
1199 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
1200 (struct ti_softc *)sc, 0, EXT_NET_DRV);
1203 m_new->m_data = m_new->m_ext.ext_buf;
1204 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
1207 m_adj(m_new, ETHER_ALIGN);
1208 /* Set up the descriptor. */
1209 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
1210 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
1211 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
1212 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1213 r->ti_flags = TI_BDFLAG_JUMBO_RING;
1214 if (sc->ti_ifp->if_hwassist)
1215 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1216 r->ti_len = m_new->m_len;
1223 #include <vm/vm_page.h>
1225 #if (PAGE_SIZE == 4096)
1231 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1232 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1233 #define NFS_HDR_LEN (UDP_HDR_LEN)
1234 static int HDR_LEN = TCP_HDR_LEN;
1238 * Initialize a jumbo receive ring descriptor. This allocates
1239 * a jumbo buffer from the pool managed internally by the driver.
1242 ti_newbuf_jumbo(sc, idx, m_old)
1243 struct ti_softc *sc;
1247 struct mbuf *cur, *m_new = NULL;
1248 struct mbuf *m[3] = {NULL, NULL, NULL};
1249 struct ti_rx_desc_ext *r;
1252 /* 1 extra buf to make nobufs easy*/
1253 struct sf_buf *sf[3] = {NULL, NULL, NULL};
1256 if (m_old != NULL) {
1258 cur = m_old->m_next;
1259 for (i = 0; i <= NPAYLOAD; i++){
1264 /* Allocate the mbufs. */
1265 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1266 if (m_new == NULL) {
1267 if_printf(sc->ti_ifp, "mbuf allocation failed "
1268 "-- packet dropped!\n");
1271 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA);
1272 if (m[NPAYLOAD] == NULL) {
1273 if_printf(sc->ti_ifp, "cluster mbuf allocation failed "
1274 "-- packet dropped!\n");
1277 MCLGET(m[NPAYLOAD], M_DONTWAIT);
1278 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1279 if_printf(sc->ti_ifp, "mbuf allocation failed "
1280 "-- packet dropped!\n");
1283 m[NPAYLOAD]->m_len = MCLBYTES;
1285 for (i = 0; i < NPAYLOAD; i++){
1286 MGET(m[i], M_DONTWAIT, MT_DATA);
1288 if_printf(sc->ti_ifp, "mbuf allocation failed "
1289 "-- packet dropped!\n");
1292 frame = vm_page_alloc(NULL, color++,
1293 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1295 if (frame == NULL) {
1296 if_printf(sc->ti_ifp, "buffer allocation "
1297 "failed -- packet dropped!\n");
1298 printf(" index %d page %d\n", idx, i);
1301 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1302 if (sf[i] == NULL) {
1303 vm_page_lock_queues();
1304 vm_page_unwire(frame, 0);
1305 vm_page_free(frame);
1306 vm_page_unlock_queues();
1307 if_printf(sc->ti_ifp, "buffer allocation "
1308 "failed -- packet dropped!\n");
1309 printf(" index %d page %d\n", idx, i);
1313 for (i = 0; i < NPAYLOAD; i++){
1314 /* Attach the buffer to the mbuf. */
1315 m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1316 m[i]->m_len = PAGE_SIZE;
1317 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1318 sf_buf_mext, sf[i], 0, EXT_DISPOSABLE);
1319 m[i]->m_next = m[i+1];
1321 /* link the buffers to the header */
1322 m_new->m_next = m[0];
1323 m_new->m_data += ETHER_ALIGN;
1324 if (sc->ti_hdrsplit)
1325 m_new->m_len = MHLEN - ETHER_ALIGN;
1327 m_new->m_len = HDR_LEN;
1328 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1331 /* Set up the descriptor. */
1332 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx];
1333 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1334 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t));
1335 r->ti_len0 = m_new->m_len;
1337 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t));
1338 r->ti_len1 = PAGE_SIZE;
1340 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t));
1341 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1343 if (PAGE_SIZE == 4096) {
1344 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t));
1345 r->ti_len3 = MCLBYTES;
1349 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1351 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1353 if (sc->ti_ifp->if_hwassist)
1354 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1364 * This can only be called before the mbufs are strung together.
1365 * If the mbufs are strung together, m_freem() will free the chain,
1366 * so that the later mbufs will be freed multiple times.
1371 for (i = 0; i < 3; i++) {
1375 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1384 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1385 * that's 1MB or memory, which is a lot. For now, we fill only the first
1386 * 256 ring entries and hope that our CPU is fast enough to keep up with
1390 ti_init_rx_ring_std(sc)
1391 struct ti_softc *sc;
1394 struct ti_cmd_desc cmd;
1396 for (i = 0; i < TI_SSLOTS; i++) {
1397 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
1401 TI_UPDATE_STDPROD(sc, i - 1);
1408 ti_free_rx_ring_std(sc)
1409 struct ti_softc *sc;
1413 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1414 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1415 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1416 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1418 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
1419 sizeof(struct ti_rx_desc));
1424 ti_init_rx_ring_jumbo(sc)
1425 struct ti_softc *sc;
1428 struct ti_cmd_desc cmd;
1430 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1431 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1435 TI_UPDATE_JUMBOPROD(sc, i - 1);
1436 sc->ti_jumbo = i - 1;
1442 ti_free_rx_ring_jumbo(sc)
1443 struct ti_softc *sc;
1447 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1448 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1449 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1450 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1452 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
1453 sizeof(struct ti_rx_desc));
1458 ti_init_rx_ring_mini(sc)
1459 struct ti_softc *sc;
1463 for (i = 0; i < TI_MSLOTS; i++) {
1464 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
1468 TI_UPDATE_MINIPROD(sc, i - 1);
1469 sc->ti_mini = i - 1;
1475 ti_free_rx_ring_mini(sc)
1476 struct ti_softc *sc;
1480 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1481 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1482 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1483 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1485 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1486 sizeof(struct ti_rx_desc));
1492 struct ti_softc *sc;
1496 if (sc->ti_rdata->ti_tx_ring == NULL)
1499 for (i = 0; i < TI_TX_RING_CNT; i++) {
1500 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1501 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1502 sc->ti_cdata.ti_tx_chain[i] = NULL;
1504 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1505 sizeof(struct ti_tx_desc));
1511 struct ti_softc *sc;
1514 sc->ti_tx_saved_considx = 0;
1515 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1520 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1521 * but we have to support the old way too so that Tigon 1 cards will
1525 ti_add_mcast(sc, addr)
1526 struct ti_softc *sc;
1527 struct ether_addr *addr;
1529 struct ti_cmd_desc cmd;
1531 u_int32_t ext[2] = {0, 0};
1533 m = (u_int16_t *)&addr->octet[0];
1535 switch (sc->ti_hwrev) {
1536 case TI_HWREV_TIGON:
1537 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1538 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1539 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1541 case TI_HWREV_TIGON_II:
1542 ext[0] = htons(m[0]);
1543 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1544 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1547 if_printf(sc->ti_ifp, "unknown hwrev\n");
1553 ti_del_mcast(sc, addr)
1554 struct ti_softc *sc;
1555 struct ether_addr *addr;
1557 struct ti_cmd_desc cmd;
1559 u_int32_t ext[2] = {0, 0};
1561 m = (u_int16_t *)&addr->octet[0];
1563 switch (sc->ti_hwrev) {
1564 case TI_HWREV_TIGON:
1565 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1566 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1567 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1569 case TI_HWREV_TIGON_II:
1570 ext[0] = htons(m[0]);
1571 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1572 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1575 if_printf(sc->ti_ifp, "unknown hwrev\n");
1581 * Configure the Tigon's multicast address filter.
1583 * The actual multicast table management is a bit of a pain, thanks to
1584 * slight brain damage on the part of both Alteon and us. With our
1585 * multicast code, we are only alerted when the multicast address table
1586 * changes and at that point we only have the current list of addresses:
1587 * we only know the current state, not the previous state, so we don't
1588 * actually know what addresses were removed or added. The firmware has
1589 * state, but we can't get our grubby mits on it, and there is no 'delete
1590 * all multicast addresses' command. Hence, we have to maintain our own
1591 * state so we know what addresses have been programmed into the NIC at
1596 struct ti_softc *sc;
1599 struct ifmultiaddr *ifma;
1600 struct ti_cmd_desc cmd;
1601 struct ti_mc_entry *mc;
1606 if (ifp->if_flags & IFF_ALLMULTI) {
1607 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1610 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1613 /* Disable interrupts. */
1614 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1615 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1617 /* First, zot all the existing filters. */
1618 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1619 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1620 ti_del_mcast(sc, &mc->mc_addr);
1621 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1625 /* Now program new ones. */
1627 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1628 if (ifma->ifma_addr->sa_family != AF_LINK)
1630 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1632 if_printf(ifp, "no memory for mcast filter entry\n");
1635 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1636 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1637 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1638 ti_add_mcast(sc, &mc->mc_addr);
1640 IF_ADDR_UNLOCK(ifp);
1642 /* Re-enable interrupts. */
1643 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1647 * Check to see if the BIOS has configured us for a 64 bit slot when
1648 * we aren't actually in one. If we detect this condition, we can work
1649 * around it on the Tigon 2 by setting a bit in the PCI state register,
1650 * but for the Tigon 1 we must give up and abort the interface attach.
1652 static int ti_64bitslot_war(sc)
1653 struct ti_softc *sc;
1655 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1656 CSR_WRITE_4(sc, 0x600, 0);
1657 CSR_WRITE_4(sc, 0x604, 0);
1658 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1659 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1660 if (sc->ti_hwrev == TI_HWREV_TIGON)
1663 TI_SETBIT(sc, TI_PCI_STATE,
1664 TI_PCISTATE_32BIT_BUS);
1674 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1675 * self-test results.
1679 struct ti_softc *sc;
1681 u_int32_t cacheline;
1682 u_int32_t pci_writemax = 0;
1685 /* Initialize link to down state. */
1686 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1688 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM)
1689 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
1691 sc->ti_ifp->if_hwassist = 0;
1693 /* Set endianness before we access any non-PCI registers. */
1694 #if BYTE_ORDER == BIG_ENDIAN
1695 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1696 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1698 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1699 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1702 /* Check the ROM failed bit to see if self-tests passed. */
1703 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1704 if_printf(sc->ti_ifp, "board self-diagnostics failed!\n");
1709 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1711 /* Figure out the hardware revision. */
1712 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1713 case TI_REV_TIGON_I:
1714 sc->ti_hwrev = TI_HWREV_TIGON;
1716 case TI_REV_TIGON_II:
1717 sc->ti_hwrev = TI_HWREV_TIGON_II;
1720 if_printf(sc->ti_ifp, "unsupported chip revision\n");
1724 /* Do special setup for Tigon 2. */
1725 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1726 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1727 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1728 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1732 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
1733 * can't do header splitting.
1735 #ifdef TI_JUMBO_HDRSPLIT
1736 if (sc->ti_hwrev != TI_HWREV_TIGON)
1737 sc->ti_hdrsplit = 1;
1739 if_printf(sc->ti_ifp,
1740 "can't do header splitting on a Tigon I board\n");
1741 #endif /* TI_JUMBO_HDRSPLIT */
1743 /* Set up the PCI state register. */
1744 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1745 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1746 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1749 /* Clear the read/write max DMA parameters. */
1750 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1751 TI_PCISTATE_READ_MAXDMA));
1753 /* Get cache line size. */
1754 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1757 * If the system has set enabled the PCI memory write
1758 * and invalidate command in the command register, set
1759 * the write max parameter accordingly. This is necessary
1760 * to use MWI with the Tigon 2.
1762 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1763 switch (cacheline) {
1772 /* Disable PCI memory write and invalidate. */
1774 if_printf(sc->ti_ifp, "cache line size %d not "
1775 "supported; disabling PCI MWI\n",
1777 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1778 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1783 #ifdef __brokenalpha__
1785 * From the Alteon sample driver:
1786 * Must insure that we do not cross an 8K (bytes) boundary
1787 * for DMA reads. Our highest limit is 1K bytes. This is a
1788 * restriction on some ALPHA platforms with early revision
1789 * 21174 PCI chipsets, such as the AlphaPC 164lx
1791 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1793 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1796 /* This sets the min dma param all the way up (0xff). */
1797 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1799 if (sc->ti_hdrsplit)
1800 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
1804 /* Configure DMA variables. */
1805 #if BYTE_ORDER == BIG_ENDIAN
1806 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1807 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1808 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1809 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
1810 #else /* BYTE_ORDER */
1811 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1812 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1813 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
1814 #endif /* BYTE_ORDER */
1817 * Only allow 1 DMA channel to be active at a time.
1818 * I don't think this is a good idea, but without it
1819 * the firmware racks up lots of nicDmaReadRingFull
1820 * errors. This is not compatible with hardware checksums.
1822 if (sc->ti_ifp->if_hwassist == 0)
1823 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1825 /* Recommended settings from Tigon manual. */
1826 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1827 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1829 if (ti_64bitslot_war(sc)) {
1830 if_printf(sc->ti_ifp, "bios thinks we're in a 64 bit slot, "
1838 #define TI_RD_OFF(x) offsetof(struct ti_ring_data, x)
1841 * Initialize the general information block and firmware, and
1842 * start the CPU(s) running.
1846 struct ti_softc *sc;
1854 rdphys = sc->ti_rdata_phys;
1856 /* Disable interrupts for now. */
1857 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1860 * Tell the chip where to find the general information block.
1861 * While this struct could go into >4GB memory, we allocate it in a
1862 * single slab with the other descriptors, and those don't seem to
1863 * support being located in a 64-bit region.
1865 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1866 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info));
1868 /* Load the firmware into SRAM. */
1871 /* Set up the contents of the general info and ring control blocks. */
1873 /* Set up the event ring and producer pointer. */
1874 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1876 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring);
1878 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1879 rdphys + TI_RD_OFF(ti_ev_prodidx_r);
1880 sc->ti_ev_prodidx.ti_idx = 0;
1881 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1882 sc->ti_ev_saved_considx = 0;
1884 /* Set up the command ring and producer mailbox. */
1885 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1887 sc->ti_rdata->ti_cmd_ring =
1888 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1889 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1891 rcb->ti_max_len = 0;
1892 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1893 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1895 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1896 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1897 sc->ti_cmd_saved_prodidx = 0;
1900 * Assign the address of the stats refresh buffer.
1901 * We re-use the current stats buffer for this to
1904 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1905 rdphys + TI_RD_OFF(ti_info.ti_stats);
1907 /* Set up the standard receive ring. */
1908 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1909 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring);
1910 rcb->ti_max_len = TI_FRAMELEN;
1912 if (sc->ti_ifp->if_hwassist)
1913 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1914 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1915 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1917 /* Set up the jumbo receive ring. */
1918 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1919 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring);
1921 #ifdef TI_PRIVATE_JUMBOS
1922 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1925 rcb->ti_max_len = PAGE_SIZE;
1926 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
1928 if (sc->ti_ifp->if_hwassist)
1929 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1930 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1931 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1934 * Set up the mini ring. Only activated on the
1935 * Tigon 2 but the slot in the config block is
1936 * still there on the Tigon 1.
1938 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1939 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring);
1940 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1941 if (sc->ti_hwrev == TI_HWREV_TIGON)
1942 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1945 if (sc->ti_ifp->if_hwassist)
1946 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1947 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1948 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1951 * Set up the receive return ring.
1953 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1954 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring);
1956 rcb->ti_max_len = TI_RETURN_RING_CNT;
1957 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1958 rdphys + TI_RD_OFF(ti_return_prodidx_r);
1961 * Set up the tx ring. Note: for the Tigon 2, we have the option
1962 * of putting the transmit ring in the host's address space and
1963 * letting the chip DMA it instead of leaving the ring in the NIC's
1964 * memory and accessing it through the shared memory region. We
1965 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1966 * so we have to revert to the shared memory scheme if we detect
1969 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1970 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1971 sc->ti_rdata->ti_tx_ring_nic =
1972 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1974 bzero((char *)sc->ti_rdata->ti_tx_ring,
1975 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1976 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1977 if (sc->ti_hwrev == TI_HWREV_TIGON)
1980 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1981 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1982 if (sc->ti_ifp->if_hwassist)
1983 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1984 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1985 rcb->ti_max_len = TI_TX_RING_CNT;
1986 if (sc->ti_hwrev == TI_HWREV_TIGON)
1987 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1989 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring);
1990 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1991 rdphys + TI_RD_OFF(ti_tx_considx_r);
1993 /* Set up tuneables */
1995 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1996 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1997 (sc->ti_rx_coal_ticks / 10));
2000 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2001 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2002 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2003 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2004 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2005 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2007 /* Turn interrupts on. */
2008 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2009 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2012 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2018 ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2020 struct ti_softc *sc;
2023 if (error || nseg != 1)
2027 * All of the Tigon data structures need to live at <4GB. This
2028 * cast is fine since busdma was told about this constraint.
2030 sc->ti_rdata_phys = (uint32_t)segs[0].ds_addr;
2035 * Probe for a Tigon chip. Check the PCI vendor and device IDs
2036 * against our list and return its name if we find a match.
2046 while (t->ti_name != NULL) {
2047 if ((pci_get_vendor(dev) == t->ti_vid) &&
2048 (pci_get_device(dev) == t->ti_did)) {
2049 device_set_desc(dev, t->ti_name);
2050 return (BUS_PROBE_DEFAULT);
2063 struct ti_softc *sc;
2067 sc = device_get_softc(dev);
2068 sc->ti_unit = device_get_unit(dev);
2070 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2071 MTX_DEF | MTX_RECURSE);
2072 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2073 ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2075 device_printf(dev, "can not if_alloc()\n");
2079 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM |
2080 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2081 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2084 * Map control/status registers.
2086 pci_enable_busmaster(dev);
2089 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2090 RF_ACTIVE|PCI_RF_DENSE);
2092 if (sc->ti_res == NULL) {
2093 device_printf(dev, "couldn't map memory\n");
2098 sc->ti_btag = rman_get_bustag(sc->ti_res);
2099 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2100 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
2102 /* Allocate interrupt */
2105 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2106 RF_SHAREABLE | RF_ACTIVE);
2108 if (sc->ti_irq == NULL) {
2109 device_printf(dev, "couldn't map interrupt\n");
2114 if (ti_chipinit(sc)) {
2115 device_printf(dev, "chip initialization failed\n");
2120 /* Zero out the NIC's on-board SRAM. */
2121 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2123 /* Init again -- zeroing memory may have clobbered some registers. */
2124 if (ti_chipinit(sc)) {
2125 device_printf(dev, "chip initialization failed\n");
2131 * Get station address from the EEPROM. Note: the manual states
2132 * that the MAC address is at offset 0x8c, however the data is
2133 * stored as two longwords (since that's how it's loaded into
2134 * the NIC). This means the MAC address is actually preceded
2135 * by two zero bytes. We need to skip over those.
2137 if (ti_read_eeprom(sc, eaddr,
2138 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2139 device_printf(dev, "failed to read station address\n");
2144 /* Allocate the general information block and ring buffers. */
2145 if (bus_dma_tag_create(NULL, /* parent */
2146 1, 0, /* algnmnt, boundary */
2147 BUS_SPACE_MAXADDR, /* lowaddr */
2148 BUS_SPACE_MAXADDR, /* highaddr */
2149 NULL, NULL, /* filter, filterarg */
2150 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2152 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2154 NULL, NULL, /* lockfunc, lockarg */
2155 &sc->ti_parent_dmat) != 0) {
2156 device_printf(dev, "Failed to allocate parent dmat\n");
2161 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */
2162 PAGE_SIZE, 0, /* algnmnt, boundary */
2163 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2164 BUS_SPACE_MAXADDR, /* highaddr */
2165 NULL, NULL, /* filter, filterarg */
2166 sizeof(struct ti_ring_data), /* maxsize */
2168 sizeof(struct ti_ring_data), /* maxsegsize */
2170 NULL, NULL, /* lockfunc, lockarg */
2171 &sc->ti_rdata_dmat) != 0) {
2172 device_printf(dev, "Failed to allocate rdata dmat\n");
2177 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata,
2178 BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) {
2179 device_printf(dev, "Failed to allocate rdata memory\n");
2184 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap,
2185 sc->ti_rdata, sizeof(struct ti_ring_data),
2186 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) {
2187 device_printf(dev, "Failed to load rdata segments\n");
2192 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
2194 /* Try to allocate memory for jumbo buffers. */
2195 #ifdef TI_PRIVATE_JUMBOS
2196 if (ti_alloc_jumbo_mem(sc)) {
2197 device_printf(dev, "jumbo buffer allocation failed\n");
2204 * We really need a better way to tell a 1000baseTX card
2205 * from a 1000baseSX one, since in theory there could be
2206 * OEMed 1000baseTX cards from lame vendors who aren't
2207 * clever enough to change the PCI ID. For the moment
2208 * though, the AceNIC is the only copper card available.
2210 if (pci_get_vendor(dev) == ALT_VENDORID &&
2211 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2213 /* Ok, it's not the only copper card available. */
2214 if (pci_get_vendor(dev) == NG_VENDORID &&
2215 pci_get_device(dev) == NG_DEVICEID_GA620T)
2218 /* Set default tuneable values. */
2219 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
2221 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
2223 sc->ti_rx_coal_ticks = 170;
2224 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
2225 sc->ti_rx_max_coal_bds = 64;
2227 sc->ti_tx_max_coal_bds = 128;
2229 sc->ti_tx_max_coal_bds = 32;
2230 sc->ti_tx_buf_ratio = 21;
2232 /* Set up ifnet structure */
2234 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2235 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
2237 tis[sc->ti_unit] = sc;
2238 ifp->if_ioctl = ti_ioctl;
2239 ifp->if_start = ti_start;
2240 ifp->if_watchdog = ti_watchdog;
2241 ifp->if_init = ti_init;
2242 ifp->if_mtu = ETHERMTU;
2243 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
2245 /* Set up ifmedia support. */
2246 if (sc->ti_copper) {
2248 * Copper cards allow manual 10/100 mode selection,
2249 * but not manual 1000baseTX mode selection. Why?
2250 * Becuase currently there's no way to specify the
2251 * master/slave setting through the firmware interface,
2252 * so Alteon decided to just bag it and handle it
2253 * via autonegotiation.
2255 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2256 ifmedia_add(&sc->ifmedia,
2257 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2258 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2259 ifmedia_add(&sc->ifmedia,
2260 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2261 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2262 ifmedia_add(&sc->ifmedia,
2263 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2265 /* Fiber cards don't support 10/100 modes. */
2266 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2267 ifmedia_add(&sc->ifmedia,
2268 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2270 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2271 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2274 * We're assuming here that card initialization is a sequential
2275 * thing. If it isn't, multiple cards probing at the same time
2276 * could stomp on the list of softcs here.
2279 /* Register the device */
2280 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR,
2281 0600, "ti%d", sc->ti_unit);
2282 sc->dev->si_drv1 = sc;
2285 * Call MI attach routine.
2287 ether_ifattach(ifp, eaddr);
2289 /* Hook interrupt last to avoid having to lock softc */
2290 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
2291 ti_intr, sc, &sc->ti_intrhand);
2294 device_printf(dev, "couldn't set up irq\n");
2295 ether_ifdetach(ifp);
2307 * Shutdown hardware and free up resources. This can be called any
2308 * time after the mutex has been initialized. It is called in both
2309 * the error case in attach and the normal detach case so it needs
2310 * to be careful about only freeing resources that have actually been
2317 struct ti_softc *sc;
2320 sc = device_get_softc(dev);
2322 destroy_dev(sc->dev);
2323 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2327 /* These should only be active if attach succeeded */
2328 if (device_is_attached(dev)) {
2330 ether_ifdetach(ifp);
2331 bus_generic_detach(dev);
2333 ifmedia_removeall(&sc->ifmedia);
2336 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata,
2337 sc->ti_rdata_dmamap);
2338 if (sc->ti_rdata_dmat)
2339 bus_dma_tag_destroy(sc->ti_rdata_dmat);
2340 if (sc->ti_parent_dmat)
2341 bus_dma_tag_destroy(sc->ti_parent_dmat);
2342 if (sc->ti_intrhand)
2343 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2345 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2347 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM,
2353 #ifdef TI_PRIVATE_JUMBOS
2354 if (sc->ti_cdata.ti_jumbo_buf)
2355 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
2358 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
2361 mtx_destroy(&sc->ti_mtx);
2366 #ifdef TI_JUMBO_HDRSPLIT
2368 * If hdr_len is 0, that means that header splitting wasn't done on
2369 * this packet for some reason. The two most likely reasons are that
2370 * the protocol isn't a supported protocol for splitting, or this
2371 * packet had a fragment offset that wasn't 0.
2373 * The header length, if it is non-zero, will always be the length of
2374 * the headers on the packet, but that length could be longer than the
2375 * first mbuf. So we take the minimum of the two as the actual
2378 static __inline void
2379 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2382 int lengths[4] = {0, 0, 0, 0};
2383 struct mbuf *m, *mp;
2386 top->m_len = min(hdr_len, top->m_len);
2387 pkt_len -= top->m_len;
2388 lengths[i++] = top->m_len;
2391 for (m = top->m_next; m && pkt_len; m = m->m_next) {
2392 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2393 pkt_len -= m->m_len;
2394 lengths[i++] = m->m_len;
2400 printf("got split packet: ");
2402 printf("got non-split packet: ");
2404 printf("%d,%d,%d,%d = %d\n", lengths[0],
2405 lengths[1], lengths[2], lengths[3],
2406 lengths[0] + lengths[1] + lengths[2] +
2411 panic("header splitting didn't");
2418 if (mp->m_next != NULL)
2419 panic("ti_hdr_split: last mbuf in chain should be null");
2421 #endif /* TI_JUMBO_HDRSPLIT */
2424 * Frame reception handling. This is called if there's a frame
2425 * on the receive return list.
2427 * Note: we have to be able to handle three possibilities here:
2428 * 1) the frame is from the mini receive ring (can only happen)
2429 * on Tigon 2 boards)
2430 * 2) the frame is from the jumbo recieve ring
2431 * 3) the frame is from the standard receive ring
2436 struct ti_softc *sc;
2439 struct ti_cmd_desc cmd;
2445 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2446 struct ti_rx_desc *cur_rx;
2448 struct mbuf *m = NULL;
2449 u_int16_t vlan_tag = 0;
2453 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
2454 rxidx = cur_rx->ti_idx;
2455 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2457 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2459 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
2462 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2464 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2465 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2466 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2467 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2469 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2472 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2474 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2477 #ifdef TI_PRIVATE_JUMBOS
2478 m->m_len = cur_rx->ti_len;
2479 #else /* TI_PRIVATE_JUMBOS */
2480 #ifdef TI_JUMBO_HDRSPLIT
2481 if (sc->ti_hdrsplit)
2482 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2483 cur_rx->ti_len, rxidx);
2485 #endif /* TI_JUMBO_HDRSPLIT */
2486 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len);
2487 #endif /* TI_PRIVATE_JUMBOS */
2488 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2489 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2490 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2491 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
2492 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2494 ti_newbuf_mini(sc, sc->ti_mini, m);
2497 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
2499 ti_newbuf_mini(sc, sc->ti_mini, m);
2502 m->m_len = cur_rx->ti_len;
2504 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2505 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2506 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
2507 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2509 ti_newbuf_std(sc, sc->ti_std, m);
2512 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
2514 ti_newbuf_std(sc, sc->ti_std, m);
2517 m->m_len = cur_rx->ti_len;
2520 m->m_pkthdr.len = cur_rx->ti_len;
2522 m->m_pkthdr.rcvif = ifp;
2524 if (ifp->if_hwassist) {
2525 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
2527 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2528 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2529 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
2533 * If we received a packet with a vlan tag,
2534 * tag it before passing the packet upward.
2537 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue);
2539 (*ifp->if_input)(ifp, m);
2543 /* Only necessary on the Tigon 1. */
2544 if (sc->ti_hwrev == TI_HWREV_TIGON)
2545 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2546 sc->ti_rx_saved_considx);
2548 TI_UPDATE_STDPROD(sc, sc->ti_std);
2549 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2550 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2555 struct ti_softc *sc;
2557 struct ti_tx_desc *cur_tx = NULL;
2563 * Go through our tx ring and free mbufs for those
2564 * frames that have been sent.
2566 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
2569 idx = sc->ti_tx_saved_considx;
2570 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2572 CSR_WRITE_4(sc, TI_WINBASE,
2573 TI_TX_RING_BASE + 6144);
2575 CSR_WRITE_4(sc, TI_WINBASE,
2576 TI_TX_RING_BASE + 4096);
2578 CSR_WRITE_4(sc, TI_WINBASE,
2579 TI_TX_RING_BASE + 2048);
2581 CSR_WRITE_4(sc, TI_WINBASE,
2583 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
2585 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2586 if (cur_tx->ti_flags & TI_BDFLAG_END)
2588 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
2589 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
2590 sc->ti_cdata.ti_tx_chain[idx] = NULL;
2593 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
2598 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2605 struct ti_softc *sc;
2613 /* Avoid this for now -- checking this register is expensive. */
2614 /* Make sure this is really our interrupt. */
2615 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2621 /* Ack interrupt and stop others from occuring. */
2622 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2624 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2625 /* Check RX return ring producer/consumer */
2628 /* Check TX ring producer/consumer */
2632 ti_handle_events(sc);
2634 /* Re-enable interrupts. */
2635 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2637 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2638 ifp->if_snd.ifq_head != NULL)
2646 struct ti_softc *sc;
2652 ifp->if_collisions +=
2653 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2654 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2655 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2656 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2661 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2662 * pointers to descriptors.
2665 ti_encap(sc, m_head, txidx)
2666 struct ti_softc *sc;
2667 struct mbuf *m_head;
2670 struct ti_tx_desc *f = NULL;
2672 u_int32_t frag, cur, cnt = 0;
2673 u_int16_t csum_flags = 0;
2677 cur = frag = *txidx;
2679 if (m_head->m_pkthdr.csum_flags) {
2680 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2681 csum_flags |= TI_BDFLAG_IP_CKSUM;
2682 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2683 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2684 if (m_head->m_flags & M_LASTFRAG)
2685 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2686 else if (m_head->m_flags & M_FRAG)
2687 csum_flags |= TI_BDFLAG_IP_FRAG;
2690 mtag = VLAN_OUTPUT_TAG(sc->ti_ifp, m);
2693 * Start packing the mbufs in this chain into
2694 * the fragment pointers. Stop when we run out
2695 * of fragments or hit the end of the mbuf chain.
2697 for (m = m_head; m != NULL; m = m->m_next) {
2698 if (m->m_len != 0) {
2699 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2701 CSR_WRITE_4(sc, TI_WINBASE,
2702 TI_TX_RING_BASE + 6144);
2703 else if (frag > 255)
2704 CSR_WRITE_4(sc, TI_WINBASE,
2705 TI_TX_RING_BASE + 4096);
2706 else if (frag > 127)
2707 CSR_WRITE_4(sc, TI_WINBASE,
2708 TI_TX_RING_BASE + 2048);
2710 CSR_WRITE_4(sc, TI_WINBASE,
2712 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2714 f = &sc->ti_rdata->ti_tx_ring[frag];
2715 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2717 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2718 f->ti_len = m->m_len;
2719 f->ti_flags = csum_flags;
2722 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2723 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff;
2729 * Sanity check: avoid coming within 16 descriptors
2730 * of the end of the ring.
2732 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2735 TI_INC(frag, TI_TX_RING_CNT);
2743 if (frag == sc->ti_tx_saved_considx)
2746 if (sc->ti_hwrev == TI_HWREV_TIGON)
2747 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2750 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2751 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2752 sc->ti_txcnt += cnt;
2760 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2761 * to the mbuf data regions directly in the transmit descriptors.
2767 struct ti_softc *sc;
2768 struct mbuf *m_head = NULL;
2769 u_int32_t prodidx = 0;
2774 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2776 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2777 IF_DEQUEUE(&ifp->if_snd, m_head);
2783 * safety overkill. If this is a fragmented packet chain
2784 * with delayed TCP/UDP checksums, then only encapsulate
2785 * it if we have enough descriptors to handle the entire
2787 * (paranoia -- may not actually be needed)
2789 if (m_head->m_flags & M_FIRSTFRAG &&
2790 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2791 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2792 m_head->m_pkthdr.csum_data + 16) {
2793 IF_PREPEND(&ifp->if_snd, m_head);
2794 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2800 * Pack the data into the transmit ring. If we
2801 * don't have room, set the OACTIVE flag and wait
2802 * for the NIC to drain the ring.
2804 if (ti_encap(sc, m_head, &prodidx)) {
2805 IF_PREPEND(&ifp->if_snd, m_head);
2806 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2811 * If there's a BPF listener, bounce a copy of this frame
2814 BPF_MTAP(ifp, m_head);
2818 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2821 * Set a timeout in case the chip goes out to lunch.
2831 struct ti_softc *sc = xsc;
2833 /* Cancel pending I/O and flush buffers. */
2837 /* Init the gen info block, ring control blocks and firmware. */
2838 if (ti_gibinit(sc)) {
2839 if_printf(sc->ti_ifp, "initialization failure\n");
2847 static void ti_init2(sc)
2848 struct ti_softc *sc;
2850 struct ti_cmd_desc cmd;
2853 struct ifmedia *ifm;
2858 /* Specify MTU and interface index. */
2859 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit);
2860 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2861 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
2862 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2864 /* Load our MAC address. */
2865 m = (u_int16_t *)IF_LLADDR(sc->ti_ifp);
2866 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2867 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2868 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2870 /* Enable or disable promiscuous mode as needed. */
2871 if (ifp->if_flags & IFF_PROMISC) {
2872 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2874 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2877 /* Program multicast filter. */
2881 * If this is a Tigon 1, we should tell the
2882 * firmware to use software packet filtering.
2884 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2885 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2889 ti_init_rx_ring_std(sc);
2891 /* Init jumbo RX ring. */
2892 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2893 ti_init_rx_ring_jumbo(sc);
2896 * If this is a Tigon 2, we can also configure the
2899 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2900 ti_init_rx_ring_mini(sc);
2902 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2903 sc->ti_rx_saved_considx = 0;
2906 ti_init_tx_ring(sc);
2908 /* Tell firmware we're alive. */
2909 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2911 /* Enable host interrupts. */
2912 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2914 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2915 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2918 * Make sure to set media properly. We have to do this
2919 * here since we have to issue commands in order to set
2920 * the link negotiation and we can't issue commands until
2921 * the firmware is running.
2924 tmp = ifm->ifm_media;
2925 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2926 ti_ifmedia_upd(ifp);
2927 ifm->ifm_media = tmp;
2931 * Set media options.
2937 struct ti_softc *sc;
2938 struct ifmedia *ifm;
2939 struct ti_cmd_desc cmd;
2945 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2950 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2953 * Transmit flow control doesn't work on the Tigon 1.
2955 flowctl = TI_GLNK_RX_FLOWCTL_Y;
2958 * Transmit flow control can also cause problems on the
2959 * Tigon 2, apparantly with both the copper and fiber
2960 * boards. The symptom is that the interface will just
2961 * hang. This was reproduced with Alteon 180 switches.
2964 if (sc->ti_hwrev != TI_HWREV_TIGON)
2965 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
2968 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2969 TI_GLNK_FULL_DUPLEX| flowctl |
2970 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2972 flowctl = TI_LNK_RX_FLOWCTL_Y;
2974 if (sc->ti_hwrev != TI_HWREV_TIGON)
2975 flowctl |= TI_LNK_TX_FLOWCTL_Y;
2978 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2979 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
2980 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2981 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2982 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2986 flowctl = TI_GLNK_RX_FLOWCTL_Y;
2988 if (sc->ti_hwrev != TI_HWREV_TIGON)
2989 flowctl |= TI_GLNK_TX_FLOWCTL_Y;
2992 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2993 flowctl |TI_GLNK_ENB);
2994 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2995 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2996 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2998 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2999 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3005 flowctl = TI_LNK_RX_FLOWCTL_Y;
3007 if (sc->ti_hwrev != TI_HWREV_TIGON)
3008 flowctl |= TI_LNK_TX_FLOWCTL_Y;
3011 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3012 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3013 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3014 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3015 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3017 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3019 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3020 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3022 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3024 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3025 TI_CMD_CODE_NEGOTIATE_10_100, 0);
3033 * Report current media status.
3036 ti_ifmedia_sts(ifp, ifmr)
3038 struct ifmediareq *ifmr;
3040 struct ti_softc *sc;
3041 u_int32_t media = 0;
3045 ifmr->ifm_status = IFM_AVALID;
3046 ifmr->ifm_active = IFM_ETHER;
3048 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
3051 ifmr->ifm_status |= IFM_ACTIVE;
3053 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3054 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3056 ifmr->ifm_active |= IFM_1000_T;
3058 ifmr->ifm_active |= IFM_1000_SX;
3059 if (media & TI_GLNK_FULL_DUPLEX)
3060 ifmr->ifm_active |= IFM_FDX;
3062 ifmr->ifm_active |= IFM_HDX;
3063 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3064 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3065 if (sc->ti_copper) {
3066 if (media & TI_LNK_100MB)
3067 ifmr->ifm_active |= IFM_100_TX;
3068 if (media & TI_LNK_10MB)
3069 ifmr->ifm_active |= IFM_10_T;
3071 if (media & TI_LNK_100MB)
3072 ifmr->ifm_active |= IFM_100_FX;
3073 if (media & TI_LNK_10MB)
3074 ifmr->ifm_active |= IFM_10_FL;
3076 if (media & TI_LNK_FULL_DUPLEX)
3077 ifmr->ifm_active |= IFM_FDX;
3078 if (media & TI_LNK_HALF_DUPLEX)
3079 ifmr->ifm_active |= IFM_HDX;
3084 ti_ioctl(ifp, command, data)
3089 struct ti_softc *sc = ifp->if_softc;
3090 struct ifreq *ifr = (struct ifreq *) data;
3091 int mask, error = 0;
3092 struct ti_cmd_desc cmd;
3098 if (ifr->ifr_mtu > TI_JUMBO_MTU)
3101 ifp->if_mtu = ifr->ifr_mtu;
3106 if (ifp->if_flags & IFF_UP) {
3108 * If only the state of the PROMISC flag changed,
3109 * then just use the 'set promisc mode' command
3110 * instead of reinitializing the entire NIC. Doing
3111 * a full re-init means reloading the firmware and
3112 * waiting for it to start up, which may take a
3115 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3116 ifp->if_flags & IFF_PROMISC &&
3117 !(sc->ti_if_flags & IFF_PROMISC)) {
3118 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3119 TI_CMD_CODE_PROMISC_ENB, 0);
3120 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3121 !(ifp->if_flags & IFF_PROMISC) &&
3122 sc->ti_if_flags & IFF_PROMISC) {
3123 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3124 TI_CMD_CODE_PROMISC_DIS, 0);
3128 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3132 sc->ti_if_flags = ifp->if_flags;
3137 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3144 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3147 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3148 if (mask & IFCAP_HWCSUM) {
3149 if (IFCAP_HWCSUM & ifp->if_capenable)
3150 ifp->if_capenable &= ~IFCAP_HWCSUM;
3152 ifp->if_capenable |= IFCAP_HWCSUM;
3153 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3159 error = ether_ioctl(ifp, command, data);
3169 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3171 struct ti_softc *sc;
3178 sc->ti_flags |= TI_FLAG_DEBUGING;
3185 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3187 struct ti_softc *sc;
3194 sc->ti_flags &= ~TI_FLAG_DEBUGING;
3201 * This ioctl routine goes along with the Tigon character device.
3204 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3208 struct ti_softc *sc;
3219 struct ti_stats *outstats;
3221 outstats = (struct ti_stats *)addr;
3223 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats,
3224 sizeof(struct ti_stats));
3227 case TIIOCGETPARAMS:
3229 struct ti_params *params;
3231 params = (struct ti_params *)addr;
3233 params->ti_stat_ticks = sc->ti_stat_ticks;
3234 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3235 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3236 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3237 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3238 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3239 params->param_mask = TI_PARAM_ALL;
3245 case TIIOCSETPARAMS:
3247 struct ti_params *params;
3249 params = (struct ti_params *)addr;
3251 if (params->param_mask & TI_PARAM_STAT_TICKS) {
3252 sc->ti_stat_ticks = params->ti_stat_ticks;
3253 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3256 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3257 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3258 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3259 sc->ti_rx_coal_ticks);
3262 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3263 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3264 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3265 sc->ti_tx_coal_ticks);
3268 if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3269 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3270 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3271 sc->ti_rx_max_coal_bds);
3274 if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3275 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3276 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3277 sc->ti_tx_max_coal_bds);
3280 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3281 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3282 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3283 sc->ti_tx_buf_ratio);
3290 case TIIOCSETTRACE: {
3291 ti_trace_type trace_type;
3293 trace_type = *(ti_trace_type *)addr;
3296 * Set tracing to whatever the user asked for. Setting
3297 * this register to 0 should have the effect of disabling
3300 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3306 case TIIOCGETTRACE: {
3307 struct ti_trace_buf *trace_buf;
3308 u_int32_t trace_start, cur_trace_ptr, trace_len;
3310 trace_buf = (struct ti_trace_buf *)addr;
3312 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3313 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3314 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3317 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3318 "trace_len = %d\n", trace_start,
3319 cur_trace_ptr, trace_len);
3320 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3321 trace_buf->buf_len);
3324 error = ti_copy_mem(sc, trace_start, min(trace_len,
3325 trace_buf->buf_len),
3326 (caddr_t)trace_buf->buf, 1, 1);
3329 trace_buf->fill_len = min(trace_len,
3330 trace_buf->buf_len);
3331 if (cur_trace_ptr < trace_start)
3332 trace_buf->cur_trace_ptr =
3333 trace_start - cur_trace_ptr;
3335 trace_buf->cur_trace_ptr =
3336 cur_trace_ptr - trace_start;
3338 trace_buf->fill_len = 0;
3344 * For debugging, five ioctls are needed:
3353 * From what I can tell, Alteon's Solaris Tigon driver
3354 * only has one character device, so you have to attach
3355 * to the Tigon board you're interested in. This seems
3356 * like a not-so-good way to do things, since unless you
3357 * subsequently specify the unit number of the device
3358 * you're interested in in every ioctl, you'll only be
3359 * able to debug one board at a time.
3363 case ALT_READ_TG_MEM:
3364 case ALT_WRITE_TG_MEM:
3366 struct tg_mem *mem_param;
3367 u_int32_t sram_end, scratch_end;
3369 mem_param = (struct tg_mem *)addr;
3371 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3372 sram_end = TI_END_SRAM_I;
3373 scratch_end = TI_END_SCRATCH_I;
3375 sram_end = TI_END_SRAM_II;
3376 scratch_end = TI_END_SCRATCH_II;
3380 * For now, we'll only handle accessing regular SRAM,
3383 if ((mem_param->tgAddr >= TI_BEG_SRAM)
3384 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) {
3386 * In this instance, we always copy to/from user
3387 * space, so the user space argument is set to 1.
3389 error = ti_copy_mem(sc, mem_param->tgAddr,
3391 mem_param->userAddr, 1,
3392 (cmd == ALT_READ_TG_MEM) ? 1 : 0);
3393 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH)
3394 && (mem_param->tgAddr <= scratch_end)) {
3395 error = ti_copy_scratch(sc, mem_param->tgAddr,
3397 mem_param->userAddr, 1,
3398 (cmd == ALT_READ_TG_MEM) ?
3399 1 : 0, TI_PROCESSOR_A);
3400 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG)
3401 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) {
3402 if (sc->ti_hwrev == TI_HWREV_TIGON) {
3403 if_printf(sc->ti_ifp,
3404 "invalid memory range for Tigon I\n");
3408 error = ti_copy_scratch(sc, mem_param->tgAddr -
3409 TI_SCRATCH_DEBUG_OFF,
3411 mem_param->userAddr, 1,
3412 (cmd == ALT_READ_TG_MEM) ?
3413 1 : 0, TI_PROCESSOR_B);
3415 if_printf(sc->ti_ifp, "memory address %#x len %d is "
3416 "out of supported range\n",
3417 mem_param->tgAddr, mem_param->len);
3423 case ALT_READ_TG_REG:
3424 case ALT_WRITE_TG_REG:
3426 struct tg_reg *regs;
3429 regs = (struct tg_reg *)addr;
3432 * Make sure the address in question isn't out of range.
3434 if (regs->addr > TI_REG_MAX) {
3438 if (cmd == ALT_READ_TG_REG) {
3439 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3440 regs->addr, &tmpval, 1);
3441 regs->data = ntohl(tmpval);
3443 if ((regs->addr == TI_CPU_STATE)
3444 || (regs->addr == TI_CPU_CTL_B)) {
3445 if_printf(sc->ti_ifp, "register %#x = %#x\n",
3446 regs->addr, tmpval);
3450 tmpval = htonl(regs->data);
3451 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3452 regs->addr, &tmpval, 1);
3468 struct ti_softc *sc;
3474 * When we're debugging, the chip is often stopped for long periods
3475 * of time, and that would normally cause the watchdog timer to fire.
3476 * Since that impedes debugging, we don't want to do that.
3478 if (sc->ti_flags & TI_FLAG_DEBUGING) {
3483 if_printf(ifp, "watchdog timeout -- resetting\n");
3492 * Stop the adapter and free any mbufs allocated to the
3497 struct ti_softc *sc;
3500 struct ti_cmd_desc cmd;
3506 /* Disable host interrupts. */
3507 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3509 * Tell firmware we're shutting down.
3511 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3513 /* Halt and reinitialize. */
3515 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
3518 /* Free the RX lists. */
3519 ti_free_rx_ring_std(sc);
3521 /* Free jumbo RX list. */
3522 ti_free_rx_ring_jumbo(sc);
3524 /* Free mini RX list. */
3525 ti_free_rx_ring_mini(sc);
3527 /* Free TX buffers. */
3528 ti_free_tx_ring(sc);
3530 sc->ti_ev_prodidx.ti_idx = 0;
3531 sc->ti_return_prodidx.ti_idx = 0;
3532 sc->ti_tx_considx.ti_idx = 0;
3533 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3535 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3540 * Stop all chip I/O so that the kernel's probe routines don't
3541 * get confused by errant DMAs when rebooting.
3547 struct ti_softc *sc;
3549 sc = device_get_softc(dev);