2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
37 * Manuals, sample driver and firmware source kits are available
38 * from http://www.alteon.com/support/openkits.
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Electrical Engineering Department
42 * Columbia University, New York City
46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
50 * filtering and jumbo (9014 byte) frames. The hardware is largely
51 * controlled by firmware, which must be loaded into the NIC during
54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
55 * revision, which supports new features such as extended commands,
56 * extended jumbo receive ring desciptors and a mini receive ring.
58 * Alteon Networks is to be commended for releasing such a vast amount
59 * of development material for the Tigon NIC without requiring an NDA
60 * (although they really should have done it a long time ago). With
61 * any luck, the other vendors will finally wise up and follow Alteon's
64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
65 * this driver by #including it as a C header file. This bloats the
66 * driver somewhat, but it's the easiest method considering that the
67 * driver code and firmware code need to be kept in sync. The source
68 * for the firmware is not provided with the FreeBSD distribution since
69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
71 * The following people deserve special thanks:
72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
74 * - Raymond Lee of Netgear, for providing a pair of Netgear
75 * GA620 Tigon 2 boards for testing
76 * - Ulf Zimmermann, for bringing the GA260 to my attention and
77 * convincing me to write this driver.
78 * - Andrew Gallatin for providing FreeBSD/Alpha support.
81 #include <sys/param.h>
82 #include <sys/systm.h>
83 #include <sys/sockio.h>
85 #include <sys/malloc.h>
86 #include <sys/kernel.h>
87 #include <sys/socket.h>
88 #include <sys/queue.h>
91 #include <net/if_arp.h>
92 #include <net/ethernet.h>
93 #include <net/if_dl.h>
94 #include <net/if_media.h>
95 #include <net/if_types.h>
96 #include <net/if_vlan_var.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
104 #include <vm/vm.h> /* for vtophys */
105 #include <vm/pmap.h> /* for vtophys */
106 #include <machine/bus_memio.h>
107 #include <machine/bus.h>
108 #include <machine/resource.h>
110 #include <sys/rman.h>
112 #include <pci/pcireg.h>
113 #include <pci/pcivar.h>
115 #include <pci/if_tireg.h>
116 #include <pci/ti_fw.h>
117 #include <pci/ti_fw2.h>
119 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
122 static const char rcsid[] =
127 * Various supported device vendors/types and their names.
130 static struct ti_type ti_devs[] = {
131 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
132 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
133 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
134 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
135 { TC_VENDORID, TC_DEVICEID_3C985,
136 "3Com 3c985-SX Gigabit Ethernet" },
137 { NG_VENDORID, NG_DEVICEID_GA620,
138 "Netgear GA620 1000baseSX Gigabit Ethernet" },
139 { NG_VENDORID, NG_DEVICEID_GA620T,
140 "Netgear GA620 1000baseT Gigabit Ethernet" },
141 { SGI_VENDORID, SGI_DEVICEID_TIGON,
142 "Silicon Graphics Gigabit Ethernet" },
143 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
144 "Farallon PN9000SX Gigabit Ethernet" },
148 static int ti_probe __P((device_t));
149 static int ti_attach __P((device_t));
150 static int ti_detach __P((device_t));
151 static void ti_txeof __P((struct ti_softc *));
152 static void ti_rxeof __P((struct ti_softc *));
154 static void ti_stats_update __P((struct ti_softc *));
155 static int ti_encap __P((struct ti_softc *, struct mbuf *,
158 static void ti_intr __P((void *));
159 static void ti_start __P((struct ifnet *));
160 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t));
161 static void ti_init __P((void *));
162 static void ti_init2 __P((struct ti_softc *));
163 static void ti_stop __P((struct ti_softc *));
164 static void ti_watchdog __P((struct ifnet *));
165 static void ti_shutdown __P((device_t));
166 static int ti_ifmedia_upd __P((struct ifnet *));
167 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
169 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int));
170 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *,
172 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int));
174 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *));
175 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *));
176 static void ti_setmulti __P((struct ti_softc *));
178 static void ti_mem __P((struct ti_softc *, u_int32_t,
179 u_int32_t, caddr_t));
180 static void ti_loadfw __P((struct ti_softc *));
181 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *));
182 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *,
184 static void ti_handle_events __P((struct ti_softc *));
185 static int ti_alloc_jumbo_mem __P((struct ti_softc *));
186 static void *ti_jalloc __P((struct ti_softc *));
187 static void ti_jfree __P((caddr_t, void *));
188 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *));
189 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *));
190 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *));
191 static int ti_init_rx_ring_std __P((struct ti_softc *));
192 static void ti_free_rx_ring_std __P((struct ti_softc *));
193 static int ti_init_rx_ring_jumbo __P((struct ti_softc *));
194 static void ti_free_rx_ring_jumbo __P((struct ti_softc *));
195 static int ti_init_rx_ring_mini __P((struct ti_softc *));
196 static void ti_free_rx_ring_mini __P((struct ti_softc *));
197 static void ti_free_tx_ring __P((struct ti_softc *));
198 static int ti_init_tx_ring __P((struct ti_softc *));
200 static int ti_64bitslot_war __P((struct ti_softc *));
201 static int ti_chipinit __P((struct ti_softc *));
202 static int ti_gibinit __P((struct ti_softc *));
204 static device_method_t ti_methods[] = {
205 /* Device interface */
206 DEVMETHOD(device_probe, ti_probe),
207 DEVMETHOD(device_attach, ti_attach),
208 DEVMETHOD(device_detach, ti_detach),
209 DEVMETHOD(device_shutdown, ti_shutdown),
213 static driver_t ti_driver = {
216 sizeof(struct ti_softc)
219 static devclass_t ti_devclass;
221 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
224 * Send an instruction or address to the EEPROM, check for ACK.
226 static u_int32_t ti_eeprom_putbyte(sc, byte)
230 register int i, ack = 0;
233 * Make sure we're in TX mode.
235 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
238 * Feed in each bit and stobe the clock.
240 for (i = 0x80; i; i >>= 1) {
242 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
244 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
255 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
260 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
261 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
262 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
268 * Read a byte of data stored in the EEPROM at address 'addr.'
269 * We have to send two address bytes since the EEPROM can hold
270 * more than 256 bytes of data.
272 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
283 * Send write control code to EEPROM.
285 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
286 printf("ti%d: failed to send write command, status: %x\n",
287 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
292 * Send first byte of address of byte we want to read.
294 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
295 printf("ti%d: failed to send address, status: %x\n",
296 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
300 * Send second byte address of byte we want to read.
302 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
303 printf("ti%d: failed to send address, status: %x\n",
304 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
311 * Send read control code to EEPROM.
313 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
314 printf("ti%d: failed to send read command, status: %x\n",
315 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
320 * Start reading bits from EEPROM.
322 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
323 for (i = 0x80; i; i >>= 1) {
324 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
326 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
328 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
335 * No ACK generated for read, so just return byte.
344 * Read a sequence of bytes from the EEPROM.
346 static int ti_read_eeprom(sc, dest, off, cnt)
355 for (i = 0; i < cnt; i++) {
356 err = ti_eeprom_getbyte(sc, off + i, &byte);
366 * NIC memory access function. Can be used to either clear a section
367 * of NIC local memory or (if buf is non-NULL) copy data into it.
369 static void ti_mem(sc, addr, len, buf)
374 int segptr, segsize, cnt;
375 caddr_t ti_winbase, ptr;
379 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
386 segsize = TI_WINLEN - (segptr % TI_WINLEN);
387 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
389 bzero((char *)ti_winbase + (segptr &
390 (TI_WINLEN - 1)), segsize);
392 bcopy((char *)ptr, (char *)ti_winbase +
393 (segptr & (TI_WINLEN - 1)), segsize);
404 * Load firmware image into the NIC. Check that the firmware revision
405 * is acceptable and see if we want the firmware for the Tigon 1 or
408 static void ti_loadfw(sc)
411 switch(sc->ti_hwrev) {
413 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
414 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
415 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
416 printf("ti%d: firmware revision mismatch; want "
417 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
418 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
419 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
420 tigonFwReleaseMinor, tigonFwReleaseFix);
423 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
424 (caddr_t)tigonFwText);
425 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
426 (caddr_t)tigonFwData);
427 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
428 (caddr_t)tigonFwRodata);
429 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
430 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
431 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
433 case TI_HWREV_TIGON_II:
434 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
435 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
436 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
437 printf("ti%d: firmware revision mismatch; want "
438 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
439 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
440 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
441 tigon2FwReleaseMinor, tigon2FwReleaseFix);
444 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
445 (caddr_t)tigon2FwText);
446 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
447 (caddr_t)tigon2FwData);
448 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
449 (caddr_t)tigon2FwRodata);
450 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
451 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
452 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
455 printf("ti%d: can't load firmware: unknown hardware rev\n",
464 * Send the NIC a command via the command ring.
466 static void ti_cmd(sc, cmd)
468 struct ti_cmd_desc *cmd;
472 if (sc->ti_rdata->ti_cmd_ring == NULL)
475 index = sc->ti_cmd_saved_prodidx;
476 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
477 TI_INC(index, TI_CMD_RING_CNT);
478 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
479 sc->ti_cmd_saved_prodidx = index;
485 * Send the NIC an extended command. The 'len' parameter specifies the
486 * number of command slots to include after the initial command.
488 static void ti_cmd_ext(sc, cmd, arg, len)
490 struct ti_cmd_desc *cmd;
497 if (sc->ti_rdata->ti_cmd_ring == NULL)
500 index = sc->ti_cmd_saved_prodidx;
501 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
502 TI_INC(index, TI_CMD_RING_CNT);
503 for (i = 0; i < len; i++) {
504 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
505 *(u_int32_t *)(&arg[i * 4]));
506 TI_INC(index, TI_CMD_RING_CNT);
508 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
509 sc->ti_cmd_saved_prodidx = index;
515 * Handle events that have triggered interrupts.
517 static void ti_handle_events(sc)
520 struct ti_event_desc *e;
522 if (sc->ti_rdata->ti_event_ring == NULL)
525 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
526 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
527 switch(e->ti_event) {
528 case TI_EV_LINKSTAT_CHANGED:
529 sc->ti_linkstat = e->ti_code;
530 if (e->ti_code == TI_EV_CODE_LINK_UP)
531 printf("ti%d: 10/100 link up\n", sc->ti_unit);
532 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
533 printf("ti%d: gigabit link up\n", sc->ti_unit);
534 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
535 printf("ti%d: link down\n", sc->ti_unit);
538 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
539 printf("ti%d: invalid command\n", sc->ti_unit);
540 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
541 printf("ti%d: unknown command\n", sc->ti_unit);
542 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
543 printf("ti%d: bad config data\n", sc->ti_unit);
545 case TI_EV_FIRMWARE_UP:
548 case TI_EV_STATS_UPDATED:
551 case TI_EV_RESET_JUMBO_RING:
552 case TI_EV_MCAST_UPDATED:
556 printf("ti%d: unknown event: %d\n",
557 sc->ti_unit, e->ti_event);
560 /* Advance the consumer index. */
561 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
562 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
569 * Memory management for the jumbo receive ring is a pain in the
570 * butt. We need to allocate at least 9018 bytes of space per frame,
571 * _and_ it has to be contiguous (unless you use the extended
572 * jumbo descriptor format). Using malloc() all the time won't
573 * work: malloc() allocates memory in powers of two, which means we
574 * would end up wasting a considerable amount of space by allocating
575 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
576 * to do our own memory management.
578 * The driver needs to allocate a contiguous chunk of memory at boot
579 * time. We then chop this up ourselves into 9K pieces and use them
580 * as external mbuf storage.
582 * One issue here is how much memory to allocate. The jumbo ring has
583 * 256 slots in it, but at 9K per slot than can consume over 2MB of
584 * RAM. This is a bit much, especially considering we also need
585 * RAM for the standard ring and mini ring (on the Tigon 2). To
586 * save space, we only actually allocate enough memory for 64 slots
587 * by default, which works out to between 500 and 600K. This can
588 * be tuned by changing a #define in if_tireg.h.
591 static int ti_alloc_jumbo_mem(sc)
596 struct ti_jpool_entry *entry;
598 /* Grab a big chunk o' storage. */
599 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
600 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
602 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
603 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
607 SLIST_INIT(&sc->ti_jfree_listhead);
608 SLIST_INIT(&sc->ti_jinuse_listhead);
611 * Now divide it up into 9K pieces and save the addresses
614 ptr = sc->ti_cdata.ti_jumbo_buf;
615 for (i = 0; i < TI_JSLOTS; i++) {
616 sc->ti_cdata.ti_jslots[i] = ptr;
618 entry = malloc(sizeof(struct ti_jpool_entry),
621 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
623 sc->ti_cdata.ti_jumbo_buf = NULL;
624 printf("ti%d: no memory for jumbo "
625 "buffer queue!\n", sc->ti_unit);
629 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
636 * Allocate a jumbo buffer.
638 static void *ti_jalloc(sc)
641 struct ti_jpool_entry *entry;
643 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
646 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
650 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
651 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
652 return(sc->ti_cdata.ti_jslots[entry->slot]);
656 * Release a jumbo buffer.
658 static void ti_jfree(buf, args)
664 struct ti_jpool_entry *entry;
666 /* Extract the softc struct pointer. */
667 sc = (struct ti_softc *)args;
670 panic("ti_jfree: didn't get softc pointer!");
672 /* calculate the slot this buffer belongs to */
673 i = ((vm_offset_t)buf
674 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
676 if ((i < 0) || (i >= TI_JSLOTS))
677 panic("ti_jfree: asked to free buffer that we don't manage!");
679 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
681 panic("ti_jfree: buffer not in use!");
683 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
684 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
691 * Intialize a standard receive ring descriptor.
693 static int ti_newbuf_std(sc, i, m)
698 struct mbuf *m_new = NULL;
699 struct ti_rx_desc *r;
702 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
704 printf("ti%d: mbuf allocation failed "
705 "-- packet dropped!\n", sc->ti_unit);
709 MCLGET(m_new, M_DONTWAIT);
710 if (!(m_new->m_flags & M_EXT)) {
711 printf("ti%d: cluster allocation failed "
712 "-- packet dropped!\n", sc->ti_unit);
716 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
719 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
720 m_new->m_data = m_new->m_ext.ext_buf;
723 m_adj(m_new, ETHER_ALIGN);
724 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
725 r = &sc->ti_rdata->ti_rx_std_ring[i];
726 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
727 r->ti_type = TI_BDTYPE_RECV_BD;
729 if (sc->arpcom.ac_if.if_hwassist)
730 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
731 r->ti_len = m_new->m_len;
738 * Intialize a mini receive ring descriptor. This only applies to
741 static int ti_newbuf_mini(sc, i, m)
746 struct mbuf *m_new = NULL;
747 struct ti_rx_desc *r;
750 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
752 printf("ti%d: mbuf allocation failed "
753 "-- packet dropped!\n", sc->ti_unit);
756 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
759 m_new->m_data = m_new->m_pktdat;
760 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
763 m_adj(m_new, ETHER_ALIGN);
764 r = &sc->ti_rdata->ti_rx_mini_ring[i];
765 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
766 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
767 r->ti_type = TI_BDTYPE_RECV_BD;
768 r->ti_flags = TI_BDFLAG_MINI_RING;
769 if (sc->arpcom.ac_if.if_hwassist)
770 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
771 r->ti_len = m_new->m_len;
778 * Initialize a jumbo receive ring descriptor. This allocates
779 * a jumbo buffer from the pool managed internally by the driver.
781 static int ti_newbuf_jumbo(sc, i, m)
786 struct mbuf *m_new = NULL;
787 struct ti_rx_desc *r;
792 /* Allocate the mbuf. */
793 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
795 printf("ti%d: mbuf allocation failed "
796 "-- packet dropped!\n", sc->ti_unit);
800 /* Allocate the jumbo buffer */
804 printf("ti%d: jumbo allocation failed "
805 "-- packet dropped!\n", sc->ti_unit);
809 /* Attach the buffer to the mbuf. */
810 m_new->m_data = (void *) buf;
811 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
812 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
813 (struct ti_softc *)sc, 0, EXT_NET_DRV);
816 m_new->m_data = m_new->m_ext.ext_buf;
817 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
820 m_adj(m_new, ETHER_ALIGN);
821 /* Set up the descriptor. */
822 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
823 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
824 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
825 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
826 r->ti_flags = TI_BDFLAG_JUMBO_RING;
827 if (sc->arpcom.ac_if.if_hwassist)
828 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
829 r->ti_len = m_new->m_len;
836 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
837 * that's 1MB or memory, which is a lot. For now, we fill only the first
838 * 256 ring entries and hope that our CPU is fast enough to keep up with
841 static int ti_init_rx_ring_std(sc)
845 struct ti_cmd_desc cmd;
847 for (i = 0; i < TI_SSLOTS; i++) {
848 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
852 TI_UPDATE_STDPROD(sc, i - 1);
858 static void ti_free_rx_ring_std(sc)
863 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
864 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
865 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
866 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
868 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
869 sizeof(struct ti_rx_desc));
875 static int ti_init_rx_ring_jumbo(sc)
879 struct ti_cmd_desc cmd;
881 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
882 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
886 TI_UPDATE_JUMBOPROD(sc, i - 1);
887 sc->ti_jumbo = i - 1;
892 static void ti_free_rx_ring_jumbo(sc)
897 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
898 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
899 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
900 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
902 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
903 sizeof(struct ti_rx_desc));
909 static int ti_init_rx_ring_mini(sc)
914 for (i = 0; i < TI_MSLOTS; i++) {
915 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
919 TI_UPDATE_MINIPROD(sc, i - 1);
925 static void ti_free_rx_ring_mini(sc)
930 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
931 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
932 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
933 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
935 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
936 sizeof(struct ti_rx_desc));
942 static void ti_free_tx_ring(sc)
947 if (sc->ti_rdata->ti_tx_ring == NULL)
950 for (i = 0; i < TI_TX_RING_CNT; i++) {
951 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
952 m_freem(sc->ti_cdata.ti_tx_chain[i]);
953 sc->ti_cdata.ti_tx_chain[i] = NULL;
955 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
956 sizeof(struct ti_tx_desc));
962 static int ti_init_tx_ring(sc)
966 sc->ti_tx_saved_considx = 0;
967 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
972 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
973 * but we have to support the old way too so that Tigon 1 cards will
976 void ti_add_mcast(sc, addr)
978 struct ether_addr *addr;
980 struct ti_cmd_desc cmd;
982 u_int32_t ext[2] = {0, 0};
984 m = (u_int16_t *)&addr->octet[0];
986 switch(sc->ti_hwrev) {
988 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
989 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
990 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
992 case TI_HWREV_TIGON_II:
993 ext[0] = htons(m[0]);
994 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
995 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
998 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1005 void ti_del_mcast(sc, addr)
1006 struct ti_softc *sc;
1007 struct ether_addr *addr;
1009 struct ti_cmd_desc cmd;
1011 u_int32_t ext[2] = {0, 0};
1013 m = (u_int16_t *)&addr->octet[0];
1015 switch(sc->ti_hwrev) {
1016 case TI_HWREV_TIGON:
1017 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1018 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1019 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1021 case TI_HWREV_TIGON_II:
1022 ext[0] = htons(m[0]);
1023 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1024 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1027 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1035 * Configure the Tigon's multicast address filter.
1037 * The actual multicast table management is a bit of a pain, thanks to
1038 * slight brain damage on the part of both Alteon and us. With our
1039 * multicast code, we are only alerted when the multicast address table
1040 * changes and at that point we only have the current list of addresses:
1041 * we only know the current state, not the previous state, so we don't
1042 * actually know what addresses were removed or added. The firmware has
1043 * state, but we can't get our grubby mits on it, and there is no 'delete
1044 * all multicast addresses' command. Hence, we have to maintain our own
1045 * state so we know what addresses have been programmed into the NIC at
1048 static void ti_setmulti(sc)
1049 struct ti_softc *sc;
1052 struct ifmultiaddr *ifma;
1053 struct ti_cmd_desc cmd;
1054 struct ti_mc_entry *mc;
1057 ifp = &sc->arpcom.ac_if;
1059 if (ifp->if_flags & IFF_ALLMULTI) {
1060 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1063 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1066 /* Disable interrupts. */
1067 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1068 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1070 /* First, zot all the existing filters. */
1071 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1072 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1073 ti_del_mcast(sc, &mc->mc_addr);
1074 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1078 /* Now program new ones. */
1079 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1080 if (ifma->ifma_addr->sa_family != AF_LINK)
1082 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1083 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1084 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1085 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1086 ti_add_mcast(sc, &mc->mc_addr);
1089 /* Re-enable interrupts. */
1090 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1096 * Check to see if the BIOS has configured us for a 64 bit slot when
1097 * we aren't actually in one. If we detect this condition, we can work
1098 * around it on the Tigon 2 by setting a bit in the PCI state register,
1099 * but for the Tigon 1 we must give up and abort the interface attach.
1101 static int ti_64bitslot_war(sc)
1102 struct ti_softc *sc;
1104 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1105 CSR_WRITE_4(sc, 0x600, 0);
1106 CSR_WRITE_4(sc, 0x604, 0);
1107 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1108 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1109 if (sc->ti_hwrev == TI_HWREV_TIGON)
1112 TI_SETBIT(sc, TI_PCI_STATE,
1113 TI_PCISTATE_32BIT_BUS);
1123 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1124 * self-test results.
1126 static int ti_chipinit(sc)
1127 struct ti_softc *sc;
1129 u_int32_t cacheline;
1130 u_int32_t pci_writemax = 0;
1132 /* Initialize link to down state. */
1133 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1135 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
1136 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1138 sc->arpcom.ac_if.if_hwassist = 0;
1140 /* Set endianness before we access any non-PCI registers. */
1141 #if BYTE_ORDER == BIG_ENDIAN
1142 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1143 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1145 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1146 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1149 /* Check the ROM failed bit to see if self-tests passed. */
1150 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1151 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1156 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1158 /* Figure out the hardware revision. */
1159 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1160 case TI_REV_TIGON_I:
1161 sc->ti_hwrev = TI_HWREV_TIGON;
1163 case TI_REV_TIGON_II:
1164 sc->ti_hwrev = TI_HWREV_TIGON_II;
1167 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1171 /* Do special setup for Tigon 2. */
1172 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1173 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1174 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1175 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1178 /* Set up the PCI state register. */
1179 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1180 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1181 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1184 /* Clear the read/write max DMA parameters. */
1185 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1186 TI_PCISTATE_READ_MAXDMA));
1188 /* Get cache line size. */
1189 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1192 * If the system has set enabled the PCI memory write
1193 * and invalidate command in the command register, set
1194 * the write max parameter accordingly. This is necessary
1195 * to use MWI with the Tigon 2.
1197 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1207 /* Disable PCI memory write and invalidate. */
1209 printf("ti%d: cache line size %d not "
1210 "supported; disabling PCI MWI\n",
1211 sc->ti_unit, cacheline);
1212 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1213 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1218 #ifdef __brokenalpha__
1220 * From the Alteon sample driver:
1221 * Must insure that we do not cross an 8K (bytes) boundary
1222 * for DMA reads. Our highest limit is 1K bytes. This is a
1223 * restriction on some ALPHA platforms with early revision
1224 * 21174 PCI chipsets, such as the AlphaPC 164lx
1226 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1228 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1231 /* This sets the min dma param all the way up (0xff). */
1232 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1234 /* Configure DMA variables. */
1235 #if BYTE_ORDER == BIG_ENDIAN
1236 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1237 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1238 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1239 TI_OPMODE_DONT_FRAG_JUMBO);
1241 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1242 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1243 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1247 * Only allow 1 DMA channel to be active at a time.
1248 * I don't think this is a good idea, but without it
1249 * the firmware racks up lots of nicDmaReadRingFull
1250 * errors. This is not compatible with hardware checksums.
1252 if (sc->arpcom.ac_if.if_hwassist == 0)
1253 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1255 /* Recommended settings from Tigon manual. */
1256 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1257 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1259 if (ti_64bitslot_war(sc)) {
1260 printf("ti%d: bios thinks we're in a 64 bit slot, "
1261 "but we aren't", sc->ti_unit);
1269 * Initialize the general information block and firmware, and
1270 * start the CPU(s) running.
1272 static int ti_gibinit(sc)
1273 struct ti_softc *sc;
1279 ifp = &sc->arpcom.ac_if;
1281 /* Disable interrupts for now. */
1282 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1284 /* Tell the chip where to find the general information block. */
1285 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1286 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1288 /* Load the firmware into SRAM. */
1291 /* Set up the contents of the general info and ring control blocks. */
1293 /* Set up the event ring and producer pointer. */
1294 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1296 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1298 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1299 vtophys(&sc->ti_ev_prodidx);
1300 sc->ti_ev_prodidx.ti_idx = 0;
1301 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1302 sc->ti_ev_saved_considx = 0;
1304 /* Set up the command ring and producer mailbox. */
1305 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1307 sc->ti_rdata->ti_cmd_ring =
1308 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1309 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1311 rcb->ti_max_len = 0;
1312 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1313 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1315 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1316 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1317 sc->ti_cmd_saved_prodidx = 0;
1320 * Assign the address of the stats refresh buffer.
1321 * We re-use the current stats buffer for this to
1324 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1325 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1327 /* Set up the standard receive ring. */
1328 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1329 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1330 rcb->ti_max_len = TI_FRAMELEN;
1332 if (sc->arpcom.ac_if.if_hwassist)
1333 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1334 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1335 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1337 /* Set up the jumbo receive ring. */
1338 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1339 TI_HOSTADDR(rcb->ti_hostaddr) =
1340 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1341 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1343 if (sc->arpcom.ac_if.if_hwassist)
1344 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1345 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1346 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1349 * Set up the mini ring. Only activated on the
1350 * Tigon 2 but the slot in the config block is
1351 * still there on the Tigon 1.
1353 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1354 TI_HOSTADDR(rcb->ti_hostaddr) =
1355 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1356 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1357 if (sc->ti_hwrev == TI_HWREV_TIGON)
1358 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1361 if (sc->arpcom.ac_if.if_hwassist)
1362 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1363 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1364 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1367 * Set up the receive return ring.
1369 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1370 TI_HOSTADDR(rcb->ti_hostaddr) =
1371 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1373 rcb->ti_max_len = TI_RETURN_RING_CNT;
1374 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1375 vtophys(&sc->ti_return_prodidx);
1378 * Set up the tx ring. Note: for the Tigon 2, we have the option
1379 * of putting the transmit ring in the host's address space and
1380 * letting the chip DMA it instead of leaving the ring in the NIC's
1381 * memory and accessing it through the shared memory region. We
1382 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1383 * so we have to revert to the shared memory scheme if we detect
1386 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1387 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1388 sc->ti_rdata->ti_tx_ring_nic =
1389 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1391 bzero((char *)sc->ti_rdata->ti_tx_ring,
1392 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1393 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1394 if (sc->ti_hwrev == TI_HWREV_TIGON)
1397 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1398 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1399 if (sc->arpcom.ac_if.if_hwassist)
1400 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1401 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1402 rcb->ti_max_len = TI_TX_RING_CNT;
1403 if (sc->ti_hwrev == TI_HWREV_TIGON)
1404 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1406 TI_HOSTADDR(rcb->ti_hostaddr) =
1407 vtophys(&sc->ti_rdata->ti_tx_ring);
1408 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1409 vtophys(&sc->ti_tx_considx);
1411 /* Set up tuneables */
1412 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1413 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1414 (sc->ti_rx_coal_ticks / 10));
1416 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1417 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1418 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1419 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1420 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1421 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1423 /* Turn interrupts on. */
1424 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1425 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1428 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1434 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1435 * against our list and return its name if we find a match.
1437 static int ti_probe(dev)
1444 while(t->ti_name != NULL) {
1445 if ((pci_get_vendor(dev) == t->ti_vid) &&
1446 (pci_get_device(dev) == t->ti_did)) {
1447 device_set_desc(dev, t->ti_name);
1456 static int ti_attach(dev)
1461 struct ti_softc *sc;
1462 int unit, error = 0, rid;
1464 sc = device_get_softc(dev);
1465 unit = device_get_unit(dev);
1466 bzero(sc, sizeof(struct ti_softc));
1468 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
1470 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM;
1471 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities;
1474 * Map control/status registers.
1476 pci_enable_busmaster(dev);
1477 pci_enable_io(dev, SYS_RES_MEMORY);
1478 command = pci_read_config(dev, PCIR_COMMAND, 4);
1480 if (!(command & PCIM_CMD_MEMEN)) {
1481 printf("ti%d: failed to enable memory mapping!\n", unit);
1487 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1488 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE);
1490 if (sc->ti_res == NULL) {
1491 printf ("ti%d: couldn't map memory\n", unit);
1496 sc->ti_btag = rman_get_bustag(sc->ti_res);
1497 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1498 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1500 /* Allocate interrupt */
1503 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1504 RF_SHAREABLE | RF_ACTIVE);
1506 if (sc->ti_irq == NULL) {
1507 printf("ti%d: couldn't map interrupt\n", unit);
1512 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1513 ti_intr, sc, &sc->ti_intrhand);
1516 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1517 bus_release_resource(dev, SYS_RES_MEMORY,
1518 TI_PCI_LOMEM, sc->ti_res);
1519 printf("ti%d: couldn't set up irq\n", unit);
1525 if (ti_chipinit(sc)) {
1526 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1527 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1528 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1529 bus_release_resource(dev, SYS_RES_MEMORY,
1530 TI_PCI_LOMEM, sc->ti_res);
1535 /* Zero out the NIC's on-board SRAM. */
1536 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1538 /* Init again -- zeroing memory may have clobbered some registers. */
1539 if (ti_chipinit(sc)) {
1540 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1541 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1542 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1543 bus_release_resource(dev, SYS_RES_MEMORY,
1544 TI_PCI_LOMEM, sc->ti_res);
1550 * Get station address from the EEPROM. Note: the manual states
1551 * that the MAC address is at offset 0x8c, however the data is
1552 * stored as two longwords (since that's how it's loaded into
1553 * the NIC). This means the MAC address is actually preceded
1554 * by two zero bytes. We need to skip over those.
1556 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1557 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1558 printf("ti%d: failed to read station address\n", unit);
1559 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1560 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1561 bus_release_resource(dev, SYS_RES_MEMORY,
1562 TI_PCI_LOMEM, sc->ti_res);
1568 * A Tigon chip was detected. Inform the world.
1570 printf("ti%d: Ethernet address: %6D\n", unit,
1571 sc->arpcom.ac_enaddr, ":");
1573 /* Allocate the general information block and ring buffers. */
1574 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1575 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1577 if (sc->ti_rdata == NULL) {
1578 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1579 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1580 bus_release_resource(dev, SYS_RES_MEMORY,
1581 TI_PCI_LOMEM, sc->ti_res);
1583 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1587 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1589 /* Try to allocate memory for jumbo buffers. */
1590 if (ti_alloc_jumbo_mem(sc)) {
1591 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1592 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1593 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1594 bus_release_resource(dev, SYS_RES_MEMORY,
1595 TI_PCI_LOMEM, sc->ti_res);
1596 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data),
1603 * We really need a better way to tell a 1000baseTX card
1604 * from a 1000baseSX one, since in theory there could be
1605 * OEMed 1000baseTX cards from lame vendors who aren't
1606 * clever enough to change the PCI ID. For the moment
1607 * though, the AceNIC is the only copper card available.
1609 if (pci_get_vendor(dev) == ALT_VENDORID &&
1610 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1612 /* Ok, it's not the only copper card available. */
1613 if (pci_get_vendor(dev) == NG_VENDORID &&
1614 pci_get_device(dev) == NG_DEVICEID_GA620T)
1617 /* Set default tuneable values. */
1618 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1619 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1620 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1621 sc->ti_rx_max_coal_bds = 64;
1622 sc->ti_tx_max_coal_bds = 128;
1623 sc->ti_tx_buf_ratio = 21;
1625 /* Set up ifnet structure */
1626 ifp = &sc->arpcom.ac_if;
1628 ifp->if_unit = sc->ti_unit;
1629 ifp->if_name = "ti";
1630 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1631 ifp->if_ioctl = ti_ioctl;
1632 ifp->if_output = ether_output;
1633 ifp->if_start = ti_start;
1634 ifp->if_watchdog = ti_watchdog;
1635 ifp->if_init = ti_init;
1636 ifp->if_mtu = ETHERMTU;
1637 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
1639 /* Set up ifmedia support. */
1640 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1641 if (sc->ti_copper) {
1643 * Copper cards allow manual 10/100 mode selection,
1644 * but not manual 1000baseTX mode selection. Why?
1645 * Becuase currently there's no way to specify the
1646 * master/slave setting through the firmware interface,
1647 * so Alteon decided to just bag it and handle it
1648 * via autonegotiation.
1650 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1651 ifmedia_add(&sc->ifmedia,
1652 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1653 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1654 ifmedia_add(&sc->ifmedia,
1655 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1656 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL);
1657 ifmedia_add(&sc->ifmedia,
1658 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL);
1660 /* Fiber cards don't support 10/100 modes. */
1661 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1662 ifmedia_add(&sc->ifmedia,
1663 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1665 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1666 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1669 * Call MI attach routine.
1671 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1677 mtx_destroy(&sc->ti_mtx);
1681 static int ti_detach(dev)
1684 struct ti_softc *sc;
1688 sc = device_get_softc(dev);
1690 ifp = &sc->arpcom.ac_if;
1692 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1695 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1696 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1697 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1699 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1700 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1701 ifmedia_removeall(&sc->ifmedia);
1704 mtx_destroy(&sc->ti_mtx);
1710 * Frame reception handling. This is called if there's a frame
1711 * on the receive return list.
1713 * Note: we have to be able to handle three possibilities here:
1714 * 1) the frame is from the mini receive ring (can only happen)
1715 * on Tigon 2 boards)
1716 * 2) the frame is from the jumbo recieve ring
1717 * 3) the frame is from the standard receive ring
1720 static void ti_rxeof(sc)
1721 struct ti_softc *sc;
1724 struct ti_cmd_desc cmd;
1726 ifp = &sc->arpcom.ac_if;
1728 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1729 struct ti_rx_desc *cur_rx;
1731 struct ether_header *eh;
1732 struct mbuf *m = NULL;
1733 u_int16_t vlan_tag = 0;
1737 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1738 rxidx = cur_rx->ti_idx;
1739 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1741 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1743 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1746 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1747 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1748 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1749 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1750 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1752 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1755 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1757 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1760 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1761 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1762 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1763 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1764 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1766 ti_newbuf_mini(sc, sc->ti_mini, m);
1769 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1771 ti_newbuf_mini(sc, sc->ti_mini, m);
1775 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1776 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1777 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1778 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1780 ti_newbuf_std(sc, sc->ti_std, m);
1783 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1785 ti_newbuf_std(sc, sc->ti_std, m);
1790 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1792 eh = mtod(m, struct ether_header *);
1793 m->m_pkthdr.rcvif = ifp;
1795 /* Remove header from mbuf and pass it on. */
1796 m_adj(m, sizeof(struct ether_header));
1798 if (ifp->if_hwassist) {
1799 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1801 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1802 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1803 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1807 * If we received a packet with a vlan tag, pass it
1808 * to vlan_input() instead of ether_input().
1811 VLAN_INPUT_TAG(ifp, eh, m, vlan_tag);
1812 have_tag = vlan_tag = 0;
1815 ether_input(ifp, eh, m);
1818 /* Only necessary on the Tigon 1. */
1819 if (sc->ti_hwrev == TI_HWREV_TIGON)
1820 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1821 sc->ti_rx_saved_considx);
1823 TI_UPDATE_STDPROD(sc, sc->ti_std);
1824 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1825 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1830 static void ti_txeof(sc)
1831 struct ti_softc *sc;
1833 struct ti_tx_desc *cur_tx = NULL;
1836 ifp = &sc->arpcom.ac_if;
1839 * Go through our tx ring and free mbufs for those
1840 * frames that have been sent.
1842 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1845 idx = sc->ti_tx_saved_considx;
1846 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1848 CSR_WRITE_4(sc, TI_WINBASE,
1849 TI_TX_RING_BASE + 6144);
1851 CSR_WRITE_4(sc, TI_WINBASE,
1852 TI_TX_RING_BASE + 4096);
1854 CSR_WRITE_4(sc, TI_WINBASE,
1855 TI_TX_RING_BASE + 2048);
1857 CSR_WRITE_4(sc, TI_WINBASE,
1859 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1861 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1862 if (cur_tx->ti_flags & TI_BDFLAG_END)
1864 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1865 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1866 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1869 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1874 ifp->if_flags &= ~IFF_OACTIVE;
1879 static void ti_intr(xsc)
1882 struct ti_softc *sc;
1887 ifp = &sc->arpcom.ac_if;
1890 /* Avoid this for now -- checking this register is expensive. */
1891 /* Make sure this is really our interrupt. */
1892 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
1898 /* Ack interrupt and stop others from occuring. */
1899 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1901 if (ifp->if_flags & IFF_RUNNING) {
1902 /* Check RX return ring producer/consumer */
1905 /* Check TX ring producer/consumer */
1909 ti_handle_events(sc);
1911 /* Re-enable interrupts. */
1912 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1914 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1922 static void ti_stats_update(sc)
1923 struct ti_softc *sc;
1927 ifp = &sc->arpcom.ac_if;
1929 ifp->if_collisions +=
1930 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
1931 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
1932 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
1933 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
1940 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1941 * pointers to descriptors.
1943 static int ti_encap(sc, m_head, txidx)
1944 struct ti_softc *sc;
1945 struct mbuf *m_head;
1948 struct ti_tx_desc *f = NULL;
1950 u_int32_t frag, cur, cnt = 0;
1951 u_int16_t csum_flags = 0;
1952 struct ifvlan *ifv = NULL;
1954 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1955 m_head->m_pkthdr.rcvif != NULL &&
1956 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1957 ifv = m_head->m_pkthdr.rcvif->if_softc;
1960 cur = frag = *txidx;
1962 if (m_head->m_pkthdr.csum_flags) {
1963 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1964 csum_flags |= TI_BDFLAG_IP_CKSUM;
1965 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1966 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
1967 if (m_head->m_flags & M_LASTFRAG)
1968 csum_flags |= TI_BDFLAG_IP_FRAG_END;
1969 else if (m_head->m_flags & M_FRAG)
1970 csum_flags |= TI_BDFLAG_IP_FRAG;
1973 * Start packing the mbufs in this chain into
1974 * the fragment pointers. Stop when we run out
1975 * of fragments or hit the end of the mbuf chain.
1977 for (m = m_head; m != NULL; m = m->m_next) {
1978 if (m->m_len != 0) {
1979 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1981 CSR_WRITE_4(sc, TI_WINBASE,
1982 TI_TX_RING_BASE + 6144);
1983 else if (frag > 255)
1984 CSR_WRITE_4(sc, TI_WINBASE,
1985 TI_TX_RING_BASE + 4096);
1986 else if (frag > 127)
1987 CSR_WRITE_4(sc, TI_WINBASE,
1988 TI_TX_RING_BASE + 2048);
1990 CSR_WRITE_4(sc, TI_WINBASE,
1992 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
1994 f = &sc->ti_rdata->ti_tx_ring[frag];
1995 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
1997 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
1998 f->ti_len = m->m_len;
1999 f->ti_flags = csum_flags;
2002 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2003 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
2009 * Sanity check: avoid coming within 16 descriptors
2010 * of the end of the ring.
2012 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2015 TI_INC(frag, TI_TX_RING_CNT);
2023 if (frag == sc->ti_tx_saved_considx)
2026 if (sc->ti_hwrev == TI_HWREV_TIGON)
2027 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2030 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2031 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2032 sc->ti_txcnt += cnt;
2040 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2041 * to the mbuf data regions directly in the transmit descriptors.
2043 static void ti_start(ifp)
2046 struct ti_softc *sc;
2047 struct mbuf *m_head = NULL;
2048 u_int32_t prodidx = 0;
2053 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2055 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2056 IF_DEQUEUE(&ifp->if_snd, m_head);
2062 * safety overkill. If this is a fragmented packet chain
2063 * with delayed TCP/UDP checksums, then only encapsulate
2064 * it if we have enough descriptors to handle the entire
2066 * (paranoia -- may not actually be needed)
2068 if (m_head->m_flags & M_FIRSTFRAG &&
2069 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2070 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2071 m_head->m_pkthdr.csum_data + 16) {
2072 IF_PREPEND(&ifp->if_snd, m_head);
2073 ifp->if_flags |= IFF_OACTIVE;
2079 * Pack the data into the transmit ring. If we
2080 * don't have room, set the OACTIVE flag and wait
2081 * for the NIC to drain the ring.
2083 if (ti_encap(sc, m_head, &prodidx)) {
2084 IF_PREPEND(&ifp->if_snd, m_head);
2085 ifp->if_flags |= IFF_OACTIVE;
2090 * If there's a BPF listener, bounce a copy of this frame
2094 bpf_mtap(ifp, m_head);
2098 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2101 * Set a timeout in case the chip goes out to lunch.
2109 static void ti_init(xsc)
2112 struct ti_softc *sc = xsc;
2114 /* Cancel pending I/O and flush buffers. */
2118 /* Init the gen info block, ring control blocks and firmware. */
2119 if (ti_gibinit(sc)) {
2120 printf("ti%d: initialization failure\n", sc->ti_unit);
2130 static void ti_init2(sc)
2131 struct ti_softc *sc;
2133 struct ti_cmd_desc cmd;
2136 struct ifmedia *ifm;
2139 ifp = &sc->arpcom.ac_if;
2141 /* Specify MTU and interface index. */
2142 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit);
2143 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2144 ETHER_HDR_LEN + ETHER_CRC_LEN);
2145 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2147 /* Load our MAC address. */
2148 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2149 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2150 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2151 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2153 /* Enable or disable promiscuous mode as needed. */
2154 if (ifp->if_flags & IFF_PROMISC) {
2155 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2157 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2160 /* Program multicast filter. */
2164 * If this is a Tigon 1, we should tell the
2165 * firmware to use software packet filtering.
2167 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2168 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2172 ti_init_rx_ring_std(sc);
2174 /* Init jumbo RX ring. */
2175 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2176 ti_init_rx_ring_jumbo(sc);
2179 * If this is a Tigon 2, we can also configure the
2182 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2183 ti_init_rx_ring_mini(sc);
2185 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2186 sc->ti_rx_saved_considx = 0;
2189 ti_init_tx_ring(sc);
2191 /* Tell firmware we're alive. */
2192 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2194 /* Enable host interrupts. */
2195 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2197 ifp->if_flags |= IFF_RUNNING;
2198 ifp->if_flags &= ~IFF_OACTIVE;
2201 * Make sure to set media properly. We have to do this
2202 * here since we have to issue commands in order to set
2203 * the link negotiation and we can't issue commands until
2204 * the firmware is running.
2207 tmp = ifm->ifm_media;
2208 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2209 ti_ifmedia_upd(ifp);
2210 ifm->ifm_media = tmp;
2216 * Set media options.
2218 static int ti_ifmedia_upd(ifp)
2221 struct ti_softc *sc;
2222 struct ifmedia *ifm;
2223 struct ti_cmd_desc cmd;
2228 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2231 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2233 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2234 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2235 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2236 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2237 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2238 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2239 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2240 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2244 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2245 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2246 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2247 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2248 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2250 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2251 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2257 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2258 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2259 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2260 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2261 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2263 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2265 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2266 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2268 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2270 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2271 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2279 * Report current media status.
2281 static void ti_ifmedia_sts(ifp, ifmr)
2283 struct ifmediareq *ifmr;
2285 struct ti_softc *sc;
2286 u_int32_t media = 0;
2290 ifmr->ifm_status = IFM_AVALID;
2291 ifmr->ifm_active = IFM_ETHER;
2293 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2296 ifmr->ifm_status |= IFM_ACTIVE;
2298 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2299 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2301 ifmr->ifm_active |= IFM_1000_TX;
2303 ifmr->ifm_active |= IFM_1000_SX;
2304 if (media & TI_GLNK_FULL_DUPLEX)
2305 ifmr->ifm_active |= IFM_FDX;
2307 ifmr->ifm_active |= IFM_HDX;
2308 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2309 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2310 if (sc->ti_copper) {
2311 if (media & TI_LNK_100MB)
2312 ifmr->ifm_active |= IFM_100_TX;
2313 if (media & TI_LNK_10MB)
2314 ifmr->ifm_active |= IFM_10_T;
2316 if (media & TI_LNK_100MB)
2317 ifmr->ifm_active |= IFM_100_FX;
2318 if (media & TI_LNK_10MB)
2319 ifmr->ifm_active |= IFM_10_FL;
2321 if (media & TI_LNK_FULL_DUPLEX)
2322 ifmr->ifm_active |= IFM_FDX;
2323 if (media & TI_LNK_HALF_DUPLEX)
2324 ifmr->ifm_active |= IFM_HDX;
2330 static int ti_ioctl(ifp, command, data)
2335 struct ti_softc *sc = ifp->if_softc;
2336 struct ifreq *ifr = (struct ifreq *) data;
2337 int mask, error = 0;
2338 struct ti_cmd_desc cmd;
2345 error = ether_ioctl(ifp, command, data);
2348 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2351 ifp->if_mtu = ifr->ifr_mtu;
2356 if (ifp->if_flags & IFF_UP) {
2358 * If only the state of the PROMISC flag changed,
2359 * then just use the 'set promisc mode' command
2360 * instead of reinitializing the entire NIC. Doing
2361 * a full re-init means reloading the firmware and
2362 * waiting for it to start up, which may take a
2365 if (ifp->if_flags & IFF_RUNNING &&
2366 ifp->if_flags & IFF_PROMISC &&
2367 !(sc->ti_if_flags & IFF_PROMISC)) {
2368 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2369 TI_CMD_CODE_PROMISC_ENB, 0);
2370 } else if (ifp->if_flags & IFF_RUNNING &&
2371 !(ifp->if_flags & IFF_PROMISC) &&
2372 sc->ti_if_flags & IFF_PROMISC) {
2373 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2374 TI_CMD_CODE_PROMISC_DIS, 0);
2378 if (ifp->if_flags & IFF_RUNNING) {
2382 sc->ti_if_flags = ifp->if_flags;
2387 if (ifp->if_flags & IFF_RUNNING) {
2394 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2397 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2398 if (mask & IFCAP_HWCSUM) {
2399 if (IFCAP_HWCSUM & ifp->if_capenable)
2400 ifp->if_capenable &= ~IFCAP_HWCSUM;
2402 ifp->if_capenable |= IFCAP_HWCSUM;
2403 if (ifp->if_flags & IFF_RUNNING)
2418 static void ti_watchdog(ifp)
2421 struct ti_softc *sc;
2426 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2437 * Stop the adapter and free any mbufs allocated to the
2440 static void ti_stop(sc)
2441 struct ti_softc *sc;
2444 struct ti_cmd_desc cmd;
2448 ifp = &sc->arpcom.ac_if;
2450 /* Disable host interrupts. */
2451 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2453 * Tell firmware we're shutting down.
2455 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2457 /* Halt and reinitialize. */
2459 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2462 /* Free the RX lists. */
2463 ti_free_rx_ring_std(sc);
2465 /* Free jumbo RX list. */
2466 ti_free_rx_ring_jumbo(sc);
2468 /* Free mini RX list. */
2469 ti_free_rx_ring_mini(sc);
2471 /* Free TX buffers. */
2472 ti_free_tx_ring(sc);
2474 sc->ti_ev_prodidx.ti_idx = 0;
2475 sc->ti_return_prodidx.ti_idx = 0;
2476 sc->ti_tx_considx.ti_idx = 0;
2477 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2479 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2486 * Stop all chip I/O so that the kernel's probe routines don't
2487 * get confused by errant DMAs when rebooting.
2489 static void ti_shutdown(dev)
2492 struct ti_softc *sc;
2494 sc = device_get_softc(dev);