2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
37 * Manuals, sample driver and firmware source kits are available
38 * from http://www.alteon.com/support/openkits.
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Electrical Engineering Department
42 * Columbia University, New York City
46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
50 * filtering and jumbo (9014 byte) frames. The hardware is largely
51 * controlled by firmware, which must be loaded into the NIC during
54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
55 * revision, which supports new features such as extended commands,
56 * extended jumbo receive ring desciptors and a mini receive ring.
58 * Alteon Networks is to be commended for releasing such a vast amount
59 * of development material for the Tigon NIC without requiring an NDA
60 * (although they really should have done it a long time ago). With
61 * any luck, the other vendors will finally wise up and follow Alteon's
64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
65 * this driver by #including it as a C header file. This bloats the
66 * driver somewhat, but it's the easiest method considering that the
67 * driver code and firmware code need to be kept in sync. The source
68 * for the firmware is not provided with the FreeBSD distribution since
69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
71 * The following people deserve special thanks:
72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
74 * - Raymond Lee of Netgear, for providing a pair of Netgear
75 * GA620 Tigon 2 boards for testing
76 * - Ulf Zimmermann, for bringing the GA260 to my attention and
77 * convincing me to write this driver.
78 * - Andrew Gallatin for providing FreeBSD/Alpha support.
83 #include <sys/param.h>
84 #include <sys/systm.h>
85 #include <sys/sockio.h>
87 #include <sys/malloc.h>
88 #include <sys/kernel.h>
89 #include <sys/socket.h>
90 #include <sys/queue.h>
93 #include <net/if_arp.h>
94 #include <net/ethernet.h>
95 #include <net/if_dl.h>
96 #include <net/if_media.h>
101 #include <net/if_types.h>
102 #include <net/if_vlan_var.h>
105 #include <netinet/in_systm.h>
106 #include <netinet/in.h>
107 #include <netinet/ip.h>
109 #include <vm/vm.h> /* for vtophys */
110 #include <vm/pmap.h> /* for vtophys */
111 #include <machine/bus_memio.h>
112 #include <machine/bus.h>
113 #include <machine/resource.h>
115 #include <sys/rman.h>
117 #include <pci/pcireg.h>
118 #include <pci/pcivar.h>
120 #include <pci/if_tireg.h>
121 #include <pci/ti_fw.h>
122 #include <pci/ti_fw2.h>
124 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
127 static const char rcsid[] =
132 * Various supported device vendors/types and their names.
135 static struct ti_type ti_devs[] = {
136 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
137 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
138 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
139 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
140 { TC_VENDORID, TC_DEVICEID_3C985,
141 "3Com 3c985-SX Gigabit Ethernet" },
142 { NG_VENDORID, NG_DEVICEID_GA620,
143 "Netgear GA620 1000baseSX Gigabit Ethernet" },
144 { NG_VENDORID, NG_DEVICEID_GA620T,
145 "Netgear GA620 1000baseT Gigabit Ethernet" },
146 { SGI_VENDORID, SGI_DEVICEID_TIGON,
147 "Silicon Graphics Gigabit Ethernet" },
148 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
149 "Farallon PN9000SX Gigabit Ethernet" },
153 static int ti_probe __P((device_t));
154 static int ti_attach __P((device_t));
155 static int ti_detach __P((device_t));
156 static void ti_txeof __P((struct ti_softc *));
157 static void ti_rxeof __P((struct ti_softc *));
159 static void ti_stats_update __P((struct ti_softc *));
160 static int ti_encap __P((struct ti_softc *, struct mbuf *,
163 static void ti_intr __P((void *));
164 static void ti_start __P((struct ifnet *));
165 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t));
166 static void ti_init __P((void *));
167 static void ti_init2 __P((struct ti_softc *));
168 static void ti_stop __P((struct ti_softc *));
169 static void ti_watchdog __P((struct ifnet *));
170 static void ti_shutdown __P((device_t));
171 static int ti_ifmedia_upd __P((struct ifnet *));
172 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
174 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int));
175 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *,
177 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int));
179 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *));
180 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *));
181 static void ti_setmulti __P((struct ti_softc *));
183 static void ti_mem __P((struct ti_softc *, u_int32_t,
184 u_int32_t, caddr_t));
185 static void ti_loadfw __P((struct ti_softc *));
186 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *));
187 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *,
189 static void ti_handle_events __P((struct ti_softc *));
190 static int ti_alloc_jumbo_mem __P((struct ti_softc *));
191 static void *ti_jalloc __P((struct ti_softc *));
192 static void ti_jfree __P((caddr_t, void *));
193 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *));
194 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *));
195 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *));
196 static int ti_init_rx_ring_std __P((struct ti_softc *));
197 static void ti_free_rx_ring_std __P((struct ti_softc *));
198 static int ti_init_rx_ring_jumbo __P((struct ti_softc *));
199 static void ti_free_rx_ring_jumbo __P((struct ti_softc *));
200 static int ti_init_rx_ring_mini __P((struct ti_softc *));
201 static void ti_free_rx_ring_mini __P((struct ti_softc *));
202 static void ti_free_tx_ring __P((struct ti_softc *));
203 static int ti_init_tx_ring __P((struct ti_softc *));
205 static int ti_64bitslot_war __P((struct ti_softc *));
206 static int ti_chipinit __P((struct ti_softc *));
207 static int ti_gibinit __P((struct ti_softc *));
209 static device_method_t ti_methods[] = {
210 /* Device interface */
211 DEVMETHOD(device_probe, ti_probe),
212 DEVMETHOD(device_attach, ti_attach),
213 DEVMETHOD(device_detach, ti_detach),
214 DEVMETHOD(device_shutdown, ti_shutdown),
218 static driver_t ti_driver = {
221 sizeof(struct ti_softc)
224 static devclass_t ti_devclass;
226 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
229 * Send an instruction or address to the EEPROM, check for ACK.
231 static u_int32_t ti_eeprom_putbyte(sc, byte)
235 register int i, ack = 0;
238 * Make sure we're in TX mode.
240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
243 * Feed in each bit and stobe the clock.
245 for (i = 0x80; i; i >>= 1) {
247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
252 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
254 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
260 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
265 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
266 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
267 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
273 * Read a byte of data stored in the EEPROM at address 'addr.'
274 * We have to send two address bytes since the EEPROM can hold
275 * more than 256 bytes of data.
277 static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
288 * Send write control code to EEPROM.
290 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
291 printf("ti%d: failed to send write command, status: %x\n",
292 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
297 * Send first byte of address of byte we want to read.
299 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
300 printf("ti%d: failed to send address, status: %x\n",
301 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
305 * Send second byte address of byte we want to read.
307 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
308 printf("ti%d: failed to send address, status: %x\n",
309 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
316 * Send read control code to EEPROM.
318 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
319 printf("ti%d: failed to send read command, status: %x\n",
320 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
325 * Start reading bits from EEPROM.
327 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
328 for (i = 0x80; i; i >>= 1) {
329 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
331 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
333 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
340 * No ACK generated for read, so just return byte.
349 * Read a sequence of bytes from the EEPROM.
351 static int ti_read_eeprom(sc, dest, off, cnt)
360 for (i = 0; i < cnt; i++) {
361 err = ti_eeprom_getbyte(sc, off + i, &byte);
371 * NIC memory access function. Can be used to either clear a section
372 * of NIC local memory or (if buf is non-NULL) copy data into it.
374 static void ti_mem(sc, addr, len, buf)
379 int segptr, segsize, cnt;
380 caddr_t ti_winbase, ptr;
384 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
391 segsize = TI_WINLEN - (segptr % TI_WINLEN);
392 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
394 bzero((char *)ti_winbase + (segptr &
395 (TI_WINLEN - 1)), segsize);
397 bcopy((char *)ptr, (char *)ti_winbase +
398 (segptr & (TI_WINLEN - 1)), segsize);
409 * Load firmware image into the NIC. Check that the firmware revision
410 * is acceptable and see if we want the firmware for the Tigon 1 or
413 static void ti_loadfw(sc)
416 switch(sc->ti_hwrev) {
418 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
419 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
420 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
421 printf("ti%d: firmware revision mismatch; want "
422 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
423 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
424 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
425 tigonFwReleaseMinor, tigonFwReleaseFix);
428 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
429 (caddr_t)tigonFwText);
430 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
431 (caddr_t)tigonFwData);
432 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
433 (caddr_t)tigonFwRodata);
434 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
435 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
436 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
438 case TI_HWREV_TIGON_II:
439 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
440 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
441 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
442 printf("ti%d: firmware revision mismatch; want "
443 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
444 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
445 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
446 tigon2FwReleaseMinor, tigon2FwReleaseFix);
449 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
450 (caddr_t)tigon2FwText);
451 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
452 (caddr_t)tigon2FwData);
453 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
454 (caddr_t)tigon2FwRodata);
455 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
456 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
457 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
460 printf("ti%d: can't load firmware: unknown hardware rev\n",
469 * Send the NIC a command via the command ring.
471 static void ti_cmd(sc, cmd)
473 struct ti_cmd_desc *cmd;
477 if (sc->ti_rdata->ti_cmd_ring == NULL)
480 index = sc->ti_cmd_saved_prodidx;
481 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
482 TI_INC(index, TI_CMD_RING_CNT);
483 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
484 sc->ti_cmd_saved_prodidx = index;
490 * Send the NIC an extended command. The 'len' parameter specifies the
491 * number of command slots to include after the initial command.
493 static void ti_cmd_ext(sc, cmd, arg, len)
495 struct ti_cmd_desc *cmd;
502 if (sc->ti_rdata->ti_cmd_ring == NULL)
505 index = sc->ti_cmd_saved_prodidx;
506 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
507 TI_INC(index, TI_CMD_RING_CNT);
508 for (i = 0; i < len; i++) {
509 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
510 *(u_int32_t *)(&arg[i * 4]));
511 TI_INC(index, TI_CMD_RING_CNT);
513 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
514 sc->ti_cmd_saved_prodidx = index;
520 * Handle events that have triggered interrupts.
522 static void ti_handle_events(sc)
525 struct ti_event_desc *e;
527 if (sc->ti_rdata->ti_event_ring == NULL)
530 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
531 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
532 switch(e->ti_event) {
533 case TI_EV_LINKSTAT_CHANGED:
534 sc->ti_linkstat = e->ti_code;
535 if (e->ti_code == TI_EV_CODE_LINK_UP)
536 printf("ti%d: 10/100 link up\n", sc->ti_unit);
537 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
538 printf("ti%d: gigabit link up\n", sc->ti_unit);
539 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
540 printf("ti%d: link down\n", sc->ti_unit);
543 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
544 printf("ti%d: invalid command\n", sc->ti_unit);
545 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
546 printf("ti%d: unknown command\n", sc->ti_unit);
547 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
548 printf("ti%d: bad config data\n", sc->ti_unit);
550 case TI_EV_FIRMWARE_UP:
553 case TI_EV_STATS_UPDATED:
556 case TI_EV_RESET_JUMBO_RING:
557 case TI_EV_MCAST_UPDATED:
561 printf("ti%d: unknown event: %d\n",
562 sc->ti_unit, e->ti_event);
565 /* Advance the consumer index. */
566 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
567 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
574 * Memory management for the jumbo receive ring is a pain in the
575 * butt. We need to allocate at least 9018 bytes of space per frame,
576 * _and_ it has to be contiguous (unless you use the extended
577 * jumbo descriptor format). Using malloc() all the time won't
578 * work: malloc() allocates memory in powers of two, which means we
579 * would end up wasting a considerable amount of space by allocating
580 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
581 * to do our own memory management.
583 * The driver needs to allocate a contiguous chunk of memory at boot
584 * time. We then chop this up ourselves into 9K pieces and use them
585 * as external mbuf storage.
587 * One issue here is how much memory to allocate. The jumbo ring has
588 * 256 slots in it, but at 9K per slot than can consume over 2MB of
589 * RAM. This is a bit much, especially considering we also need
590 * RAM for the standard ring and mini ring (on the Tigon 2). To
591 * save space, we only actually allocate enough memory for 64 slots
592 * by default, which works out to between 500 and 600K. This can
593 * be tuned by changing a #define in if_tireg.h.
596 static int ti_alloc_jumbo_mem(sc)
601 struct ti_jpool_entry *entry;
603 /* Grab a big chunk o' storage. */
604 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
605 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
607 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
608 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
612 SLIST_INIT(&sc->ti_jfree_listhead);
613 SLIST_INIT(&sc->ti_jinuse_listhead);
616 * Now divide it up into 9K pieces and save the addresses
619 ptr = sc->ti_cdata.ti_jumbo_buf;
620 for (i = 0; i < TI_JSLOTS; i++) {
621 sc->ti_cdata.ti_jslots[i] = ptr;
623 entry = malloc(sizeof(struct ti_jpool_entry),
626 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
628 sc->ti_cdata.ti_jumbo_buf = NULL;
629 printf("ti%d: no memory for jumbo "
630 "buffer queue!\n", sc->ti_unit);
634 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
641 * Allocate a jumbo buffer.
643 static void *ti_jalloc(sc)
646 struct ti_jpool_entry *entry;
648 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
651 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
655 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
656 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
657 return(sc->ti_cdata.ti_jslots[entry->slot]);
661 * Release a jumbo buffer.
663 static void ti_jfree(buf, args)
669 struct ti_jpool_entry *entry;
671 /* Extract the softc struct pointer. */
672 sc = (struct ti_softc *)args;
675 panic("ti_jfree: didn't get softc pointer!");
677 /* calculate the slot this buffer belongs to */
678 i = ((vm_offset_t)buf
679 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
681 if ((i < 0) || (i >= TI_JSLOTS))
682 panic("ti_jfree: asked to free buffer that we don't manage!");
684 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
686 panic("ti_jfree: buffer not in use!");
688 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
689 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
696 * Intialize a standard receive ring descriptor.
698 static int ti_newbuf_std(sc, i, m)
703 struct mbuf *m_new = NULL;
704 struct ti_rx_desc *r;
707 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
709 printf("ti%d: mbuf allocation failed "
710 "-- packet dropped!\n", sc->ti_unit);
714 MCLGET(m_new, M_DONTWAIT);
715 if (!(m_new->m_flags & M_EXT)) {
716 printf("ti%d: cluster allocation failed "
717 "-- packet dropped!\n", sc->ti_unit);
721 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
724 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
725 m_new->m_data = m_new->m_ext.ext_buf;
728 m_adj(m_new, ETHER_ALIGN);
729 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
730 r = &sc->ti_rdata->ti_rx_std_ring[i];
731 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
732 r->ti_type = TI_BDTYPE_RECV_BD;
734 if (sc->arpcom.ac_if.if_hwassist)
735 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
736 r->ti_len = m_new->m_len;
743 * Intialize a mini receive ring descriptor. This only applies to
746 static int ti_newbuf_mini(sc, i, m)
751 struct mbuf *m_new = NULL;
752 struct ti_rx_desc *r;
755 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
757 printf("ti%d: mbuf allocation failed "
758 "-- packet dropped!\n", sc->ti_unit);
761 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
764 m_new->m_data = m_new->m_pktdat;
765 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
768 m_adj(m_new, ETHER_ALIGN);
769 r = &sc->ti_rdata->ti_rx_mini_ring[i];
770 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
771 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
772 r->ti_type = TI_BDTYPE_RECV_BD;
773 r->ti_flags = TI_BDFLAG_MINI_RING;
774 if (sc->arpcom.ac_if.if_hwassist)
775 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
776 r->ti_len = m_new->m_len;
783 * Initialize a jumbo receive ring descriptor. This allocates
784 * a jumbo buffer from the pool managed internally by the driver.
786 static int ti_newbuf_jumbo(sc, i, m)
791 struct mbuf *m_new = NULL;
792 struct ti_rx_desc *r;
797 /* Allocate the mbuf. */
798 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
800 printf("ti%d: mbuf allocation failed "
801 "-- packet dropped!\n", sc->ti_unit);
805 /* Allocate the jumbo buffer */
809 printf("ti%d: jumbo allocation failed "
810 "-- packet dropped!\n", sc->ti_unit);
814 /* Attach the buffer to the mbuf. */
815 m_new->m_data = (void *) buf;
816 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
817 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
818 (struct ti_softc *)sc, 0, EXT_NET_DRV);
821 m_new->m_data = m_new->m_ext.ext_buf;
822 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
825 m_adj(m_new, ETHER_ALIGN);
826 /* Set up the descriptor. */
827 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
828 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
829 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
830 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
831 r->ti_flags = TI_BDFLAG_JUMBO_RING;
832 if (sc->arpcom.ac_if.if_hwassist)
833 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
834 r->ti_len = m_new->m_len;
841 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
842 * that's 1MB or memory, which is a lot. For now, we fill only the first
843 * 256 ring entries and hope that our CPU is fast enough to keep up with
846 static int ti_init_rx_ring_std(sc)
850 struct ti_cmd_desc cmd;
852 for (i = 0; i < TI_SSLOTS; i++) {
853 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
857 TI_UPDATE_STDPROD(sc, i - 1);
863 static void ti_free_rx_ring_std(sc)
868 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
869 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
870 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
871 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
873 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
874 sizeof(struct ti_rx_desc));
880 static int ti_init_rx_ring_jumbo(sc)
884 struct ti_cmd_desc cmd;
886 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
887 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
891 TI_UPDATE_JUMBOPROD(sc, i - 1);
892 sc->ti_jumbo = i - 1;
897 static void ti_free_rx_ring_jumbo(sc)
902 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
903 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
904 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
905 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
907 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
908 sizeof(struct ti_rx_desc));
914 static int ti_init_rx_ring_mini(sc)
919 for (i = 0; i < TI_MSLOTS; i++) {
920 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
924 TI_UPDATE_MINIPROD(sc, i - 1);
930 static void ti_free_rx_ring_mini(sc)
935 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
936 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
937 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
938 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
940 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
941 sizeof(struct ti_rx_desc));
947 static void ti_free_tx_ring(sc)
952 if (sc->ti_rdata->ti_tx_ring == NULL)
955 for (i = 0; i < TI_TX_RING_CNT; i++) {
956 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
957 m_freem(sc->ti_cdata.ti_tx_chain[i]);
958 sc->ti_cdata.ti_tx_chain[i] = NULL;
960 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
961 sizeof(struct ti_tx_desc));
967 static int ti_init_tx_ring(sc)
971 sc->ti_tx_saved_considx = 0;
972 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
977 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
978 * but we have to support the old way too so that Tigon 1 cards will
981 void ti_add_mcast(sc, addr)
983 struct ether_addr *addr;
985 struct ti_cmd_desc cmd;
987 u_int32_t ext[2] = {0, 0};
989 m = (u_int16_t *)&addr->octet[0];
991 switch(sc->ti_hwrev) {
993 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
994 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
995 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
997 case TI_HWREV_TIGON_II:
998 ext[0] = htons(m[0]);
999 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1000 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1003 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1010 void ti_del_mcast(sc, addr)
1011 struct ti_softc *sc;
1012 struct ether_addr *addr;
1014 struct ti_cmd_desc cmd;
1016 u_int32_t ext[2] = {0, 0};
1018 m = (u_int16_t *)&addr->octet[0];
1020 switch(sc->ti_hwrev) {
1021 case TI_HWREV_TIGON:
1022 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1023 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1024 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1026 case TI_HWREV_TIGON_II:
1027 ext[0] = htons(m[0]);
1028 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1029 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1032 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1040 * Configure the Tigon's multicast address filter.
1042 * The actual multicast table management is a bit of a pain, thanks to
1043 * slight brain damage on the part of both Alteon and us. With our
1044 * multicast code, we are only alerted when the multicast address table
1045 * changes and at that point we only have the current list of addresses:
1046 * we only know the current state, not the previous state, so we don't
1047 * actually know what addresses were removed or added. The firmware has
1048 * state, but we can't get our grubby mits on it, and there is no 'delete
1049 * all multicast addresses' command. Hence, we have to maintain our own
1050 * state so we know what addresses have been programmed into the NIC at
1053 static void ti_setmulti(sc)
1054 struct ti_softc *sc;
1057 struct ifmultiaddr *ifma;
1058 struct ti_cmd_desc cmd;
1059 struct ti_mc_entry *mc;
1062 ifp = &sc->arpcom.ac_if;
1064 if (ifp->if_flags & IFF_ALLMULTI) {
1065 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1068 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1071 /* Disable interrupts. */
1072 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1073 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1075 /* First, zot all the existing filters. */
1076 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1077 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1078 ti_del_mcast(sc, &mc->mc_addr);
1079 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1083 /* Now program new ones. */
1084 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1085 if (ifma->ifma_addr->sa_family != AF_LINK)
1087 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1088 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1089 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1090 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1091 ti_add_mcast(sc, &mc->mc_addr);
1094 /* Re-enable interrupts. */
1095 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1101 * Check to see if the BIOS has configured us for a 64 bit slot when
1102 * we aren't actually in one. If we detect this condition, we can work
1103 * around it on the Tigon 2 by setting a bit in the PCI state register,
1104 * but for the Tigon 1 we must give up and abort the interface attach.
1106 static int ti_64bitslot_war(sc)
1107 struct ti_softc *sc;
1109 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1110 CSR_WRITE_4(sc, 0x600, 0);
1111 CSR_WRITE_4(sc, 0x604, 0);
1112 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1113 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1114 if (sc->ti_hwrev == TI_HWREV_TIGON)
1117 TI_SETBIT(sc, TI_PCI_STATE,
1118 TI_PCISTATE_32BIT_BUS);
1128 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1129 * self-test results.
1131 static int ti_chipinit(sc)
1132 struct ti_softc *sc;
1134 u_int32_t cacheline;
1135 u_int32_t pci_writemax = 0;
1137 /* Initialize link to down state. */
1138 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1140 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1142 /* Set endianness before we access any non-PCI registers. */
1143 #if BYTE_ORDER == BIG_ENDIAN
1144 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1145 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1147 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1148 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1151 /* Check the ROM failed bit to see if self-tests passed. */
1152 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1153 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1158 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1160 /* Figure out the hardware revision. */
1161 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1162 case TI_REV_TIGON_I:
1163 sc->ti_hwrev = TI_HWREV_TIGON;
1165 case TI_REV_TIGON_II:
1166 sc->ti_hwrev = TI_HWREV_TIGON_II;
1169 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1173 /* Do special setup for Tigon 2. */
1174 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1175 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1176 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1177 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1180 /* Set up the PCI state register. */
1181 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1182 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1183 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1186 /* Clear the read/write max DMA parameters. */
1187 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1188 TI_PCISTATE_READ_MAXDMA));
1190 /* Get cache line size. */
1191 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1194 * If the system has set enabled the PCI memory write
1195 * and invalidate command in the command register, set
1196 * the write max parameter accordingly. This is necessary
1197 * to use MWI with the Tigon 2.
1199 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1209 /* Disable PCI memory write and invalidate. */
1211 printf("ti%d: cache line size %d not "
1212 "supported; disabling PCI MWI\n",
1213 sc->ti_unit, cacheline);
1214 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1215 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1220 #ifdef __brokenalpha__
1222 * From the Alteon sample driver:
1223 * Must insure that we do not cross an 8K (bytes) boundary
1224 * for DMA reads. Our highest limit is 1K bytes. This is a
1225 * restriction on some ALPHA platforms with early revision
1226 * 21174 PCI chipsets, such as the AlphaPC 164lx
1228 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1230 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1233 /* This sets the min dma param all the way up (0xff). */
1234 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1236 /* Configure DMA variables. */
1237 #if BYTE_ORDER == BIG_ENDIAN
1238 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1239 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1240 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1241 TI_OPMODE_DONT_FRAG_JUMBO);
1243 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1244 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1245 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1249 * Only allow 1 DMA channel to be active at a time.
1250 * I don't think this is a good idea, but without it
1251 * the firmware racks up lots of nicDmaReadRingFull
1252 * errors. This is not compatible with hardware checksums.
1254 if (sc->arpcom.ac_if.if_hwassist == 0)
1255 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1257 /* Recommended settings from Tigon manual. */
1258 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1259 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1261 if (ti_64bitslot_war(sc)) {
1262 printf("ti%d: bios thinks we're in a 64 bit slot, "
1263 "but we aren't", sc->ti_unit);
1271 * Initialize the general information block and firmware, and
1272 * start the CPU(s) running.
1274 static int ti_gibinit(sc)
1275 struct ti_softc *sc;
1281 ifp = &sc->arpcom.ac_if;
1283 /* Disable interrupts for now. */
1284 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1286 /* Tell the chip where to find the general information block. */
1287 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1288 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1290 /* Load the firmware into SRAM. */
1293 /* Set up the contents of the general info and ring control blocks. */
1295 /* Set up the event ring and producer pointer. */
1296 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1298 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1300 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1301 vtophys(&sc->ti_ev_prodidx);
1302 sc->ti_ev_prodidx.ti_idx = 0;
1303 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1304 sc->ti_ev_saved_considx = 0;
1306 /* Set up the command ring and producer mailbox. */
1307 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1309 sc->ti_rdata->ti_cmd_ring =
1310 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1311 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1313 rcb->ti_max_len = 0;
1314 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1315 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1317 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1318 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1319 sc->ti_cmd_saved_prodidx = 0;
1322 * Assign the address of the stats refresh buffer.
1323 * We re-use the current stats buffer for this to
1326 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1327 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1329 /* Set up the standard receive ring. */
1330 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1331 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1332 rcb->ti_max_len = TI_FRAMELEN;
1334 if (sc->arpcom.ac_if.if_hwassist)
1335 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1336 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1338 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1341 /* Set up the jumbo receive ring. */
1342 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1343 TI_HOSTADDR(rcb->ti_hostaddr) =
1344 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1345 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1347 if (sc->arpcom.ac_if.if_hwassist)
1348 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1349 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1351 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1355 * Set up the mini ring. Only activated on the
1356 * Tigon 2 but the slot in the config block is
1357 * still there on the Tigon 1.
1359 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1360 TI_HOSTADDR(rcb->ti_hostaddr) =
1361 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1362 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1363 if (sc->ti_hwrev == TI_HWREV_TIGON)
1364 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1367 if (sc->arpcom.ac_if.if_hwassist)
1368 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1369 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1371 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1375 * Set up the receive return ring.
1377 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1378 TI_HOSTADDR(rcb->ti_hostaddr) =
1379 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1381 rcb->ti_max_len = TI_RETURN_RING_CNT;
1382 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1383 vtophys(&sc->ti_return_prodidx);
1386 * Set up the tx ring. Note: for the Tigon 2, we have the option
1387 * of putting the transmit ring in the host's address space and
1388 * letting the chip DMA it instead of leaving the ring in the NIC's
1389 * memory and accessing it through the shared memory region. We
1390 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1391 * so we have to revert to the shared memory scheme if we detect
1394 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1395 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1396 sc->ti_rdata->ti_tx_ring_nic =
1397 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1399 bzero((char *)sc->ti_rdata->ti_tx_ring,
1400 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1401 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1402 if (sc->ti_hwrev == TI_HWREV_TIGON)
1405 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1407 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1409 if (sc->arpcom.ac_if.if_hwassist)
1410 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1411 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1412 rcb->ti_max_len = TI_TX_RING_CNT;
1413 if (sc->ti_hwrev == TI_HWREV_TIGON)
1414 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1416 TI_HOSTADDR(rcb->ti_hostaddr) =
1417 vtophys(&sc->ti_rdata->ti_tx_ring);
1418 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1419 vtophys(&sc->ti_tx_considx);
1421 /* Set up tuneables */
1422 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1423 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1424 (sc->ti_rx_coal_ticks / 10));
1426 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1427 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1428 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1429 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1430 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1431 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1433 /* Turn interrupts on. */
1434 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1435 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1438 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1444 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1445 * against our list and return its name if we find a match.
1447 static int ti_probe(dev)
1454 while(t->ti_name != NULL) {
1455 if ((pci_get_vendor(dev) == t->ti_vid) &&
1456 (pci_get_device(dev) == t->ti_did)) {
1457 device_set_desc(dev, t->ti_name);
1466 static int ti_attach(dev)
1471 struct ti_softc *sc;
1472 int unit, error = 0, rid;
1474 sc = device_get_softc(dev);
1475 unit = device_get_unit(dev);
1476 bzero(sc, sizeof(struct ti_softc));
1478 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
1482 * Map control/status registers.
1484 pci_enable_busmaster(dev);
1485 pci_enable_io(dev, SYS_RES_MEMORY);
1486 command = pci_read_config(dev, PCIR_COMMAND, 4);
1488 if (!(command & PCIM_CMD_MEMEN)) {
1489 printf("ti%d: failed to enable memory mapping!\n", unit);
1495 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1496 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE);
1498 if (sc->ti_res == NULL) {
1499 printf ("ti%d: couldn't map memory\n", unit);
1504 sc->ti_btag = rman_get_bustag(sc->ti_res);
1505 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1506 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1508 /* Allocate interrupt */
1511 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1512 RF_SHAREABLE | RF_ACTIVE);
1514 if (sc->ti_irq == NULL) {
1515 printf("ti%d: couldn't map interrupt\n", unit);
1520 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1521 ti_intr, sc, &sc->ti_intrhand);
1524 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1525 bus_release_resource(dev, SYS_RES_MEMORY,
1526 TI_PCI_LOMEM, sc->ti_res);
1527 printf("ti%d: couldn't set up irq\n", unit);
1533 if (ti_chipinit(sc)) {
1534 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1535 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1536 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1537 bus_release_resource(dev, SYS_RES_MEMORY,
1538 TI_PCI_LOMEM, sc->ti_res);
1543 /* Zero out the NIC's on-board SRAM. */
1544 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1546 /* Init again -- zeroing memory may have clobbered some registers. */
1547 if (ti_chipinit(sc)) {
1548 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1549 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1550 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1551 bus_release_resource(dev, SYS_RES_MEMORY,
1552 TI_PCI_LOMEM, sc->ti_res);
1558 * Get station address from the EEPROM. Note: the manual states
1559 * that the MAC address is at offset 0x8c, however the data is
1560 * stored as two longwords (since that's how it's loaded into
1561 * the NIC). This means the MAC address is actually preceded
1562 * by two zero bytes. We need to skip over those.
1564 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1565 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1566 printf("ti%d: failed to read station address\n", unit);
1567 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1568 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1569 bus_release_resource(dev, SYS_RES_MEMORY,
1570 TI_PCI_LOMEM, sc->ti_res);
1576 * A Tigon chip was detected. Inform the world.
1578 printf("ti%d: Ethernet address: %6D\n", unit,
1579 sc->arpcom.ac_enaddr, ":");
1581 /* Allocate the general information block and ring buffers. */
1582 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1583 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1585 if (sc->ti_rdata == NULL) {
1586 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1587 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1588 bus_release_resource(dev, SYS_RES_MEMORY,
1589 TI_PCI_LOMEM, sc->ti_res);
1591 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1595 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1597 /* Try to allocate memory for jumbo buffers. */
1598 if (ti_alloc_jumbo_mem(sc)) {
1599 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1600 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1601 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1602 bus_release_resource(dev, SYS_RES_MEMORY,
1603 TI_PCI_LOMEM, sc->ti_res);
1604 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data),
1611 * We really need a better way to tell a 1000baseTX card
1612 * from a 1000baseSX one, since in theory there could be
1613 * OEMed 1000baseTX cards from lame vendors who aren't
1614 * clever enough to change the PCI ID. For the moment
1615 * though, the AceNIC is the only copper card available.
1617 if (pci_get_vendor(dev) == ALT_VENDORID &&
1618 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1620 /* Ok, it's not the only copper card available. */
1621 if (pci_get_vendor(dev) == NG_VENDORID &&
1622 pci_get_device(dev) == NG_DEVICEID_GA620T)
1625 /* Set default tuneable values. */
1626 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1627 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1628 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1629 sc->ti_rx_max_coal_bds = 64;
1630 sc->ti_tx_max_coal_bds = 128;
1631 sc->ti_tx_buf_ratio = 21;
1633 /* Set up ifnet structure */
1634 ifp = &sc->arpcom.ac_if;
1636 ifp->if_unit = sc->ti_unit;
1637 ifp->if_name = "ti";
1638 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1639 ifp->if_ioctl = ti_ioctl;
1640 ifp->if_output = ether_output;
1641 ifp->if_start = ti_start;
1642 ifp->if_watchdog = ti_watchdog;
1643 ifp->if_init = ti_init;
1644 ifp->if_mtu = ETHERMTU;
1645 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
1647 /* Set up ifmedia support. */
1648 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1649 if (sc->ti_copper) {
1651 * Copper cards allow manual 10/100 mode selection,
1652 * but not manual 1000baseTX mode selection. Why?
1653 * Becuase currently there's no way to specify the
1654 * master/slave setting through the firmware interface,
1655 * so Alteon decided to just bag it and handle it
1656 * via autonegotiation.
1658 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1659 ifmedia_add(&sc->ifmedia,
1660 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1661 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1662 ifmedia_add(&sc->ifmedia,
1663 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1664 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL);
1665 ifmedia_add(&sc->ifmedia,
1666 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL);
1668 /* Fiber cards don't support 10/100 modes. */
1669 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1670 ifmedia_add(&sc->ifmedia,
1671 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1673 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1674 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1677 * Call MI attach routine.
1679 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1685 mtx_destroy(&sc->ti_mtx);
1689 static int ti_detach(dev)
1692 struct ti_softc *sc;
1696 sc = device_get_softc(dev);
1698 ifp = &sc->arpcom.ac_if;
1700 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1703 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1704 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1705 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1707 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1708 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1709 ifmedia_removeall(&sc->ifmedia);
1712 mtx_destroy(&sc->ti_mtx);
1718 * Frame reception handling. This is called if there's a frame
1719 * on the receive return list.
1721 * Note: we have to be able to handle three possibilities here:
1722 * 1) the frame is from the mini receive ring (can only happen)
1723 * on Tigon 2 boards)
1724 * 2) the frame is from the jumbo recieve ring
1725 * 3) the frame is from the standard receive ring
1728 static void ti_rxeof(sc)
1729 struct ti_softc *sc;
1732 struct ti_cmd_desc cmd;
1734 ifp = &sc->arpcom.ac_if;
1736 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1737 struct ti_rx_desc *cur_rx;
1739 struct ether_header *eh;
1740 struct mbuf *m = NULL;
1742 u_int16_t vlan_tag = 0;
1747 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1748 rxidx = cur_rx->ti_idx;
1749 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1752 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1754 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1758 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1759 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1760 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1761 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1762 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1764 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1767 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1769 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1772 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1773 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1774 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1775 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1776 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1778 ti_newbuf_mini(sc, sc->ti_mini, m);
1781 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1783 ti_newbuf_mini(sc, sc->ti_mini, m);
1787 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1788 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1789 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1790 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1792 ti_newbuf_std(sc, sc->ti_std, m);
1795 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1797 ti_newbuf_std(sc, sc->ti_std, m);
1802 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1804 eh = mtod(m, struct ether_header *);
1805 m->m_pkthdr.rcvif = ifp;
1807 /* Remove header from mbuf and pass it on. */
1808 m_adj(m, sizeof(struct ether_header));
1810 if (ifp->if_hwassist) {
1811 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1813 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1814 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1815 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1820 * If we received a packet with a vlan tag, pass it
1821 * to vlan_input() instead of ether_input().
1824 vlan_input_tag(eh, m, vlan_tag);
1825 have_tag = vlan_tag = 0;
1829 ether_input(ifp, eh, m);
1832 /* Only necessary on the Tigon 1. */
1833 if (sc->ti_hwrev == TI_HWREV_TIGON)
1834 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1835 sc->ti_rx_saved_considx);
1837 TI_UPDATE_STDPROD(sc, sc->ti_std);
1838 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1839 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1844 static void ti_txeof(sc)
1845 struct ti_softc *sc;
1847 struct ti_tx_desc *cur_tx = NULL;
1850 ifp = &sc->arpcom.ac_if;
1853 * Go through our tx ring and free mbufs for those
1854 * frames that have been sent.
1856 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1859 idx = sc->ti_tx_saved_considx;
1860 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1862 CSR_WRITE_4(sc, TI_WINBASE,
1863 TI_TX_RING_BASE + 6144);
1865 CSR_WRITE_4(sc, TI_WINBASE,
1866 TI_TX_RING_BASE + 4096);
1868 CSR_WRITE_4(sc, TI_WINBASE,
1869 TI_TX_RING_BASE + 2048);
1871 CSR_WRITE_4(sc, TI_WINBASE,
1873 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1875 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1876 if (cur_tx->ti_flags & TI_BDFLAG_END)
1878 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1879 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1880 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1883 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1888 ifp->if_flags &= ~IFF_OACTIVE;
1893 static void ti_intr(xsc)
1896 struct ti_softc *sc;
1901 ifp = &sc->arpcom.ac_if;
1904 /* Avoid this for now -- checking this register is expensive. */
1905 /* Make sure this is really our interrupt. */
1906 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
1912 /* Ack interrupt and stop others from occuring. */
1913 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1915 if (ifp->if_flags & IFF_RUNNING) {
1916 /* Check RX return ring producer/consumer */
1919 /* Check TX ring producer/consumer */
1923 ti_handle_events(sc);
1925 /* Re-enable interrupts. */
1926 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1928 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1936 static void ti_stats_update(sc)
1937 struct ti_softc *sc;
1941 ifp = &sc->arpcom.ac_if;
1943 ifp->if_collisions +=
1944 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
1945 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
1946 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
1947 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
1954 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1955 * pointers to descriptors.
1957 static int ti_encap(sc, m_head, txidx)
1958 struct ti_softc *sc;
1959 struct mbuf *m_head;
1962 struct ti_tx_desc *f = NULL;
1964 u_int32_t frag, cur, cnt = 0;
1965 u_int16_t csum_flags = 0;
1967 struct ifvlan *ifv = NULL;
1969 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1970 m_head->m_pkthdr.rcvif != NULL &&
1971 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1972 ifv = m_head->m_pkthdr.rcvif->if_softc;
1976 cur = frag = *txidx;
1978 if (m_head->m_pkthdr.csum_flags) {
1979 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1980 csum_flags |= TI_BDFLAG_IP_CKSUM;
1981 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1982 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
1983 if (m_head->m_flags & M_LASTFRAG)
1984 csum_flags |= TI_BDFLAG_IP_FRAG_END;
1985 else if (m_head->m_flags & M_FRAG)
1986 csum_flags |= TI_BDFLAG_IP_FRAG;
1989 * Start packing the mbufs in this chain into
1990 * the fragment pointers. Stop when we run out
1991 * of fragments or hit the end of the mbuf chain.
1993 for (m = m_head; m != NULL; m = m->m_next) {
1994 if (m->m_len != 0) {
1995 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1997 CSR_WRITE_4(sc, TI_WINBASE,
1998 TI_TX_RING_BASE + 6144);
1999 else if (frag > 255)
2000 CSR_WRITE_4(sc, TI_WINBASE,
2001 TI_TX_RING_BASE + 4096);
2002 else if (frag > 127)
2003 CSR_WRITE_4(sc, TI_WINBASE,
2004 TI_TX_RING_BASE + 2048);
2006 CSR_WRITE_4(sc, TI_WINBASE,
2008 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2010 f = &sc->ti_rdata->ti_tx_ring[frag];
2011 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2013 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2014 f->ti_len = m->m_len;
2015 f->ti_flags = csum_flags;
2018 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2019 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
2025 * Sanity check: avoid coming within 16 descriptors
2026 * of the end of the ring.
2028 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2031 TI_INC(frag, TI_TX_RING_CNT);
2039 if (frag == sc->ti_tx_saved_considx)
2042 if (sc->ti_hwrev == TI_HWREV_TIGON)
2043 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2046 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2047 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2048 sc->ti_txcnt += cnt;
2056 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2057 * to the mbuf data regions directly in the transmit descriptors.
2059 static void ti_start(ifp)
2062 struct ti_softc *sc;
2063 struct mbuf *m_head = NULL;
2064 u_int32_t prodidx = 0;
2069 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2071 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2072 IF_DEQUEUE(&ifp->if_snd, m_head);
2078 * safety overkill. If this is a fragmented packet chain
2079 * with delayed TCP/UDP checksums, then only encapsulate
2080 * it if we have enough descriptors to handle the entire
2082 * (paranoia -- may not actually be needed)
2084 if (m_head->m_flags & M_FIRSTFRAG &&
2085 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2086 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2087 m_head->m_pkthdr.csum_data + 16) {
2088 IF_PREPEND(&ifp->if_snd, m_head);
2089 ifp->if_flags |= IFF_OACTIVE;
2095 * Pack the data into the transmit ring. If we
2096 * don't have room, set the OACTIVE flag and wait
2097 * for the NIC to drain the ring.
2099 if (ti_encap(sc, m_head, &prodidx)) {
2100 IF_PREPEND(&ifp->if_snd, m_head);
2101 ifp->if_flags |= IFF_OACTIVE;
2106 * If there's a BPF listener, bounce a copy of this frame
2110 bpf_mtap(ifp, m_head);
2114 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2117 * Set a timeout in case the chip goes out to lunch.
2125 static void ti_init(xsc)
2128 struct ti_softc *sc = xsc;
2130 /* Cancel pending I/O and flush buffers. */
2134 /* Init the gen info block, ring control blocks and firmware. */
2135 if (ti_gibinit(sc)) {
2136 printf("ti%d: initialization failure\n", sc->ti_unit);
2146 static void ti_init2(sc)
2147 struct ti_softc *sc;
2149 struct ti_cmd_desc cmd;
2152 struct ifmedia *ifm;
2155 ifp = &sc->arpcom.ac_if;
2157 /* Specify MTU and interface index. */
2158 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit);
2159 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2160 ETHER_HDR_LEN + ETHER_CRC_LEN);
2161 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2163 /* Load our MAC address. */
2164 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2165 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2166 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2167 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2169 /* Enable or disable promiscuous mode as needed. */
2170 if (ifp->if_flags & IFF_PROMISC) {
2171 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2173 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2176 /* Program multicast filter. */
2180 * If this is a Tigon 1, we should tell the
2181 * firmware to use software packet filtering.
2183 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2184 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2188 ti_init_rx_ring_std(sc);
2190 /* Init jumbo RX ring. */
2191 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2192 ti_init_rx_ring_jumbo(sc);
2195 * If this is a Tigon 2, we can also configure the
2198 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2199 ti_init_rx_ring_mini(sc);
2201 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2202 sc->ti_rx_saved_considx = 0;
2205 ti_init_tx_ring(sc);
2207 /* Tell firmware we're alive. */
2208 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2210 /* Enable host interrupts. */
2211 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2213 ifp->if_flags |= IFF_RUNNING;
2214 ifp->if_flags &= ~IFF_OACTIVE;
2217 * Make sure to set media properly. We have to do this
2218 * here since we have to issue commands in order to set
2219 * the link negotiation and we can't issue commands until
2220 * the firmware is running.
2223 tmp = ifm->ifm_media;
2224 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2225 ti_ifmedia_upd(ifp);
2226 ifm->ifm_media = tmp;
2232 * Set media options.
2234 static int ti_ifmedia_upd(ifp)
2237 struct ti_softc *sc;
2238 struct ifmedia *ifm;
2239 struct ti_cmd_desc cmd;
2244 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2247 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2249 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2250 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2251 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2252 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2253 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2254 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2255 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2256 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2260 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2261 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2262 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2263 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2264 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2266 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2267 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2273 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2274 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2275 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2276 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2277 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2279 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2281 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2282 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2284 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2286 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2287 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2295 * Report current media status.
2297 static void ti_ifmedia_sts(ifp, ifmr)
2299 struct ifmediareq *ifmr;
2301 struct ti_softc *sc;
2302 u_int32_t media = 0;
2306 ifmr->ifm_status = IFM_AVALID;
2307 ifmr->ifm_active = IFM_ETHER;
2309 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2312 ifmr->ifm_status |= IFM_ACTIVE;
2314 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2315 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2317 ifmr->ifm_active |= IFM_1000_TX;
2319 ifmr->ifm_active |= IFM_1000_SX;
2320 if (media & TI_GLNK_FULL_DUPLEX)
2321 ifmr->ifm_active |= IFM_FDX;
2323 ifmr->ifm_active |= IFM_HDX;
2324 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2325 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2326 if (sc->ti_copper) {
2327 if (media & TI_LNK_100MB)
2328 ifmr->ifm_active |= IFM_100_TX;
2329 if (media & TI_LNK_10MB)
2330 ifmr->ifm_active |= IFM_10_T;
2332 if (media & TI_LNK_100MB)
2333 ifmr->ifm_active |= IFM_100_FX;
2334 if (media & TI_LNK_10MB)
2335 ifmr->ifm_active |= IFM_10_FL;
2337 if (media & TI_LNK_FULL_DUPLEX)
2338 ifmr->ifm_active |= IFM_FDX;
2339 if (media & TI_LNK_HALF_DUPLEX)
2340 ifmr->ifm_active |= IFM_HDX;
2346 static int ti_ioctl(ifp, command, data)
2351 struct ti_softc *sc = ifp->if_softc;
2352 struct ifreq *ifr = (struct ifreq *) data;
2354 struct ti_cmd_desc cmd;
2361 error = ether_ioctl(ifp, command, data);
2364 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2367 ifp->if_mtu = ifr->ifr_mtu;
2372 if (ifp->if_flags & IFF_UP) {
2374 * If only the state of the PROMISC flag changed,
2375 * then just use the 'set promisc mode' command
2376 * instead of reinitializing the entire NIC. Doing
2377 * a full re-init means reloading the firmware and
2378 * waiting for it to start up, which may take a
2381 if (ifp->if_flags & IFF_RUNNING &&
2382 ifp->if_flags & IFF_PROMISC &&
2383 !(sc->ti_if_flags & IFF_PROMISC)) {
2384 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2385 TI_CMD_CODE_PROMISC_ENB, 0);
2386 } else if (ifp->if_flags & IFF_RUNNING &&
2387 !(ifp->if_flags & IFF_PROMISC) &&
2388 sc->ti_if_flags & IFF_PROMISC) {
2389 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2390 TI_CMD_CODE_PROMISC_DIS, 0);
2394 if (ifp->if_flags & IFF_RUNNING) {
2398 sc->ti_if_flags = ifp->if_flags;
2403 if (ifp->if_flags & IFF_RUNNING) {
2410 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2422 static void ti_watchdog(ifp)
2425 struct ti_softc *sc;
2430 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2441 * Stop the adapter and free any mbufs allocated to the
2444 static void ti_stop(sc)
2445 struct ti_softc *sc;
2448 struct ti_cmd_desc cmd;
2452 ifp = &sc->arpcom.ac_if;
2454 /* Disable host interrupts. */
2455 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2457 * Tell firmware we're shutting down.
2459 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2461 /* Halt and reinitialize. */
2463 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2466 /* Free the RX lists. */
2467 ti_free_rx_ring_std(sc);
2469 /* Free jumbo RX list. */
2470 ti_free_rx_ring_jumbo(sc);
2472 /* Free mini RX list. */
2473 ti_free_rx_ring_mini(sc);
2475 /* Free TX buffers. */
2476 ti_free_tx_ring(sc);
2478 sc->ti_ev_prodidx.ti_idx = 0;
2479 sc->ti_return_prodidx.ti_idx = 0;
2480 sc->ti_tx_considx.ti_idx = 0;
2481 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2483 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2490 * Stop all chip I/O so that the kernel's probe routines don't
2491 * get confused by errant DMAs when rebooting.
2493 static void ti_shutdown(dev)
2496 struct ti_softc *sc;
2498 sc = device_get_softc(dev);