2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
38 * the National Semiconductor DP83840A physical interface and the
39 * Microchip Technology 24Cxx series serial EEPROM.
41 * Written using the following four documents:
43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
44 * National Semiconductor DP83840A data sheet (www.national.com)
45 * Microchip Technology 24C02C data sheet (www.microchip.com)
46 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
48 * Written by Bill Paul <wpaul@ctr.columbia.edu>
49 * Electrical Engineering Department
50 * Columbia University, New York City
54 * Some notes about the ThunderLAN:
56 * The ThunderLAN controller is a single chip containing PCI controller
57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
61 * to act as a complete ethernet interface.
63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
65 * in full or half duplex. Some of the Compaq Deskpro machines use a
66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
68 * concert with the ThunderLAN's internal PHY to provide full 10/100
69 * support. This is cheaper than using a standalone external PHY for both
70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
71 * A serial EEPROM is also attached to the ThunderLAN chip to provide
72 * power-up default register settings and for storing the adapter's
73 * station address. Although not supported by this driver, the ThunderLAN
74 * chip can also be connected to token ring PHYs.
76 * The ThunderLAN has a set of registers which can be used to issue
77 * commands, acknowledge interrupts, and to manipulate other internal
78 * registers on its DIO bus. The primary registers can be accessed
79 * using either programmed I/O (inb/outb) or via PCI memory mapping,
80 * depending on how the card is configured during the PCI probing
81 * phase. It is even possible to have both PIO and memory mapped
82 * access turned on at the same time.
84 * Frame reception and transmission with the ThunderLAN chip is done
85 * using frame 'lists.' A list structure looks more or less like this:
88 * u_int32_t fragment_address;
89 * u_int32_t fragment_size;
92 * u_int32_t forward_pointer;
94 * u_int16_t frame_size;
95 * struct tl_frag fragments[10];
98 * The forward pointer in the list header can be either a 0 or the address
99 * of another list, which allows several lists to be linked together. Each
100 * list contains up to 10 fragment descriptors. This means the chip allows
101 * ethernet frames to be broken up into up to 10 chunks for transfer to
102 * and from the SRAM. Note that the forward pointer and fragment buffer
103 * addresses are physical memory addresses, not virtual. Note also that
104 * a single ethernet frame can not span lists: if the host wants to
105 * transmit a frame and the frame data is split up over more than 10
106 * buffers, the frame has to collapsed before it can be transmitted.
108 * To receive frames, the driver sets up a number of lists and populates
109 * the fragment descriptors, then it sends an RX GO command to the chip.
110 * When a frame is received, the chip will DMA it into the memory regions
111 * specified by the fragment descriptors and then trigger an RX 'end of
112 * frame interrupt' when done. The driver may choose to use only one
113 * fragment per list; this may result is slighltly less efficient use
114 * of memory in exchange for improving performance.
116 * To transmit frames, the driver again sets up lists and fragment
117 * descriptors, only this time the buffers contain frame data that
118 * is to be DMA'ed into the chip instead of out of it. Once the chip
119 * has transfered the data into its on-board SRAM, it will trigger a
120 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
121 * interrupt when it reaches the end of the list.
125 * Some notes about this driver:
127 * The ThunderLAN chip provides a couple of different ways to organize
128 * reception, transmission and interrupt handling. The simplest approach
129 * is to use one list each for transmission and reception. In this mode,
130 * the ThunderLAN will generate two interrupts for every received frame
131 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
132 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
133 * performance to have to handle so many interrupts.
135 * Initially I wanted to create a circular list of receive buffers so
136 * that the ThunderLAN chip would think there was an infinitely long
137 * receive channel and never deliver an RXEOC interrupt. However this
138 * doesn't work correctly under heavy load: while the manual says the
139 * chip will trigger an RXEOF interrupt each time a frame is copied into
140 * memory, you can't count on the chip waiting around for you to acknowledge
141 * the interrupt before it starts trying to DMA the next frame. The result
142 * is that the chip might traverse the entire circular list and then wrap
143 * around before you have a chance to do anything about it. Consequently,
144 * the receive list is terminated (with a 0 in the forward pointer in the
145 * last element). Each time an RXEOF interrupt arrives, the used list
146 * is shifted to the end of the list. This gives the appearance of an
147 * infinitely large RX chain so long as the driver doesn't fall behind
148 * the chip and allow all of the lists to be filled up.
150 * If all the lists are filled, the adapter will deliver an RX 'end of
151 * channel' interrupt when it hits the 0 forward pointer at the end of
152 * the chain. The RXEOC handler then cleans out the RX chain and resets
153 * the list head pointer in the ch_parm register and restarts the receiver.
155 * For frame transmission, it is possible to program the ThunderLAN's
156 * transmit interrupt threshold so that the chip can acknowledge multiple
157 * lists with only a single TX EOF interrupt. This allows the driver to
158 * queue several frames in one shot, and only have to handle a total
159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
160 * are transmitted. Frame transmission is done directly out of the
161 * mbufs passed to the tl_start() routine via the interface send queue.
162 * The driver simply sets up the fragment descriptors in the transmit
163 * lists to point to the mbuf data regions and sends a TX GO command.
165 * Note that since the RX and TX lists themselves are always used
166 * only by the driver, the are malloc()ed once at driver initialization
167 * time and never free()ed.
169 * Also, in order to remain as platform independent as possible, this
170 * driver uses memory mapped register access to manipulate the card
171 * as opposed to programmed I/O. This avoids the use of the inb/outb
172 * (and related) instructions which are specific to the i386 platform.
174 * Using these techniques, this driver achieves very high performance
175 * by minimizing the amount of interrupts generated during large
176 * transfers and by completely avoiding buffer copies. Frame transfer
177 * to and from the ThunderLAN chip is performed entirely by the chip
178 * itself thereby reducing the load on the host CPU.
181 #include <sys/param.h>
182 #include <sys/systm.h>
183 #include <sys/sockio.h>
184 #include <sys/mbuf.h>
185 #include <sys/malloc.h>
186 #include <sys/kernel.h>
187 #include <sys/socket.h>
190 #include <net/if_arp.h>
191 #include <net/ethernet.h>
192 #include <net/if_dl.h>
193 #include <net/if_media.h>
197 #include <vm/vm.h> /* for vtophys */
198 #include <vm/pmap.h> /* for vtophys */
199 #include <machine/bus_memio.h>
200 #include <machine/bus_pio.h>
201 #include <machine/bus.h>
202 #include <machine/resource.h>
204 #include <sys/rman.h>
206 #include <dev/mii/mii.h>
207 #include <dev/mii/miivar.h>
209 #include <pci/pcireg.h>
210 #include <pci/pcivar.h>
213 * Default to using PIO register access mode to pacify certain
214 * laptop docking stations with built-in ThunderLAN chips that
215 * don't seem to handle memory mapped mode properly.
217 #define TL_USEIOSPACE
219 #include <pci/if_tlreg.h>
221 MODULE_DEPEND(tl, miibus, 1, 1, 1);
223 /* "controller miibus0" required. See GENERIC if you get errors here. */
224 #include "miibus_if.h"
227 static const char rcsid[] =
232 * Various supported device vendors/types and their names.
235 static struct tl_type tl_devs[] = {
236 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
237 "Texas Instruments ThunderLAN" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
239 "Compaq Netelligent 10" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
241 "Compaq Netelligent 10/100" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
243 "Compaq Netelligent 10/100 Proliant" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
245 "Compaq Netelligent 10/100 Dual Port" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
247 "Compaq NetFlex-3/P Integrated" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
249 "Compaq NetFlex-3/P" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
251 "Compaq NetFlex 3/P w/ BNC" },
252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
253 "Compaq Netelligent 10/100 TX Embedded UTP" },
254 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
255 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
256 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
257 "Compaq Netelligent 10/100 TX UTP" },
258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
259 "Olicom OC-2183/2185" },
260 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
262 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
263 "Olicom OC-2326 10/100 TX UTP" },
267 static int tl_probe (device_t);
268 static int tl_attach (device_t);
269 static int tl_detach (device_t);
270 static int tl_intvec_rxeoc (void *, u_int32_t);
271 static int tl_intvec_txeoc (void *, u_int32_t);
272 static int tl_intvec_txeof (void *, u_int32_t);
273 static int tl_intvec_rxeof (void *, u_int32_t);
274 static int tl_intvec_adchk (void *, u_int32_t);
275 static int tl_intvec_netsts (void *, u_int32_t);
277 static int tl_newbuf (struct tl_softc *, struct tl_chain_onefrag *);
278 static void tl_stats_update (void *);
279 static int tl_encap (struct tl_softc *, struct tl_chain *,
282 static void tl_intr (void *);
283 static void tl_start (struct ifnet *);
284 static int tl_ioctl (struct ifnet *, u_long, caddr_t);
285 static void tl_init (void *);
286 static void tl_stop (struct tl_softc *);
287 static void tl_watchdog (struct ifnet *);
288 static void tl_shutdown (device_t);
289 static int tl_ifmedia_upd (struct ifnet *);
290 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
292 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int);
293 static u_int8_t tl_eeprom_getbyte (struct tl_softc *, int, u_int8_t *);
294 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int);
296 static void tl_mii_sync (struct tl_softc *);
297 static void tl_mii_send (struct tl_softc *, u_int32_t, int);
298 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *);
299 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *);
300 static int tl_miibus_readreg (device_t, int, int);
301 static int tl_miibus_writereg (device_t, int, int, int);
302 static void tl_miibus_statchg (device_t);
304 static void tl_setmode (struct tl_softc *, int);
305 static int tl_calchash (caddr_t);
306 static void tl_setmulti (struct tl_softc *);
307 static void tl_setfilt (struct tl_softc *, caddr_t, int);
308 static void tl_softreset (struct tl_softc *, int);
309 static void tl_hardreset (device_t);
310 static int tl_list_rx_init (struct tl_softc *);
311 static int tl_list_tx_init (struct tl_softc *);
313 static u_int8_t tl_dio_read8 (struct tl_softc *, int);
314 static u_int16_t tl_dio_read16 (struct tl_softc *, int);
315 static u_int32_t tl_dio_read32 (struct tl_softc *, int);
316 static void tl_dio_write8 (struct tl_softc *, int, int);
317 static void tl_dio_write16 (struct tl_softc *, int, int);
318 static void tl_dio_write32 (struct tl_softc *, int, int);
319 static void tl_dio_setbit (struct tl_softc *, int, int);
320 static void tl_dio_clrbit (struct tl_softc *, int, int);
321 static void tl_dio_setbit16 (struct tl_softc *, int, int);
322 static void tl_dio_clrbit16 (struct tl_softc *, int, int);
325 #define TL_RES SYS_RES_IOPORT
326 #define TL_RID TL_PCI_LOIO
328 #define TL_RES SYS_RES_MEMORY
329 #define TL_RID TL_PCI_LOMEM
332 static device_method_t tl_methods[] = {
333 /* Device interface */
334 DEVMETHOD(device_probe, tl_probe),
335 DEVMETHOD(device_attach, tl_attach),
336 DEVMETHOD(device_detach, tl_detach),
337 DEVMETHOD(device_shutdown, tl_shutdown),
340 DEVMETHOD(bus_print_child, bus_generic_print_child),
341 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
344 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
345 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
346 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
351 static driver_t tl_driver = {
354 sizeof(struct tl_softc)
357 static devclass_t tl_devclass;
359 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0);
360 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
362 static u_int8_t tl_dio_read8(sc, reg)
366 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
367 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
370 static u_int16_t tl_dio_read16(sc, reg)
374 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
375 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
378 static u_int32_t tl_dio_read32(sc, reg)
382 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
383 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
386 static void tl_dio_write8(sc, reg, val)
391 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
392 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
396 static void tl_dio_write16(sc, reg, val)
401 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
402 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
406 static void tl_dio_write32(sc, reg, val)
411 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
412 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
416 static void tl_dio_setbit(sc, reg, bit)
423 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
424 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
426 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
431 static void tl_dio_clrbit(sc, reg, bit)
438 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
439 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
441 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
446 static void tl_dio_setbit16(sc, reg, bit)
453 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
454 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
456 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
461 static void tl_dio_clrbit16(sc, reg, bit)
468 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
469 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
471 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
477 * Send an instruction or address to the EEPROM, check for ACK.
479 static u_int8_t tl_eeprom_putbyte(sc, byte)
483 register int i, ack = 0;
486 * Make sure we're in TX mode.
488 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
491 * Feed in each bit and stobe the clock.
493 for (i = 0x80; i; i >>= 1) {
495 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
497 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
500 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
502 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
508 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
513 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
514 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
515 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
521 * Read a byte of data stored in the EEPROM at address 'addr.'
523 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
531 tl_dio_write8(sc, TL_NETSIO, 0);
536 * Send write control code to EEPROM.
538 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
539 printf("tl%d: failed to send write command, status: %x\n",
540 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
545 * Send address of byte we want to read.
547 if (tl_eeprom_putbyte(sc, addr)) {
548 printf("tl%d: failed to send address, status: %x\n",
549 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
556 * Send read control code to EEPROM.
558 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
559 printf("tl%d: failed to send write command, status: %x\n",
560 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
565 * Start reading bits from EEPROM.
567 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
568 for (i = 0x80; i; i >>= 1) {
569 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
571 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
573 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
580 * No ACK generated for read, so just return byte.
589 * Read a sequence of bytes from the EEPROM.
591 static int tl_read_eeprom(sc, dest, off, cnt)
600 for (i = 0; i < cnt; i++) {
601 err = tl_eeprom_getbyte(sc, off + i, &byte);
610 static void tl_mii_sync(sc)
615 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
617 for (i = 0; i < 32; i++) {
618 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
619 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
625 static void tl_mii_send(sc, bits, cnt)
632 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
633 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
635 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
637 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
639 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
643 static int tl_mii_readreg(sc, frame)
645 struct tl_mii_frame *frame;
656 * Set up frame for RX.
658 frame->mii_stdelim = TL_MII_STARTDELIM;
659 frame->mii_opcode = TL_MII_READOP;
660 frame->mii_turnaround = 0;
664 * Turn off MII interrupt by forcing MINTEN low.
666 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
668 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
674 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
677 * Send command/address info.
679 tl_mii_send(sc, frame->mii_stdelim, 2);
680 tl_mii_send(sc, frame->mii_opcode, 2);
681 tl_mii_send(sc, frame->mii_phyaddr, 5);
682 tl_mii_send(sc, frame->mii_regaddr, 5);
687 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
690 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
691 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
694 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
695 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
697 /* Complete the cycle */
698 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
701 * Now try reading data bits. If the ack failed, we still
702 * need to clock through 16 cycles to keep the PHYs in sync.
705 for(i = 0; i < 16; i++) {
706 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
707 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
712 for (i = 0x8000; i; i >>= 1) {
713 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
715 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
716 frame->mii_data |= i;
718 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
723 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
724 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
726 /* Reenable interrupts */
728 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
738 static int tl_mii_writereg(sc, frame)
740 struct tl_mii_frame *frame;
750 * Set up frame for TX.
753 frame->mii_stdelim = TL_MII_STARTDELIM;
754 frame->mii_opcode = TL_MII_WRITEOP;
755 frame->mii_turnaround = TL_MII_TURNAROUND;
758 * Turn off MII interrupt by forcing MINTEN low.
760 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
762 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
766 * Turn on data output.
768 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
770 tl_mii_send(sc, frame->mii_stdelim, 2);
771 tl_mii_send(sc, frame->mii_opcode, 2);
772 tl_mii_send(sc, frame->mii_phyaddr, 5);
773 tl_mii_send(sc, frame->mii_regaddr, 5);
774 tl_mii_send(sc, frame->mii_turnaround, 2);
775 tl_mii_send(sc, frame->mii_data, 16);
777 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
778 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
783 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
785 /* Reenable interrupts */
787 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
794 static int tl_miibus_readreg(dev, phy, reg)
799 struct tl_mii_frame frame;
801 sc = device_get_softc(dev);
802 bzero((char *)&frame, sizeof(frame));
804 frame.mii_phyaddr = phy;
805 frame.mii_regaddr = reg;
806 tl_mii_readreg(sc, &frame);
808 return(frame.mii_data);
811 static int tl_miibus_writereg(dev, phy, reg, data)
816 struct tl_mii_frame frame;
818 sc = device_get_softc(dev);
819 bzero((char *)&frame, sizeof(frame));
821 frame.mii_phyaddr = phy;
822 frame.mii_regaddr = reg;
823 frame.mii_data = data;
825 tl_mii_writereg(sc, &frame);
830 static void tl_miibus_statchg(dev)
834 struct mii_data *mii;
836 sc = device_get_softc(dev);
838 mii = device_get_softc(sc->tl_miibus);
840 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
841 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
843 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
851 * Set modes for bitrate devices.
853 static void tl_setmode(sc, media)
857 if (IFM_SUBTYPE(media) == IFM_10_5)
858 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
859 if (IFM_SUBTYPE(media) == IFM_10_T) {
860 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
861 if ((media & IFM_GMASK) == IFM_FDX) {
862 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
863 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
865 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
866 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
874 * Calculate the hash of a MAC address for programming the multicast hash
875 * table. This hash is simply the address split into 6-bit chunks
877 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
878 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
879 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
880 * the folded 24-bit value is split into 6-bit portions and XOR'd.
882 static int tl_calchash(addr)
887 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
889 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
893 * The ThunderLAN has a perfect MAC address filter in addition to
894 * the multicast hash filter. The perfect filter can be programmed
895 * with up to four MAC addresses. The first one is always used to
896 * hold the station address, which leaves us free to use the other
897 * three for multicast addresses.
899 static void tl_setfilt(sc, addr, slot)
907 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
909 for (i = 0; i < ETHER_ADDR_LEN; i++)
910 tl_dio_write8(sc, regaddr + i, *(addr + i));
916 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
917 * linked list. This is fine, except addresses are added from the head
918 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
919 * group to always be in the perfect filter, but as more groups are added,
920 * the 224.0.0.1 entry (which is always added first) gets pushed down
921 * the list and ends up at the tail. So after 3 or 4 multicast groups
922 * are added, the all-hosts entry gets pushed out of the perfect filter
923 * and into the hash table.
925 * Because the multicast list is a doubly-linked list as opposed to a
926 * circular queue, we don't have the ability to just grab the tail of
927 * the list and traverse it backwards. Instead, we have to traverse
928 * the list once to find the tail, then traverse it again backwards to
929 * update the multicast filter.
931 static void tl_setmulti(sc)
935 u_int32_t hashes[2] = { 0, 0 };
937 struct ifmultiaddr *ifma;
938 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
939 ifp = &sc->arpcom.ac_if;
941 /* First, zot all the existing filters. */
942 for (i = 1; i < 4; i++)
943 tl_setfilt(sc, (caddr_t)&dummy, i);
944 tl_dio_write32(sc, TL_HASH1, 0);
945 tl_dio_write32(sc, TL_HASH2, 0);
947 /* Now program new ones. */
948 if (ifp->if_flags & IFF_ALLMULTI) {
949 hashes[0] = 0xFFFFFFFF;
950 hashes[1] = 0xFFFFFFFF;
953 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
954 if (ifma->ifma_addr->sa_family != AF_LINK)
957 * Program the first three multicast groups
958 * into the perfect filter. For all others,
959 * use the hash table.
963 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
969 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
971 hashes[0] |= (1 << h);
973 hashes[1] |= (1 << (h - 32));
977 tl_dio_write32(sc, TL_HASH1, hashes[0]);
978 tl_dio_write32(sc, TL_HASH2, hashes[1]);
984 * This routine is recommended by the ThunderLAN manual to insure that
985 * the internal PHY is powered up correctly. It also recommends a one
986 * second pause at the end to 'wait for the clocks to start' but in my
987 * experience this isn't necessary.
989 static void tl_hardreset(dev)
996 sc = device_get_softc(dev);
1000 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
1002 for (i = 0; i < MII_NPHY; i++)
1003 tl_miibus_writereg(dev, i, MII_BMCR, flags);
1005 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
1007 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
1009 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
1015 static void tl_softreset(sc, internal)
1016 struct tl_softc *sc;
1019 u_int32_t cmd, dummy, i;
1021 /* Assert the adapter reset bit. */
1022 CMD_SET(sc, TL_CMD_ADRST);
1024 /* Turn off interrupts */
1025 CMD_SET(sc, TL_CMD_INTSOFF);
1027 /* First, clear the stats registers. */
1028 for (i = 0; i < 5; i++)
1029 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
1031 /* Clear Areg and Hash registers */
1032 for (i = 0; i < 8; i++)
1033 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
1036 * Set up Netconfig register. Enable one channel and
1037 * one fragment mode.
1039 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
1040 if (internal && !sc->tl_bitrate) {
1041 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1043 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1046 /* Handle cards with bitrate devices. */
1048 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1051 * Load adapter irq pacing timer and tx threshold.
1052 * We make the transmit threshold 1 initially but we may
1053 * change that later.
1055 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1057 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1058 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1059 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1061 /* Unreset the MII */
1062 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1064 /* Take the adapter out of reset */
1065 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1067 /* Wait for things to settle down a little. */
1074 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1075 * against our list and return its name if we find a match.
1077 static int tl_probe(dev)
1084 while(t->tl_name != NULL) {
1085 if ((pci_get_vendor(dev) == t->tl_vid) &&
1086 (pci_get_device(dev) == t->tl_did)) {
1087 device_set_desc(dev, t->tl_name);
1096 static int tl_attach(dev)
1104 struct tl_softc *sc;
1105 int unit, error = 0, rid;
1107 vid = pci_get_vendor(dev);
1108 did = pci_get_device(dev);
1109 sc = device_get_softc(dev);
1110 unit = device_get_unit(dev);
1111 bzero(sc, sizeof(struct tl_softc));
1114 while(t->tl_name != NULL) {
1115 if (vid == t->tl_vid && did == t->tl_did)
1120 if (t->tl_name == NULL) {
1121 printf("tl%d: unknown device!?\n", unit);
1125 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1126 MTX_DEF | MTX_RECURSE);
1130 * Map control/status registers.
1132 pci_enable_busmaster(dev);
1133 pci_enable_io(dev, SYS_RES_IOPORT);
1134 pci_enable_io(dev, SYS_RES_MEMORY);
1135 command = pci_read_config(dev, PCIR_COMMAND, 4);
1137 #ifdef TL_USEIOSPACE
1138 if (!(command & PCIM_CMD_PORTEN)) {
1139 printf("tl%d: failed to enable I/O ports!\n", unit);
1145 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1146 0, ~0, 1, RF_ACTIVE);
1149 * Some cards have the I/O and memory mapped address registers
1150 * reversed. Try both combinations before giving up.
1152 if (sc->tl_res == NULL) {
1154 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1155 0, ~0, 1, RF_ACTIVE);
1158 if (!(command & PCIM_CMD_MEMEN)) {
1159 printf("tl%d: failed to enable memory mapping!\n", unit);
1165 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1166 0, ~0, 1, RF_ACTIVE);
1167 if (sc->tl_res == NULL) {
1169 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1170 0, ~0, 1, RF_ACTIVE);
1174 if (sc->tl_res == NULL) {
1175 printf("tl%d: couldn't map ports/memory\n", unit);
1180 sc->tl_btag = rman_get_bustag(sc->tl_res);
1181 sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
1185 * The ThunderLAN manual suggests jacking the PCI latency
1186 * timer all the way up to its maximum value. I'm not sure
1187 * if this is really necessary, but what the manual wants,
1190 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1191 command |= 0x0000FF00;
1192 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1195 /* Allocate interrupt */
1197 sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1198 RF_SHAREABLE | RF_ACTIVE);
1200 if (sc->tl_irq == NULL) {
1201 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1202 printf("tl%d: couldn't map interrupt\n", unit);
1207 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET,
1208 tl_intr, sc, &sc->tl_intrhand);
1211 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1212 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1213 printf("tl%d: couldn't set up irq\n", unit);
1218 * Now allocate memory for the TX and RX lists.
1220 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1221 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1223 if (sc->tl_ldata == NULL) {
1224 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1225 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1226 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1227 printf("tl%d: no memory for list buffers!\n", unit);
1232 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1236 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1237 sc->tl_eeaddr = TL_EEPROM_EADDR;
1238 if (t->tl_vid == OLICOM_VENDORID)
1239 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1241 /* Reset the adapter. */
1242 tl_softreset(sc, 1);
1244 tl_softreset(sc, 1);
1247 * Get station address from the EEPROM.
1249 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1250 sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1251 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1252 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1253 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1254 contigfree(sc->tl_ldata,
1255 sizeof(struct tl_list_data), M_DEVBUF);
1256 printf("tl%d: failed to read station address\n", unit);
1262 * XXX Olicom, in its desire to be different from the
1263 * rest of the world, has done strange things with the
1264 * encoding of the station address in the EEPROM. First
1265 * of all, they store the address at offset 0xF8 rather
1266 * than at 0x83 like the ThunderLAN manual suggests.
1267 * Second, they store the address in three 16-bit words in
1268 * network byte order, as opposed to storing it sequentially
1269 * like all the other ThunderLAN cards. In order to get
1270 * the station address in a form that matches what the Olicom
1271 * diagnostic utility specifies, we have to byte-swap each
1272 * word. To make things even more confusing, neither 00:00:28
1273 * nor 00:00:24 appear in the IEEE OUI database.
1275 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1276 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1278 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i];
1284 * A ThunderLAN chip was detected. Inform the world.
1286 printf("tl%d: Ethernet address: %6D\n", unit,
1287 sc->arpcom.ac_enaddr, ":");
1289 ifp = &sc->arpcom.ac_if;
1291 ifp->if_unit = sc->tl_unit;
1292 ifp->if_name = "tl";
1293 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1294 ifp->if_ioctl = tl_ioctl;
1295 ifp->if_output = ether_output;
1296 ifp->if_start = tl_start;
1297 ifp->if_watchdog = tl_watchdog;
1298 ifp->if_init = tl_init;
1299 ifp->if_mtu = ETHERMTU;
1300 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1;
1301 callout_handle_init(&sc->tl_stat_ch);
1303 /* Reset the adapter again. */
1304 tl_softreset(sc, 1);
1306 tl_softreset(sc, 1);
1309 * Do MII setup. If no PHYs are found, then this is a
1310 * bitrate ThunderLAN chip that only supports 10baseT
1313 if (mii_phy_probe(dev, &sc->tl_miibus,
1314 tl_ifmedia_upd, tl_ifmedia_sts)) {
1315 struct ifmedia *ifm;
1317 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1318 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1319 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1320 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1321 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1322 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1323 /* Reset again, this time setting bitrate mode. */
1324 tl_softreset(sc, 1);
1326 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1327 tl_ifmedia_upd(ifp);
1331 * Call MI attach routine.
1333 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1339 mtx_destroy(&sc->tl_mtx);
1343 static int tl_detach(dev)
1346 struct tl_softc *sc;
1349 sc = device_get_softc(dev);
1351 ifp = &sc->arpcom.ac_if;
1354 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1356 bus_generic_detach(dev);
1357 device_delete_child(dev, sc->tl_miibus);
1359 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1361 ifmedia_removeall(&sc->ifmedia);
1363 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1364 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1365 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1368 mtx_destroy(&sc->tl_mtx);
1374 * Initialize the transmit lists.
1376 static int tl_list_tx_init(sc)
1377 struct tl_softc *sc;
1379 struct tl_chain_data *cd;
1380 struct tl_list_data *ld;
1385 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1386 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1387 if (i == (TL_TX_LIST_CNT - 1))
1388 cd->tl_tx_chain[i].tl_next = NULL;
1390 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1393 cd->tl_tx_free = &cd->tl_tx_chain[0];
1394 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1401 * Initialize the RX lists and allocate mbufs for them.
1403 static int tl_list_rx_init(sc)
1404 struct tl_softc *sc;
1406 struct tl_chain_data *cd;
1407 struct tl_list_data *ld;
1413 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1414 cd->tl_rx_chain[i].tl_ptr =
1415 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1416 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1418 if (i == (TL_RX_LIST_CNT - 1)) {
1419 cd->tl_rx_chain[i].tl_next = NULL;
1420 ld->tl_rx_list[i].tlist_fptr = 0;
1422 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1423 ld->tl_rx_list[i].tlist_fptr =
1424 vtophys(&ld->tl_rx_list[i + 1]);
1428 cd->tl_rx_head = &cd->tl_rx_chain[0];
1429 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1434 static int tl_newbuf(sc, c)
1435 struct tl_softc *sc;
1436 struct tl_chain_onefrag *c;
1438 struct mbuf *m_new = NULL;
1440 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1444 MCLGET(m_new, M_DONTWAIT);
1445 if (!(m_new->m_flags & M_EXT)) {
1456 c->tl_ptr->tlist_frsize = MCLBYTES;
1457 c->tl_ptr->tlist_fptr = 0;
1458 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1459 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1460 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1465 * Interrupt handler for RX 'end of frame' condition (EOF). This
1466 * tells us that a full ethernet frame has been captured and we need
1469 * Reception is done using 'lists' which consist of a header and a
1470 * series of 10 data count/data address pairs that point to buffers.
1471 * Initially you're supposed to create a list, populate it with pointers
1472 * to buffers, then load the physical address of the list into the
1473 * ch_parm register. The adapter is then supposed to DMA the received
1474 * frame into the buffers for you.
1476 * To make things as fast as possible, we have the chip DMA directly
1477 * into mbufs. This saves us from having to do a buffer copy: we can
1478 * just hand the mbufs directly to ether_input(). Once the frame has
1479 * been sent on its way, the 'list' structure is assigned a new buffer
1480 * and moved to the end of the RX chain. As long we we stay ahead of
1481 * the chip, it will always think it has an endless receive channel.
1483 * If we happen to fall behind and the chip manages to fill up all of
1484 * the buffers, it will generate an end of channel interrupt and wait
1485 * for us to empty the chain and restart the receiver.
1487 static int tl_intvec_rxeof(xsc, type)
1491 struct tl_softc *sc;
1492 int r = 0, total_len = 0;
1493 struct ether_header *eh;
1496 struct tl_chain_onefrag *cur_rx;
1499 ifp = &sc->arpcom.ac_if;
1501 while(sc->tl_cdata.tl_rx_head != NULL) {
1502 cur_rx = sc->tl_cdata.tl_rx_head;
1503 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1506 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1507 m = cur_rx->tl_mbuf;
1508 total_len = cur_rx->tl_ptr->tlist_frsize;
1510 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1512 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1513 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1514 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1518 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1519 vtophys(cur_rx->tl_ptr);
1520 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1521 sc->tl_cdata.tl_rx_tail = cur_rx;
1523 eh = mtod(m, struct ether_header *);
1524 m->m_pkthdr.rcvif = ifp;
1527 * Note: when the ThunderLAN chip is in 'capture all
1528 * frames' mode, it will receive its own transmissions.
1529 * We drop don't need to process our own transmissions,
1530 * so we drop them here and continue.
1532 /*if (ifp->if_flags & IFF_PROMISC && */
1533 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1539 /* Remove header from mbuf and pass it on. */
1540 m->m_pkthdr.len = m->m_len =
1541 total_len - sizeof(struct ether_header);
1542 m->m_data += sizeof(struct ether_header);
1543 ether_input(ifp, eh, m);
1550 * The RX-EOC condition hits when the ch_parm address hasn't been
1551 * initialized or the adapter reached a list with a forward pointer
1552 * of 0 (which indicates the end of the chain). In our case, this means
1553 * the card has hit the end of the receive buffer chain and we need to
1554 * empty out the buffers and shift the pointer back to the beginning again.
1556 static int tl_intvec_rxeoc(xsc, type)
1560 struct tl_softc *sc;
1562 struct tl_chain_data *cd;
1568 /* Flush out the receive queue and ack RXEOF interrupts. */
1569 r = tl_intvec_rxeof(xsc, type);
1570 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1572 cd->tl_rx_head = &cd->tl_rx_chain[0];
1573 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1574 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1575 r |= (TL_CMD_GO|TL_CMD_RT);
1579 static int tl_intvec_txeof(xsc, type)
1583 struct tl_softc *sc;
1585 struct tl_chain *cur_tx;
1590 * Go through our tx list and free mbufs for those
1591 * frames that have been sent.
1593 while (sc->tl_cdata.tl_tx_head != NULL) {
1594 cur_tx = sc->tl_cdata.tl_tx_head;
1595 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1597 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1600 m_freem(cur_tx->tl_mbuf);
1601 cur_tx->tl_mbuf = NULL;
1603 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1604 sc->tl_cdata.tl_tx_free = cur_tx;
1605 if (!cur_tx->tl_ptr->tlist_fptr)
1613 * The transmit end of channel interrupt. The adapter triggers this
1614 * interrupt to tell us it hit the end of the current transmit list.
1616 * A note about this: it's possible for a condition to arise where
1617 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1618 * You have to avoid this since the chip expects things to go in a
1619 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1620 * When the TXEOF handler is called, it will free all of the transmitted
1621 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1622 * interrupt should be received and acknowledged before any more frames
1623 * are queued for transmission. If tl_statrt() is called after TXEOF
1624 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1625 * it could attempt to issue a transmit command prematurely.
1627 * To guard against this, tl_start() will only issue transmit commands
1628 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1629 * can set this flag once tl_start() has cleared it.
1631 static int tl_intvec_txeoc(xsc, type)
1635 struct tl_softc *sc;
1640 ifp = &sc->arpcom.ac_if;
1642 /* Clear the timeout timer. */
1645 if (sc->tl_cdata.tl_tx_head == NULL) {
1646 ifp->if_flags &= ~IFF_OACTIVE;
1647 sc->tl_cdata.tl_tx_tail = NULL;
1651 /* First we have to ack the EOC interrupt. */
1652 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1653 /* Then load the address of the next TX list. */
1654 CSR_WRITE_4(sc, TL_CH_PARM,
1655 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1656 /* Restart TX channel. */
1657 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1659 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1667 static int tl_intvec_adchk(xsc, type)
1671 struct tl_softc *sc;
1676 printf("tl%d: adapter check: %x\n", sc->tl_unit,
1677 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1679 tl_softreset(sc, 1);
1682 CMD_SET(sc, TL_CMD_INTSON);
1687 static int tl_intvec_netsts(xsc, type)
1691 struct tl_softc *sc;
1696 netsts = tl_dio_read16(sc, TL_NETSTS);
1697 tl_dio_write16(sc, TL_NETSTS, netsts);
1699 printf("tl%d: network status: %x\n", sc->tl_unit, netsts);
1704 static void tl_intr(xsc)
1707 struct tl_softc *sc;
1717 /* Disable interrupts */
1718 ints = CSR_READ_2(sc, TL_HOST_INT);
1719 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1720 type = (ints << 16) & 0xFFFF0000;
1721 ivec = (ints & TL_VEC_MASK) >> 5;
1722 ints = (ints & TL_INT_MASK) >> 2;
1724 ifp = &sc->arpcom.ac_if;
1727 case (TL_INTR_INVALID):
1729 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit);
1731 /* Re-enable interrupts but don't ack this one. */
1735 case (TL_INTR_TXEOF):
1736 r = tl_intvec_txeof((void *)sc, type);
1738 case (TL_INTR_TXEOC):
1739 r = tl_intvec_txeoc((void *)sc, type);
1741 case (TL_INTR_STATOFLOW):
1742 tl_stats_update(sc);
1745 case (TL_INTR_RXEOF):
1746 r = tl_intvec_rxeof((void *)sc, type);
1748 case (TL_INTR_DUMMY):
1749 printf("tl%d: got a dummy interrupt\n", sc->tl_unit);
1752 case (TL_INTR_ADCHK):
1754 r = tl_intvec_adchk((void *)sc, type);
1756 r = tl_intvec_netsts((void *)sc, type);
1758 case (TL_INTR_RXEOC):
1759 r = tl_intvec_rxeoc((void *)sc, type);
1762 printf("tl%d: bogus interrupt type\n", ifp->if_unit);
1766 /* Re-enable interrupts */
1768 CMD_PUT(sc, TL_CMD_ACK | r | type);
1771 if (ifp->if_snd.ifq_head != NULL)
1779 static void tl_stats_update(xsc)
1782 struct tl_softc *sc;
1784 struct tl_stats tl_stats;
1785 struct mii_data *mii;
1788 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1792 ifp = &sc->arpcom.ac_if;
1794 p = (u_int32_t *)&tl_stats;
1796 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1797 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1798 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1799 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1800 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1801 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1803 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1804 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1805 tl_stats.tl_tx_multi_collision;
1806 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1807 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1808 tl_rx_overrun(tl_stats);
1809 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1811 if (tl_tx_underrun(tl_stats)) {
1813 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1814 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1817 printf("tl%d: tx underrun -- increasing "
1818 "tx threshold to %d bytes\n", sc->tl_unit,
1819 (64 * (tx_thresh * 4)));
1820 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1821 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1825 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
1827 if (!sc->tl_bitrate) {
1828 mii = device_get_softc(sc->tl_miibus);
1838 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1839 * pointers to the fragment pointers.
1841 static int tl_encap(sc, c, m_head)
1842 struct tl_softc *sc;
1844 struct mbuf *m_head;
1847 struct tl_frag *f = NULL;
1852 * Start packing the mbufs in this chain into
1853 * the fragment pointers. Stop when we run out
1854 * of fragments or hit the end of the mbuf chain.
1859 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1860 if (m->m_len != 0) {
1861 if (frag == TL_MAXFRAGS)
1863 total_len+= m->m_len;
1864 c->tl_ptr->tl_frag[frag].tlist_dadr =
1865 vtophys(mtod(m, vm_offset_t));
1866 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1872 * Handle special cases.
1873 * Special case #1: we used up all 10 fragments, but
1874 * we have more mbufs left in the chain. Copy the
1875 * data into an mbuf cluster. Note that we don't
1876 * bother clearing the values in the other fragment
1877 * pointers/counters; it wouldn't gain us anything,
1878 * and would waste cycles.
1881 struct mbuf *m_new = NULL;
1883 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1884 if (m_new == NULL) {
1885 printf("tl%d: no memory for tx list\n", sc->tl_unit);
1888 if (m_head->m_pkthdr.len > MHLEN) {
1889 MCLGET(m_new, M_DONTWAIT);
1890 if (!(m_new->m_flags & M_EXT)) {
1892 printf("tl%d: no memory for tx list\n",
1897 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1898 mtod(m_new, caddr_t));
1899 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1902 f = &c->tl_ptr->tl_frag[0];
1903 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1904 f->tlist_dcnt = total_len = m_new->m_len;
1909 * Special case #2: the frame is smaller than the minimum
1910 * frame size. We have to pad it to make the chip happy.
1912 if (total_len < TL_MIN_FRAMELEN) {
1913 if (frag == TL_MAXFRAGS)
1914 printf("tl%d: all frags filled but "
1915 "frame still to small!\n", sc->tl_unit);
1916 f = &c->tl_ptr->tl_frag[frag];
1917 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1918 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1919 total_len += f->tlist_dcnt;
1923 c->tl_mbuf = m_head;
1924 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1925 c->tl_ptr->tlist_frsize = total_len;
1926 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1927 c->tl_ptr->tlist_fptr = 0;
1933 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1934 * to the mbuf data regions directly in the transmit lists. We also save a
1935 * copy of the pointers since the transmit list fragment pointers are
1936 * physical addresses.
1938 static void tl_start(ifp)
1941 struct tl_softc *sc;
1942 struct mbuf *m_head = NULL;
1944 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1950 * Check for an available queue slot. If there are none,
1953 if (sc->tl_cdata.tl_tx_free == NULL) {
1954 ifp->if_flags |= IFF_OACTIVE;
1959 start_tx = sc->tl_cdata.tl_tx_free;
1961 while(sc->tl_cdata.tl_tx_free != NULL) {
1962 IF_DEQUEUE(&ifp->if_snd, m_head);
1966 /* Pick a chain member off the free list. */
1967 cur_tx = sc->tl_cdata.tl_tx_free;
1968 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1970 cur_tx->tl_next = NULL;
1972 /* Pack the data into the list. */
1973 tl_encap(sc, cur_tx, m_head);
1975 /* Chain it together */
1977 prev->tl_next = cur_tx;
1978 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1983 * If there's a BPF listener, bounce a copy of this frame
1987 bpf_mtap(ifp, cur_tx->tl_mbuf);
1991 * If there are no packets queued, bail.
1993 if (cur_tx == NULL) {
1999 * That's all we can stands, we can't stands no more.
2000 * If there are no other transfers pending, then issue the
2001 * TX GO command to the adapter to start things moving.
2002 * Otherwise, just leave the data in the queue and let
2003 * the EOF/EOC interrupt handler send.
2005 if (sc->tl_cdata.tl_tx_head == NULL) {
2006 sc->tl_cdata.tl_tx_head = start_tx;
2007 sc->tl_cdata.tl_tx_tail = cur_tx;
2011 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
2012 cmd = CSR_READ_4(sc, TL_HOSTCMD);
2014 cmd |= TL_CMD_GO|TL_CMD_INTSON;
2018 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
2019 sc->tl_cdata.tl_tx_tail = cur_tx;
2023 * Set a timeout in case the chip goes out to lunch.
2031 static void tl_init(xsc)
2034 struct tl_softc *sc = xsc;
2035 struct ifnet *ifp = &sc->arpcom.ac_if;
2036 struct mii_data *mii;
2040 ifp = &sc->arpcom.ac_if;
2043 * Cancel pending I/O.
2047 /* Initialize TX FIFO threshold */
2048 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
2049 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
2051 /* Set PCI burst size */
2052 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
2055 * Set 'capture all frames' bit for promiscuous mode.
2057 if (ifp->if_flags & IFF_PROMISC)
2058 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2060 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2063 * Set capture broadcast bit to capture broadcast frames.
2065 if (ifp->if_flags & IFF_BROADCAST)
2066 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2068 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2070 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
2072 /* Init our MAC address */
2073 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
2075 /* Init multicast filter, if needed. */
2078 /* Init circular RX list. */
2079 if (tl_list_rx_init(sc) == ENOBUFS) {
2080 printf("tl%d: initialization failed: no "
2081 "memory for rx buffers\n", sc->tl_unit);
2087 /* Init TX pointers. */
2088 tl_list_tx_init(sc);
2090 /* Enable PCI interrupts. */
2091 CMD_SET(sc, TL_CMD_INTSON);
2093 /* Load the address of the rx list */
2094 CMD_SET(sc, TL_CMD_RT);
2095 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2097 if (!sc->tl_bitrate) {
2098 if (sc->tl_miibus != NULL) {
2099 mii = device_get_softc(sc->tl_miibus);
2104 /* Send the RX go command */
2105 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2107 ifp->if_flags |= IFF_RUNNING;
2108 ifp->if_flags &= ~IFF_OACTIVE;
2110 /* Start the stats update counter */
2111 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
2118 * Set media options.
2120 static int tl_ifmedia_upd(ifp)
2123 struct tl_softc *sc;
2124 struct mii_data *mii = NULL;
2129 tl_setmode(sc, sc->ifmedia.ifm_media);
2131 mii = device_get_softc(sc->tl_miibus);
2139 * Report current media status.
2141 static void tl_ifmedia_sts(ifp, ifmr)
2143 struct ifmediareq *ifmr;
2145 struct tl_softc *sc;
2146 struct mii_data *mii;
2150 ifmr->ifm_active = IFM_ETHER;
2152 if (sc->tl_bitrate) {
2153 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2154 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2156 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2157 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2158 ifmr->ifm_active |= IFM_HDX;
2160 ifmr->ifm_active |= IFM_FDX;
2163 mii = device_get_softc(sc->tl_miibus);
2165 ifmr->ifm_active = mii->mii_media_active;
2166 ifmr->ifm_status = mii->mii_media_status;
2172 static int tl_ioctl(ifp, command, data)
2177 struct tl_softc *sc = ifp->if_softc;
2178 struct ifreq *ifr = (struct ifreq *) data;
2187 error = ether_ioctl(ifp, command, data);
2190 if (ifp->if_flags & IFF_UP) {
2191 if (ifp->if_flags & IFF_RUNNING &&
2192 ifp->if_flags & IFF_PROMISC &&
2193 !(sc->tl_if_flags & IFF_PROMISC)) {
2194 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2196 } else if (ifp->if_flags & IFF_RUNNING &&
2197 !(ifp->if_flags & IFF_PROMISC) &&
2198 sc->tl_if_flags & IFF_PROMISC) {
2199 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2204 if (ifp->if_flags & IFF_RUNNING) {
2208 sc->tl_if_flags = ifp->if_flags;
2219 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2221 struct mii_data *mii;
2222 mii = device_get_softc(sc->tl_miibus);
2223 error = ifmedia_ioctl(ifp, ifr,
2224 &mii->mii_media, command);
2237 static void tl_watchdog(ifp)
2240 struct tl_softc *sc;
2244 printf("tl%d: device timeout\n", sc->tl_unit);
2248 tl_softreset(sc, 1);
2255 * Stop the adapter and free any mbufs allocated to the
2258 static void tl_stop(sc)
2259 struct tl_softc *sc;
2266 ifp = &sc->arpcom.ac_if;
2268 /* Stop the stats updater. */
2269 untimeout(tl_stats_update, sc, sc->tl_stat_ch);
2271 /* Stop the transmitter */
2272 CMD_CLR(sc, TL_CMD_RT);
2273 CMD_SET(sc, TL_CMD_STOP);
2274 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2276 /* Stop the receiver */
2277 CMD_SET(sc, TL_CMD_RT);
2278 CMD_SET(sc, TL_CMD_STOP);
2279 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2282 * Disable host interrupts.
2284 CMD_SET(sc, TL_CMD_INTSOFF);
2287 * Clear list pointer.
2289 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2292 * Free the RX lists.
2294 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2295 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2296 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2297 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2300 bzero((char *)&sc->tl_ldata->tl_rx_list,
2301 sizeof(sc->tl_ldata->tl_rx_list));
2304 * Free the TX list buffers.
2306 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2307 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2308 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2309 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2312 bzero((char *)&sc->tl_ldata->tl_tx_list,
2313 sizeof(sc->tl_ldata->tl_tx_list));
2315 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2322 * Stop all chip I/O so that the kernel's probe routines don't
2323 * get confused by errant DMAs when rebooting.
2325 static void tl_shutdown(dev)
2328 struct tl_softc *sc;
2330 sc = device_get_softc(dev);