2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
38 * the National Semiconductor DP83840A physical interface and the
39 * Microchip Technology 24Cxx series serial EEPROM.
41 * Written using the following four documents:
43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
44 * National Semiconductor DP83840A data sheet (www.national.com)
45 * Microchip Technology 24C02C data sheet (www.microchip.com)
46 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
48 * Written by Bill Paul <wpaul@ctr.columbia.edu>
49 * Electrical Engineering Department
50 * Columbia University, New York City
54 * Some notes about the ThunderLAN:
56 * The ThunderLAN controller is a single chip containing PCI controller
57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
61 * to act as a complete ethernet interface.
63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
65 * in full or half duplex. Some of the Compaq Deskpro machines use a
66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
68 * concert with the ThunderLAN's internal PHY to provide full 10/100
69 * support. This is cheaper than using a standalone external PHY for both
70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
71 * A serial EEPROM is also attached to the ThunderLAN chip to provide
72 * power-up default register settings and for storing the adapter's
73 * station address. Although not supported by this driver, the ThunderLAN
74 * chip can also be connected to token ring PHYs.
76 * The ThunderLAN has a set of registers which can be used to issue
77 * commands, acknowledge interrupts, and to manipulate other internal
78 * registers on its DIO bus. The primary registers can be accessed
79 * using either programmed I/O (inb/outb) or via PCI memory mapping,
80 * depending on how the card is configured during the PCI probing
81 * phase. It is even possible to have both PIO and memory mapped
82 * access turned on at the same time.
84 * Frame reception and transmission with the ThunderLAN chip is done
85 * using frame 'lists.' A list structure looks more or less like this:
88 * u_int32_t fragment_address;
89 * u_int32_t fragment_size;
92 * u_int32_t forward_pointer;
94 * u_int16_t frame_size;
95 * struct tl_frag fragments[10];
98 * The forward pointer in the list header can be either a 0 or the address
99 * of another list, which allows several lists to be linked together. Each
100 * list contains up to 10 fragment descriptors. This means the chip allows
101 * ethernet frames to be broken up into up to 10 chunks for transfer to
102 * and from the SRAM. Note that the forward pointer and fragment buffer
103 * addresses are physical memory addresses, not virtual. Note also that
104 * a single ethernet frame can not span lists: if the host wants to
105 * transmit a frame and the frame data is split up over more than 10
106 * buffers, the frame has to collapsed before it can be transmitted.
108 * To receive frames, the driver sets up a number of lists and populates
109 * the fragment descriptors, then it sends an RX GO command to the chip.
110 * When a frame is received, the chip will DMA it into the memory regions
111 * specified by the fragment descriptors and then trigger an RX 'end of
112 * frame interrupt' when done. The driver may choose to use only one
113 * fragment per list; this may result is slighltly less efficient use
114 * of memory in exchange for improving performance.
116 * To transmit frames, the driver again sets up lists and fragment
117 * descriptors, only this time the buffers contain frame data that
118 * is to be DMA'ed into the chip instead of out of it. Once the chip
119 * has transfered the data into its on-board SRAM, it will trigger a
120 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
121 * interrupt when it reaches the end of the list.
125 * Some notes about this driver:
127 * The ThunderLAN chip provides a couple of different ways to organize
128 * reception, transmission and interrupt handling. The simplest approach
129 * is to use one list each for transmission and reception. In this mode,
130 * the ThunderLAN will generate two interrupts for every received frame
131 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
132 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
133 * performance to have to handle so many interrupts.
135 * Initially I wanted to create a circular list of receive buffers so
136 * that the ThunderLAN chip would think there was an infinitely long
137 * receive channel and never deliver an RXEOC interrupt. However this
138 * doesn't work correctly under heavy load: while the manual says the
139 * chip will trigger an RXEOF interrupt each time a frame is copied into
140 * memory, you can't count on the chip waiting around for you to acknowledge
141 * the interrupt before it starts trying to DMA the next frame. The result
142 * is that the chip might traverse the entire circular list and then wrap
143 * around before you have a chance to do anything about it. Consequently,
144 * the receive list is terminated (with a 0 in the forward pointer in the
145 * last element). Each time an RXEOF interrupt arrives, the used list
146 * is shifted to the end of the list. This gives the appearance of an
147 * infinitely large RX chain so long as the driver doesn't fall behind
148 * the chip and allow all of the lists to be filled up.
150 * If all the lists are filled, the adapter will deliver an RX 'end of
151 * channel' interrupt when it hits the 0 forward pointer at the end of
152 * the chain. The RXEOC handler then cleans out the RX chain and resets
153 * the list head pointer in the ch_parm register and restarts the receiver.
155 * For frame transmission, it is possible to program the ThunderLAN's
156 * transmit interrupt threshold so that the chip can acknowledge multiple
157 * lists with only a single TX EOF interrupt. This allows the driver to
158 * queue several frames in one shot, and only have to handle a total
159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
160 * are transmitted. Frame transmission is done directly out of the
161 * mbufs passed to the tl_start() routine via the interface send queue.
162 * The driver simply sets up the fragment descriptors in the transmit
163 * lists to point to the mbuf data regions and sends a TX GO command.
165 * Note that since the RX and TX lists themselves are always used
166 * only by the driver, the are malloc()ed once at driver initialization
167 * time and never free()ed.
169 * Also, in order to remain as platform independent as possible, this
170 * driver uses memory mapped register access to manipulate the card
171 * as opposed to programmed I/O. This avoids the use of the inb/outb
172 * (and related) instructions which are specific to the i386 platform.
174 * Using these techniques, this driver achieves very high performance
175 * by minimizing the amount of interrupts generated during large
176 * transfers and by completely avoiding buffer copies. Frame transfer
177 * to and from the ThunderLAN chip is performed entirely by the chip
178 * itself thereby reducing the load on the host CPU.
181 #include <sys/param.h>
182 #include <sys/systm.h>
183 #include <sys/sockio.h>
184 #include <sys/mbuf.h>
185 #include <sys/malloc.h>
186 #include <sys/kernel.h>
187 #include <sys/socket.h>
190 #include <net/if_arp.h>
191 #include <net/ethernet.h>
192 #include <net/if_dl.h>
193 #include <net/if_media.h>
197 #include <vm/vm.h> /* for vtophys */
198 #include <vm/pmap.h> /* for vtophys */
199 #include <machine/bus_memio.h>
200 #include <machine/bus_pio.h>
201 #include <machine/bus.h>
202 #include <machine/resource.h>
204 #include <sys/rman.h>
206 #include <dev/mii/mii.h>
207 #include <dev/mii/miivar.h>
209 #include <pci/pcireg.h>
210 #include <pci/pcivar.h>
213 * Default to using PIO register access mode to pacify certain
214 * laptop docking stations with built-in ThunderLAN chips that
215 * don't seem to handle memory mapped mode properly.
217 #define TL_USEIOSPACE
219 #include <pci/if_tlreg.h>
221 MODULE_DEPEND(tl, miibus, 1, 1, 1);
223 /* "controller miibus0" required. See GENERIC if you get errors here. */
224 #include "miibus_if.h"
227 static const char rcsid[] =
232 * Various supported device vendors/types and their names.
235 static struct tl_type tl_devs[] = {
236 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
237 "Texas Instruments ThunderLAN" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
239 "Compaq Netelligent 10" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
241 "Compaq Netelligent 10/100" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
243 "Compaq Netelligent 10/100 Proliant" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
245 "Compaq Netelligent 10/100 Dual Port" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
247 "Compaq NetFlex-3/P Integrated" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
249 "Compaq NetFlex-3/P" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
251 "Compaq NetFlex 3/P w/ BNC" },
252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
253 "Compaq Netelligent 10/100 TX Embedded UTP" },
254 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
255 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
256 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
257 "Compaq Netelligent 10/100 TX UTP" },
258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
259 "Olicom OC-2183/2185" },
260 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
262 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
263 "Olicom OC-2326 10/100 TX UTP" },
267 static int tl_probe __P((device_t));
268 static int tl_attach __P((device_t));
269 static int tl_detach __P((device_t));
270 static int tl_intvec_rxeoc __P((void *, u_int32_t));
271 static int tl_intvec_txeoc __P((void *, u_int32_t));
272 static int tl_intvec_txeof __P((void *, u_int32_t));
273 static int tl_intvec_rxeof __P((void *, u_int32_t));
274 static int tl_intvec_adchk __P((void *, u_int32_t));
275 static int tl_intvec_netsts __P((void *, u_int32_t));
277 static int tl_newbuf __P((struct tl_softc *,
278 struct tl_chain_onefrag *));
279 static void tl_stats_update __P((void *));
280 static int tl_encap __P((struct tl_softc *, struct tl_chain *,
283 static void tl_intr __P((void *));
284 static void tl_start __P((struct ifnet *));
285 static int tl_ioctl __P((struct ifnet *, u_long, caddr_t));
286 static void tl_init __P((void *));
287 static void tl_stop __P((struct tl_softc *));
288 static void tl_watchdog __P((struct ifnet *));
289 static void tl_shutdown __P((device_t));
290 static int tl_ifmedia_upd __P((struct ifnet *));
291 static void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
293 static u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, int));
294 static u_int8_t tl_eeprom_getbyte __P((struct tl_softc *,
296 static int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int));
298 static void tl_mii_sync __P((struct tl_softc *));
299 static void tl_mii_send __P((struct tl_softc *, u_int32_t, int));
300 static int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *));
301 static int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *));
302 static int tl_miibus_readreg __P((device_t, int, int));
303 static int tl_miibus_writereg __P((device_t, int, int, int));
304 static void tl_miibus_statchg __P((device_t));
306 static void tl_setmode __P((struct tl_softc *, int));
307 static int tl_calchash __P((caddr_t));
308 static void tl_setmulti __P((struct tl_softc *));
309 static void tl_setfilt __P((struct tl_softc *, caddr_t, int));
310 static void tl_softreset __P((struct tl_softc *, int));
311 static void tl_hardreset __P((device_t));
312 static int tl_list_rx_init __P((struct tl_softc *));
313 static int tl_list_tx_init __P((struct tl_softc *));
315 static u_int8_t tl_dio_read8 __P((struct tl_softc *, int));
316 static u_int16_t tl_dio_read16 __P((struct tl_softc *, int));
317 static u_int32_t tl_dio_read32 __P((struct tl_softc *, int));
318 static void tl_dio_write8 __P((struct tl_softc *, int, int));
319 static void tl_dio_write16 __P((struct tl_softc *, int, int));
320 static void tl_dio_write32 __P((struct tl_softc *, int, int));
321 static void tl_dio_setbit __P((struct tl_softc *, int, int));
322 static void tl_dio_clrbit __P((struct tl_softc *, int, int));
323 static void tl_dio_setbit16 __P((struct tl_softc *, int, int));
324 static void tl_dio_clrbit16 __P((struct tl_softc *, int, int));
327 #define TL_RES SYS_RES_IOPORT
328 #define TL_RID TL_PCI_LOIO
330 #define TL_RES SYS_RES_MEMORY
331 #define TL_RID TL_PCI_LOMEM
334 static device_method_t tl_methods[] = {
335 /* Device interface */
336 DEVMETHOD(device_probe, tl_probe),
337 DEVMETHOD(device_attach, tl_attach),
338 DEVMETHOD(device_detach, tl_detach),
339 DEVMETHOD(device_shutdown, tl_shutdown),
342 DEVMETHOD(bus_print_child, bus_generic_print_child),
343 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
346 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
347 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
348 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
353 static driver_t tl_driver = {
356 sizeof(struct tl_softc)
359 static devclass_t tl_devclass;
361 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0);
362 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
364 static u_int8_t tl_dio_read8(sc, reg)
368 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
369 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
372 static u_int16_t tl_dio_read16(sc, reg)
376 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
377 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
380 static u_int32_t tl_dio_read32(sc, reg)
384 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
385 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
388 static void tl_dio_write8(sc, reg, val)
393 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
394 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
398 static void tl_dio_write16(sc, reg, val)
403 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
404 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
408 static void tl_dio_write32(sc, reg, val)
413 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
414 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
418 static void tl_dio_setbit(sc, reg, bit)
425 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
426 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
428 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
433 static void tl_dio_clrbit(sc, reg, bit)
440 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
441 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
443 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
448 static void tl_dio_setbit16(sc, reg, bit)
455 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
456 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
458 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
463 static void tl_dio_clrbit16(sc, reg, bit)
470 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
471 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
473 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
479 * Send an instruction or address to the EEPROM, check for ACK.
481 static u_int8_t tl_eeprom_putbyte(sc, byte)
485 register int i, ack = 0;
488 * Make sure we're in TX mode.
490 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
493 * Feed in each bit and stobe the clock.
495 for (i = 0x80; i; i >>= 1) {
497 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
499 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
502 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
504 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
510 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
515 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
516 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
517 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
523 * Read a byte of data stored in the EEPROM at address 'addr.'
525 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
533 tl_dio_write8(sc, TL_NETSIO, 0);
538 * Send write control code to EEPROM.
540 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
541 printf("tl%d: failed to send write command, status: %x\n",
542 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
547 * Send address of byte we want to read.
549 if (tl_eeprom_putbyte(sc, addr)) {
550 printf("tl%d: failed to send address, status: %x\n",
551 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
558 * Send read control code to EEPROM.
560 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
561 printf("tl%d: failed to send write command, status: %x\n",
562 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
567 * Start reading bits from EEPROM.
569 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
570 for (i = 0x80; i; i >>= 1) {
571 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
573 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
575 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
582 * No ACK generated for read, so just return byte.
591 * Read a sequence of bytes from the EEPROM.
593 static int tl_read_eeprom(sc, dest, off, cnt)
602 for (i = 0; i < cnt; i++) {
603 err = tl_eeprom_getbyte(sc, off + i, &byte);
612 static void tl_mii_sync(sc)
617 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
619 for (i = 0; i < 32; i++) {
620 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
621 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
627 static void tl_mii_send(sc, bits, cnt)
634 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
635 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
637 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
639 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
641 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
645 static int tl_mii_readreg(sc, frame)
647 struct tl_mii_frame *frame;
658 * Set up frame for RX.
660 frame->mii_stdelim = TL_MII_STARTDELIM;
661 frame->mii_opcode = TL_MII_READOP;
662 frame->mii_turnaround = 0;
666 * Turn off MII interrupt by forcing MINTEN low.
668 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
670 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
676 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
679 * Send command/address info.
681 tl_mii_send(sc, frame->mii_stdelim, 2);
682 tl_mii_send(sc, frame->mii_opcode, 2);
683 tl_mii_send(sc, frame->mii_phyaddr, 5);
684 tl_mii_send(sc, frame->mii_regaddr, 5);
689 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
692 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
693 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
696 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
697 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
699 /* Complete the cycle */
700 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
703 * Now try reading data bits. If the ack failed, we still
704 * need to clock through 16 cycles to keep the PHYs in sync.
707 for(i = 0; i < 16; i++) {
708 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
709 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
714 for (i = 0x8000; i; i >>= 1) {
715 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
717 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
718 frame->mii_data |= i;
720 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
725 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
726 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
728 /* Reenable interrupts */
730 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
740 static int tl_mii_writereg(sc, frame)
742 struct tl_mii_frame *frame;
752 * Set up frame for TX.
755 frame->mii_stdelim = TL_MII_STARTDELIM;
756 frame->mii_opcode = TL_MII_WRITEOP;
757 frame->mii_turnaround = TL_MII_TURNAROUND;
760 * Turn off MII interrupt by forcing MINTEN low.
762 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
764 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
768 * Turn on data output.
770 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
772 tl_mii_send(sc, frame->mii_stdelim, 2);
773 tl_mii_send(sc, frame->mii_opcode, 2);
774 tl_mii_send(sc, frame->mii_phyaddr, 5);
775 tl_mii_send(sc, frame->mii_regaddr, 5);
776 tl_mii_send(sc, frame->mii_turnaround, 2);
777 tl_mii_send(sc, frame->mii_data, 16);
779 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
780 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
785 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
787 /* Reenable interrupts */
789 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
796 static int tl_miibus_readreg(dev, phy, reg)
801 struct tl_mii_frame frame;
803 sc = device_get_softc(dev);
804 bzero((char *)&frame, sizeof(frame));
806 frame.mii_phyaddr = phy;
807 frame.mii_regaddr = reg;
808 tl_mii_readreg(sc, &frame);
810 return(frame.mii_data);
813 static int tl_miibus_writereg(dev, phy, reg, data)
818 struct tl_mii_frame frame;
820 sc = device_get_softc(dev);
821 bzero((char *)&frame, sizeof(frame));
823 frame.mii_phyaddr = phy;
824 frame.mii_regaddr = reg;
825 frame.mii_data = data;
827 tl_mii_writereg(sc, &frame);
832 static void tl_miibus_statchg(dev)
836 struct mii_data *mii;
838 sc = device_get_softc(dev);
840 mii = device_get_softc(sc->tl_miibus);
842 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
843 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
845 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
853 * Set modes for bitrate devices.
855 static void tl_setmode(sc, media)
859 if (IFM_SUBTYPE(media) == IFM_10_5)
860 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
861 if (IFM_SUBTYPE(media) == IFM_10_T) {
862 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
863 if ((media & IFM_GMASK) == IFM_FDX) {
864 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
865 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
867 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
868 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
876 * Calculate the hash of a MAC address for programming the multicast hash
877 * table. This hash is simply the address split into 6-bit chunks
879 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
880 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
881 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
882 * the folded 24-bit value is split into 6-bit portions and XOR'd.
884 static int tl_calchash(addr)
889 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
891 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
895 * The ThunderLAN has a perfect MAC address filter in addition to
896 * the multicast hash filter. The perfect filter can be programmed
897 * with up to four MAC addresses. The first one is always used to
898 * hold the station address, which leaves us free to use the other
899 * three for multicast addresses.
901 static void tl_setfilt(sc, addr, slot)
909 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
911 for (i = 0; i < ETHER_ADDR_LEN; i++)
912 tl_dio_write8(sc, regaddr + i, *(addr + i));
918 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
919 * linked list. This is fine, except addresses are added from the head
920 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
921 * group to always be in the perfect filter, but as more groups are added,
922 * the 224.0.0.1 entry (which is always added first) gets pushed down
923 * the list and ends up at the tail. So after 3 or 4 multicast groups
924 * are added, the all-hosts entry gets pushed out of the perfect filter
925 * and into the hash table.
927 * Because the multicast list is a doubly-linked list as opposed to a
928 * circular queue, we don't have the ability to just grab the tail of
929 * the list and traverse it backwards. Instead, we have to traverse
930 * the list once to find the tail, then traverse it again backwards to
931 * update the multicast filter.
933 static void tl_setmulti(sc)
937 u_int32_t hashes[2] = { 0, 0 };
939 struct ifmultiaddr *ifma;
940 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
941 ifp = &sc->arpcom.ac_if;
943 /* First, zot all the existing filters. */
944 for (i = 1; i < 4; i++)
945 tl_setfilt(sc, (caddr_t)&dummy, i);
946 tl_dio_write32(sc, TL_HASH1, 0);
947 tl_dio_write32(sc, TL_HASH2, 0);
949 /* Now program new ones. */
950 if (ifp->if_flags & IFF_ALLMULTI) {
951 hashes[0] = 0xFFFFFFFF;
952 hashes[1] = 0xFFFFFFFF;
955 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
956 if (ifma->ifma_addr->sa_family != AF_LINK)
959 * Program the first three multicast groups
960 * into the perfect filter. For all others,
961 * use the hash table.
965 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
971 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
973 hashes[0] |= (1 << h);
975 hashes[1] |= (1 << (h - 32));
979 tl_dio_write32(sc, TL_HASH1, hashes[0]);
980 tl_dio_write32(sc, TL_HASH2, hashes[1]);
986 * This routine is recommended by the ThunderLAN manual to insure that
987 * the internal PHY is powered up correctly. It also recommends a one
988 * second pause at the end to 'wait for the clocks to start' but in my
989 * experience this isn't necessary.
991 static void tl_hardreset(dev)
998 sc = device_get_softc(dev);
1002 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
1004 for (i = 0; i < MII_NPHY; i++)
1005 tl_miibus_writereg(dev, i, MII_BMCR, flags);
1007 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
1009 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
1011 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
1017 static void tl_softreset(sc, internal)
1018 struct tl_softc *sc;
1021 u_int32_t cmd, dummy, i;
1023 /* Assert the adapter reset bit. */
1024 CMD_SET(sc, TL_CMD_ADRST);
1026 /* Turn off interrupts */
1027 CMD_SET(sc, TL_CMD_INTSOFF);
1029 /* First, clear the stats registers. */
1030 for (i = 0; i < 5; i++)
1031 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
1033 /* Clear Areg and Hash registers */
1034 for (i = 0; i < 8; i++)
1035 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
1038 * Set up Netconfig register. Enable one channel and
1039 * one fragment mode.
1041 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
1042 if (internal && !sc->tl_bitrate) {
1043 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1045 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1048 /* Handle cards with bitrate devices. */
1050 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1053 * Load adapter irq pacing timer and tx threshold.
1054 * We make the transmit threshold 1 initially but we may
1055 * change that later.
1057 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1059 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1060 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1061 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1063 /* Unreset the MII */
1064 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1066 /* Take the adapter out of reset */
1067 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1069 /* Wait for things to settle down a little. */
1076 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1077 * against our list and return its name if we find a match.
1079 static int tl_probe(dev)
1086 while(t->tl_name != NULL) {
1087 if ((pci_get_vendor(dev) == t->tl_vid) &&
1088 (pci_get_device(dev) == t->tl_did)) {
1089 device_set_desc(dev, t->tl_name);
1098 static int tl_attach(dev)
1106 struct tl_softc *sc;
1107 int unit, error = 0, rid;
1109 vid = pci_get_vendor(dev);
1110 did = pci_get_device(dev);
1111 sc = device_get_softc(dev);
1112 unit = device_get_unit(dev);
1113 bzero(sc, sizeof(struct tl_softc));
1116 while(t->tl_name != NULL) {
1117 if (vid == t->tl_vid && did == t->tl_did)
1122 if (t->tl_name == NULL) {
1123 printf("tl%d: unknown device!?\n", unit);
1127 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
1131 * Map control/status registers.
1133 pci_enable_busmaster(dev);
1134 pci_enable_io(dev, SYS_RES_IOPORT);
1135 pci_enable_io(dev, SYS_RES_MEMORY);
1136 command = pci_read_config(dev, PCIR_COMMAND, 4);
1138 #ifdef TL_USEIOSPACE
1139 if (!(command & PCIM_CMD_PORTEN)) {
1140 printf("tl%d: failed to enable I/O ports!\n", unit);
1146 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1147 0, ~0, 1, RF_ACTIVE);
1150 * Some cards have the I/O and memory mapped address registers
1151 * reversed. Try both combinations before giving up.
1153 if (sc->tl_res == NULL) {
1155 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1156 0, ~0, 1, RF_ACTIVE);
1159 if (!(command & PCIM_CMD_MEMEN)) {
1160 printf("tl%d: failed to enable memory mapping!\n", unit);
1166 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1167 0, ~0, 1, RF_ACTIVE);
1168 if (sc->tl_res == NULL) {
1170 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1171 0, ~0, 1, RF_ACTIVE);
1175 if (sc->tl_res == NULL) {
1176 printf("tl%d: couldn't map ports/memory\n", unit);
1181 sc->tl_btag = rman_get_bustag(sc->tl_res);
1182 sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
1186 * The ThunderLAN manual suggests jacking the PCI latency
1187 * timer all the way up to its maximum value. I'm not sure
1188 * if this is really necessary, but what the manual wants,
1191 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1192 command |= 0x0000FF00;
1193 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1196 /* Allocate interrupt */
1198 sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1199 RF_SHAREABLE | RF_ACTIVE);
1201 if (sc->tl_irq == NULL) {
1202 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1203 printf("tl%d: couldn't map interrupt\n", unit);
1208 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET,
1209 tl_intr, sc, &sc->tl_intrhand);
1212 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1213 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1214 printf("tl%d: couldn't set up irq\n", unit);
1219 * Now allocate memory for the TX and RX lists.
1221 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1222 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1224 if (sc->tl_ldata == NULL) {
1225 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1226 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1227 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1228 printf("tl%d: no memory for list buffers!\n", unit);
1233 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1237 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1238 sc->tl_eeaddr = TL_EEPROM_EADDR;
1239 if (t->tl_vid == OLICOM_VENDORID)
1240 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1242 /* Reset the adapter. */
1243 tl_softreset(sc, 1);
1245 tl_softreset(sc, 1);
1248 * Get station address from the EEPROM.
1250 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1251 sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1252 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1253 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1254 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1255 contigfree(sc->tl_ldata,
1256 sizeof(struct tl_list_data), M_DEVBUF);
1257 printf("tl%d: failed to read station address\n", unit);
1263 * XXX Olicom, in its desire to be different from the
1264 * rest of the world, has done strange things with the
1265 * encoding of the station address in the EEPROM. First
1266 * of all, they store the address at offset 0xF8 rather
1267 * than at 0x83 like the ThunderLAN manual suggests.
1268 * Second, they store the address in three 16-bit words in
1269 * network byte order, as opposed to storing it sequentially
1270 * like all the other ThunderLAN cards. In order to get
1271 * the station address in a form that matches what the Olicom
1272 * diagnostic utility specifies, we have to byte-swap each
1273 * word. To make things even more confusing, neither 00:00:28
1274 * nor 00:00:24 appear in the IEEE OUI database.
1276 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1277 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1279 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i];
1285 * A ThunderLAN chip was detected. Inform the world.
1287 printf("tl%d: Ethernet address: %6D\n", unit,
1288 sc->arpcom.ac_enaddr, ":");
1290 ifp = &sc->arpcom.ac_if;
1292 ifp->if_unit = sc->tl_unit;
1293 ifp->if_name = "tl";
1294 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1295 ifp->if_ioctl = tl_ioctl;
1296 ifp->if_output = ether_output;
1297 ifp->if_start = tl_start;
1298 ifp->if_watchdog = tl_watchdog;
1299 ifp->if_init = tl_init;
1300 ifp->if_mtu = ETHERMTU;
1301 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1;
1302 callout_handle_init(&sc->tl_stat_ch);
1304 /* Reset the adapter again. */
1305 tl_softreset(sc, 1);
1307 tl_softreset(sc, 1);
1310 * Do MII setup. If no PHYs are found, then this is a
1311 * bitrate ThunderLAN chip that only supports 10baseT
1314 if (mii_phy_probe(dev, &sc->tl_miibus,
1315 tl_ifmedia_upd, tl_ifmedia_sts)) {
1316 struct ifmedia *ifm;
1318 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1319 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1320 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1321 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1322 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1323 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1324 /* Reset again, this time setting bitrate mode. */
1325 tl_softreset(sc, 1);
1327 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1328 tl_ifmedia_upd(ifp);
1332 * Call MI attach routine.
1334 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1340 mtx_destroy(&sc->tl_mtx);
1344 static int tl_detach(dev)
1347 struct tl_softc *sc;
1350 sc = device_get_softc(dev);
1352 ifp = &sc->arpcom.ac_if;
1355 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1357 bus_generic_detach(dev);
1358 device_delete_child(dev, sc->tl_miibus);
1360 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1362 ifmedia_removeall(&sc->ifmedia);
1364 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1365 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1366 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1369 mtx_destroy(&sc->tl_mtx);
1375 * Initialize the transmit lists.
1377 static int tl_list_tx_init(sc)
1378 struct tl_softc *sc;
1380 struct tl_chain_data *cd;
1381 struct tl_list_data *ld;
1386 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1387 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1388 if (i == (TL_TX_LIST_CNT - 1))
1389 cd->tl_tx_chain[i].tl_next = NULL;
1391 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1394 cd->tl_tx_free = &cd->tl_tx_chain[0];
1395 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1402 * Initialize the RX lists and allocate mbufs for them.
1404 static int tl_list_rx_init(sc)
1405 struct tl_softc *sc;
1407 struct tl_chain_data *cd;
1408 struct tl_list_data *ld;
1414 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1415 cd->tl_rx_chain[i].tl_ptr =
1416 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1417 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1419 if (i == (TL_RX_LIST_CNT - 1)) {
1420 cd->tl_rx_chain[i].tl_next = NULL;
1421 ld->tl_rx_list[i].tlist_fptr = 0;
1423 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1424 ld->tl_rx_list[i].tlist_fptr =
1425 vtophys(&ld->tl_rx_list[i + 1]);
1429 cd->tl_rx_head = &cd->tl_rx_chain[0];
1430 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1435 static int tl_newbuf(sc, c)
1436 struct tl_softc *sc;
1437 struct tl_chain_onefrag *c;
1439 struct mbuf *m_new = NULL;
1441 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1445 MCLGET(m_new, M_DONTWAIT);
1446 if (!(m_new->m_flags & M_EXT)) {
1457 c->tl_ptr->tlist_frsize = MCLBYTES;
1458 c->tl_ptr->tlist_fptr = 0;
1459 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1460 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1461 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1466 * Interrupt handler for RX 'end of frame' condition (EOF). This
1467 * tells us that a full ethernet frame has been captured and we need
1470 * Reception is done using 'lists' which consist of a header and a
1471 * series of 10 data count/data address pairs that point to buffers.
1472 * Initially you're supposed to create a list, populate it with pointers
1473 * to buffers, then load the physical address of the list into the
1474 * ch_parm register. The adapter is then supposed to DMA the received
1475 * frame into the buffers for you.
1477 * To make things as fast as possible, we have the chip DMA directly
1478 * into mbufs. This saves us from having to do a buffer copy: we can
1479 * just hand the mbufs directly to ether_input(). Once the frame has
1480 * been sent on its way, the 'list' structure is assigned a new buffer
1481 * and moved to the end of the RX chain. As long we we stay ahead of
1482 * the chip, it will always think it has an endless receive channel.
1484 * If we happen to fall behind and the chip manages to fill up all of
1485 * the buffers, it will generate an end of channel interrupt and wait
1486 * for us to empty the chain and restart the receiver.
1488 static int tl_intvec_rxeof(xsc, type)
1492 struct tl_softc *sc;
1493 int r = 0, total_len = 0;
1494 struct ether_header *eh;
1497 struct tl_chain_onefrag *cur_rx;
1500 ifp = &sc->arpcom.ac_if;
1502 while(sc->tl_cdata.tl_rx_head != NULL) {
1503 cur_rx = sc->tl_cdata.tl_rx_head;
1504 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1507 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1508 m = cur_rx->tl_mbuf;
1509 total_len = cur_rx->tl_ptr->tlist_frsize;
1511 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1513 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1514 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1515 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1519 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1520 vtophys(cur_rx->tl_ptr);
1521 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1522 sc->tl_cdata.tl_rx_tail = cur_rx;
1524 eh = mtod(m, struct ether_header *);
1525 m->m_pkthdr.rcvif = ifp;
1528 * Note: when the ThunderLAN chip is in 'capture all
1529 * frames' mode, it will receive its own transmissions.
1530 * We drop don't need to process our own transmissions,
1531 * so we drop them here and continue.
1533 /*if (ifp->if_flags & IFF_PROMISC && */
1534 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1540 /* Remove header from mbuf and pass it on. */
1541 m->m_pkthdr.len = m->m_len =
1542 total_len - sizeof(struct ether_header);
1543 m->m_data += sizeof(struct ether_header);
1544 ether_input(ifp, eh, m);
1551 * The RX-EOC condition hits when the ch_parm address hasn't been
1552 * initialized or the adapter reached a list with a forward pointer
1553 * of 0 (which indicates the end of the chain). In our case, this means
1554 * the card has hit the end of the receive buffer chain and we need to
1555 * empty out the buffers and shift the pointer back to the beginning again.
1557 static int tl_intvec_rxeoc(xsc, type)
1561 struct tl_softc *sc;
1563 struct tl_chain_data *cd;
1569 /* Flush out the receive queue and ack RXEOF interrupts. */
1570 r = tl_intvec_rxeof(xsc, type);
1571 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1573 cd->tl_rx_head = &cd->tl_rx_chain[0];
1574 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1575 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1576 r |= (TL_CMD_GO|TL_CMD_RT);
1580 static int tl_intvec_txeof(xsc, type)
1584 struct tl_softc *sc;
1586 struct tl_chain *cur_tx;
1591 * Go through our tx list and free mbufs for those
1592 * frames that have been sent.
1594 while (sc->tl_cdata.tl_tx_head != NULL) {
1595 cur_tx = sc->tl_cdata.tl_tx_head;
1596 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1598 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1601 m_freem(cur_tx->tl_mbuf);
1602 cur_tx->tl_mbuf = NULL;
1604 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1605 sc->tl_cdata.tl_tx_free = cur_tx;
1606 if (!cur_tx->tl_ptr->tlist_fptr)
1614 * The transmit end of channel interrupt. The adapter triggers this
1615 * interrupt to tell us it hit the end of the current transmit list.
1617 * A note about this: it's possible for a condition to arise where
1618 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1619 * You have to avoid this since the chip expects things to go in a
1620 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1621 * When the TXEOF handler is called, it will free all of the transmitted
1622 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1623 * interrupt should be received and acknowledged before any more frames
1624 * are queued for transmission. If tl_statrt() is called after TXEOF
1625 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1626 * it could attempt to issue a transmit command prematurely.
1628 * To guard against this, tl_start() will only issue transmit commands
1629 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1630 * can set this flag once tl_start() has cleared it.
1632 static int tl_intvec_txeoc(xsc, type)
1636 struct tl_softc *sc;
1641 ifp = &sc->arpcom.ac_if;
1643 /* Clear the timeout timer. */
1646 if (sc->tl_cdata.tl_tx_head == NULL) {
1647 ifp->if_flags &= ~IFF_OACTIVE;
1648 sc->tl_cdata.tl_tx_tail = NULL;
1652 /* First we have to ack the EOC interrupt. */
1653 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1654 /* Then load the address of the next TX list. */
1655 CSR_WRITE_4(sc, TL_CH_PARM,
1656 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1657 /* Restart TX channel. */
1658 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1660 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1668 static int tl_intvec_adchk(xsc, type)
1672 struct tl_softc *sc;
1677 printf("tl%d: adapter check: %x\n", sc->tl_unit,
1678 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1680 tl_softreset(sc, 1);
1683 CMD_SET(sc, TL_CMD_INTSON);
1688 static int tl_intvec_netsts(xsc, type)
1692 struct tl_softc *sc;
1697 netsts = tl_dio_read16(sc, TL_NETSTS);
1698 tl_dio_write16(sc, TL_NETSTS, netsts);
1700 printf("tl%d: network status: %x\n", sc->tl_unit, netsts);
1705 static void tl_intr(xsc)
1708 struct tl_softc *sc;
1718 /* Disable interrupts */
1719 ints = CSR_READ_2(sc, TL_HOST_INT);
1720 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1721 type = (ints << 16) & 0xFFFF0000;
1722 ivec = (ints & TL_VEC_MASK) >> 5;
1723 ints = (ints & TL_INT_MASK) >> 2;
1725 ifp = &sc->arpcom.ac_if;
1728 case (TL_INTR_INVALID):
1730 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit);
1732 /* Re-enable interrupts but don't ack this one. */
1736 case (TL_INTR_TXEOF):
1737 r = tl_intvec_txeof((void *)sc, type);
1739 case (TL_INTR_TXEOC):
1740 r = tl_intvec_txeoc((void *)sc, type);
1742 case (TL_INTR_STATOFLOW):
1743 tl_stats_update(sc);
1746 case (TL_INTR_RXEOF):
1747 r = tl_intvec_rxeof((void *)sc, type);
1749 case (TL_INTR_DUMMY):
1750 printf("tl%d: got a dummy interrupt\n", sc->tl_unit);
1753 case (TL_INTR_ADCHK):
1755 r = tl_intvec_adchk((void *)sc, type);
1757 r = tl_intvec_netsts((void *)sc, type);
1759 case (TL_INTR_RXEOC):
1760 r = tl_intvec_rxeoc((void *)sc, type);
1763 printf("tl%d: bogus interrupt type\n", ifp->if_unit);
1767 /* Re-enable interrupts */
1769 CMD_PUT(sc, TL_CMD_ACK | r | type);
1772 if (ifp->if_snd.ifq_head != NULL)
1780 static void tl_stats_update(xsc)
1783 struct tl_softc *sc;
1785 struct tl_stats tl_stats;
1786 struct mii_data *mii;
1789 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1793 ifp = &sc->arpcom.ac_if;
1795 p = (u_int32_t *)&tl_stats;
1797 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1798 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1799 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1800 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1801 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1802 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1804 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1805 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1806 tl_stats.tl_tx_multi_collision;
1807 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1808 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1809 tl_rx_overrun(tl_stats);
1810 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1812 if (tl_tx_underrun(tl_stats)) {
1814 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1815 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1818 printf("tl%d: tx underrun -- increasing "
1819 "tx threshold to %d bytes\n", sc->tl_unit,
1820 (64 * (tx_thresh * 4)));
1821 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1822 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1826 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
1828 if (!sc->tl_bitrate) {
1829 mii = device_get_softc(sc->tl_miibus);
1839 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1840 * pointers to the fragment pointers.
1842 static int tl_encap(sc, c, m_head)
1843 struct tl_softc *sc;
1845 struct mbuf *m_head;
1848 struct tl_frag *f = NULL;
1853 * Start packing the mbufs in this chain into
1854 * the fragment pointers. Stop when we run out
1855 * of fragments or hit the end of the mbuf chain.
1860 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1861 if (m->m_len != 0) {
1862 if (frag == TL_MAXFRAGS)
1864 total_len+= m->m_len;
1865 c->tl_ptr->tl_frag[frag].tlist_dadr =
1866 vtophys(mtod(m, vm_offset_t));
1867 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1873 * Handle special cases.
1874 * Special case #1: we used up all 10 fragments, but
1875 * we have more mbufs left in the chain. Copy the
1876 * data into an mbuf cluster. Note that we don't
1877 * bother clearing the values in the other fragment
1878 * pointers/counters; it wouldn't gain us anything,
1879 * and would waste cycles.
1882 struct mbuf *m_new = NULL;
1884 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1885 if (m_new == NULL) {
1886 printf("tl%d: no memory for tx list\n", sc->tl_unit);
1889 if (m_head->m_pkthdr.len > MHLEN) {
1890 MCLGET(m_new, M_DONTWAIT);
1891 if (!(m_new->m_flags & M_EXT)) {
1893 printf("tl%d: no memory for tx list\n",
1898 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1899 mtod(m_new, caddr_t));
1900 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1903 f = &c->tl_ptr->tl_frag[0];
1904 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1905 f->tlist_dcnt = total_len = m_new->m_len;
1910 * Special case #2: the frame is smaller than the minimum
1911 * frame size. We have to pad it to make the chip happy.
1913 if (total_len < TL_MIN_FRAMELEN) {
1914 if (frag == TL_MAXFRAGS)
1915 printf("tl%d: all frags filled but "
1916 "frame still to small!\n", sc->tl_unit);
1917 f = &c->tl_ptr->tl_frag[frag];
1918 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1919 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1920 total_len += f->tlist_dcnt;
1924 c->tl_mbuf = m_head;
1925 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1926 c->tl_ptr->tlist_frsize = total_len;
1927 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1928 c->tl_ptr->tlist_fptr = 0;
1934 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1935 * to the mbuf data regions directly in the transmit lists. We also save a
1936 * copy of the pointers since the transmit list fragment pointers are
1937 * physical addresses.
1939 static void tl_start(ifp)
1942 struct tl_softc *sc;
1943 struct mbuf *m_head = NULL;
1945 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1951 * Check for an available queue slot. If there are none,
1954 if (sc->tl_cdata.tl_tx_free == NULL) {
1955 ifp->if_flags |= IFF_OACTIVE;
1960 start_tx = sc->tl_cdata.tl_tx_free;
1962 while(sc->tl_cdata.tl_tx_free != NULL) {
1963 IF_DEQUEUE(&ifp->if_snd, m_head);
1967 /* Pick a chain member off the free list. */
1968 cur_tx = sc->tl_cdata.tl_tx_free;
1969 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1971 cur_tx->tl_next = NULL;
1973 /* Pack the data into the list. */
1974 tl_encap(sc, cur_tx, m_head);
1976 /* Chain it together */
1978 prev->tl_next = cur_tx;
1979 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1984 * If there's a BPF listener, bounce a copy of this frame
1988 bpf_mtap(ifp, cur_tx->tl_mbuf);
1992 * If there are no packets queued, bail.
1994 if (cur_tx == NULL) {
2000 * That's all we can stands, we can't stands no more.
2001 * If there are no other transfers pending, then issue the
2002 * TX GO command to the adapter to start things moving.
2003 * Otherwise, just leave the data in the queue and let
2004 * the EOF/EOC interrupt handler send.
2006 if (sc->tl_cdata.tl_tx_head == NULL) {
2007 sc->tl_cdata.tl_tx_head = start_tx;
2008 sc->tl_cdata.tl_tx_tail = cur_tx;
2012 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
2013 cmd = CSR_READ_4(sc, TL_HOSTCMD);
2015 cmd |= TL_CMD_GO|TL_CMD_INTSON;
2019 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
2020 sc->tl_cdata.tl_tx_tail = cur_tx;
2024 * Set a timeout in case the chip goes out to lunch.
2032 static void tl_init(xsc)
2035 struct tl_softc *sc = xsc;
2036 struct ifnet *ifp = &sc->arpcom.ac_if;
2037 struct mii_data *mii;
2041 ifp = &sc->arpcom.ac_if;
2044 * Cancel pending I/O.
2048 /* Initialize TX FIFO threshold */
2049 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
2050 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
2052 /* Set PCI burst size */
2053 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
2056 * Set 'capture all frames' bit for promiscuous mode.
2058 if (ifp->if_flags & IFF_PROMISC)
2059 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2061 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2064 * Set capture broadcast bit to capture broadcast frames.
2066 if (ifp->if_flags & IFF_BROADCAST)
2067 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2069 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2071 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
2073 /* Init our MAC address */
2074 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
2076 /* Init multicast filter, if needed. */
2079 /* Init circular RX list. */
2080 if (tl_list_rx_init(sc) == ENOBUFS) {
2081 printf("tl%d: initialization failed: no "
2082 "memory for rx buffers\n", sc->tl_unit);
2088 /* Init TX pointers. */
2089 tl_list_tx_init(sc);
2091 /* Enable PCI interrupts. */
2092 CMD_SET(sc, TL_CMD_INTSON);
2094 /* Load the address of the rx list */
2095 CMD_SET(sc, TL_CMD_RT);
2096 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2098 if (!sc->tl_bitrate) {
2099 if (sc->tl_miibus != NULL) {
2100 mii = device_get_softc(sc->tl_miibus);
2105 /* Send the RX go command */
2106 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2108 ifp->if_flags |= IFF_RUNNING;
2109 ifp->if_flags &= ~IFF_OACTIVE;
2111 /* Start the stats update counter */
2112 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
2119 * Set media options.
2121 static int tl_ifmedia_upd(ifp)
2124 struct tl_softc *sc;
2125 struct mii_data *mii = NULL;
2130 tl_setmode(sc, sc->ifmedia.ifm_media);
2132 mii = device_get_softc(sc->tl_miibus);
2140 * Report current media status.
2142 static void tl_ifmedia_sts(ifp, ifmr)
2144 struct ifmediareq *ifmr;
2146 struct tl_softc *sc;
2147 struct mii_data *mii;
2151 ifmr->ifm_active = IFM_ETHER;
2153 if (sc->tl_bitrate) {
2154 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2155 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2157 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2158 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2159 ifmr->ifm_active |= IFM_HDX;
2161 ifmr->ifm_active |= IFM_FDX;
2164 mii = device_get_softc(sc->tl_miibus);
2166 ifmr->ifm_active = mii->mii_media_active;
2167 ifmr->ifm_status = mii->mii_media_status;
2173 static int tl_ioctl(ifp, command, data)
2178 struct tl_softc *sc = ifp->if_softc;
2179 struct ifreq *ifr = (struct ifreq *) data;
2188 error = ether_ioctl(ifp, command, data);
2191 if (ifp->if_flags & IFF_UP) {
2192 if (ifp->if_flags & IFF_RUNNING &&
2193 ifp->if_flags & IFF_PROMISC &&
2194 !(sc->tl_if_flags & IFF_PROMISC)) {
2195 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2197 } else if (ifp->if_flags & IFF_RUNNING &&
2198 !(ifp->if_flags & IFF_PROMISC) &&
2199 sc->tl_if_flags & IFF_PROMISC) {
2200 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2205 if (ifp->if_flags & IFF_RUNNING) {
2209 sc->tl_if_flags = ifp->if_flags;
2220 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2222 struct mii_data *mii;
2223 mii = device_get_softc(sc->tl_miibus);
2224 error = ifmedia_ioctl(ifp, ifr,
2225 &mii->mii_media, command);
2238 static void tl_watchdog(ifp)
2241 struct tl_softc *sc;
2245 printf("tl%d: device timeout\n", sc->tl_unit);
2249 tl_softreset(sc, 1);
2256 * Stop the adapter and free any mbufs allocated to the
2259 static void tl_stop(sc)
2260 struct tl_softc *sc;
2267 ifp = &sc->arpcom.ac_if;
2269 /* Stop the stats updater. */
2270 untimeout(tl_stats_update, sc, sc->tl_stat_ch);
2272 /* Stop the transmitter */
2273 CMD_CLR(sc, TL_CMD_RT);
2274 CMD_SET(sc, TL_CMD_STOP);
2275 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2277 /* Stop the receiver */
2278 CMD_SET(sc, TL_CMD_RT);
2279 CMD_SET(sc, TL_CMD_STOP);
2280 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2283 * Disable host interrupts.
2285 CMD_SET(sc, TL_CMD_INTSOFF);
2288 * Clear list pointer.
2290 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2293 * Free the RX lists.
2295 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2296 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2297 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2298 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2301 bzero((char *)&sc->tl_ldata->tl_rx_list,
2302 sizeof(sc->tl_ldata->tl_rx_list));
2305 * Free the TX list buffers.
2307 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2308 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2309 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2310 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2313 bzero((char *)&sc->tl_ldata->tl_tx_list,
2314 sizeof(sc->tl_ldata->tl_tx_list));
2316 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2323 * Stop all chip I/O so that the kernel's probe routines don't
2324 * get confused by errant DMAs when rebooting.
2326 static void tl_shutdown(dev)
2329 struct tl_softc *sc;
2331 sc = device_get_softc(dev);