2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Winbond fast ethernet PCI NIC driver
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
92 #include <sys/malloc.h>
93 #include <sys/module.h>
94 #include <sys/kernel.h>
95 #include <sys/socket.h>
96 #include <sys/queue.h>
99 #include <net/if_arp.h>
100 #include <net/ethernet.h>
101 #include <net/if_dl.h>
102 #include <net/if_media.h>
103 #include <net/if_types.h>
107 #include <vm/vm.h> /* for vtophys */
108 #include <vm/pmap.h> /* for vtophys */
109 #include <machine/bus.h>
110 #include <machine/resource.h>
112 #include <sys/rman.h>
114 #include <dev/pci/pcireg.h>
115 #include <dev/pci/pcivar.h>
117 #include <dev/mii/mii.h>
118 #include <dev/mii/miivar.h>
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
123 #define WB_USEIOSPACE
125 #include <pci/if_wbreg.h>
127 MODULE_DEPEND(wb, pci, 1, 1, 1);
128 MODULE_DEPEND(wb, ether, 1, 1, 1);
129 MODULE_DEPEND(wb, miibus, 1, 1, 1);
132 * Various supported device vendors/types and their names.
134 static struct wb_type wb_devs[] = {
135 { WB_VENDORID, WB_DEVICEID_840F,
136 "Winbond W89C840F 10/100BaseTX" },
137 { CP_VENDORID, CP_DEVICEID_RL100,
138 "Compex RL100-ATX 10/100baseTX" },
142 static int wb_probe(device_t);
143 static int wb_attach(device_t);
144 static int wb_detach(device_t);
146 static void wb_bfree(void *addr, void *args);
147 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
149 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
151 static void wb_rxeof(struct wb_softc *);
152 static void wb_rxeoc(struct wb_softc *);
153 static void wb_txeof(struct wb_softc *);
154 static void wb_txeoc(struct wb_softc *);
155 static void wb_intr(void *);
156 static void wb_tick(void *);
157 static void wb_start(struct ifnet *);
158 static int wb_ioctl(struct ifnet *, u_long, caddr_t);
159 static void wb_init(void *);
160 static void wb_stop(struct wb_softc *);
161 static void wb_watchdog(struct ifnet *);
162 static void wb_shutdown(device_t);
163 static int wb_ifmedia_upd(struct ifnet *);
164 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
166 static void wb_eeprom_putbyte(struct wb_softc *, int);
167 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
168 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
169 static void wb_mii_sync(struct wb_softc *);
170 static void wb_mii_send(struct wb_softc *, u_int32_t, int);
171 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
172 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
174 static void wb_setcfg(struct wb_softc *, u_int32_t);
175 static void wb_setmulti(struct wb_softc *);
176 static void wb_reset(struct wb_softc *);
177 static void wb_fixmedia(struct wb_softc *);
178 static int wb_list_rx_init(struct wb_softc *);
179 static int wb_list_tx_init(struct wb_softc *);
181 static int wb_miibus_readreg(device_t, int, int);
182 static int wb_miibus_writereg(device_t, int, int, int);
183 static void wb_miibus_statchg(device_t);
186 #define WB_RES SYS_RES_IOPORT
187 #define WB_RID WB_PCI_LOIO
189 #define WB_RES SYS_RES_MEMORY
190 #define WB_RID WB_PCI_LOMEM
193 static device_method_t wb_methods[] = {
194 /* Device interface */
195 DEVMETHOD(device_probe, wb_probe),
196 DEVMETHOD(device_attach, wb_attach),
197 DEVMETHOD(device_detach, wb_detach),
198 DEVMETHOD(device_shutdown, wb_shutdown),
200 /* bus interface, for miibus */
201 DEVMETHOD(bus_print_child, bus_generic_print_child),
202 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
205 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
206 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
207 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
211 static driver_t wb_driver = {
214 sizeof(struct wb_softc)
217 static devclass_t wb_devclass;
219 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
220 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
222 #define WB_SETBIT(sc, reg, x) \
223 CSR_WRITE_4(sc, reg, \
224 CSR_READ_4(sc, reg) | (x))
226 #define WB_CLRBIT(sc, reg, x) \
227 CSR_WRITE_4(sc, reg, \
228 CSR_READ_4(sc, reg) & ~(x))
231 CSR_WRITE_4(sc, WB_SIO, \
232 CSR_READ_4(sc, WB_SIO) | (x))
235 CSR_WRITE_4(sc, WB_SIO, \
236 CSR_READ_4(sc, WB_SIO) & ~(x))
239 * Send a read command and address to the EEPROM, check for ACK.
242 wb_eeprom_putbyte(sc, addr)
248 d = addr | WB_EECMD_READ;
251 * Feed in each bit and stobe the clock.
253 for (i = 0x400; i; i >>= 1) {
255 SIO_SET(WB_SIO_EE_DATAIN);
257 SIO_CLR(WB_SIO_EE_DATAIN);
260 SIO_SET(WB_SIO_EE_CLK);
262 SIO_CLR(WB_SIO_EE_CLK);
270 * Read a word of data stored in the EEPROM at address 'addr.'
273 wb_eeprom_getword(sc, addr, dest)
281 /* Enter EEPROM access mode. */
282 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
285 * Send address of word we want to read.
287 wb_eeprom_putbyte(sc, addr);
289 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
292 * Start reading bits from EEPROM.
294 for (i = 0x8000; i; i >>= 1) {
295 SIO_SET(WB_SIO_EE_CLK);
297 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
299 SIO_CLR(WB_SIO_EE_CLK);
303 /* Turn off EEPROM access mode. */
304 CSR_WRITE_4(sc, WB_SIO, 0);
312 * Read a sequence of words from the EEPROM.
315 wb_read_eeprom(sc, dest, off, cnt, swap)
323 u_int16_t word = 0, *ptr;
325 for (i = 0; i < cnt; i++) {
326 wb_eeprom_getword(sc, off + i, &word);
327 ptr = (u_int16_t *)(dest + (i * 2));
338 * Sync the PHYs by setting data bit and strobing the clock 32 times.
346 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
348 for (i = 0; i < 32; i++) {
349 SIO_SET(WB_SIO_MII_CLK);
351 SIO_CLR(WB_SIO_MII_CLK);
359 * Clock a series of bits through the MII.
362 wb_mii_send(sc, bits, cnt)
369 SIO_CLR(WB_SIO_MII_CLK);
371 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
373 SIO_SET(WB_SIO_MII_DATAIN);
375 SIO_CLR(WB_SIO_MII_DATAIN);
378 SIO_CLR(WB_SIO_MII_CLK);
380 SIO_SET(WB_SIO_MII_CLK);
385 * Read an PHY register through the MII.
388 wb_mii_readreg(sc, frame)
390 struct wb_mii_frame *frame;
398 * Set up frame for RX.
400 frame->mii_stdelim = WB_MII_STARTDELIM;
401 frame->mii_opcode = WB_MII_READOP;
402 frame->mii_turnaround = 0;
405 CSR_WRITE_4(sc, WB_SIO, 0);
410 SIO_SET(WB_SIO_MII_DIR);
415 * Send command/address info.
417 wb_mii_send(sc, frame->mii_stdelim, 2);
418 wb_mii_send(sc, frame->mii_opcode, 2);
419 wb_mii_send(sc, frame->mii_phyaddr, 5);
420 wb_mii_send(sc, frame->mii_regaddr, 5);
423 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
425 SIO_SET(WB_SIO_MII_CLK);
429 SIO_CLR(WB_SIO_MII_DIR);
431 SIO_CLR(WB_SIO_MII_CLK);
433 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
434 SIO_SET(WB_SIO_MII_CLK);
436 SIO_CLR(WB_SIO_MII_CLK);
438 SIO_SET(WB_SIO_MII_CLK);
442 * Now try reading data bits. If the ack failed, we still
443 * need to clock through 16 cycles to keep the PHY(s) in sync.
446 for(i = 0; i < 16; i++) {
447 SIO_CLR(WB_SIO_MII_CLK);
449 SIO_SET(WB_SIO_MII_CLK);
455 for (i = 0x8000; i; i >>= 1) {
456 SIO_CLR(WB_SIO_MII_CLK);
459 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
460 frame->mii_data |= i;
463 SIO_SET(WB_SIO_MII_CLK);
469 SIO_CLR(WB_SIO_MII_CLK);
471 SIO_SET(WB_SIO_MII_CLK);
482 * Write to a PHY register through the MII.
485 wb_mii_writereg(sc, frame)
487 struct wb_mii_frame *frame;
493 * Set up frame for TX.
496 frame->mii_stdelim = WB_MII_STARTDELIM;
497 frame->mii_opcode = WB_MII_WRITEOP;
498 frame->mii_turnaround = WB_MII_TURNAROUND;
501 * Turn on data output.
503 SIO_SET(WB_SIO_MII_DIR);
507 wb_mii_send(sc, frame->mii_stdelim, 2);
508 wb_mii_send(sc, frame->mii_opcode, 2);
509 wb_mii_send(sc, frame->mii_phyaddr, 5);
510 wb_mii_send(sc, frame->mii_regaddr, 5);
511 wb_mii_send(sc, frame->mii_turnaround, 2);
512 wb_mii_send(sc, frame->mii_data, 16);
515 SIO_SET(WB_SIO_MII_CLK);
517 SIO_CLR(WB_SIO_MII_CLK);
523 SIO_CLR(WB_SIO_MII_DIR);
531 wb_miibus_readreg(dev, phy, reg)
536 struct wb_mii_frame frame;
538 sc = device_get_softc(dev);
540 bzero((char *)&frame, sizeof(frame));
542 frame.mii_phyaddr = phy;
543 frame.mii_regaddr = reg;
544 wb_mii_readreg(sc, &frame);
546 return(frame.mii_data);
550 wb_miibus_writereg(dev, phy, reg, data)
555 struct wb_mii_frame frame;
557 sc = device_get_softc(dev);
559 bzero((char *)&frame, sizeof(frame));
561 frame.mii_phyaddr = phy;
562 frame.mii_regaddr = reg;
563 frame.mii_data = data;
565 wb_mii_writereg(sc, &frame);
571 wb_miibus_statchg(dev)
575 struct mii_data *mii;
577 sc = device_get_softc(dev);
579 mii = device_get_softc(sc->wb_miibus);
580 wb_setcfg(sc, mii->mii_media_active);
587 * Program the 64-bit multicast hash filter.
595 u_int32_t hashes[2] = { 0, 0 };
596 struct ifmultiaddr *ifma;
602 rxfilt = CSR_READ_4(sc, WB_NETCFG);
604 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
605 rxfilt |= WB_NETCFG_RX_MULTI;
606 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
607 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
608 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
612 /* first, zot all the existing hash bits */
613 CSR_WRITE_4(sc, WB_MAR0, 0);
614 CSR_WRITE_4(sc, WB_MAR1, 0);
616 /* now program new ones */
618 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
619 if (ifma->ifma_addr->sa_family != AF_LINK)
621 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
622 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
624 hashes[0] |= (1 << h);
626 hashes[1] |= (1 << (h - 32));
632 rxfilt |= WB_NETCFG_RX_MULTI;
634 rxfilt &= ~WB_NETCFG_RX_MULTI;
636 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
637 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
638 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
644 * The Winbond manual states that in order to fiddle with the
645 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
646 * first have to put the transmit and/or receive logic in the idle state.
655 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
657 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
659 for (i = 0; i < WB_TIMEOUT; i++) {
661 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
662 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
667 printf("wb%d: failed to force tx and "
668 "rx to idle state\n", sc->wb_unit);
671 if (IFM_SUBTYPE(media) == IFM_10_T)
672 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
674 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
676 if ((media & IFM_GMASK) == IFM_FDX)
677 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
679 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
682 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
692 struct mii_data *mii;
694 CSR_WRITE_4(sc, WB_NETCFG, 0);
695 CSR_WRITE_4(sc, WB_BUSCTL, 0);
696 CSR_WRITE_4(sc, WB_TXADDR, 0);
697 CSR_WRITE_4(sc, WB_RXADDR, 0);
699 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
700 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
702 for (i = 0; i < WB_TIMEOUT; i++) {
704 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
708 printf("wb%d: reset never completed!\n", sc->wb_unit);
710 /* Wait a little while for the chip to get its brains in order. */
713 if (sc->wb_miibus == NULL)
716 mii = device_get_softc(sc->wb_miibus);
720 if (mii->mii_instance) {
721 struct mii_softc *miisc;
722 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
723 mii_phy_reset(miisc);
733 struct mii_data *mii = NULL;
737 if (sc->wb_miibus == NULL)
740 mii = device_get_softc(sc->wb_miibus);
744 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
745 media = mii->mii_media_active & ~IFM_10_T;
747 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
748 media = mii->mii_media_active & ~IFM_100_TX;
753 ifmedia_set(&mii->mii_media, media);
759 * Probe for a Winbond chip. Check the PCI vendor and device
760 * IDs against our list and return a device name if we find a match.
770 while(t->wb_name != NULL) {
771 if ((pci_get_vendor(dev) == t->wb_vid) &&
772 (pci_get_device(dev) == t->wb_did)) {
773 device_set_desc(dev, t->wb_name);
774 return (BUS_PROBE_DEFAULT);
783 * Attach the interface. Allocate softc structures, do ifmedia
784 * setup and ethernet/BPF attach.
790 u_char eaddr[ETHER_ADDR_LEN];
793 int unit, error = 0, rid;
795 sc = device_get_softc(dev);
796 unit = device_get_unit(dev);
798 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
799 MTX_DEF | MTX_RECURSE);
801 * Map control/status registers.
803 pci_enable_busmaster(dev);
806 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
808 if (sc->wb_res == NULL) {
809 printf("wb%d: couldn't map ports/memory\n", unit);
814 sc->wb_btag = rman_get_bustag(sc->wb_res);
815 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
817 /* Allocate interrupt */
819 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
820 RF_SHAREABLE | RF_ACTIVE);
822 if (sc->wb_irq == NULL) {
823 printf("wb%d: couldn't map interrupt\n", unit);
828 /* Save the cache line size. */
829 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
831 /* Reset the adapter. */
835 * Get station address from the EEPROM.
837 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
841 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
842 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
844 if (sc->wb_ldata == NULL) {
845 printf("wb%d: no memory for list buffers!\n", unit);
850 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
852 ifp = sc->wb_ifp = if_alloc(IFT_ETHER);
854 printf("wb%d: can not if_alloc()\n", unit);
859 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
860 ifp->if_mtu = ETHERMTU;
861 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
863 ifp->if_ioctl = wb_ioctl;
864 ifp->if_start = wb_start;
865 ifp->if_watchdog = wb_watchdog;
866 ifp->if_init = wb_init;
867 ifp->if_baudrate = 10000000;
868 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
873 if (mii_phy_probe(dev, &sc->wb_miibus,
874 wb_ifmedia_upd, wb_ifmedia_sts)) {
880 * Call MI attach routine.
882 ether_ifattach(ifp, eaddr);
884 /* Hook interrupt last to avoid having to lock softc */
885 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
886 wb_intr, sc, &sc->wb_intrhand);
889 printf("wb%d: couldn't set up irq\n", unit);
903 * Shutdown hardware and free up resources. This can be called any
904 * time after the mutex has been initialized. It is called in both
905 * the error case in attach and the normal detach case so it needs
906 * to be careful about only freeing resources that have actually been
916 sc = device_get_softc(dev);
917 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized"));
922 * Delete any miibus and phy devices attached to this interface.
923 * This should only be done if attach succeeded.
925 if (device_is_attached(dev)) {
931 device_delete_child(dev, sc->wb_miibus);
932 bus_generic_detach(dev);
935 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
939 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
942 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8,
947 mtx_destroy(&sc->wb_mtx);
953 * Initialize the transmit descriptors.
959 struct wb_chain_data *cd;
960 struct wb_list_data *ld;
966 for (i = 0; i < WB_TX_LIST_CNT; i++) {
967 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
968 if (i == (WB_TX_LIST_CNT - 1)) {
969 cd->wb_tx_chain[i].wb_nextdesc =
972 cd->wb_tx_chain[i].wb_nextdesc =
973 &cd->wb_tx_chain[i + 1];
977 cd->wb_tx_free = &cd->wb_tx_chain[0];
978 cd->wb_tx_tail = cd->wb_tx_head = NULL;
985 * Initialize the RX descriptors and allocate mbufs for them. Note that
986 * we arrange the descriptors in a closed ring, so that the last descriptor
987 * points back to the first.
993 struct wb_chain_data *cd;
994 struct wb_list_data *ld;
1000 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1001 cd->wb_rx_chain[i].wb_ptr =
1002 (struct wb_desc *)&ld->wb_rx_list[i];
1003 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
1004 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1006 if (i == (WB_RX_LIST_CNT - 1)) {
1007 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1008 ld->wb_rx_list[i].wb_next =
1009 vtophys(&ld->wb_rx_list[0]);
1011 cd->wb_rx_chain[i].wb_nextdesc =
1012 &cd->wb_rx_chain[i + 1];
1013 ld->wb_rx_list[i].wb_next =
1014 vtophys(&ld->wb_rx_list[i + 1]);
1018 cd->wb_rx_head = &cd->wb_rx_chain[0];
1032 * Initialize an RX descriptor and attach an MBUF cluster.
1036 struct wb_softc *sc;
1037 struct wb_chain_onefrag *c;
1040 struct mbuf *m_new = NULL;
1043 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1046 m_new->m_data = c->wb_buf;
1047 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
1048 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0,
1052 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1053 m_new->m_data = m_new->m_ext.ext_buf;
1056 m_adj(m_new, sizeof(u_int64_t));
1059 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1060 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1061 c->wb_ptr->wb_status = WB_RXSTAT;
1067 * A frame has been uploaded: pass the resulting mbuf chain up to
1068 * the higher level protocols.
1072 struct wb_softc *sc;
1074 struct mbuf *m = NULL;
1076 struct wb_chain_onefrag *cur_rx;
1084 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1086 struct mbuf *m0 = NULL;
1088 cur_rx = sc->wb_cdata.wb_rx_head;
1089 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1091 m = cur_rx->wb_mbuf;
1093 if ((rxstat & WB_RXSTAT_MIIERR) ||
1094 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1095 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1096 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1097 !(rxstat & WB_RXSTAT_RXCMP)) {
1099 wb_newbuf(sc, cur_rx, m);
1100 printf("wb%x: receiver babbling: possible chip "
1101 "bug, forcing reset\n", sc->wb_unit);
1108 if (rxstat & WB_RXSTAT_RXERR) {
1110 wb_newbuf(sc, cur_rx, m);
1114 /* No errors; receive the packet. */
1115 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1118 * XXX The Winbond chip includes the CRC with every
1119 * received frame, and there's no way to turn this
1120 * behavior off (at least, I can't find anything in
1121 * the manual that explains how to do it) so we have
1122 * to trim off the CRC manually.
1124 total_len -= ETHER_CRC_LEN;
1126 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
1128 wb_newbuf(sc, cur_rx, m);
1137 (*ifp->if_input)(ifp, m);
1144 struct wb_softc *sc;
1148 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1149 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1150 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1151 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1152 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1158 * A frame was downloaded to the chip. It's safe for us to clean up
1163 struct wb_softc *sc;
1165 struct wb_chain *cur_tx;
1170 /* Clear the timeout timer. */
1173 if (sc->wb_cdata.wb_tx_head == NULL)
1177 * Go through our tx list and free mbufs for those
1178 * frames that have been transmitted.
1180 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1183 cur_tx = sc->wb_cdata.wb_tx_head;
1184 txstat = WB_TXSTATUS(cur_tx);
1186 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1189 if (txstat & WB_TXSTAT_TXERR) {
1191 if (txstat & WB_TXSTAT_ABORT)
1192 ifp->if_collisions++;
1193 if (txstat & WB_TXSTAT_LATECOLL)
1194 ifp->if_collisions++;
1197 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1200 m_freem(cur_tx->wb_mbuf);
1201 cur_tx->wb_mbuf = NULL;
1203 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1204 sc->wb_cdata.wb_tx_head = NULL;
1205 sc->wb_cdata.wb_tx_tail = NULL;
1209 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1216 * TX 'end of channel' interrupt handler.
1220 struct wb_softc *sc;
1228 if (sc->wb_cdata.wb_tx_head == NULL) {
1229 ifp->if_flags &= ~IFF_OACTIVE;
1230 sc->wb_cdata.wb_tx_tail = NULL;
1232 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1233 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1235 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1246 struct wb_softc *sc;
1254 if (!(ifp->if_flags & IFF_UP)) {
1259 /* Disable interrupts. */
1260 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1264 status = CSR_READ_4(sc, WB_ISR);
1266 CSR_WRITE_4(sc, WB_ISR, status);
1268 if ((status & WB_INTRS) == 0)
1271 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1274 if (status & WB_ISR_RX_ERR)
1280 if (status & WB_ISR_RX_OK)
1283 if (status & WB_ISR_RX_IDLE)
1286 if (status & WB_ISR_TX_OK)
1289 if (status & WB_ISR_TX_NOBUF)
1292 if (status & WB_ISR_TX_IDLE) {
1294 if (sc->wb_cdata.wb_tx_head != NULL) {
1295 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1296 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1300 if (status & WB_ISR_TX_UNDERRUN) {
1303 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1304 /* Jack up TX threshold */
1305 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1306 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1307 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1308 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1311 if (status & WB_ISR_BUS_ERR) {
1318 /* Re-enable interrupts. */
1319 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1321 if (ifp->if_snd.ifq_head != NULL) {
1334 struct wb_softc *sc;
1335 struct mii_data *mii;
1339 mii = device_get_softc(sc->wb_miibus);
1343 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1351 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1352 * pointers to the fragment pointers.
1355 wb_encap(sc, c, m_head)
1356 struct wb_softc *sc;
1358 struct mbuf *m_head;
1361 struct wb_desc *f = NULL;
1366 * Start packing the mbufs in this chain into
1367 * the fragment pointers. Stop when we run out
1368 * of fragments or hit the end of the mbuf chain.
1373 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1374 if (m->m_len != 0) {
1375 if (frag == WB_MAXFRAGS)
1377 total_len += m->m_len;
1378 f = &c->wb_ptr->wb_frag[frag];
1379 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1381 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1384 f->wb_status = WB_TXSTAT_OWN;
1385 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1386 f->wb_data = vtophys(mtod(m, vm_offset_t));
1392 * Handle special case: we used up all 16 fragments,
1393 * but we have more mbufs left in the chain. Copy the
1394 * data into an mbuf cluster. Note that we don't
1395 * bother clearing the values in the other fragment
1396 * pointers/counters; it wouldn't gain us anything,
1397 * and would waste cycles.
1400 struct mbuf *m_new = NULL;
1402 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1405 if (m_head->m_pkthdr.len > MHLEN) {
1406 MCLGET(m_new, M_DONTWAIT);
1407 if (!(m_new->m_flags & M_EXT)) {
1412 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1413 mtod(m_new, caddr_t));
1414 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1417 f = &c->wb_ptr->wb_frag[0];
1419 f->wb_data = vtophys(mtod(m_new, caddr_t));
1420 f->wb_ctl = total_len = m_new->m_len;
1421 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1425 if (total_len < WB_MIN_FRAMELEN) {
1426 f = &c->wb_ptr->wb_frag[frag];
1427 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1428 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1429 f->wb_ctl |= WB_TXCTL_TLINK;
1430 f->wb_status = WB_TXSTAT_OWN;
1434 c->wb_mbuf = m_head;
1435 c->wb_lastdesc = frag - 1;
1436 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1437 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1443 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1444 * to the mbuf data regions directly in the transmit lists. We also save a
1445 * copy of the pointers since the transmit list fragment pointers are
1446 * physical addresses.
1453 struct wb_softc *sc;
1454 struct mbuf *m_head = NULL;
1455 struct wb_chain *cur_tx = NULL, *start_tx;
1461 * Check for an available queue slot. If there are none,
1464 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1465 ifp->if_flags |= IFF_OACTIVE;
1470 start_tx = sc->wb_cdata.wb_tx_free;
1472 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1473 IF_DEQUEUE(&ifp->if_snd, m_head);
1477 /* Pick a descriptor off the free list. */
1478 cur_tx = sc->wb_cdata.wb_tx_free;
1479 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1481 /* Pack the data into the descriptor. */
1482 wb_encap(sc, cur_tx, m_head);
1484 if (cur_tx != start_tx)
1485 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1488 * If there's a BPF listener, bounce a copy of this frame
1491 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1495 * If there are no packets queued, bail.
1497 if (cur_tx == NULL) {
1503 * Place the request for the upload interrupt
1504 * in the last descriptor in the chain. This way, if
1505 * we're chaining several packets at once, we'll only
1506 * get an interupt once for the whole chain rather than
1507 * once for each packet.
1509 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1510 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1511 sc->wb_cdata.wb_tx_tail = cur_tx;
1513 if (sc->wb_cdata.wb_tx_head == NULL) {
1514 sc->wb_cdata.wb_tx_head = start_tx;
1515 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1516 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1519 * We need to distinguish between the case where
1520 * the own bit is clear because the chip cleared it
1521 * and where the own bit is clear because we haven't
1522 * set it yet. The magic value WB_UNSET is just some
1523 * ramdomly chosen number which doesn't have the own
1524 * bit set. When we actually transmit the frame, the
1525 * status word will have _only_ the own bit set, so
1526 * the txeoc handler will be able to tell if it needs
1527 * to initiate another transmission to flush out pending
1530 WB_TXOWN(start_tx) = WB_UNSENT;
1534 * Set a timeout in case the chip goes out to lunch.
1546 struct wb_softc *sc = xsc;
1547 struct ifnet *ifp = sc->wb_ifp;
1549 struct mii_data *mii;
1552 mii = device_get_softc(sc->wb_miibus);
1555 * Cancel pending I/O and free all RX/TX buffers.
1560 sc->wb_txthresh = WB_TXTHRESH_INIT;
1563 * Set cache alignment and burst length.
1566 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1567 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1568 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1571 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1572 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1573 switch(sc->wb_cachesize) {
1575 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1578 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1581 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1585 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1589 /* This doesn't tend to work too well at 100Mbps. */
1590 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1592 /* Init our MAC address */
1593 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1594 CSR_WRITE_1(sc, WB_NODE0 + i, IFP2ENADDR(sc->wb_ifp)[i]);
1597 /* Init circular RX list. */
1598 if (wb_list_rx_init(sc) == ENOBUFS) {
1599 printf("wb%d: initialization failed: no "
1600 "memory for rx buffers\n", sc->wb_unit);
1606 /* Init TX descriptors. */
1607 wb_list_tx_init(sc);
1609 /* If we want promiscuous mode, set the allframes bit. */
1610 if (ifp->if_flags & IFF_PROMISC) {
1611 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1613 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1617 * Set capture broadcast bit to capture broadcast frames.
1619 if (ifp->if_flags & IFF_BROADCAST) {
1620 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1622 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1626 * Program the multicast filter, if necessary.
1631 * Load the address of the RX list.
1633 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1634 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1637 * Enable interrupts.
1639 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1640 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1642 /* Enable receiver and transmitter. */
1643 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1644 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1646 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1647 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1648 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1652 ifp->if_flags |= IFF_RUNNING;
1653 ifp->if_flags &= ~IFF_OACTIVE;
1655 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1662 * Set media options.
1668 struct wb_softc *sc;
1672 if (ifp->if_flags & IFF_UP)
1679 * Report current media status.
1682 wb_ifmedia_sts(ifp, ifmr)
1684 struct ifmediareq *ifmr;
1686 struct wb_softc *sc;
1687 struct mii_data *mii;
1691 mii = device_get_softc(sc->wb_miibus);
1694 ifmr->ifm_active = mii->mii_media_active;
1695 ifmr->ifm_status = mii->mii_media_status;
1701 wb_ioctl(ifp, command, data)
1706 struct wb_softc *sc = ifp->if_softc;
1707 struct mii_data *mii;
1708 struct ifreq *ifr = (struct ifreq *) data;
1715 if (ifp->if_flags & IFF_UP) {
1718 if (ifp->if_flags & IFF_RUNNING)
1730 mii = device_get_softc(sc->wb_miibus);
1731 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1734 error = ether_ioctl(ifp, command, data);
1747 struct wb_softc *sc;
1753 printf("wb%d: watchdog timeout\n", sc->wb_unit);
1755 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1756 printf("wb%d: no carrier - transceiver cable problem?\n",
1763 if (ifp->if_snd.ifq_head != NULL)
1771 * Stop the adapter and free any mbufs allocated to the
1776 struct wb_softc *sc;
1785 untimeout(wb_tick, sc, sc->wb_stat_ch);
1787 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1788 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1789 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1790 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1793 * Free data in the RX lists.
1795 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1796 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1797 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1798 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1801 bzero((char *)&sc->wb_ldata->wb_rx_list,
1802 sizeof(sc->wb_ldata->wb_rx_list));
1805 * Free the TX list buffers.
1807 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1808 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1809 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1810 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1814 bzero((char *)&sc->wb_ldata->wb_tx_list,
1815 sizeof(sc->wb_ldata->wb_tx_list));
1817 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1824 * Stop all chip I/O so that the kernel's probe routines don't
1825 * get confused by errant DMAs when rebooting.
1831 struct wb_softc *sc;
1833 sc = device_get_softc(dev);