2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * Winbond register definitions.
39 #define WB_BUSCTL 0x00 /* bus control */
40 #define WB_TXSTART 0x04 /* tx start demand */
41 #define WB_RXSTART 0x08 /* rx start demand */
42 #define WB_RXADDR 0x0C /* rx descriptor list start addr */
43 #define WB_TXADDR 0x10 /* tx descriptor list start addr */
44 #define WB_ISR 0x14 /* interrupt status register */
45 #define WB_NETCFG 0x18 /* network config register */
46 #define WB_IMR 0x1C /* interrupt mask */
47 #define WB_FRAMESDISCARDED 0x20 /* # of discarded frames */
48 #define WB_SIO 0x24 /* MII and ROM/EEPROM access */
49 #define WB_BOOTROMADDR 0x28
50 #define WB_TIMER 0x2C /* general timer */
51 #define WB_CURRXCTL 0x30 /* current RX descriptor */
52 #define WB_CURRXBUF 0x34 /* current RX buffer */
53 #define WB_MAR0 0x38 /* multicast filter 0 */
54 #define WB_MAR1 0x3C /* multicast filter 1 */
55 #define WB_NODE0 0x40 /* station address 0 */
56 #define WB_NODE1 0x44 /* station address 1 */
57 #define WB_BOOTROMSIZE 0x48 /* boot ROM size */
58 #define WB_CURTXCTL 0x4C /* current TX descriptor */
59 #define WB_CURTXBUF 0x50 /* current TX buffer */
64 #define WB_BUSCTL_RESET 0x00000001
65 #define WB_BUSCTL_ARBITRATION 0x00000002
66 #define WB_BUSCTL_SKIPLEN 0x0000007C
67 #define WB_BUSCTL_BUF_BIGENDIAN 0x00000080
68 #define WB_BUSCTL_BURSTLEN 0x00003F00
69 #define WB_BUSCTL_CACHEALIGN 0x0000C000
70 #define WB_BUSCTL_DES_BIGENDIAN 0x00100000
71 #define WB_BUSCTL_WAIT 0x00200000
72 #define WB_BUSCTL_MUSTBEONE 0x00400000
74 #define WB_SKIPLEN_1LONG 0x00000004
75 #define WB_SKIPLEN_2LONG 0x00000008
76 #define WB_SKIPLEN_3LONG 0x00000010
77 #define WB_SKIPLEN_4LONG 0x00000020
78 #define WB_SKIPLEN_5LONG 0x00000040
80 #define WB_CACHEALIGN_NONE 0x00000000
81 #define WB_CACHEALIGN_8LONG 0x00004000
82 #define WB_CACHEALIGN_16LONG 0x00008000
83 #define WB_CACHEALIGN_32LONG 0x0000C000
85 #define WB_BURSTLEN_USECA 0x00000000
86 #define WB_BURSTLEN_1LONG 0x00000100
87 #define WB_BURSTLEN_2LONG 0x00000200
88 #define WB_BURSTLEN_4LONG 0x00000400
89 #define WB_BURSTLEN_8LONG 0x00000800
90 #define WB_BURSTLEN_16LONG 0x00001000
91 #define WB_BURSTLEN_32LONG 0x00002000
93 #define WB_BUSCTL_CONFIG (WB_CACHEALIGN_8LONG|WB_SKIPLEN_3LONG| \
97 * Interrupt status bits.
99 #define WB_ISR_TX_OK 0x00000001
100 #define WB_ISR_TX_IDLE 0x00000002
101 #define WB_ISR_TX_NOBUF 0x00000004
102 #define WB_ISR_RX_EARLY 0x00000008
103 #define WB_ISR_RX_ERR 0x00000010
104 #define WB_ISR_TX_UNDERRUN 0x00000020
105 #define WB_ISR_RX_OK 0x00000040
106 #define WB_ISR_RX_NOBUF 0x00000080
107 #define WB_ISR_RX_IDLE 0x00000100
108 #define WB_ISR_TX_EARLY 0x00000400
109 #define WB_ISR_TIMER_EXPIRED 0x00000800
110 #define WB_ISR_BUS_ERR 0x00002000
111 #define WB_ISR_ABNORMAL 0x00008000
112 #define WB_ISR_NORMAL 0x00010000
113 #define WB_ISR_RX_STATE 0x000E0000
114 #define WB_ISR_TX_STATE 0x00700000
115 #define WB_ISR_BUSERRTYPE 0x03800000
118 * The RX_STATE and TX_STATE fields are not described anywhere in the
119 * Winbond datasheet, however it appears that the Winbond chip is an
120 * attempt at a DEC 'tulip' clone, hence the ISR register is identical
121 * to that of the tulip chip and we can steal the bit definitions from
122 * the tulip documentation.
124 #define WB_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
125 #define WB_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
126 #define WB_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
127 #define WB_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
128 #define WB_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
129 #define WB_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
130 #define WB_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
131 #define WB_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
133 #define WB_TXSTATE_RESET 0x00000000 /* 000 - reset */
134 #define WB_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
135 #define WB_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
136 #define WB_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
137 #define WB_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
138 #define WB_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
139 #define WB_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
140 #define WB_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
143 * Network config bits.
145 #define WB_NETCFG_RX_ON 0x00000002
146 #define WB_NETCFG_RX_ALLPHYS 0x00000008
147 #define WB_NETCFG_RX_MULTI 0x00000010
148 #define WB_NETCFG_RX_BROAD 0x00000020
149 #define WB_NETCFG_RX_RUNT 0x00000040
150 #define WB_NETCFG_RX_ERR 0x00000080
151 #define WB_NETCFG_FULLDUPLEX 0x00000200
152 #define WB_NETCFG_LOOPBACK 0x00000C00
153 #define WB_NETCFG_TX_ON 0x00002000
154 #define WB_NETCFG_TX_THRESH 0x001FC000
155 #define WB_NETCFG_RX_EARLYTHRSH 0x1FE00000
156 #define WB_NETCFG_100MBPS 0x20000000
157 #define WB_NETCFG_TX_EARLY_ON 0x40000000
158 #define WB_NETCFG_RX_EARLY_ON 0x80000000
161 * The tx threshold can be adjusted in increments of 32 bytes.
163 #define WB_TXTHRESH(x) ((x >> 5) << 14)
164 #define WB_TXTHRESH_CHUNK 32
165 #define WB_TXTHRESH_INIT 0 /*72*/
168 * Interrupt mask bits.
170 #define WB_IMR_TX_OK 0x00000001
171 #define WB_IMR_TX_IDLE 0x00000002
172 #define WB_IMR_TX_NOBUF 0x00000004
173 #define WB_IMR_RX_EARLY 0x00000008
174 #define WB_IMR_RX_ERR 0x00000010
175 #define WB_IMR_TX_UNDERRUN 0x00000020
176 #define WB_IMR_RX_OK 0x00000040
177 #define WB_IMR_RX_NOBUF 0x00000080
178 #define WB_IMR_RX_IDLE 0x00000100
179 #define WB_IMR_TX_EARLY 0x00000400
180 #define WB_IMR_TIMER_EXPIRED 0x00000800
181 #define WB_IMR_BUS_ERR 0x00002000
182 #define WB_IMR_ABNORMAL 0x00008000
183 #define WB_IMR_NORMAL 0x00010000
186 (WB_IMR_RX_OK|WB_IMR_TX_OK|WB_IMR_RX_NOBUF|WB_IMR_RX_ERR| \
187 WB_IMR_TX_NOBUF|WB_IMR_TX_UNDERRUN|WB_IMR_BUS_ERR| \
188 WB_IMR_ABNORMAL|WB_IMR_NORMAL|WB_IMR_TX_EARLY)
190 * Serial I/O (EEPROM/ROM) bits.
192 #define WB_SIO_EE_CS 0x00000001 /* EEPROM chip select */
193 #define WB_SIO_EE_CLK 0x00000002 /* EEPROM clock */
194 #define WB_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
195 #define WB_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
196 #define WB_SIO_ROMDATA4 0x00000010
197 #define WB_SIO_ROMDATA5 0x00000020
198 #define WB_SIO_ROMDATA6 0x00000040
199 #define WB_SIO_ROMDATA7 0x00000080
200 #define WB_SIO_ROMCTL_WRITE 0x00000200
201 #define WB_SIO_ROMCTL_READ 0x00000400
202 #define WB_SIO_EESEL 0x00000800
203 #define WB_SIO_MII_CLK 0x00010000 /* MDIO clock */
204 #define WB_SIO_MII_DATAIN 0x00020000 /* MDIO data out */
205 #define WB_SIO_MII_DIR 0x00040000 /* MDIO dir */
206 #define WB_SIO_MII_DATAOUT 0x00080000 /* MDIO data in */
208 #define WB_EECMD_WRITE 0x140
209 #define WB_EECMD_READ 0x180
210 #define WB_EECMD_ERASE 0x1c0
213 * Winbond TX/RX descriptor structure.
223 #define wb_data wb_ptr1
224 #define wb_next wb_ptr2
226 #define WB_RXSTAT_CRCERR 0x00000002
227 #define WB_RXSTAT_DRIBBLE 0x00000004
228 #define WB_RXSTAT_MIIERR 0x00000008
229 #define WB_RXSTAT_LATEEVENT 0x00000040
230 #define WB_RXSTAT_GIANT 0x00000080
231 #define WB_RXSTAT_LASTFRAG 0x00000100
232 #define WB_RXSTAT_FIRSTFRAG 0x00000200
233 #define WB_RXSTAT_MULTICAST 0x00000400
234 #define WB_RXSTAT_RUNT 0x00000800
235 #define WB_RXSTAT_RXTYPE 0x00003000
236 #define WB_RXSTAT_RXERR 0x00008000
237 #define WB_RXSTAT_RXLEN 0x3FFF0000
238 #define WB_RXSTAT_RXCMP 0x40000000
239 #define WB_RXSTAT_OWN 0x80000000
241 #define WB_RXBYTES(x) ((x & WB_RXSTAT_RXLEN) >> 16)
242 #define WB_RXSTAT (WB_RXSTAT_FIRSTFRAG|WB_RXSTAT_LASTFRAG|WB_RXSTAT_OWN)
244 #define WB_RXCTL_BUFLEN1 0x00000FFF
245 #define WB_RXCTL_BUFLEN2 0x00FFF000
246 #define WB_RXCTL_RLINK 0x01000000
247 #define WB_RXCTL_RLAST 0x02000000
249 #define WB_TXSTAT_DEFER 0x00000001
250 #define WB_TXSTAT_UNDERRUN 0x00000002
251 #define WB_TXSTAT_COLLCNT 0x00000078
252 #define WB_TXSTAT_SQE 0x00000080
253 #define WB_TXSTAT_ABORT 0x00000100
254 #define WB_TXSTAT_LATECOLL 0x00000200
255 #define WB_TXSTAT_NOCARRIER 0x00000400
256 #define WB_TXSTAT_CARRLOST 0x00000800
257 #define WB_TXSTAT_TXERR 0x00001000
258 #define WB_TXSTAT_OWN 0x80000000
260 #define WB_TXCTL_BUFLEN1 0x000007FF
261 #define WB_TXCTL_BUFLEN2 0x003FF800
262 #define WB_TXCTL_PAD 0x00800000
263 #define WB_TXCTL_TLINK 0x01000000
264 #define WB_TXCTL_TLAST 0x02000000
265 #define WB_TXCTL_NOCRC 0x08000000
266 #define WB_TXCTL_FIRSTFRAG 0x20000000
267 #define WB_TXCTL_LASTFRAG 0x40000000
268 #define WB_TXCTL_FINT 0x80000000
270 #define WB_MAXFRAGS 16
271 #define WB_RX_LIST_CNT 64
272 #define WB_TX_LIST_CNT 128
273 #define WB_MIN_FRAMELEN 60
274 #define ETHER_ALIGN 2
277 * A transmit 'super descriptor' is actually WB_MAXFRAGS regular
278 * descriptors clumped together. The idea here is to emulate the
279 * multi-fragment descriptor layout found in devices such as the
280 * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips.
281 * The advantage to using this scheme is that it avoids buffer copies.
282 * The disadvantage is that there's a certain amount of overhead due
283 * to the fact that each 'fragment' is 16 bytes long. In my tests,
284 * this limits top speed to about 10.5MB/sec. It should be more like
285 * 11.5MB/sec. However, the upshot is that you can achieve better
286 * results on slower machines: a Pentium 200 can pump out packets at
287 * same speed as a PII 400.
290 struct wb_desc wb_frag[WB_MAXFRAGS];
293 #define WB_TXNEXT(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_next
294 #define WB_TXSTATUS(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status
295 #define WB_TXCTL(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl
296 #define WB_TXDATA(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data
298 #define WB_TXOWN(x) x->wb_ptr->wb_frag[0].wb_status
300 #define WB_UNSENT 0x1234
302 #define WB_BUFBYTES (1024 * sizeof(u_int32_t))
305 u_int32_t wb_data[1024];
308 struct wb_list_data {
309 struct wb_buf wb_rxbufs[WB_RX_LIST_CNT];
310 struct wb_desc wb_rx_list[WB_RX_LIST_CNT];
311 struct wb_txdesc wb_tx_list[WB_TX_LIST_CNT];
315 struct wb_txdesc *wb_ptr;
316 struct mbuf *wb_mbuf;
317 struct wb_chain *wb_nextdesc;
318 u_int8_t wb_lastdesc;
321 struct wb_chain_onefrag {
322 struct wb_desc *wb_ptr;
323 struct mbuf *wb_mbuf;
325 struct wb_chain_onefrag *wb_nextdesc;
329 struct wb_chain_data {
330 u_int8_t wb_pad[WB_MIN_FRAMELEN];
331 struct wb_chain_onefrag wb_rx_chain[WB_RX_LIST_CNT];
332 struct wb_chain wb_tx_chain[WB_TX_LIST_CNT];
334 struct wb_chain_onefrag *wb_rx_head;
336 struct wb_chain *wb_tx_head;
337 struct wb_chain *wb_tx_tail;
338 struct wb_chain *wb_tx_free;
347 struct wb_mii_frame {
348 u_int8_t mii_stdelim;
350 u_int8_t mii_phyaddr;
351 u_int8_t mii_regaddr;
352 u_int8_t mii_turnaround;
359 #define WB_MII_STARTDELIM 0x01
360 #define WB_MII_READOP 0x02
361 #define WB_MII_WRITEOP 0x01
362 #define WB_MII_TURNAROUND 0x02
365 struct ifnet *wb_ifp; /* interface info */
368 bus_space_handle_t wb_bhandle;
369 bus_space_tag_t wb_btag;
370 struct resource *wb_res;
371 struct resource *wb_irq;
373 struct wb_type *wb_info; /* Winbond adapter info */
375 u_int16_t wb_txthresh;
377 caddr_t wb_ldata_ptr;
378 struct wb_list_data *wb_ldata;
379 struct wb_chain_data wb_cdata;
380 struct callout wb_stat_callout;
384 #define WB_LOCK(_sc) mtx_lock(&(_sc)->wb_mtx)
385 #define WB_UNLOCK(_sc) mtx_unlock(&(_sc)->wb_mtx)
386 #define WB_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->wb_mtx, MA_OWNED)
389 * register space access macros
391 #define CSR_WRITE_4(sc, reg, val) \
392 bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
393 #define CSR_WRITE_2(sc, reg, val) \
394 bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
395 #define CSR_WRITE_1(sc, reg, val) \
396 bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
398 #define CSR_READ_4(sc, reg) \
399 bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)
400 #define CSR_READ_2(sc, reg) \
401 bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)
402 #define CSR_READ_1(sc, reg) \
403 bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)
405 #define WB_TIMEOUT 1000
408 * General constants that are fun to know.
410 * Winbond PCI vendor ID
412 #define WB_VENDORID 0x1050
415 * Winbond device IDs.
417 #define WB_DEVICEID_840F 0x0840
422 #define CP_VENDORID 0x11F6
427 #define CP_DEVICEID_RL100 0x2011
430 * PCI low memory base and low I/O base register, and
431 * other PCI registers.
434 #define WB_PCI_VENDOR_ID 0x00
435 #define WB_PCI_DEVICE_ID 0x02
436 #define WB_PCI_COMMAND 0x04
437 #define WB_PCI_STATUS 0x06
438 #define WB_PCI_CLASSCODE 0x09
439 #define WB_PCI_CACHELEN 0x0C
440 #define WB_PCI_LATENCY_TIMER 0x0D
441 #define WB_PCI_HEADER_TYPE 0x0E
442 #define WB_PCI_LOIO 0x10
443 #define WB_PCI_LOMEM 0x14
444 #define WB_PCI_BIOSROM 0x30
445 #define WB_PCI_INTLINE 0x3C
446 #define WB_PCI_INTPIN 0x3D
447 #define WB_PCI_MINGNT 0x3E
448 #define WB_PCI_MINLAT 0x0F
449 #define WB_PCI_RESETOPT 0x48
450 #define WB_PCI_EEPROM_DATA 0x4C
452 /* power management registers */
453 #define WB_PCI_CAPID 0xDC /* 8 bits */
454 #define WB_PCI_NEXTPTR 0xDD /* 8 bits */
455 #define WB_PCI_PWRMGMTCAP 0xDE /* 16 bits */
456 #define WB_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
458 #define WB_PSTATE_MASK 0x0003
459 #define WB_PSTATE_D0 0x0000
460 #define WB_PSTATE_D1 0x0002
461 #define WB_PSTATE_D2 0x0002
462 #define WB_PSTATE_D3 0x0003
463 #define WB_PME_EN 0x0010
464 #define WB_PME_STATUS 0x8000