2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
100 * This driver is in the /sys/pci directory because it only supports
104 #include <sys/param.h>
105 #include <sys/systm.h>
106 #include <sys/sockio.h>
107 #include <sys/endian.h>
108 #include <sys/mbuf.h>
109 #include <sys/kernel.h>
110 #include <sys/module.h>
111 #include <sys/socket.h>
112 #include <sys/taskqueue.h>
115 #include <net/if_arp.h>
116 #include <net/ethernet.h>
117 #include <net/if_dl.h>
118 #include <net/if_media.h>
119 #include <net/if_types.h>
123 #include <machine/bus.h>
124 #include <machine/resource.h>
126 #include <sys/rman.h>
128 #include <dev/mii/mii.h>
129 #include <dev/mii/miivar.h>
131 #include <dev/pci/pcireg.h>
132 #include <dev/pci/pcivar.h>
134 MODULE_DEPEND(xl, pci, 1, 1, 1);
135 MODULE_DEPEND(xl, ether, 1, 1, 1);
136 MODULE_DEPEND(xl, miibus, 1, 1, 1);
138 /* "device miibus" required. See GENERIC if you get errors here. */
139 #include "miibus_if.h"
141 #include <pci/if_xlreg.h>
144 * TX Checksumming is disabled by default for two reasons:
145 * - TX Checksumming will occasionally produce corrupt packets
146 * - TX Checksumming seems to reduce performance
148 * Only 905B/C cards were reported to have this problem, it is possible
149 * that later chips _may_ be immune.
151 #define XL905B_TXCSUM_BROKEN 1
153 #ifdef XL905B_TXCSUM_BROKEN
154 #define XL905B_CSUM_FEATURES 0
156 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
160 * Various supported device vendors/types and their names.
162 static struct xl_type xl_devs[] = {
163 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
164 "3Com 3c900-TPO Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
166 "3Com 3c900-COMBO Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
168 "3Com 3c905-TX Fast Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
170 "3Com 3c905-T4 Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
172 "3Com 3c900B-TPO Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
174 "3Com 3c900B-COMBO Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
176 "3Com 3c900B-TPC Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
178 "3Com 3c900B-FL Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
180 "3Com 3c905B-TX Fast Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
182 "3Com 3c905B-T4 Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
184 "3Com 3c905B-FX/SC Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
186 "3Com 3c905B-COMBO Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
188 "3Com 3c905C-TX Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
190 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
192 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
194 "3Com 3c980 Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
196 "3Com 3c980C Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
198 "3Com 3cSOHO100-TX OfficeConnect" },
199 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
200 "3Com 3c450-TX HomeConnect" },
201 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
202 "3Com 3c555 Fast Etherlink XL" },
203 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
204 "3Com 3c556 Fast Etherlink XL" },
205 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
206 "3Com 3c556B Fast Etherlink XL" },
207 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
208 "3Com 3c575TX Fast Etherlink XL" },
209 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
210 "3Com 3c575B Fast Etherlink XL" },
211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
212 "3Com 3c575C Fast Etherlink XL" },
213 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
214 "3Com 3c656 Fast Etherlink XL" },
215 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
216 "3Com 3c656B Fast Etherlink XL" },
217 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
218 "3Com 3c656C Fast Etherlink XL" },
222 static int xl_probe(device_t);
223 static int xl_attach(device_t);
224 static int xl_detach(device_t);
226 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
227 static void xl_stats_update(void *);
228 static void xl_stats_update_locked(struct xl_softc *);
229 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf *);
230 static void xl_rxeof(struct xl_softc *);
231 static void xl_rxeof_task(void *, int);
232 static int xl_rx_resync(struct xl_softc *);
233 static void xl_txeof(struct xl_softc *);
234 static void xl_txeof_90xB(struct xl_softc *);
235 static void xl_txeoc(struct xl_softc *);
236 static void xl_intr(void *);
237 static void xl_start(struct ifnet *);
238 static void xl_start_locked(struct ifnet *);
239 static void xl_start_90xB_locked(struct ifnet *);
240 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
241 static void xl_init(void *);
242 static void xl_init_locked(struct xl_softc *);
243 static void xl_stop(struct xl_softc *);
244 static void xl_watchdog(struct ifnet *);
245 static void xl_shutdown(device_t);
246 static int xl_suspend(device_t);
247 static int xl_resume(device_t);
249 #ifdef DEVICE_POLLING
250 static void xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
251 static void xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
252 #endif /* DEVICE_POLLING */
254 static int xl_ifmedia_upd(struct ifnet *);
255 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
257 static int xl_eeprom_wait(struct xl_softc *);
258 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
259 static void xl_mii_sync(struct xl_softc *);
260 static void xl_mii_send(struct xl_softc *, u_int32_t, int);
261 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *);
262 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *);
264 static void xl_setcfg(struct xl_softc *);
265 static void xl_setmode(struct xl_softc *, int);
266 static void xl_setmulti(struct xl_softc *);
267 static void xl_setmulti_hash(struct xl_softc *);
268 static void xl_reset(struct xl_softc *);
269 static int xl_list_rx_init(struct xl_softc *);
270 static int xl_list_tx_init(struct xl_softc *);
271 static int xl_list_tx_init_90xB(struct xl_softc *);
272 static void xl_wait(struct xl_softc *);
273 static void xl_mediacheck(struct xl_softc *);
274 static void xl_choose_media(struct xl_softc *sc, int *media);
275 static void xl_choose_xcvr(struct xl_softc *, int);
276 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
277 static void xl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
278 static void xl_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
280 static void xl_testpacket(struct xl_softc *);
283 static int xl_miibus_readreg(device_t, int, int);
284 static int xl_miibus_writereg(device_t, int, int, int);
285 static void xl_miibus_statchg(device_t);
286 static void xl_miibus_mediainit(device_t);
288 static device_method_t xl_methods[] = {
289 /* Device interface */
290 DEVMETHOD(device_probe, xl_probe),
291 DEVMETHOD(device_attach, xl_attach),
292 DEVMETHOD(device_detach, xl_detach),
293 DEVMETHOD(device_shutdown, xl_shutdown),
294 DEVMETHOD(device_suspend, xl_suspend),
295 DEVMETHOD(device_resume, xl_resume),
298 DEVMETHOD(bus_print_child, bus_generic_print_child),
299 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
302 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
303 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
304 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
305 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
310 static driver_t xl_driver = {
313 sizeof(struct xl_softc)
316 static devclass_t xl_devclass;
318 DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0);
319 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0);
320 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
323 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
328 *paddr = segs->ds_addr;
332 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
333 bus_size_t mapsize, int error)
340 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
342 *paddr = segs->ds_addr;
346 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
347 bus_size_t mapsize, int error)
355 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
359 for (i = 0; i < nseg; i++) {
360 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
361 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
362 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
363 total_len += segs[i].ds_len;
365 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
367 l->xl_status = htole32(total_len);
372 * Murphy's law says that it's possible the chip can wedge and
373 * the 'command in progress' bit may never clear. Hence, we wait
374 * only a finite amount of time to avoid getting caught in an
375 * infinite loop. Normally this delay routine would be a macro,
376 * but it isn't called during normal operation so we can afford
377 * to make it a function.
380 xl_wait(struct xl_softc *sc)
384 for (i = 0; i < XL_TIMEOUT; i++) {
385 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
390 if_printf(sc->xl_ifp, "command never completed!\n");
394 * MII access routines are provided for adapters with external
395 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
396 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
397 * Note: if you don't perform the MDIO operations just right,
398 * it's possible to end up with code that works correctly with
399 * some chips/CPUs/processor speeds/bus speeds/etc but not
403 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
404 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
407 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
408 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
411 * Sync the PHYs by setting data bit and strobing the clock 32 times.
414 xl_mii_sync(struct xl_softc *sc)
419 MII_SET(XL_MII_DIR|XL_MII_DATA);
421 for (i = 0; i < 32; i++) {
423 MII_SET(XL_MII_DATA);
424 MII_SET(XL_MII_DATA);
426 MII_SET(XL_MII_DATA);
427 MII_SET(XL_MII_DATA);
432 * Clock a series of bits through the MII.
435 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
442 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
444 MII_SET(XL_MII_DATA);
446 MII_CLR(XL_MII_DATA);
454 * Read an PHY register through the MII.
457 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
461 /* Set up frame for RX. */
462 frame->mii_stdelim = XL_MII_STARTDELIM;
463 frame->mii_opcode = XL_MII_READOP;
464 frame->mii_turnaround = 0;
467 /* Select register window 4. */
470 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
471 /* Turn on data xmit. */
476 /* Send command/address info. */
477 xl_mii_send(sc, frame->mii_stdelim, 2);
478 xl_mii_send(sc, frame->mii_opcode, 2);
479 xl_mii_send(sc, frame->mii_phyaddr, 5);
480 xl_mii_send(sc, frame->mii_regaddr, 5);
483 MII_CLR((XL_MII_CLK|XL_MII_DATA));
491 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
495 * Now try reading data bits. If the ack failed, we still
496 * need to clock through 16 cycles to keep the PHY(s) in sync.
499 for (i = 0; i < 16; i++) {
506 for (i = 0x8000; i; i >>= 1) {
509 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
510 frame->mii_data |= i;
519 return (ack ? 1 : 0);
523 * Write to a PHY register through the MII.
526 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
529 /* Set up frame for TX. */
530 frame->mii_stdelim = XL_MII_STARTDELIM;
531 frame->mii_opcode = XL_MII_WRITEOP;
532 frame->mii_turnaround = XL_MII_TURNAROUND;
534 /* Select the window 4. */
537 /* Turn on data output. */
542 xl_mii_send(sc, frame->mii_stdelim, 2);
543 xl_mii_send(sc, frame->mii_opcode, 2);
544 xl_mii_send(sc, frame->mii_phyaddr, 5);
545 xl_mii_send(sc, frame->mii_regaddr, 5);
546 xl_mii_send(sc, frame->mii_turnaround, 2);
547 xl_mii_send(sc, frame->mii_data, 16);
560 xl_miibus_readreg(device_t dev, int phy, int reg)
563 struct xl_mii_frame frame;
565 sc = device_get_softc(dev);
568 * Pretend that PHYs are only available at MII address 24.
569 * This is to guard against problems with certain 3Com ASIC
570 * revisions that incorrectly map the internal transceiver
571 * control registers at all MII addresses. This can cause
572 * the miibus code to attach the same PHY several times over.
574 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
577 bzero((char *)&frame, sizeof(frame));
578 frame.mii_phyaddr = phy;
579 frame.mii_regaddr = reg;
581 xl_mii_readreg(sc, &frame);
583 return (frame.mii_data);
587 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
590 struct xl_mii_frame frame;
592 sc = device_get_softc(dev);
594 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
597 bzero((char *)&frame, sizeof(frame));
598 frame.mii_phyaddr = phy;
599 frame.mii_regaddr = reg;
600 frame.mii_data = data;
602 xl_mii_writereg(sc, &frame);
608 xl_miibus_statchg(device_t dev)
611 struct mii_data *mii;
613 sc = device_get_softc(dev);
614 mii = device_get_softc(sc->xl_miibus);
618 /* Set ASIC's duplex mode to match the PHY. */
620 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
621 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
623 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
624 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
628 * Special support for the 3c905B-COMBO. This card has 10/100 support
629 * plus BNC and AUI ports. This means we will have both an miibus attached
630 * plus some non-MII media settings. In order to allow this, we have to
631 * add the extra media to the miibus's ifmedia struct, but we can't do
632 * that during xl_attach() because the miibus hasn't been attached yet.
633 * So instead, we wait until the miibus probe/attach is done, at which
634 * point we will get a callback telling is that it's safe to add our
638 xl_miibus_mediainit(device_t dev)
641 struct mii_data *mii;
644 sc = device_get_softc(dev);
645 mii = device_get_softc(sc->xl_miibus);
646 ifm = &mii->mii_media;
648 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
650 * Check for a 10baseFL board in disguise.
652 if (sc->xl_type == XL_TYPE_905B &&
653 sc->xl_media == XL_MEDIAOPT_10FL) {
655 if_printf(sc->xl_ifp,
657 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
658 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
660 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
662 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
665 if_printf(sc->xl_ifp, "found AUI\n");
666 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
670 if (sc->xl_media & XL_MEDIAOPT_BNC) {
672 if_printf(sc->xl_ifp, "found BNC\n");
673 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
678 * The EEPROM is slow: give it time to come ready after issuing
682 xl_eeprom_wait(struct xl_softc *sc)
686 for (i = 0; i < 100; i++) {
687 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
694 if_printf(sc->xl_ifp, "eeprom failed to come ready\n");
702 * Read a sequence of words from the EEPROM. Note that ethernet address
703 * data is stored in the EEPROM in network byte order.
706 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
709 u_int16_t word = 0, *ptr;
711 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
712 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
714 * XXX: WARNING! DANGER!
715 * It's easy to accidentally overwrite the rom content!
716 * Note: the 3c575 uses 8bit EEPROM offsets.
720 if (xl_eeprom_wait(sc))
723 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
726 for (i = 0; i < cnt; i++) {
727 if (sc->xl_flags & XL_FLAG_8BITROM)
728 CSR_WRITE_2(sc, XL_W0_EE_CMD,
729 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
731 CSR_WRITE_2(sc, XL_W0_EE_CMD,
732 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
733 err = xl_eeprom_wait(sc);
736 word = CSR_READ_2(sc, XL_W0_EE_DATA);
737 ptr = (u_int16_t *)(dest + (i * 2));
744 return (err ? 1 : 0);
748 * NICs older than the 3c905B have only one multicast option, which
749 * is to enable reception of all multicast frames.
752 xl_setmulti(struct xl_softc *sc)
754 struct ifnet *ifp = sc->xl_ifp;
755 struct ifmultiaddr *ifma;
762 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
764 if (ifp->if_flags & IFF_ALLMULTI) {
765 rxfilt |= XL_RXFILTER_ALLMULTI;
766 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
771 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
776 rxfilt |= XL_RXFILTER_ALLMULTI;
778 rxfilt &= ~XL_RXFILTER_ALLMULTI;
780 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
784 * 3c905B adapters have a hash filter that we can program.
787 xl_setmulti_hash(struct xl_softc *sc)
789 struct ifnet *ifp = sc->xl_ifp;
791 struct ifmultiaddr *ifma;
798 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
800 if (ifp->if_flags & IFF_ALLMULTI) {
801 rxfilt |= XL_RXFILTER_ALLMULTI;
802 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
805 rxfilt &= ~XL_RXFILTER_ALLMULTI;
807 /* first, zot all the existing hash bits */
808 for (i = 0; i < XL_HASHFILT_SIZE; i++)
809 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
811 /* now program new ones */
813 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
814 if (ifma->ifma_addr->sa_family != AF_LINK)
817 * Note: the 3c905B currently only supports a 64-bit hash
818 * table, which means we really only need 6 bits, but the
819 * manual indicates that future chip revisions will have a
820 * 256-bit hash table, hence the routine is set up to
821 * calculate 8 bits of position info in case we need it some
823 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have
824 * a 256 bit hash table. This means we have to use all 8 bits
825 * regardless. On older cards, the upper 2 bits will be
828 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
829 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
830 CSR_WRITE_2(sc, XL_COMMAND,
831 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
837 rxfilt |= XL_RXFILTER_MULTIHASH;
839 rxfilt &= ~XL_RXFILTER_MULTIHASH;
841 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
846 xl_testpacket(struct xl_softc *sc)
849 struct ifnet *ifp = sc->xl_ifp;
851 MGETHDR(m, M_DONTWAIT, MT_DATA);
856 bcopy(&IFP2ENADDR(sc->xl_ifp),
857 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
858 bcopy(&IFP2ENADDR(sc->xl_ifp),
859 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
860 mtod(m, struct ether_header *)->ether_type = htons(3);
861 mtod(m, unsigned char *)[14] = 0;
862 mtod(m, unsigned char *)[15] = 0;
863 mtod(m, unsigned char *)[16] = 0xE3;
864 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
865 IFQ_ENQUEUE(&ifp->if_snd, m);
871 xl_setcfg(struct xl_softc *sc)
875 /*XL_LOCK_ASSERT(sc);*/
878 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
879 icfg &= ~XL_ICFG_CONNECTOR_MASK;
880 if (sc->xl_media & XL_MEDIAOPT_MII ||
881 sc->xl_media & XL_MEDIAOPT_BT4)
882 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
883 if (sc->xl_media & XL_MEDIAOPT_BTX)
884 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
886 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
887 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
891 xl_setmode(struct xl_softc *sc, int media)
895 char *pmsg = "", *dmsg = "";
900 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
902 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
904 if (sc->xl_media & XL_MEDIAOPT_BT) {
905 if (IFM_SUBTYPE(media) == IFM_10_T) {
906 pmsg = "10baseT transceiver";
907 sc->xl_xcvr = XL_XCVR_10BT;
908 icfg &= ~XL_ICFG_CONNECTOR_MASK;
909 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
910 mediastat |= XL_MEDIASTAT_LINKBEAT |
911 XL_MEDIASTAT_JABGUARD;
912 mediastat &= ~XL_MEDIASTAT_SQEENB;
916 if (sc->xl_media & XL_MEDIAOPT_BFX) {
917 if (IFM_SUBTYPE(media) == IFM_100_FX) {
918 pmsg = "100baseFX port";
919 sc->xl_xcvr = XL_XCVR_100BFX;
920 icfg &= ~XL_ICFG_CONNECTOR_MASK;
921 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
922 mediastat |= XL_MEDIASTAT_LINKBEAT;
923 mediastat &= ~XL_MEDIASTAT_SQEENB;
927 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
928 if (IFM_SUBTYPE(media) == IFM_10_5) {
930 sc->xl_xcvr = XL_XCVR_AUI;
931 icfg &= ~XL_ICFG_CONNECTOR_MASK;
932 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
933 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
934 XL_MEDIASTAT_JABGUARD);
935 mediastat |= ~XL_MEDIASTAT_SQEENB;
937 if (IFM_SUBTYPE(media) == IFM_10_FL) {
938 pmsg = "10baseFL transceiver";
939 sc->xl_xcvr = XL_XCVR_AUI;
940 icfg &= ~XL_ICFG_CONNECTOR_MASK;
941 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
942 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
943 XL_MEDIASTAT_JABGUARD);
944 mediastat |= ~XL_MEDIASTAT_SQEENB;
948 if (sc->xl_media & XL_MEDIAOPT_BNC) {
949 if (IFM_SUBTYPE(media) == IFM_10_2) {
951 sc->xl_xcvr = XL_XCVR_COAX;
952 icfg &= ~XL_ICFG_CONNECTOR_MASK;
953 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
954 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
955 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
959 if ((media & IFM_GMASK) == IFM_FDX ||
960 IFM_SUBTYPE(media) == IFM_100_FX) {
963 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
967 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
968 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
971 if (IFM_SUBTYPE(media) == IFM_10_2)
972 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
974 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
976 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
978 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
983 if_printf(sc->xl_ifp, "selecting %s, %s duplex\n", pmsg, dmsg);
987 xl_reset(struct xl_softc *sc)
994 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
995 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
996 XL_RESETOPT_DISADVFD:0));
999 * If we're using memory mapped register mode, pause briefly
1000 * after issuing the reset command before trying to access any
1001 * other registers. With my 3c575C cardbus card, failing to do
1002 * this results in the system locking up while trying to poll
1003 * the command busy bit in the status register.
1005 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1008 for (i = 0; i < XL_TIMEOUT; i++) {
1010 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1014 if (i == XL_TIMEOUT)
1015 if_printf(sc->xl_ifp, "reset didn't complete\n");
1017 /* Reset TX and RX. */
1018 /* Note: the RX reset takes an absurd amount of time
1019 * on newer versions of the Tornado chips such as those
1020 * on the 3c905CX and newer 3c908C cards. We wait an
1021 * extra amount of time so that xl_wait() doesn't complain
1022 * and annoy the users.
1024 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1027 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1030 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1031 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1033 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
1034 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
1035 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
1036 XL_RESETOPT_INVERT_LED : 0) |
1037 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
1038 XL_RESETOPT_INVERT_MII : 0));
1041 /* Wait a little while for the chip to get its brains in order. */
1046 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1047 * IDs against our list and return a device name if we find a match.
1050 xl_probe(device_t dev)
1056 while (t->xl_name != NULL) {
1057 if ((pci_get_vendor(dev) == t->xl_vid) &&
1058 (pci_get_device(dev) == t->xl_did)) {
1059 device_set_desc(dev, t->xl_name);
1060 return (BUS_PROBE_DEFAULT);
1069 * This routine is a kludge to work around possible hardware faults
1070 * or manufacturing defects that can cause the media options register
1071 * (or reset options register, as it's called for the first generation
1072 * 3c90x adapters) to return an incorrect result. I have encountered
1073 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1074 * which doesn't have any of the 'mediaopt' bits set. This screws up
1075 * the attach routine pretty badly because it doesn't know what media
1076 * to look for. If we find ourselves in this predicament, this routine
1077 * will try to guess the media options values and warn the user of a
1078 * possible manufacturing defect with his adapter/system/whatever.
1081 xl_mediacheck(struct xl_softc *sc)
1085 * If some of the media options bits are set, assume they are
1086 * correct. If not, try to figure it out down below.
1087 * XXX I should check for 10baseFL, but I don't have an adapter
1090 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1092 * Check the XCVR value. If it's not in the normal range
1093 * of values, we need to fake it up here.
1095 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1098 if_printf(sc->xl_ifp,
1099 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
1100 if_printf(sc->xl_ifp,
1101 "choosing new default based on card type\n");
1104 if (sc->xl_type == XL_TYPE_905B &&
1105 sc->xl_media & XL_MEDIAOPT_10FL)
1107 if_printf(sc->xl_ifp,
1108 "WARNING: no media options bits set in the media options register!!\n");
1109 if_printf(sc->xl_ifp,
1110 "this could be a manufacturing defect in your adapter or system\n");
1111 if_printf(sc->xl_ifp,
1112 "attempting to guess media type; you should probably consult your vendor\n");
1115 xl_choose_xcvr(sc, 1);
1119 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1124 * Read the device ID from the EEPROM.
1125 * This is what's loaded into the PCI device ID register, so it has
1126 * to be correct otherwise we wouldn't have gotten this far.
1128 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1131 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1132 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1133 sc->xl_media = XL_MEDIAOPT_BT;
1134 sc->xl_xcvr = XL_XCVR_10BT;
1136 if_printf(sc->xl_ifp,
1137 "guessing 10BaseT transceiver\n");
1139 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1140 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1141 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1142 sc->xl_xcvr = XL_XCVR_10BT;
1144 if_printf(sc->xl_ifp,
1145 "guessing COMBO (AUI/BNC/TP)\n");
1147 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1148 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1149 sc->xl_xcvr = XL_XCVR_10BT;
1151 if_printf(sc->xl_ifp, "guessing TPC (BNC/TP)\n");
1153 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1154 sc->xl_media = XL_MEDIAOPT_10FL;
1155 sc->xl_xcvr = XL_XCVR_AUI;
1157 if_printf(sc->xl_ifp, "guessing 10baseFL\n");
1159 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1160 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1161 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1162 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1163 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1164 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1165 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1166 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1167 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1168 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1169 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1170 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1171 sc->xl_media = XL_MEDIAOPT_MII;
1172 sc->xl_xcvr = XL_XCVR_MII;
1174 if_printf(sc->xl_ifp, "guessing MII\n");
1176 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1177 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1178 sc->xl_media = XL_MEDIAOPT_BT4;
1179 sc->xl_xcvr = XL_XCVR_MII;
1181 if_printf(sc->xl_ifp,
1182 "guessing 100baseT4/MII\n");
1184 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1185 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1186 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1187 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1188 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1189 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1190 sc->xl_media = XL_MEDIAOPT_BTX;
1191 sc->xl_xcvr = XL_XCVR_AUTO;
1193 if_printf(sc->xl_ifp,
1194 "guessing 10/100 internal\n");
1196 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1197 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1198 sc->xl_xcvr = XL_XCVR_AUTO;
1200 if_printf(sc->xl_ifp,
1201 "guessing 10/100 plus BNC/AUI\n");
1204 if_printf(sc->xl_ifp,
1205 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1206 sc->xl_media = XL_MEDIAOPT_BT;
1212 * Attach the interface. Allocate softc structures, do ifmedia
1213 * setup and ethernet/BPF attach.
1216 xl_attach(device_t dev)
1218 u_char eaddr[ETHER_ADDR_LEN];
1220 struct xl_softc *sc;
1223 int unit, error = 0, rid, res;
1226 sc = device_get_softc(dev);
1227 unit = device_get_unit(dev);
1229 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1231 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1233 did = pci_get_device(dev);
1236 if (did == TC_DEVICEID_HURRICANE_555)
1237 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1238 if (did == TC_DEVICEID_HURRICANE_556 ||
1239 did == TC_DEVICEID_HURRICANE_556B)
1240 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1241 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1242 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1243 if (did == TC_DEVICEID_HURRICANE_555 ||
1244 did == TC_DEVICEID_HURRICANE_556)
1245 sc->xl_flags |= XL_FLAG_8BITROM;
1246 if (did == TC_DEVICEID_HURRICANE_556B)
1247 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1249 if (did == TC_DEVICEID_HURRICANE_575B ||
1250 did == TC_DEVICEID_HURRICANE_575C ||
1251 did == TC_DEVICEID_HURRICANE_656B ||
1252 did == TC_DEVICEID_TORNADO_656C)
1253 sc->xl_flags |= XL_FLAG_FUNCREG;
1254 if (did == TC_DEVICEID_HURRICANE_575A ||
1255 did == TC_DEVICEID_HURRICANE_575B ||
1256 did == TC_DEVICEID_HURRICANE_575C ||
1257 did == TC_DEVICEID_HURRICANE_656B ||
1258 did == TC_DEVICEID_TORNADO_656C)
1259 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1261 if (did == TC_DEVICEID_HURRICANE_656)
1262 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1263 if (did == TC_DEVICEID_HURRICANE_575B)
1264 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1265 if (did == TC_DEVICEID_HURRICANE_575C)
1266 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1267 if (did == TC_DEVICEID_TORNADO_656C)
1268 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1269 if (did == TC_DEVICEID_HURRICANE_656 ||
1270 did == TC_DEVICEID_HURRICANE_656B)
1271 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1272 XL_FLAG_INVERT_LED_PWR;
1273 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1274 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1275 sc->xl_flags |= XL_FLAG_PHYOK;
1278 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1279 case TC_DEVICEID_HURRICANE_575A:
1280 case TC_DEVICEID_HURRICANE_575B:
1281 case TC_DEVICEID_HURRICANE_575C:
1282 sc->xl_flags |= XL_FLAG_NO_MMIO;
1289 * Map control/status registers.
1291 pci_enable_busmaster(dev);
1293 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1295 res = SYS_RES_MEMORY;
1297 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1300 if (sc->xl_res != NULL) {
1301 sc->xl_flags |= XL_FLAG_USE_MMIO;
1303 device_printf(dev, "using memory mapped I/O\n");
1306 res = SYS_RES_IOPORT;
1307 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1308 if (sc->xl_res == NULL) {
1309 device_printf(dev, "couldn't map ports/memory\n");
1314 device_printf(dev, "using port I/O\n");
1317 sc->xl_btag = rman_get_bustag(sc->xl_res);
1318 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1320 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1321 rid = XL_PCI_FUNCMEM;
1322 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1325 if (sc->xl_fres == NULL) {
1326 device_printf(dev, "couldn't map funcreg memory\n");
1331 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1332 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1335 /* Allocate interrupt */
1337 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1338 RF_SHAREABLE | RF_ACTIVE);
1339 if (sc->xl_irq == NULL) {
1340 device_printf(dev, "couldn't map interrupt\n");
1345 /* Initialize interface name. */
1346 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1348 device_printf(dev, "can not if_alloc()\n");
1353 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1355 /* Reset the adapter. */
1361 * Get station address from the EEPROM.
1363 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1364 device_printf(dev, "failed to read station address\n");
1370 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0);
1371 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1374 * Now allocate a tag for the DMA descriptor lists and a chunk
1375 * of DMA-able memory based on the tag. Also obtain the DMA
1376 * addresses of the RX and TX ring, which we'll need later.
1377 * All of our lists are allocated as a contiguous block
1380 error = bus_dma_tag_create(NULL, 8, 0,
1381 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1382 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1383 &sc->xl_ldata.xl_rx_tag);
1385 device_printf(dev, "failed to allocate rx dma tag\n");
1389 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1390 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1391 &sc->xl_ldata.xl_rx_dmamap);
1393 device_printf(dev, "no memory for rx list buffers!\n");
1394 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1395 sc->xl_ldata.xl_rx_tag = NULL;
1399 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1400 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1401 XL_RX_LIST_SZ, xl_dma_map_addr,
1402 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1404 device_printf(dev, "cannot get dma address of the rx ring!\n");
1405 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1406 sc->xl_ldata.xl_rx_dmamap);
1407 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1408 sc->xl_ldata.xl_rx_tag = NULL;
1412 error = bus_dma_tag_create(NULL, 8, 0,
1413 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1414 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1415 &sc->xl_ldata.xl_tx_tag);
1417 device_printf(dev, "failed to allocate tx dma tag\n");
1421 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1422 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1423 &sc->xl_ldata.xl_tx_dmamap);
1425 device_printf(dev, "no memory for list buffers!\n");
1426 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1427 sc->xl_ldata.xl_tx_tag = NULL;
1431 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1432 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1433 XL_TX_LIST_SZ, xl_dma_map_addr,
1434 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1436 device_printf(dev, "cannot get dma address of the tx ring!\n");
1437 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1438 sc->xl_ldata.xl_tx_dmamap);
1439 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1440 sc->xl_ldata.xl_tx_tag = NULL;
1445 * Allocate a DMA tag for the mapping of mbufs.
1447 error = bus_dma_tag_create(NULL, 1, 0,
1448 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1449 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1450 NULL, &sc->xl_mtag);
1452 device_printf(dev, "failed to allocate mbuf dma tag\n");
1456 /* We need a spare DMA map for the RX ring. */
1457 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1462 * Figure out the card type. 3c905B adapters have the
1463 * 'supportsNoTxLength' bit set in the capabilities
1464 * word in the EEPROM.
1465 * Note: my 3c575C cardbus card lies. It returns a value
1466 * of 0x1578 for its capabilities word, which is somewhat
1467 * nonsensical. Another way to distinguish a 3c90x chip
1468 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1469 * bit. This will only be set for 3c90x boomerage chips.
1471 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1472 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1473 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1474 sc->xl_type = XL_TYPE_905B;
1476 sc->xl_type = XL_TYPE_90X;
1478 ifp->if_mtu = ETHERMTU;
1479 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1480 ifp->if_ioctl = xl_ioctl;
1481 ifp->if_capabilities = IFCAP_VLAN_MTU;
1482 if (sc->xl_type == XL_TYPE_905B) {
1483 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1484 #ifdef XL905B_TXCSUM_BROKEN
1485 ifp->if_capabilities |= IFCAP_RXCSUM;
1487 ifp->if_capabilities |= IFCAP_HWCSUM;
1490 #ifdef DEVICE_POLLING
1491 ifp->if_capabilities |= IFCAP_POLLING;
1492 #endif /* DEVICE_POLLING */
1493 ifp->if_start = xl_start;
1494 ifp->if_watchdog = xl_watchdog;
1495 ifp->if_init = xl_init;
1496 ifp->if_baudrate = 10000000;
1497 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1498 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1499 IFQ_SET_READY(&ifp->if_snd);
1500 ifp->if_capenable = ifp->if_capabilities;
1503 * Now we have to see what sort of media we have.
1504 * This includes probing for an MII interace and a
1508 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1510 device_printf(dev, "media options word: %x\n", sc->xl_media);
1512 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1513 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1514 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1515 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1519 if (sc->xl_media & XL_MEDIAOPT_MII ||
1520 sc->xl_media & XL_MEDIAOPT_BTX ||
1521 sc->xl_media & XL_MEDIAOPT_BT4) {
1523 device_printf(dev, "found MII/AUTO\n");
1525 if (mii_phy_probe(dev, &sc->xl_miibus,
1526 xl_ifmedia_upd, xl_ifmedia_sts)) {
1527 device_printf(dev, "no PHY found!\n");
1535 * Sanity check. If the user has selected "auto" and this isn't
1536 * a 10/100 card of some kind, we need to force the transceiver
1537 * type to something sane.
1539 if (sc->xl_xcvr == XL_XCVR_AUTO)
1540 xl_choose_xcvr(sc, bootverbose);
1545 if (sc->xl_media & XL_MEDIAOPT_BT) {
1547 device_printf(dev, "found 10baseT\n");
1548 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1549 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1550 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1551 ifmedia_add(&sc->ifmedia,
1552 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1555 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1557 * Check for a 10baseFL board in disguise.
1559 if (sc->xl_type == XL_TYPE_905B &&
1560 sc->xl_media == XL_MEDIAOPT_10FL) {
1562 device_printf(dev, "found 10baseFL\n");
1563 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1564 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1566 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1567 ifmedia_add(&sc->ifmedia,
1568 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1571 device_printf(dev, "found AUI\n");
1572 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1576 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1578 device_printf(dev, "found BNC\n");
1579 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1582 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1584 device_printf(dev, "found 100baseFX\n");
1585 ifp->if_baudrate = 100000000;
1586 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1589 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1590 xl_choose_media(sc, &media);
1592 if (sc->xl_miibus == NULL)
1593 ifmedia_set(&sc->ifmedia, media);
1596 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1598 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1602 * Call MI attach routine.
1604 ether_ifattach(ifp, eaddr);
1606 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1607 xl_intr, sc, &sc->xl_intrhand);
1609 device_printf(dev, "couldn't set up irq\n");
1610 ether_ifdetach(ifp);
1622 * Choose a default media.
1623 * XXX This is a leaf function only called by xl_attach() and
1624 * acquires/releases the non-recursible driver mutex to
1625 * satisfy lock assertions.
1628 xl_choose_media(struct xl_softc *sc, int *media)
1633 switch (sc->xl_xcvr) {
1635 *media = IFM_ETHER|IFM_10_T;
1636 xl_setmode(sc, *media);
1639 if (sc->xl_type == XL_TYPE_905B &&
1640 sc->xl_media == XL_MEDIAOPT_10FL) {
1641 *media = IFM_ETHER|IFM_10_FL;
1642 xl_setmode(sc, *media);
1644 *media = IFM_ETHER|IFM_10_5;
1645 xl_setmode(sc, *media);
1649 *media = IFM_ETHER|IFM_10_2;
1650 xl_setmode(sc, *media);
1653 case XL_XCVR_100BTX:
1655 /* Chosen by miibus */
1657 case XL_XCVR_100BFX:
1658 *media = IFM_ETHER|IFM_100_FX;
1661 if_printf(sc->xl_ifp, "unknown XCVR type: %d\n",
1664 * This will probably be wrong, but it prevents
1665 * the ifmedia code from panicking.
1667 *media = IFM_ETHER|IFM_10_T;
1675 * Shutdown hardware and free up resources. This can be called any
1676 * time after the mutex has been initialized. It is called in both
1677 * the error case in attach and the normal detach case so it needs
1678 * to be careful about only freeing resources that have actually been
1682 xl_detach(device_t dev)
1684 struct xl_softc *sc;
1688 sc = device_get_softc(dev);
1691 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1693 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1695 res = SYS_RES_MEMORY;
1698 res = SYS_RES_IOPORT;
1701 /* These should only be active if attach succeeded */
1702 if (device_is_attached(dev)) {
1707 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1708 callout_drain(&sc->xl_stat_callout);
1709 ether_ifdetach(ifp);
1714 device_delete_child(dev, sc->xl_miibus);
1715 bus_generic_detach(dev);
1716 ifmedia_removeall(&sc->ifmedia);
1718 if (sc->xl_intrhand)
1719 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1721 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1722 if (sc->xl_fres != NULL)
1723 bus_release_resource(dev, SYS_RES_MEMORY,
1724 XL_PCI_FUNCMEM, sc->xl_fres);
1726 bus_release_resource(dev, res, rid, sc->xl_res);
1729 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1730 bus_dma_tag_destroy(sc->xl_mtag);
1732 if (sc->xl_ldata.xl_rx_tag) {
1733 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1734 sc->xl_ldata.xl_rx_dmamap);
1735 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1736 sc->xl_ldata.xl_rx_dmamap);
1737 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1739 if (sc->xl_ldata.xl_tx_tag) {
1740 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1741 sc->xl_ldata.xl_tx_dmamap);
1742 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1743 sc->xl_ldata.xl_tx_dmamap);
1744 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1747 mtx_destroy(&sc->xl_mtx);
1753 * Initialize the transmit descriptors.
1756 xl_list_tx_init(struct xl_softc *sc)
1758 struct xl_chain_data *cd;
1759 struct xl_list_data *ld;
1766 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1767 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1768 error = bus_dmamap_create(sc->xl_mtag, 0,
1769 &cd->xl_tx_chain[i].xl_map);
1772 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1773 i * sizeof(struct xl_list);
1774 if (i == (XL_TX_LIST_CNT - 1))
1775 cd->xl_tx_chain[i].xl_next = NULL;
1777 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1780 cd->xl_tx_free = &cd->xl_tx_chain[0];
1781 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1783 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1788 * Initialize the transmit descriptors.
1791 xl_list_tx_init_90xB(struct xl_softc *sc)
1793 struct xl_chain_data *cd;
1794 struct xl_list_data *ld;
1801 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1802 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1803 error = bus_dmamap_create(sc->xl_mtag, 0,
1804 &cd->xl_tx_chain[i].xl_map);
1807 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1808 i * sizeof(struct xl_list);
1809 if (i == (XL_TX_LIST_CNT - 1))
1810 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1812 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1814 cd->xl_tx_chain[i].xl_prev =
1815 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1817 cd->xl_tx_chain[i].xl_prev =
1818 &cd->xl_tx_chain[i - 1];
1821 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1822 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1828 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1833 * Initialize the RX descriptors and allocate mbufs for them. Note that
1834 * we arrange the descriptors in a closed ring, so that the last descriptor
1835 * points back to the first.
1838 xl_list_rx_init(struct xl_softc *sc)
1840 struct xl_chain_data *cd;
1841 struct xl_list_data *ld;
1850 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1851 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1852 error = bus_dmamap_create(sc->xl_mtag, 0,
1853 &cd->xl_rx_chain[i].xl_map);
1856 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1859 if (i == (XL_RX_LIST_CNT - 1))
1863 nextptr = ld->xl_rx_dmaaddr +
1864 next * sizeof(struct xl_list_onefrag);
1865 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1866 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1869 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1870 cd->xl_rx_head = &cd->xl_rx_chain[0];
1876 * Initialize an RX descriptor and attach an MBUF cluster.
1877 * If we fail to do so, we need to leave the old mbuf and
1878 * the old DMA map untouched so that it can be reused.
1881 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1883 struct mbuf *m_new = NULL;
1890 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1894 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1896 /* Force longword alignment for packet payload. */
1897 m_adj(m_new, ETHER_ALIGN);
1899 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1900 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1903 if_printf(sc->xl_ifp, "can't map mbuf (error %d)\n",
1908 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1910 c->xl_map = sc->xl_tmpmap;
1911 sc->xl_tmpmap = map;
1913 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1914 c->xl_ptr->xl_status = 0;
1915 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
1916 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1921 xl_rx_resync(struct xl_softc *sc)
1923 struct xl_chain_onefrag *pos;
1928 pos = sc->xl_cdata.xl_rx_head;
1930 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1931 if (pos->xl_ptr->xl_status)
1936 if (i == XL_RX_LIST_CNT)
1939 sc->xl_cdata.xl_rx_head = pos;
1945 * A frame has been uploaded: pass the resulting mbuf chain up to
1946 * the higher level protocols.
1949 xl_rxeof(struct xl_softc *sc)
1952 struct ifnet *ifp = sc->xl_ifp;
1953 struct xl_chain_onefrag *cur_rx;
1959 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1960 BUS_DMASYNC_POSTREAD);
1961 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1962 #ifdef DEVICE_POLLING
1963 if (ifp->if_flags & IFF_POLLING) {
1964 if (sc->rxcycles <= 0)
1968 #endif /* DEVICE_POLLING */
1969 cur_rx = sc->xl_cdata.xl_rx_head;
1970 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1971 total_len = rxstat & XL_RXSTAT_LENMASK;
1974 * Since we have told the chip to allow large frames,
1975 * we need to trap giant frame errors in software. We allow
1976 * a little more than the normal frame size to account for
1977 * frames with VLAN tags.
1979 if (total_len > XL_MAX_FRAMELEN)
1980 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1983 * If an error occurs, update stats, clear the
1984 * status word and leave the mbuf cluster in place:
1985 * it should simply get re-used next time this descriptor
1986 * comes up in the ring.
1988 if (rxstat & XL_RXSTAT_UP_ERROR) {
1990 cur_rx->xl_ptr->xl_status = 0;
1991 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1992 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1997 * If the error bit was not set, the upload complete
1998 * bit should be set which means we have a valid packet.
1999 * If not, something truly strange has happened.
2001 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2003 "bad receive status -- packet dropped\n");
2005 cur_rx->xl_ptr->xl_status = 0;
2006 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2007 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2011 /* No errors; receive the packet. */
2012 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2013 BUS_DMASYNC_POSTREAD);
2014 m = cur_rx->xl_mbuf;
2017 * Try to conjure up a new mbuf cluster. If that
2018 * fails, it means we have an out of memory condition and
2019 * should leave the buffer in place and continue. This will
2020 * result in a lost packet, but there's little else we
2021 * can do in this situation.
2023 if (xl_newbuf(sc, cur_rx)) {
2025 cur_rx->xl_ptr->xl_status = 0;
2026 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2027 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2030 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2031 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2034 m->m_pkthdr.rcvif = ifp;
2035 m->m_pkthdr.len = m->m_len = total_len;
2037 if (ifp->if_capenable & IFCAP_RXCSUM) {
2038 /* Do IP checksum checking. */
2039 if (rxstat & XL_RXSTAT_IPCKOK)
2040 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2041 if (!(rxstat & XL_RXSTAT_IPCKERR))
2042 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2043 if ((rxstat & XL_RXSTAT_TCPCOK &&
2044 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2045 (rxstat & XL_RXSTAT_UDPCKOK &&
2046 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2047 m->m_pkthdr.csum_flags |=
2048 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2049 m->m_pkthdr.csum_data = 0xffff;
2054 (*ifp->if_input)(ifp, m);
2058 * If we are running from the taskqueue, the interface
2059 * might have been stopped while we were passing the last
2060 * packet up the network stack.
2062 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
2067 * Handle the 'end of channel' condition. When the upload
2068 * engine hits the end of the RX ring, it will stall. This
2069 * is our cue to flush the RX ring, reload the uplist pointer
2070 * register and unstall the engine.
2071 * XXX This is actually a little goofy. With the ThunderLAN
2072 * chip, you get an interrupt when the receiver hits the end
2073 * of the receive ring, which tells you exactly when you
2074 * you need to reload the ring pointer. Here we have to
2075 * fake it. I'm mad at myself for not being clever enough
2076 * to avoid the use of a goto here.
2078 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2079 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2080 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2082 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2083 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2084 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2090 * Taskqueue wrapper for xl_rxeof().
2093 xl_rxeof_task(void *arg, int pending)
2095 struct xl_softc *sc = (struct xl_softc *)arg;
2099 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
2106 * A frame was downloaded to the chip. It's safe for us to clean up
2110 xl_txeof(struct xl_softc *sc)
2112 struct xl_chain *cur_tx;
2113 struct ifnet *ifp = sc->xl_ifp;
2117 /* Clear the timeout timer. */
2121 * Go through our tx list and free mbufs for those
2122 * frames that have been uploaded. Note: the 3c905B
2123 * sets a special bit in the status word to let us
2124 * know that a frame has been downloaded, but the
2125 * original 3c900/3c905 adapters don't do that.
2126 * Consequently, we have to use a different test if
2127 * xl_type != XL_TYPE_905B.
2129 while (sc->xl_cdata.xl_tx_head != NULL) {
2130 cur_tx = sc->xl_cdata.xl_tx_head;
2132 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2135 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2136 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2137 BUS_DMASYNC_POSTWRITE);
2138 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2139 m_freem(cur_tx->xl_mbuf);
2140 cur_tx->xl_mbuf = NULL;
2143 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2144 sc->xl_cdata.xl_tx_free = cur_tx;
2147 if (sc->xl_cdata.xl_tx_head == NULL) {
2148 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2149 sc->xl_cdata.xl_tx_tail = NULL;
2151 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2152 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2153 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2154 sc->xl_cdata.xl_tx_head->xl_phys);
2155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2161 xl_txeof_90xB(struct xl_softc *sc)
2163 struct xl_chain *cur_tx = NULL;
2164 struct ifnet *ifp = sc->xl_ifp;
2169 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2170 BUS_DMASYNC_POSTREAD);
2171 idx = sc->xl_cdata.xl_tx_cons;
2172 while (idx != sc->xl_cdata.xl_tx_prod) {
2174 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2176 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2177 XL_TXSTAT_DL_COMPLETE))
2180 if (cur_tx->xl_mbuf != NULL) {
2181 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2182 BUS_DMASYNC_POSTWRITE);
2183 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2184 m_freem(cur_tx->xl_mbuf);
2185 cur_tx->xl_mbuf = NULL;
2190 sc->xl_cdata.xl_tx_cnt--;
2191 XL_INC(idx, XL_TX_LIST_CNT);
2195 sc->xl_cdata.xl_tx_cons = idx;
2198 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2202 * TX 'end of channel' interrupt handler. Actually, we should
2203 * only get a 'TX complete' interrupt if there's a transmit error,
2204 * so this is really TX error handler.
2207 xl_txeoc(struct xl_softc *sc)
2213 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2214 if (txstat & XL_TXSTATUS_UNDERRUN ||
2215 txstat & XL_TXSTATUS_JABBER ||
2216 txstat & XL_TXSTATUS_RECLAIM) {
2217 if_printf(sc->xl_ifp,
2218 "transmission error: %x\n", txstat);
2219 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2221 if (sc->xl_type == XL_TYPE_905B) {
2222 if (sc->xl_cdata.xl_tx_cnt) {
2226 i = sc->xl_cdata.xl_tx_cons;
2227 c = &sc->xl_cdata.xl_tx_chain[i];
2228 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2230 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2233 if (sc->xl_cdata.xl_tx_head != NULL)
2234 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2235 sc->xl_cdata.xl_tx_head->xl_phys);
2238 * Remember to set this for the
2239 * first generation 3c90X chips.
2241 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2242 if (txstat & XL_TXSTATUS_UNDERRUN &&
2243 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2244 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2245 if_printf(sc->xl_ifp,
2246 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2248 CSR_WRITE_2(sc, XL_COMMAND,
2249 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2250 if (sc->xl_type == XL_TYPE_905B) {
2251 CSR_WRITE_2(sc, XL_COMMAND,
2252 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2254 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2255 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2257 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2258 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2261 * Write an arbitrary byte to the TX_STATUS register
2262 * to clear this interrupt/error and advance to the next.
2264 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2271 struct xl_softc *sc = arg;
2272 struct ifnet *ifp = sc->xl_ifp;
2277 #ifdef DEVICE_POLLING
2278 if (ifp->if_flags & IFF_POLLING) {
2283 if ((ifp->if_capenable & IFCAP_POLLING) &&
2284 ether_poll_register(xl_poll, ifp)) {
2285 /* Disable interrupts. */
2286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2288 if (sc->xl_flags & XL_FLAG_FUNCREG)
2289 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle,
2291 xl_poll_locked(ifp, 0, 1);
2295 #endif /* DEVICE_POLLING */
2297 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS &&
2299 CSR_WRITE_2(sc, XL_COMMAND,
2300 XL_CMD_INTR_ACK|(status & XL_INTRS));
2302 if (status & XL_STAT_UP_COMPLETE) {
2305 curpkts = ifp->if_ipackets;
2307 if (curpkts == ifp->if_ipackets) {
2308 while (xl_rx_resync(sc))
2313 if (status & XL_STAT_DOWN_COMPLETE) {
2314 if (sc->xl_type == XL_TYPE_905B)
2320 if (status & XL_STAT_TX_COMPLETE) {
2325 if (status & XL_STAT_ADFAIL) {
2330 if (status & XL_STAT_STATSOFLOW) {
2331 sc->xl_stats_no_timeout = 1;
2332 xl_stats_update_locked(sc);
2333 sc->xl_stats_no_timeout = 0;
2337 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2338 if (sc->xl_type == XL_TYPE_905B)
2339 xl_start_90xB_locked(ifp);
2341 xl_start_locked(ifp);
2347 #ifdef DEVICE_POLLING
2349 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2351 struct xl_softc *sc = ifp->if_softc;
2354 xl_poll_locked(ifp, cmd, count);
2359 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2361 struct xl_softc *sc = ifp->if_softc;
2365 if (!(ifp->if_capenable & IFCAP_POLLING)) {
2366 ether_poll_deregister(ifp);
2367 cmd = POLL_DEREGISTER;
2370 if (cmd == POLL_DEREGISTER) {
2371 /* Final call; enable interrupts. */
2372 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2373 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2374 if (sc->xl_flags & XL_FLAG_FUNCREG)
2375 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle,
2380 sc->rxcycles = count;
2382 if (sc->xl_type == XL_TYPE_905B)
2387 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2388 if (sc->xl_type == XL_TYPE_905B)
2389 xl_start_90xB_locked(ifp);
2391 xl_start_locked(ifp);
2394 if (cmd == POLL_AND_CHECK_STATUS) {
2397 status = CSR_READ_2(sc, XL_STATUS);
2398 if (status & XL_INTRS && status != 0xFFFF) {
2399 CSR_WRITE_2(sc, XL_COMMAND,
2400 XL_CMD_INTR_ACK|(status & XL_INTRS));
2402 if (status & XL_STAT_TX_COMPLETE) {
2407 if (status & XL_STAT_ADFAIL) {
2412 if (status & XL_STAT_STATSOFLOW) {
2413 sc->xl_stats_no_timeout = 1;
2414 xl_stats_update_locked(sc);
2415 sc->xl_stats_no_timeout = 0;
2420 #endif /* DEVICE_POLLING */
2423 * XXX: This is an entry point for callout which needs to take the lock.
2426 xl_stats_update(void *xsc)
2428 struct xl_softc *sc = xsc;
2431 xl_stats_update_locked(sc);
2435 xl_stats_update_locked(struct xl_softc *sc)
2437 struct ifnet *ifp = sc->xl_ifp;
2438 struct xl_stats xl_stats;
2441 struct mii_data *mii = NULL;
2445 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2447 if (sc->xl_miibus != NULL)
2448 mii = device_get_softc(sc->xl_miibus);
2450 p = (u_int8_t *)&xl_stats;
2452 /* Read all the stats registers. */
2455 for (i = 0; i < 16; i++)
2456 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2458 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2460 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2461 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision;
2464 * Boomerang and cyclone chips have an extra stats counter
2465 * in window 4 (BadSSD). We have to read this too in order
2466 * to clear out all the stats registers and avoid a statsoflow
2470 CSR_READ_1(sc, XL_W4_BADSSD);
2472 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2477 if (!sc->xl_stats_no_timeout)
2478 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
2482 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2483 * pointers to the fragment pointers.
2486 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2490 struct ifnet *ifp = sc->xl_ifp;
2495 * Start packing the mbufs in this chain into
2496 * the fragment pointers. Stop when we run out
2497 * of fragments or hit the end of the mbuf chain.
2499 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2500 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2502 if (error && error != EFBIG) {
2504 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2509 * Handle special case: we used up all 63 fragments,
2510 * but we have more mbufs left in the chain. Copy the
2511 * data into an mbuf cluster. Note that we don't
2512 * bother clearing the values in the other fragment
2513 * pointers/counters; it wouldn't gain us anything,
2514 * and would waste cycles.
2519 m_new = m_defrag(m_head, M_DONTWAIT);
2520 if (m_new == NULL) {
2527 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2528 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2531 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2536 if (sc->xl_type == XL_TYPE_905B) {
2537 status = XL_TXSTAT_RND_DEFEAT;
2539 #ifndef XL905B_TXCSUM_BROKEN
2540 if (m_head->m_pkthdr.csum_flags) {
2541 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2542 status |= XL_TXSTAT_IPCKSUM;
2543 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2544 status |= XL_TXSTAT_TCPCKSUM;
2545 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2546 status |= XL_TXSTAT_UDPCKSUM;
2549 c->xl_ptr->xl_status = htole32(status);
2552 c->xl_mbuf = m_head;
2553 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2558 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2559 * to the mbuf data regions directly in the transmit lists. We also save a
2560 * copy of the pointers since the transmit list fragment pointers are
2561 * physical addresses.
2565 xl_start(struct ifnet *ifp)
2567 struct xl_softc *sc = ifp->if_softc;
2571 if (sc->xl_type == XL_TYPE_905B)
2572 xl_start_90xB_locked(ifp);
2574 xl_start_locked(ifp);
2580 xl_start_locked(struct ifnet *ifp)
2582 struct xl_softc *sc = ifp->if_softc;
2583 struct mbuf *m_head = NULL;
2584 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2585 struct xl_chain *prev_tx;
2592 * Check for an available queue slot. If there are none,
2595 if (sc->xl_cdata.xl_tx_free == NULL) {
2598 if (sc->xl_cdata.xl_tx_free == NULL) {
2599 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2604 start_tx = sc->xl_cdata.xl_tx_free;
2606 while (sc->xl_cdata.xl_tx_free != NULL) {
2607 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2611 /* Pick a descriptor off the free list. */
2613 cur_tx = sc->xl_cdata.xl_tx_free;
2615 /* Pack the data into the descriptor. */
2616 error = xl_encap(sc, cur_tx, m_head);
2622 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2623 cur_tx->xl_next = NULL;
2625 /* Chain it together. */
2627 prev->xl_next = cur_tx;
2628 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2633 * If there's a BPF listener, bounce a copy of this frame
2636 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2640 * If there are no packets queued, bail.
2646 * Place the request for the upload interrupt
2647 * in the last descriptor in the chain. This way, if
2648 * we're chaining several packets at once, we'll only
2649 * get an interupt once for the whole chain rather than
2650 * once for each packet.
2652 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2654 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2655 BUS_DMASYNC_PREWRITE);
2658 * Queue the packets. If the TX channel is clear, update
2659 * the downlist pointer register.
2661 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2664 if (sc->xl_cdata.xl_tx_head != NULL) {
2665 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2666 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2667 htole32(start_tx->xl_phys);
2668 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2669 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2670 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2671 sc->xl_cdata.xl_tx_tail = cur_tx;
2673 sc->xl_cdata.xl_tx_head = start_tx;
2674 sc->xl_cdata.xl_tx_tail = cur_tx;
2676 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2677 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2679 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2684 * Set a timeout in case the chip goes out to lunch.
2689 * XXX Under certain conditions, usually on slower machines
2690 * where interrupts may be dropped, it's possible for the
2691 * adapter to chew up all the buffers in the receive ring
2692 * and stall, without us being able to do anything about it.
2693 * To guard against this, we need to make a pass over the
2694 * RX queue to make sure there aren't any packets pending.
2695 * Doing it here means we can flush the receive ring at the
2696 * same time the chip is DMAing the transmit descriptors we
2699 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2700 * nature of their chips in all their marketing literature;
2701 * we may as well take advantage of it. :)
2703 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2707 xl_start_90xB_locked(struct ifnet *ifp)
2709 struct xl_softc *sc = ifp->if_softc;
2710 struct mbuf *m_head = NULL;
2711 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2712 struct xl_chain *prev_tx;
2717 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
2720 idx = sc->xl_cdata.xl_tx_prod;
2721 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2723 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2725 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2726 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2730 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2735 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2737 /* Pack the data into the descriptor. */
2738 error = xl_encap(sc, cur_tx, m_head);
2744 /* Chain it together. */
2746 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2750 * If there's a BPF listener, bounce a copy of this frame
2753 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2755 XL_INC(idx, XL_TX_LIST_CNT);
2756 sc->xl_cdata.xl_tx_cnt++;
2760 * If there are no packets queued, bail.
2766 * Place the request for the upload interrupt
2767 * in the last descriptor in the chain. This way, if
2768 * we're chaining several packets at once, we'll only
2769 * get an interupt once for the whole chain rather than
2770 * once for each packet.
2772 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2774 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2775 BUS_DMASYNC_PREWRITE);
2777 /* Start transmission */
2778 sc->xl_cdata.xl_tx_prod = idx;
2779 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2782 * Set a timeout in case the chip goes out to lunch.
2790 struct xl_softc *sc = xsc;
2798 xl_init_locked(struct xl_softc *sc)
2800 struct ifnet *ifp = sc->xl_ifp;
2802 u_int16_t rxfilt = 0;
2803 struct mii_data *mii = NULL;
2808 * Cancel pending I/O and free all RX/TX buffers.
2812 if (sc->xl_miibus == NULL) {
2813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2816 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2820 if (sc->xl_miibus != NULL)
2821 mii = device_get_softc(sc->xl_miibus);
2823 /* Init our MAC address */
2825 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2826 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2827 IFP2ENADDR(sc->xl_ifp)[i]);
2830 /* Clear the station mask. */
2831 for (i = 0; i < 3; i++)
2832 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2834 /* Reset TX and RX. */
2835 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2837 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2840 /* Init circular RX list. */
2841 error = xl_list_rx_init(sc);
2843 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2849 /* Init TX descriptors. */
2850 if (sc->xl_type == XL_TYPE_905B)
2851 error = xl_list_tx_init_90xB(sc);
2853 error = xl_list_tx_init(sc);
2855 if_printf(ifp, "initialization of the tx ring failed (%d)\n",
2862 * Set the TX freethresh value.
2863 * Note that this has no effect on 3c905B "cyclone"
2864 * cards but is required for 3c900/3c905 "boomerang"
2865 * cards in order to enable the download engine.
2867 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2869 /* Set the TX start threshold for best performance. */
2870 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2871 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2874 * If this is a 3c905B, also set the tx reclaim threshold.
2875 * This helps cut down on the number of tx reclaim errors
2876 * that could happen on a busy network. The chip multiplies
2877 * the register value by 16 to obtain the actual threshold
2878 * in bytes, so we divide by 16 when setting the value here.
2879 * The existing threshold value can be examined by reading
2880 * the register at offset 9 in window 5.
2882 if (sc->xl_type == XL_TYPE_905B) {
2883 CSR_WRITE_2(sc, XL_COMMAND,
2884 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2887 /* Set RX filter bits. */
2889 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2891 /* Set the individual bit to receive frames for this host only. */
2892 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2894 /* If we want promiscuous mode, set the allframes bit. */
2895 if (ifp->if_flags & IFF_PROMISC) {
2896 rxfilt |= XL_RXFILTER_ALLFRAMES;
2897 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2899 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2900 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2904 * Set capture broadcast bit to capture broadcast frames.
2906 if (ifp->if_flags & IFF_BROADCAST) {
2907 rxfilt |= XL_RXFILTER_BROADCAST;
2908 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2910 rxfilt &= ~XL_RXFILTER_BROADCAST;
2911 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2915 * Program the multicast filter, if necessary.
2917 if (sc->xl_type == XL_TYPE_905B)
2918 xl_setmulti_hash(sc);
2923 * Load the address of the RX list. We have to
2924 * stall the upload engine before we can manipulate
2925 * the uplist pointer register, then unstall it when
2926 * we're finished. We also have to wait for the
2927 * stall command to complete before proceeding.
2928 * Note that we have to do this after any RX resets
2929 * have completed since the uplist register is cleared
2932 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2934 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2938 if (sc->xl_type == XL_TYPE_905B) {
2939 /* Set polling interval */
2940 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2941 /* Load the address of the TX list */
2942 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2944 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2945 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2946 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2951 * If the coax transceiver is on, make sure to enable
2952 * the DC-DC converter.
2955 if (sc->xl_xcvr == XL_XCVR_COAX)
2956 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2961 * increase packet size to allow reception of 802.1q or ISL packets.
2962 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2963 * control register. For 3c90xB/C chips, use the RX packet size
2967 if (sc->xl_type == XL_TYPE_905B)
2968 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2971 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2972 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2973 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2976 /* Clear out the stats counters. */
2977 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2978 sc->xl_stats_no_timeout = 1;
2979 xl_stats_update_locked(sc);
2980 sc->xl_stats_no_timeout = 0;
2982 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2983 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2986 * Enable interrupts.
2988 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2989 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2990 #ifdef DEVICE_POLLING
2991 /* Disable interrupts if we are polling. */
2992 if (ifp->if_flags & IFF_POLLING)
2993 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2995 #endif /* DEVICE_POLLING */
2996 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2997 if (sc->xl_flags & XL_FLAG_FUNCREG)
2998 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3000 /* Set the RX early threshold */
3001 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
3002 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
3004 /* Enable receiver and transmitter. */
3005 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
3007 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3010 /* XXX Downcall to miibus. */
3014 /* Select window 7 for normal operations. */
3017 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3018 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3020 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
3024 * Set media options.
3027 xl_ifmedia_upd(struct ifnet *ifp)
3029 struct xl_softc *sc = ifp->if_softc;
3030 struct ifmedia *ifm = NULL;
3031 struct mii_data *mii = NULL;
3035 if (sc->xl_miibus != NULL)
3036 mii = device_get_softc(sc->xl_miibus);
3040 ifm = &mii->mii_media;
3042 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3047 xl_setmode(sc, ifm->ifm_media);
3054 if (sc->xl_media & XL_MEDIAOPT_MII ||
3055 sc->xl_media & XL_MEDIAOPT_BTX ||
3056 sc->xl_media & XL_MEDIAOPT_BT4) {
3059 xl_setmode(sc, ifm->ifm_media);
3068 * Report current media status.
3071 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3073 struct xl_softc *sc = ifp->if_softc;
3075 u_int16_t status = 0;
3076 struct mii_data *mii = NULL;
3080 if (sc->xl_miibus != NULL)
3081 mii = device_get_softc(sc->xl_miibus);
3084 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3087 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3088 icfg >>= XL_ICFG_CONNECTOR_BITS;
3090 ifmr->ifm_active = IFM_ETHER;
3091 ifmr->ifm_status = IFM_AVALID;
3093 if ((status & XL_MEDIASTAT_CARRIER) == 0)
3094 ifmr->ifm_status |= IFM_ACTIVE;
3098 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3099 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3100 ifmr->ifm_active |= IFM_FDX;
3102 ifmr->ifm_active |= IFM_HDX;
3105 if (sc->xl_type == XL_TYPE_905B &&
3106 sc->xl_media == XL_MEDIAOPT_10FL) {
3107 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3108 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3109 ifmr->ifm_active |= IFM_FDX;
3111 ifmr->ifm_active |= IFM_HDX;
3113 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3116 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3119 * XXX MII and BTX/AUTO should be separate cases.
3122 case XL_XCVR_100BTX:
3127 ifmr->ifm_active = mii->mii_media_active;
3128 ifmr->ifm_status = mii->mii_media_status;
3131 case XL_XCVR_100BFX:
3132 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3135 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3143 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3145 struct xl_softc *sc = ifp->if_softc;
3146 struct ifreq *ifr = (struct ifreq *) data;
3148 struct mii_data *mii = NULL;
3156 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3157 if (ifp->if_flags & IFF_UP) {
3158 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3159 ifp->if_flags & IFF_PROMISC &&
3160 !(sc->xl_if_flags & IFF_PROMISC)) {
3161 rxfilt |= XL_RXFILTER_ALLFRAMES;
3162 CSR_WRITE_2(sc, XL_COMMAND,
3163 XL_CMD_RX_SET_FILT|rxfilt);
3165 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3166 !(ifp->if_flags & IFF_PROMISC) &&
3167 sc->xl_if_flags & IFF_PROMISC) {
3168 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3169 CSR_WRITE_2(sc, XL_COMMAND,
3170 XL_CMD_RX_SET_FILT|rxfilt);
3173 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3177 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3180 sc->xl_if_flags = ifp->if_flags;
3186 /* XXX Downcall from if_addmulti() possibly with locks held. */
3188 if (sc->xl_type == XL_TYPE_905B)
3189 xl_setmulti_hash(sc);
3197 if (sc->xl_miibus != NULL)
3198 mii = device_get_softc(sc->xl_miibus);
3200 error = ifmedia_ioctl(ifp, ifr,
3201 &sc->ifmedia, command);
3203 error = ifmedia_ioctl(ifp, ifr,
3204 &mii->mii_media, command);
3208 ifp->if_capenable = ifr->ifr_reqcap;
3209 if (ifp->if_capenable & IFCAP_TXCSUM)
3210 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3212 ifp->if_hwassist = 0;
3216 error = ether_ioctl(ifp, command, data);
3224 * XXX: Invoked from ifnet slow timer. Lock coverage needed.
3227 xl_watchdog(struct ifnet *ifp)
3229 struct xl_softc *sc = ifp->if_softc;
3230 u_int16_t status = 0;
3236 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3237 if_printf(ifp, "watchdog timeout\n");
3239 if (status & XL_MEDIASTAT_CARRIER)
3240 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3248 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3249 if (sc->xl_type == XL_TYPE_905B)
3250 xl_start_90xB_locked(ifp);
3252 xl_start_locked(ifp);
3259 * Stop the adapter and free any mbufs allocated to the
3263 xl_stop(struct xl_softc *sc)
3266 struct ifnet *ifp = sc->xl_ifp;
3271 #ifdef DEVICE_POLLING
3272 ether_poll_deregister(ifp);
3273 #endif /* DEVICE_POLLING */
3275 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3276 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3277 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3278 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3280 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3281 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3285 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3291 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3292 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3293 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3294 if (sc->xl_flags & XL_FLAG_FUNCREG)
3295 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3297 /* Stop the stats updater. */
3298 callout_stop(&sc->xl_stat_callout);
3301 * Free data in the RX lists.
3303 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3304 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3305 bus_dmamap_unload(sc->xl_mtag,
3306 sc->xl_cdata.xl_rx_chain[i].xl_map);
3307 bus_dmamap_destroy(sc->xl_mtag,
3308 sc->xl_cdata.xl_rx_chain[i].xl_map);
3309 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3310 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3313 if (sc->xl_ldata.xl_rx_list != NULL)
3314 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3316 * Free the TX list buffers.
3318 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3319 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3320 bus_dmamap_unload(sc->xl_mtag,
3321 sc->xl_cdata.xl_tx_chain[i].xl_map);
3322 bus_dmamap_destroy(sc->xl_mtag,
3323 sc->xl_cdata.xl_tx_chain[i].xl_map);
3324 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3325 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3328 if (sc->xl_ldata.xl_tx_list != NULL)
3329 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3331 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3335 * Stop all chip I/O so that the kernel's probe routines don't
3336 * get confused by errant DMAs when rebooting.
3339 xl_shutdown(device_t dev)
3341 struct xl_softc *sc;
3343 sc = device_get_softc(dev);
3352 xl_suspend(device_t dev)
3354 struct xl_softc *sc;
3356 sc = device_get_softc(dev);
3366 xl_resume(device_t dev)
3368 struct xl_softc *sc;
3371 sc = device_get_softc(dev);
3377 if (ifp->if_flags & IFF_UP)