2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
100 * This driver is in the /sys/pci directory because it only supports
104 #ifdef HAVE_KERNEL_OPTION_HEADERS
105 #include "opt_device_polling.h"
108 #include <sys/param.h>
109 #include <sys/systm.h>
110 #include <sys/sockio.h>
111 #include <sys/endian.h>
112 #include <sys/mbuf.h>
113 #include <sys/kernel.h>
114 #include <sys/module.h>
115 #include <sys/socket.h>
116 #include <sys/taskqueue.h>
119 #include <net/if_arp.h>
120 #include <net/ethernet.h>
121 #include <net/if_dl.h>
122 #include <net/if_media.h>
123 #include <net/if_types.h>
127 #include <machine/bus.h>
128 #include <machine/resource.h>
130 #include <sys/rman.h>
132 #include <dev/mii/mii.h>
133 #include <dev/mii/miivar.h>
135 #include <dev/pci/pcireg.h>
136 #include <dev/pci/pcivar.h>
138 MODULE_DEPEND(xl, pci, 1, 1, 1);
139 MODULE_DEPEND(xl, ether, 1, 1, 1);
140 MODULE_DEPEND(xl, miibus, 1, 1, 1);
142 /* "device miibus" required. See GENERIC if you get errors here. */
143 #include "miibus_if.h"
145 #include <pci/if_xlreg.h>
148 * TX Checksumming is disabled by default for two reasons:
149 * - TX Checksumming will occasionally produce corrupt packets
150 * - TX Checksumming seems to reduce performance
152 * Only 905B/C cards were reported to have this problem, it is possible
153 * that later chips _may_ be immune.
155 #define XL905B_TXCSUM_BROKEN 1
157 #ifdef XL905B_TXCSUM_BROKEN
158 #define XL905B_CSUM_FEATURES 0
160 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
164 * Various supported device vendors/types and their names.
166 static struct xl_type xl_devs[] = {
167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
168 "3Com 3c900-TPO Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
170 "3Com 3c900-COMBO Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
172 "3Com 3c905-TX Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
174 "3Com 3c905-T4 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
176 "3Com 3c900B-TPO Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
178 "3Com 3c900B-COMBO Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
180 "3Com 3c900B-TPC Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
182 "3Com 3c900B-FL Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
184 "3Com 3c905B-TX Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
186 "3Com 3c905B-T4 Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
188 "3Com 3c905B-FX/SC Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
190 "3Com 3c905B-COMBO Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
192 "3Com 3c905C-TX Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
194 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
196 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
198 "3Com 3c980 Fast Etherlink XL" },
199 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
200 "3Com 3c980C Fast Etherlink XL" },
201 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
202 "3Com 3cSOHO100-TX OfficeConnect" },
203 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
204 "3Com 3c450-TX HomeConnect" },
205 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
206 "3Com 3c555 Fast Etherlink XL" },
207 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
208 "3Com 3c556 Fast Etherlink XL" },
209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
210 "3Com 3c556B Fast Etherlink XL" },
211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
212 "3Com 3c575TX Fast Etherlink XL" },
213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
214 "3Com 3c575B Fast Etherlink XL" },
215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
216 "3Com 3c575C Fast Etherlink XL" },
217 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
218 "3Com 3c656 Fast Etherlink XL" },
219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
220 "3Com 3c656B Fast Etherlink XL" },
221 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
222 "3Com 3c656C Fast Etherlink XL" },
226 static int xl_probe(device_t);
227 static int xl_attach(device_t);
228 static int xl_detach(device_t);
230 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
231 static void xl_stats_update(void *);
232 static void xl_stats_update_locked(struct xl_softc *);
233 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf *);
234 static void xl_rxeof(struct xl_softc *);
235 static void xl_rxeof_task(void *, int);
236 static int xl_rx_resync(struct xl_softc *);
237 static void xl_txeof(struct xl_softc *);
238 static void xl_txeof_90xB(struct xl_softc *);
239 static void xl_txeoc(struct xl_softc *);
240 static void xl_intr(void *);
241 static void xl_start(struct ifnet *);
242 static void xl_start_locked(struct ifnet *);
243 static void xl_start_90xB_locked(struct ifnet *);
244 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
245 static void xl_init(void *);
246 static void xl_init_locked(struct xl_softc *);
247 static void xl_stop(struct xl_softc *);
248 static int xl_watchdog(struct xl_softc *);
249 static void xl_shutdown(device_t);
250 static int xl_suspend(device_t);
251 static int xl_resume(device_t);
253 #ifdef DEVICE_POLLING
254 static void xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
255 static void xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
258 static int xl_ifmedia_upd(struct ifnet *);
259 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
261 static int xl_eeprom_wait(struct xl_softc *);
262 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
263 static void xl_mii_sync(struct xl_softc *);
264 static void xl_mii_send(struct xl_softc *, u_int32_t, int);
265 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *);
266 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *);
268 static void xl_setcfg(struct xl_softc *);
269 static void xl_setmode(struct xl_softc *, int);
270 static void xl_setmulti(struct xl_softc *);
271 static void xl_setmulti_hash(struct xl_softc *);
272 static void xl_reset(struct xl_softc *);
273 static int xl_list_rx_init(struct xl_softc *);
274 static int xl_list_tx_init(struct xl_softc *);
275 static int xl_list_tx_init_90xB(struct xl_softc *);
276 static void xl_wait(struct xl_softc *);
277 static void xl_mediacheck(struct xl_softc *);
278 static void xl_choose_media(struct xl_softc *sc, int *media);
279 static void xl_choose_xcvr(struct xl_softc *, int);
280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
281 static void xl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
282 static void xl_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
284 static void xl_testpacket(struct xl_softc *);
287 static int xl_miibus_readreg(device_t, int, int);
288 static int xl_miibus_writereg(device_t, int, int, int);
289 static void xl_miibus_statchg(device_t);
290 static void xl_miibus_mediainit(device_t);
292 static device_method_t xl_methods[] = {
293 /* Device interface */
294 DEVMETHOD(device_probe, xl_probe),
295 DEVMETHOD(device_attach, xl_attach),
296 DEVMETHOD(device_detach, xl_detach),
297 DEVMETHOD(device_shutdown, xl_shutdown),
298 DEVMETHOD(device_suspend, xl_suspend),
299 DEVMETHOD(device_resume, xl_resume),
302 DEVMETHOD(bus_print_child, bus_generic_print_child),
303 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
306 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
307 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
308 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
309 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
314 static driver_t xl_driver = {
317 sizeof(struct xl_softc)
320 static devclass_t xl_devclass;
322 DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0);
323 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0);
324 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
327 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
332 *paddr = segs->ds_addr;
336 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
337 bus_size_t mapsize, int error)
344 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
346 *paddr = segs->ds_addr;
350 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
351 bus_size_t mapsize, int error)
359 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
363 for (i = 0; i < nseg; i++) {
364 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
365 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
366 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
367 total_len += segs[i].ds_len;
369 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
371 l->xl_status = htole32(total_len);
376 * Murphy's law says that it's possible the chip can wedge and
377 * the 'command in progress' bit may never clear. Hence, we wait
378 * only a finite amount of time to avoid getting caught in an
379 * infinite loop. Normally this delay routine would be a macro,
380 * but it isn't called during normal operation so we can afford
381 * to make it a function.
384 xl_wait(struct xl_softc *sc)
388 for (i = 0; i < XL_TIMEOUT; i++) {
389 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
394 device_printf(sc->xl_dev, "command never completed!\n");
398 * MII access routines are provided for adapters with external
399 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
400 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
401 * Note: if you don't perform the MDIO operations just right,
402 * it's possible to end up with code that works correctly with
403 * some chips/CPUs/processor speeds/bus speeds/etc but not
407 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
408 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
412 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
415 * Sync the PHYs by setting data bit and strobing the clock 32 times.
418 xl_mii_sync(struct xl_softc *sc)
423 MII_SET(XL_MII_DIR|XL_MII_DATA);
425 for (i = 0; i < 32; i++) {
427 MII_SET(XL_MII_DATA);
428 MII_SET(XL_MII_DATA);
430 MII_SET(XL_MII_DATA);
431 MII_SET(XL_MII_DATA);
436 * Clock a series of bits through the MII.
439 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
446 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
448 MII_SET(XL_MII_DATA);
450 MII_CLR(XL_MII_DATA);
458 * Read an PHY register through the MII.
461 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
465 /* Set up frame for RX. */
466 frame->mii_stdelim = XL_MII_STARTDELIM;
467 frame->mii_opcode = XL_MII_READOP;
468 frame->mii_turnaround = 0;
471 /* Select register window 4. */
474 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
475 /* Turn on data xmit. */
480 /* Send command/address info. */
481 xl_mii_send(sc, frame->mii_stdelim, 2);
482 xl_mii_send(sc, frame->mii_opcode, 2);
483 xl_mii_send(sc, frame->mii_phyaddr, 5);
484 xl_mii_send(sc, frame->mii_regaddr, 5);
487 MII_CLR((XL_MII_CLK|XL_MII_DATA));
495 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
499 * Now try reading data bits. If the ack failed, we still
500 * need to clock through 16 cycles to keep the PHY(s) in sync.
503 for (i = 0; i < 16; i++) {
510 for (i = 0x8000; i; i >>= 1) {
513 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
514 frame->mii_data |= i;
523 return (ack ? 1 : 0);
527 * Write to a PHY register through the MII.
530 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
533 /* Set up frame for TX. */
534 frame->mii_stdelim = XL_MII_STARTDELIM;
535 frame->mii_opcode = XL_MII_WRITEOP;
536 frame->mii_turnaround = XL_MII_TURNAROUND;
538 /* Select the window 4. */
541 /* Turn on data output. */
546 xl_mii_send(sc, frame->mii_stdelim, 2);
547 xl_mii_send(sc, frame->mii_opcode, 2);
548 xl_mii_send(sc, frame->mii_phyaddr, 5);
549 xl_mii_send(sc, frame->mii_regaddr, 5);
550 xl_mii_send(sc, frame->mii_turnaround, 2);
551 xl_mii_send(sc, frame->mii_data, 16);
564 xl_miibus_readreg(device_t dev, int phy, int reg)
567 struct xl_mii_frame frame;
569 sc = device_get_softc(dev);
572 * Pretend that PHYs are only available at MII address 24.
573 * This is to guard against problems with certain 3Com ASIC
574 * revisions that incorrectly map the internal transceiver
575 * control registers at all MII addresses. This can cause
576 * the miibus code to attach the same PHY several times over.
578 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
581 bzero((char *)&frame, sizeof(frame));
582 frame.mii_phyaddr = phy;
583 frame.mii_regaddr = reg;
585 xl_mii_readreg(sc, &frame);
587 return (frame.mii_data);
591 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
594 struct xl_mii_frame frame;
596 sc = device_get_softc(dev);
598 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
601 bzero((char *)&frame, sizeof(frame));
602 frame.mii_phyaddr = phy;
603 frame.mii_regaddr = reg;
604 frame.mii_data = data;
606 xl_mii_writereg(sc, &frame);
612 xl_miibus_statchg(device_t dev)
615 struct mii_data *mii;
617 sc = device_get_softc(dev);
618 mii = device_get_softc(sc->xl_miibus);
622 /* Set ASIC's duplex mode to match the PHY. */
624 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
625 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
627 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
628 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
632 * Special support for the 3c905B-COMBO. This card has 10/100 support
633 * plus BNC and AUI ports. This means we will have both an miibus attached
634 * plus some non-MII media settings. In order to allow this, we have to
635 * add the extra media to the miibus's ifmedia struct, but we can't do
636 * that during xl_attach() because the miibus hasn't been attached yet.
637 * So instead, we wait until the miibus probe/attach is done, at which
638 * point we will get a callback telling is that it's safe to add our
642 xl_miibus_mediainit(device_t dev)
645 struct mii_data *mii;
648 sc = device_get_softc(dev);
649 mii = device_get_softc(sc->xl_miibus);
650 ifm = &mii->mii_media;
652 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
654 * Check for a 10baseFL board in disguise.
656 if (sc->xl_type == XL_TYPE_905B &&
657 sc->xl_media == XL_MEDIAOPT_10FL) {
659 device_printf(sc->xl_dev, "found 10baseFL\n");
660 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
661 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
663 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
665 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
668 device_printf(sc->xl_dev, "found AUI\n");
669 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
673 if (sc->xl_media & XL_MEDIAOPT_BNC) {
675 device_printf(sc->xl_dev, "found BNC\n");
676 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
681 * The EEPROM is slow: give it time to come ready after issuing
685 xl_eeprom_wait(struct xl_softc *sc)
689 for (i = 0; i < 100; i++) {
690 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
697 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
705 * Read a sequence of words from the EEPROM. Note that ethernet address
706 * data is stored in the EEPROM in network byte order.
709 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
712 u_int16_t word = 0, *ptr;
714 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
715 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
717 * XXX: WARNING! DANGER!
718 * It's easy to accidentally overwrite the rom content!
719 * Note: the 3c575 uses 8bit EEPROM offsets.
723 if (xl_eeprom_wait(sc))
726 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
729 for (i = 0; i < cnt; i++) {
730 if (sc->xl_flags & XL_FLAG_8BITROM)
731 CSR_WRITE_2(sc, XL_W0_EE_CMD,
732 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
734 CSR_WRITE_2(sc, XL_W0_EE_CMD,
735 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
736 err = xl_eeprom_wait(sc);
739 word = CSR_READ_2(sc, XL_W0_EE_DATA);
740 ptr = (u_int16_t *)(dest + (i * 2));
747 return (err ? 1 : 0);
751 * NICs older than the 3c905B have only one multicast option, which
752 * is to enable reception of all multicast frames.
755 xl_setmulti(struct xl_softc *sc)
757 struct ifnet *ifp = sc->xl_ifp;
758 struct ifmultiaddr *ifma;
765 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
767 if (ifp->if_flags & IFF_ALLMULTI) {
768 rxfilt |= XL_RXFILTER_ALLMULTI;
769 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
774 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
779 rxfilt |= XL_RXFILTER_ALLMULTI;
781 rxfilt &= ~XL_RXFILTER_ALLMULTI;
783 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
787 * 3c905B adapters have a hash filter that we can program.
790 xl_setmulti_hash(struct xl_softc *sc)
792 struct ifnet *ifp = sc->xl_ifp;
794 struct ifmultiaddr *ifma;
801 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
803 if (ifp->if_flags & IFF_ALLMULTI) {
804 rxfilt |= XL_RXFILTER_ALLMULTI;
805 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
808 rxfilt &= ~XL_RXFILTER_ALLMULTI;
810 /* first, zot all the existing hash bits */
811 for (i = 0; i < XL_HASHFILT_SIZE; i++)
812 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
814 /* now program new ones */
816 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
817 if (ifma->ifma_addr->sa_family != AF_LINK)
820 * Note: the 3c905B currently only supports a 64-bit hash
821 * table, which means we really only need 6 bits, but the
822 * manual indicates that future chip revisions will have a
823 * 256-bit hash table, hence the routine is set up to
824 * calculate 8 bits of position info in case we need it some
826 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have
827 * a 256 bit hash table. This means we have to use all 8 bits
828 * regardless. On older cards, the upper 2 bits will be
831 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
832 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
833 CSR_WRITE_2(sc, XL_COMMAND,
834 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
840 rxfilt |= XL_RXFILTER_MULTIHASH;
842 rxfilt &= ~XL_RXFILTER_MULTIHASH;
844 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
849 xl_testpacket(struct xl_softc *sc)
852 struct ifnet *ifp = sc->xl_ifp;
854 MGETHDR(m, M_DONTWAIT, MT_DATA);
859 bcopy(IF_LLADDR(sc->xl_ifp),
860 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
861 bcopy(IF_LLADDR(sc->xl_ifp),
862 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
863 mtod(m, struct ether_header *)->ether_type = htons(3);
864 mtod(m, unsigned char *)[14] = 0;
865 mtod(m, unsigned char *)[15] = 0;
866 mtod(m, unsigned char *)[16] = 0xE3;
867 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
868 IFQ_ENQUEUE(&ifp->if_snd, m);
874 xl_setcfg(struct xl_softc *sc)
878 /*XL_LOCK_ASSERT(sc);*/
881 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
882 icfg &= ~XL_ICFG_CONNECTOR_MASK;
883 if (sc->xl_media & XL_MEDIAOPT_MII ||
884 sc->xl_media & XL_MEDIAOPT_BT4)
885 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
886 if (sc->xl_media & XL_MEDIAOPT_BTX)
887 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
889 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
894 xl_setmode(struct xl_softc *sc, int media)
898 char *pmsg = "", *dmsg = "";
903 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
905 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
907 if (sc->xl_media & XL_MEDIAOPT_BT) {
908 if (IFM_SUBTYPE(media) == IFM_10_T) {
909 pmsg = "10baseT transceiver";
910 sc->xl_xcvr = XL_XCVR_10BT;
911 icfg &= ~XL_ICFG_CONNECTOR_MASK;
912 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
913 mediastat |= XL_MEDIASTAT_LINKBEAT |
914 XL_MEDIASTAT_JABGUARD;
915 mediastat &= ~XL_MEDIASTAT_SQEENB;
919 if (sc->xl_media & XL_MEDIAOPT_BFX) {
920 if (IFM_SUBTYPE(media) == IFM_100_FX) {
921 pmsg = "100baseFX port";
922 sc->xl_xcvr = XL_XCVR_100BFX;
923 icfg &= ~XL_ICFG_CONNECTOR_MASK;
924 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
925 mediastat |= XL_MEDIASTAT_LINKBEAT;
926 mediastat &= ~XL_MEDIASTAT_SQEENB;
930 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
931 if (IFM_SUBTYPE(media) == IFM_10_5) {
933 sc->xl_xcvr = XL_XCVR_AUI;
934 icfg &= ~XL_ICFG_CONNECTOR_MASK;
935 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
936 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
937 XL_MEDIASTAT_JABGUARD);
938 mediastat |= ~XL_MEDIASTAT_SQEENB;
940 if (IFM_SUBTYPE(media) == IFM_10_FL) {
941 pmsg = "10baseFL transceiver";
942 sc->xl_xcvr = XL_XCVR_AUI;
943 icfg &= ~XL_ICFG_CONNECTOR_MASK;
944 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
945 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
946 XL_MEDIASTAT_JABGUARD);
947 mediastat |= ~XL_MEDIASTAT_SQEENB;
951 if (sc->xl_media & XL_MEDIAOPT_BNC) {
952 if (IFM_SUBTYPE(media) == IFM_10_2) {
954 sc->xl_xcvr = XL_XCVR_COAX;
955 icfg &= ~XL_ICFG_CONNECTOR_MASK;
956 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
957 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
958 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
962 if ((media & IFM_GMASK) == IFM_FDX ||
963 IFM_SUBTYPE(media) == IFM_100_FX) {
966 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
970 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
971 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
974 if (IFM_SUBTYPE(media) == IFM_10_2)
975 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
977 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
979 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
981 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
986 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
990 xl_reset(struct xl_softc *sc)
997 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
998 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
999 XL_RESETOPT_DISADVFD:0));
1002 * If we're using memory mapped register mode, pause briefly
1003 * after issuing the reset command before trying to access any
1004 * other registers. With my 3c575C cardbus card, failing to do
1005 * this results in the system locking up while trying to poll
1006 * the command busy bit in the status register.
1008 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1011 for (i = 0; i < XL_TIMEOUT; i++) {
1013 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1017 if (i == XL_TIMEOUT)
1018 device_printf(sc->xl_dev, "reset didn't complete\n");
1020 /* Reset TX and RX. */
1021 /* Note: the RX reset takes an absurd amount of time
1022 * on newer versions of the Tornado chips such as those
1023 * on the 3c905CX and newer 3c908C cards. We wait an
1024 * extra amount of time so that xl_wait() doesn't complain
1025 * and annoy the users.
1027 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1030 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1033 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1034 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1036 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
1037 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
1038 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
1039 XL_RESETOPT_INVERT_LED : 0) |
1040 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
1041 XL_RESETOPT_INVERT_MII : 0));
1044 /* Wait a little while for the chip to get its brains in order. */
1049 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1050 * IDs against our list and return a device name if we find a match.
1053 xl_probe(device_t dev)
1059 while (t->xl_name != NULL) {
1060 if ((pci_get_vendor(dev) == t->xl_vid) &&
1061 (pci_get_device(dev) == t->xl_did)) {
1062 device_set_desc(dev, t->xl_name);
1063 return (BUS_PROBE_DEFAULT);
1072 * This routine is a kludge to work around possible hardware faults
1073 * or manufacturing defects that can cause the media options register
1074 * (or reset options register, as it's called for the first generation
1075 * 3c90x adapters) to return an incorrect result. I have encountered
1076 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1077 * which doesn't have any of the 'mediaopt' bits set. This screws up
1078 * the attach routine pretty badly because it doesn't know what media
1079 * to look for. If we find ourselves in this predicament, this routine
1080 * will try to guess the media options values and warn the user of a
1081 * possible manufacturing defect with his adapter/system/whatever.
1084 xl_mediacheck(struct xl_softc *sc)
1088 * If some of the media options bits are set, assume they are
1089 * correct. If not, try to figure it out down below.
1090 * XXX I should check for 10baseFL, but I don't have an adapter
1093 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1095 * Check the XCVR value. If it's not in the normal range
1096 * of values, we need to fake it up here.
1098 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1101 device_printf(sc->xl_dev,
1102 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
1103 device_printf(sc->xl_dev,
1104 "choosing new default based on card type\n");
1107 if (sc->xl_type == XL_TYPE_905B &&
1108 sc->xl_media & XL_MEDIAOPT_10FL)
1110 device_printf(sc->xl_dev,
1111 "WARNING: no media options bits set in the media options register!!\n");
1112 device_printf(sc->xl_dev,
1113 "this could be a manufacturing defect in your adapter or system\n");
1114 device_printf(sc->xl_dev,
1115 "attempting to guess media type; you should probably consult your vendor\n");
1118 xl_choose_xcvr(sc, 1);
1122 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1127 * Read the device ID from the EEPROM.
1128 * This is what's loaded into the PCI device ID register, so it has
1129 * to be correct otherwise we wouldn't have gotten this far.
1131 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1134 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1135 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1136 sc->xl_media = XL_MEDIAOPT_BT;
1137 sc->xl_xcvr = XL_XCVR_10BT;
1139 device_printf(sc->xl_dev,
1140 "guessing 10BaseT transceiver\n");
1142 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1143 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1144 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1145 sc->xl_xcvr = XL_XCVR_10BT;
1147 device_printf(sc->xl_dev,
1148 "guessing COMBO (AUI/BNC/TP)\n");
1150 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1151 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1152 sc->xl_xcvr = XL_XCVR_10BT;
1154 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1156 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1157 sc->xl_media = XL_MEDIAOPT_10FL;
1158 sc->xl_xcvr = XL_XCVR_AUI;
1160 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1162 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1163 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1164 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1165 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1166 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1167 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1168 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1169 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1170 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1171 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1172 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1173 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1174 sc->xl_media = XL_MEDIAOPT_MII;
1175 sc->xl_xcvr = XL_XCVR_MII;
1177 device_printf(sc->xl_dev, "guessing MII\n");
1179 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1180 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1181 sc->xl_media = XL_MEDIAOPT_BT4;
1182 sc->xl_xcvr = XL_XCVR_MII;
1184 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1186 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1187 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1188 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1189 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1190 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1191 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1192 sc->xl_media = XL_MEDIAOPT_BTX;
1193 sc->xl_xcvr = XL_XCVR_AUTO;
1195 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1197 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1198 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1199 sc->xl_xcvr = XL_XCVR_AUTO;
1201 device_printf(sc->xl_dev,
1202 "guessing 10/100 plus BNC/AUI\n");
1205 device_printf(sc->xl_dev,
1206 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1207 sc->xl_media = XL_MEDIAOPT_BT;
1213 * Attach the interface. Allocate softc structures, do ifmedia
1214 * setup and ethernet/BPF attach.
1217 xl_attach(device_t dev)
1219 u_char eaddr[ETHER_ADDR_LEN];
1221 struct xl_softc *sc;
1224 int unit, error = 0, rid, res;
1227 sc = device_get_softc(dev);
1230 unit = device_get_unit(dev);
1232 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1234 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1236 did = pci_get_device(dev);
1239 if (did == TC_DEVICEID_HURRICANE_555)
1240 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1241 if (did == TC_DEVICEID_HURRICANE_556 ||
1242 did == TC_DEVICEID_HURRICANE_556B)
1243 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1244 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1245 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1246 if (did == TC_DEVICEID_HURRICANE_555 ||
1247 did == TC_DEVICEID_HURRICANE_556)
1248 sc->xl_flags |= XL_FLAG_8BITROM;
1249 if (did == TC_DEVICEID_HURRICANE_556B)
1250 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1252 if (did == TC_DEVICEID_HURRICANE_575B ||
1253 did == TC_DEVICEID_HURRICANE_575C ||
1254 did == TC_DEVICEID_HURRICANE_656B ||
1255 did == TC_DEVICEID_TORNADO_656C)
1256 sc->xl_flags |= XL_FLAG_FUNCREG;
1257 if (did == TC_DEVICEID_HURRICANE_575A ||
1258 did == TC_DEVICEID_HURRICANE_575B ||
1259 did == TC_DEVICEID_HURRICANE_575C ||
1260 did == TC_DEVICEID_HURRICANE_656B ||
1261 did == TC_DEVICEID_TORNADO_656C)
1262 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1264 if (did == TC_DEVICEID_HURRICANE_656)
1265 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1266 if (did == TC_DEVICEID_HURRICANE_575B)
1267 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1268 if (did == TC_DEVICEID_HURRICANE_575C)
1269 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1270 if (did == TC_DEVICEID_TORNADO_656C)
1271 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1272 if (did == TC_DEVICEID_HURRICANE_656 ||
1273 did == TC_DEVICEID_HURRICANE_656B)
1274 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1275 XL_FLAG_INVERT_LED_PWR;
1276 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1277 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1278 sc->xl_flags |= XL_FLAG_PHYOK;
1281 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1282 case TC_DEVICEID_HURRICANE_575A:
1283 case TC_DEVICEID_HURRICANE_575B:
1284 case TC_DEVICEID_HURRICANE_575C:
1285 sc->xl_flags |= XL_FLAG_NO_MMIO;
1292 * Map control/status registers.
1294 pci_enable_busmaster(dev);
1296 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1298 res = SYS_RES_MEMORY;
1300 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1303 if (sc->xl_res != NULL) {
1304 sc->xl_flags |= XL_FLAG_USE_MMIO;
1306 device_printf(dev, "using memory mapped I/O\n");
1309 res = SYS_RES_IOPORT;
1310 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1311 if (sc->xl_res == NULL) {
1312 device_printf(dev, "couldn't map ports/memory\n");
1317 device_printf(dev, "using port I/O\n");
1320 sc->xl_btag = rman_get_bustag(sc->xl_res);
1321 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1323 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1324 rid = XL_PCI_FUNCMEM;
1325 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1328 if (sc->xl_fres == NULL) {
1329 device_printf(dev, "couldn't map funcreg memory\n");
1334 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1335 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1338 /* Allocate interrupt */
1340 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1341 RF_SHAREABLE | RF_ACTIVE);
1342 if (sc->xl_irq == NULL) {
1343 device_printf(dev, "couldn't map interrupt\n");
1348 /* Initialize interface name. */
1349 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1351 device_printf(dev, "can not if_alloc()\n");
1356 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1358 /* Reset the adapter. */
1364 * Get station address from the EEPROM.
1366 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1367 device_printf(dev, "failed to read station address\n");
1373 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0);
1374 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1377 * Now allocate a tag for the DMA descriptor lists and a chunk
1378 * of DMA-able memory based on the tag. Also obtain the DMA
1379 * addresses of the RX and TX ring, which we'll need later.
1380 * All of our lists are allocated as a contiguous block
1383 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1384 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1385 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1386 &sc->xl_ldata.xl_rx_tag);
1388 device_printf(dev, "failed to allocate rx dma tag\n");
1392 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1393 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1394 &sc->xl_ldata.xl_rx_dmamap);
1396 device_printf(dev, "no memory for rx list buffers!\n");
1397 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1398 sc->xl_ldata.xl_rx_tag = NULL;
1402 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1403 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1404 XL_RX_LIST_SZ, xl_dma_map_addr,
1405 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1407 device_printf(dev, "cannot get dma address of the rx ring!\n");
1408 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1409 sc->xl_ldata.xl_rx_dmamap);
1410 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1411 sc->xl_ldata.xl_rx_tag = NULL;
1415 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1416 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1417 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1418 &sc->xl_ldata.xl_tx_tag);
1420 device_printf(dev, "failed to allocate tx dma tag\n");
1424 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1425 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1426 &sc->xl_ldata.xl_tx_dmamap);
1428 device_printf(dev, "no memory for list buffers!\n");
1429 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1430 sc->xl_ldata.xl_tx_tag = NULL;
1434 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1435 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1436 XL_TX_LIST_SZ, xl_dma_map_addr,
1437 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1439 device_printf(dev, "cannot get dma address of the tx ring!\n");
1440 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1441 sc->xl_ldata.xl_tx_dmamap);
1442 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1443 sc->xl_ldata.xl_tx_tag = NULL;
1448 * Allocate a DMA tag for the mapping of mbufs.
1450 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1451 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1452 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1453 NULL, &sc->xl_mtag);
1455 device_printf(dev, "failed to allocate mbuf dma tag\n");
1459 /* We need a spare DMA map for the RX ring. */
1460 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1465 * Figure out the card type. 3c905B adapters have the
1466 * 'supportsNoTxLength' bit set in the capabilities
1467 * word in the EEPROM.
1468 * Note: my 3c575C cardbus card lies. It returns a value
1469 * of 0x1578 for its capabilities word, which is somewhat
1470 * nonsensical. Another way to distinguish a 3c90x chip
1471 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1472 * bit. This will only be set for 3c90x boomerage chips.
1474 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1475 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1476 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1477 sc->xl_type = XL_TYPE_905B;
1479 sc->xl_type = XL_TYPE_90X;
1481 /* Set the TX start threshold for best performance. */
1482 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1484 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1485 ifp->if_ioctl = xl_ioctl;
1486 ifp->if_capabilities = IFCAP_VLAN_MTU;
1487 if (sc->xl_type == XL_TYPE_905B) {
1488 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1489 #ifdef XL905B_TXCSUM_BROKEN
1490 ifp->if_capabilities |= IFCAP_RXCSUM;
1492 ifp->if_capabilities |= IFCAP_HWCSUM;
1495 ifp->if_capenable = ifp->if_capabilities;
1496 #ifdef DEVICE_POLLING
1497 ifp->if_capabilities |= IFCAP_POLLING;
1499 ifp->if_start = xl_start;
1500 ifp->if_init = xl_init;
1501 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1502 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1503 IFQ_SET_READY(&ifp->if_snd);
1506 * Now we have to see what sort of media we have.
1507 * This includes probing for an MII interace and a
1511 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1513 device_printf(dev, "media options word: %x\n", sc->xl_media);
1515 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1516 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1517 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1518 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1522 if (sc->xl_media & XL_MEDIAOPT_MII ||
1523 sc->xl_media & XL_MEDIAOPT_BTX ||
1524 sc->xl_media & XL_MEDIAOPT_BT4) {
1526 device_printf(dev, "found MII/AUTO\n");
1528 if (mii_phy_probe(dev, &sc->xl_miibus,
1529 xl_ifmedia_upd, xl_ifmedia_sts)) {
1530 device_printf(dev, "no PHY found!\n");
1538 * Sanity check. If the user has selected "auto" and this isn't
1539 * a 10/100 card of some kind, we need to force the transceiver
1540 * type to something sane.
1542 if (sc->xl_xcvr == XL_XCVR_AUTO)
1543 xl_choose_xcvr(sc, bootverbose);
1548 if (sc->xl_media & XL_MEDIAOPT_BT) {
1550 device_printf(dev, "found 10baseT\n");
1551 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1552 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1553 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1554 ifmedia_add(&sc->ifmedia,
1555 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1558 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1560 * Check for a 10baseFL board in disguise.
1562 if (sc->xl_type == XL_TYPE_905B &&
1563 sc->xl_media == XL_MEDIAOPT_10FL) {
1565 device_printf(dev, "found 10baseFL\n");
1566 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1567 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1569 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1570 ifmedia_add(&sc->ifmedia,
1571 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1574 device_printf(dev, "found AUI\n");
1575 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1579 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1581 device_printf(dev, "found BNC\n");
1582 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1585 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1587 device_printf(dev, "found 100baseFX\n");
1588 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1591 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1592 xl_choose_media(sc, &media);
1594 if (sc->xl_miibus == NULL)
1595 ifmedia_set(&sc->ifmedia, media);
1598 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1600 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1604 * Call MI attach routine.
1606 ether_ifattach(ifp, eaddr);
1608 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1609 NULL, xl_intr, sc, &sc->xl_intrhand);
1611 device_printf(dev, "couldn't set up irq\n");
1612 ether_ifdetach(ifp);
1624 * Choose a default media.
1625 * XXX This is a leaf function only called by xl_attach() and
1626 * acquires/releases the non-recursible driver mutex to
1627 * satisfy lock assertions.
1630 xl_choose_media(struct xl_softc *sc, int *media)
1635 switch (sc->xl_xcvr) {
1637 *media = IFM_ETHER|IFM_10_T;
1638 xl_setmode(sc, *media);
1641 if (sc->xl_type == XL_TYPE_905B &&
1642 sc->xl_media == XL_MEDIAOPT_10FL) {
1643 *media = IFM_ETHER|IFM_10_FL;
1644 xl_setmode(sc, *media);
1646 *media = IFM_ETHER|IFM_10_5;
1647 xl_setmode(sc, *media);
1651 *media = IFM_ETHER|IFM_10_2;
1652 xl_setmode(sc, *media);
1655 case XL_XCVR_100BTX:
1657 /* Chosen by miibus */
1659 case XL_XCVR_100BFX:
1660 *media = IFM_ETHER|IFM_100_FX;
1663 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1666 * This will probably be wrong, but it prevents
1667 * the ifmedia code from panicking.
1669 *media = IFM_ETHER|IFM_10_T;
1677 * Shutdown hardware and free up resources. This can be called any
1678 * time after the mutex has been initialized. It is called in both
1679 * the error case in attach and the normal detach case so it needs
1680 * to be careful about only freeing resources that have actually been
1684 xl_detach(device_t dev)
1686 struct xl_softc *sc;
1690 sc = device_get_softc(dev);
1693 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1695 #ifdef DEVICE_POLLING
1696 if (ifp && ifp->if_capenable & IFCAP_POLLING)
1697 ether_poll_deregister(ifp);
1700 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1702 res = SYS_RES_MEMORY;
1705 res = SYS_RES_IOPORT;
1708 /* These should only be active if attach succeeded */
1709 if (device_is_attached(dev)) {
1714 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1715 callout_drain(&sc->xl_stat_callout);
1716 ether_ifdetach(ifp);
1719 device_delete_child(dev, sc->xl_miibus);
1720 bus_generic_detach(dev);
1721 ifmedia_removeall(&sc->ifmedia);
1723 if (sc->xl_intrhand)
1724 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1726 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1727 if (sc->xl_fres != NULL)
1728 bus_release_resource(dev, SYS_RES_MEMORY,
1729 XL_PCI_FUNCMEM, sc->xl_fres);
1731 bus_release_resource(dev, res, rid, sc->xl_res);
1737 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1738 bus_dma_tag_destroy(sc->xl_mtag);
1740 if (sc->xl_ldata.xl_rx_tag) {
1741 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1742 sc->xl_ldata.xl_rx_dmamap);
1743 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1744 sc->xl_ldata.xl_rx_dmamap);
1745 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1747 if (sc->xl_ldata.xl_tx_tag) {
1748 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1749 sc->xl_ldata.xl_tx_dmamap);
1750 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1751 sc->xl_ldata.xl_tx_dmamap);
1752 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1755 mtx_destroy(&sc->xl_mtx);
1761 * Initialize the transmit descriptors.
1764 xl_list_tx_init(struct xl_softc *sc)
1766 struct xl_chain_data *cd;
1767 struct xl_list_data *ld;
1774 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1775 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1776 error = bus_dmamap_create(sc->xl_mtag, 0,
1777 &cd->xl_tx_chain[i].xl_map);
1780 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1781 i * sizeof(struct xl_list);
1782 if (i == (XL_TX_LIST_CNT - 1))
1783 cd->xl_tx_chain[i].xl_next = NULL;
1785 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1788 cd->xl_tx_free = &cd->xl_tx_chain[0];
1789 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1791 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1796 * Initialize the transmit descriptors.
1799 xl_list_tx_init_90xB(struct xl_softc *sc)
1801 struct xl_chain_data *cd;
1802 struct xl_list_data *ld;
1809 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1810 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1811 error = bus_dmamap_create(sc->xl_mtag, 0,
1812 &cd->xl_tx_chain[i].xl_map);
1815 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1816 i * sizeof(struct xl_list);
1817 if (i == (XL_TX_LIST_CNT - 1))
1818 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1820 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1822 cd->xl_tx_chain[i].xl_prev =
1823 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1825 cd->xl_tx_chain[i].xl_prev =
1826 &cd->xl_tx_chain[i - 1];
1829 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1830 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1836 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1841 * Initialize the RX descriptors and allocate mbufs for them. Note that
1842 * we arrange the descriptors in a closed ring, so that the last descriptor
1843 * points back to the first.
1846 xl_list_rx_init(struct xl_softc *sc)
1848 struct xl_chain_data *cd;
1849 struct xl_list_data *ld;
1858 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1859 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1860 error = bus_dmamap_create(sc->xl_mtag, 0,
1861 &cd->xl_rx_chain[i].xl_map);
1864 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1867 if (i == (XL_RX_LIST_CNT - 1))
1871 nextptr = ld->xl_rx_dmaaddr +
1872 next * sizeof(struct xl_list_onefrag);
1873 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1874 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1877 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1878 cd->xl_rx_head = &cd->xl_rx_chain[0];
1884 * Initialize an RX descriptor and attach an MBUF cluster.
1885 * If we fail to do so, we need to leave the old mbuf and
1886 * the old DMA map untouched so that it can be reused.
1889 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1891 struct mbuf *m_new = NULL;
1898 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1902 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1904 /* Force longword alignment for packet payload. */
1905 m_adj(m_new, ETHER_ALIGN);
1907 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1908 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1911 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1916 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1918 c->xl_map = sc->xl_tmpmap;
1919 sc->xl_tmpmap = map;
1921 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1922 c->xl_ptr->xl_status = 0;
1923 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
1924 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1929 xl_rx_resync(struct xl_softc *sc)
1931 struct xl_chain_onefrag *pos;
1936 pos = sc->xl_cdata.xl_rx_head;
1938 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1939 if (pos->xl_ptr->xl_status)
1944 if (i == XL_RX_LIST_CNT)
1947 sc->xl_cdata.xl_rx_head = pos;
1953 * A frame has been uploaded: pass the resulting mbuf chain up to
1954 * the higher level protocols.
1957 xl_rxeof(struct xl_softc *sc)
1960 struct ifnet *ifp = sc->xl_ifp;
1961 struct xl_chain_onefrag *cur_rx;
1967 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1968 BUS_DMASYNC_POSTREAD);
1969 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1970 #ifdef DEVICE_POLLING
1971 if (ifp->if_capenable & IFCAP_POLLING) {
1972 if (sc->rxcycles <= 0)
1977 cur_rx = sc->xl_cdata.xl_rx_head;
1978 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1979 total_len = rxstat & XL_RXSTAT_LENMASK;
1982 * Since we have told the chip to allow large frames,
1983 * we need to trap giant frame errors in software. We allow
1984 * a little more than the normal frame size to account for
1985 * frames with VLAN tags.
1987 if (total_len > XL_MAX_FRAMELEN)
1988 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1991 * If an error occurs, update stats, clear the
1992 * status word and leave the mbuf cluster in place:
1993 * it should simply get re-used next time this descriptor
1994 * comes up in the ring.
1996 if (rxstat & XL_RXSTAT_UP_ERROR) {
1998 cur_rx->xl_ptr->xl_status = 0;
1999 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2000 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2005 * If the error bit was not set, the upload complete
2006 * bit should be set which means we have a valid packet.
2007 * If not, something truly strange has happened.
2009 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2010 device_printf(sc->xl_dev,
2011 "bad receive status -- packet dropped\n");
2013 cur_rx->xl_ptr->xl_status = 0;
2014 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2015 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2019 /* No errors; receive the packet. */
2020 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2021 BUS_DMASYNC_POSTREAD);
2022 m = cur_rx->xl_mbuf;
2025 * Try to conjure up a new mbuf cluster. If that
2026 * fails, it means we have an out of memory condition and
2027 * should leave the buffer in place and continue. This will
2028 * result in a lost packet, but there's little else we
2029 * can do in this situation.
2031 if (xl_newbuf(sc, cur_rx)) {
2033 cur_rx->xl_ptr->xl_status = 0;
2034 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2035 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2038 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2039 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2042 m->m_pkthdr.rcvif = ifp;
2043 m->m_pkthdr.len = m->m_len = total_len;
2045 if (ifp->if_capenable & IFCAP_RXCSUM) {
2046 /* Do IP checksum checking. */
2047 if (rxstat & XL_RXSTAT_IPCKOK)
2048 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2049 if (!(rxstat & XL_RXSTAT_IPCKERR))
2050 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2051 if ((rxstat & XL_RXSTAT_TCPCOK &&
2052 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2053 (rxstat & XL_RXSTAT_UDPCKOK &&
2054 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2055 m->m_pkthdr.csum_flags |=
2056 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2057 m->m_pkthdr.csum_data = 0xffff;
2062 (*ifp->if_input)(ifp, m);
2066 * If we are running from the taskqueue, the interface
2067 * might have been stopped while we were passing the last
2068 * packet up the network stack.
2070 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
2075 * Handle the 'end of channel' condition. When the upload
2076 * engine hits the end of the RX ring, it will stall. This
2077 * is our cue to flush the RX ring, reload the uplist pointer
2078 * register and unstall the engine.
2079 * XXX This is actually a little goofy. With the ThunderLAN
2080 * chip, you get an interrupt when the receiver hits the end
2081 * of the receive ring, which tells you exactly when you
2082 * you need to reload the ring pointer. Here we have to
2083 * fake it. I'm mad at myself for not being clever enough
2084 * to avoid the use of a goto here.
2086 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2087 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2088 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2090 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2091 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2092 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2098 * Taskqueue wrapper for xl_rxeof().
2101 xl_rxeof_task(void *arg, int pending)
2103 struct xl_softc *sc = (struct xl_softc *)arg;
2107 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
2114 * A frame was downloaded to the chip. It's safe for us to clean up
2118 xl_txeof(struct xl_softc *sc)
2120 struct xl_chain *cur_tx;
2121 struct ifnet *ifp = sc->xl_ifp;
2126 * Go through our tx list and free mbufs for those
2127 * frames that have been uploaded. Note: the 3c905B
2128 * sets a special bit in the status word to let us
2129 * know that a frame has been downloaded, but the
2130 * original 3c900/3c905 adapters don't do that.
2131 * Consequently, we have to use a different test if
2132 * xl_type != XL_TYPE_905B.
2134 while (sc->xl_cdata.xl_tx_head != NULL) {
2135 cur_tx = sc->xl_cdata.xl_tx_head;
2137 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2140 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2141 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2142 BUS_DMASYNC_POSTWRITE);
2143 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2144 m_freem(cur_tx->xl_mbuf);
2145 cur_tx->xl_mbuf = NULL;
2148 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2149 sc->xl_cdata.xl_tx_free = cur_tx;
2152 if (sc->xl_cdata.xl_tx_head == NULL) {
2153 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2154 sc->xl_wdog_timer = 0;
2155 sc->xl_cdata.xl_tx_tail = NULL;
2157 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2158 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2159 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2160 sc->xl_cdata.xl_tx_head->xl_phys);
2161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2167 xl_txeof_90xB(struct xl_softc *sc)
2169 struct xl_chain *cur_tx = NULL;
2170 struct ifnet *ifp = sc->xl_ifp;
2175 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2176 BUS_DMASYNC_POSTREAD);
2177 idx = sc->xl_cdata.xl_tx_cons;
2178 while (idx != sc->xl_cdata.xl_tx_prod) {
2180 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2182 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2183 XL_TXSTAT_DL_COMPLETE))
2186 if (cur_tx->xl_mbuf != NULL) {
2187 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2188 BUS_DMASYNC_POSTWRITE);
2189 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2190 m_freem(cur_tx->xl_mbuf);
2191 cur_tx->xl_mbuf = NULL;
2196 sc->xl_cdata.xl_tx_cnt--;
2197 XL_INC(idx, XL_TX_LIST_CNT);
2200 if (sc->xl_cdata.xl_tx_cnt == 0)
2201 sc->xl_wdog_timer = 0;
2202 sc->xl_cdata.xl_tx_cons = idx;
2205 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2209 * TX 'end of channel' interrupt handler. Actually, we should
2210 * only get a 'TX complete' interrupt if there's a transmit error,
2211 * so this is really TX error handler.
2214 xl_txeoc(struct xl_softc *sc)
2220 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2221 if (txstat & XL_TXSTATUS_UNDERRUN ||
2222 txstat & XL_TXSTATUS_JABBER ||
2223 txstat & XL_TXSTATUS_RECLAIM) {
2224 device_printf(sc->xl_dev,
2225 "transmission error: %x\n", txstat);
2226 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2228 if (sc->xl_type == XL_TYPE_905B) {
2229 if (sc->xl_cdata.xl_tx_cnt) {
2233 i = sc->xl_cdata.xl_tx_cons;
2234 c = &sc->xl_cdata.xl_tx_chain[i];
2235 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2237 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2240 if (sc->xl_cdata.xl_tx_head != NULL)
2241 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2242 sc->xl_cdata.xl_tx_head->xl_phys);
2245 * Remember to set this for the
2246 * first generation 3c90X chips.
2248 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2249 if (txstat & XL_TXSTATUS_UNDERRUN &&
2250 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2251 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2252 device_printf(sc->xl_dev,
2253 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2255 CSR_WRITE_2(sc, XL_COMMAND,
2256 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2257 if (sc->xl_type == XL_TYPE_905B) {
2258 CSR_WRITE_2(sc, XL_COMMAND,
2259 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2261 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2262 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2264 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2265 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2268 * Write an arbitrary byte to the TX_STATUS register
2269 * to clear this interrupt/error and advance to the next.
2271 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2278 struct xl_softc *sc = arg;
2279 struct ifnet *ifp = sc->xl_ifp;
2284 #ifdef DEVICE_POLLING
2285 if (ifp->if_capenable & IFCAP_POLLING) {
2291 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS &&
2293 CSR_WRITE_2(sc, XL_COMMAND,
2294 XL_CMD_INTR_ACK|(status & XL_INTRS));
2296 if (status & XL_STAT_UP_COMPLETE) {
2299 curpkts = ifp->if_ipackets;
2301 if (curpkts == ifp->if_ipackets) {
2302 while (xl_rx_resync(sc))
2307 if (status & XL_STAT_DOWN_COMPLETE) {
2308 if (sc->xl_type == XL_TYPE_905B)
2314 if (status & XL_STAT_TX_COMPLETE) {
2319 if (status & XL_STAT_ADFAIL) {
2324 if (status & XL_STAT_STATSOFLOW) {
2325 sc->xl_stats_no_timeout = 1;
2326 xl_stats_update_locked(sc);
2327 sc->xl_stats_no_timeout = 0;
2331 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2332 if (sc->xl_type == XL_TYPE_905B)
2333 xl_start_90xB_locked(ifp);
2335 xl_start_locked(ifp);
2341 #ifdef DEVICE_POLLING
2343 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2345 struct xl_softc *sc = ifp->if_softc;
2348 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2349 xl_poll_locked(ifp, cmd, count);
2354 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2356 struct xl_softc *sc = ifp->if_softc;
2360 sc->rxcycles = count;
2362 if (sc->xl_type == XL_TYPE_905B)
2367 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2368 if (sc->xl_type == XL_TYPE_905B)
2369 xl_start_90xB_locked(ifp);
2371 xl_start_locked(ifp);
2374 if (cmd == POLL_AND_CHECK_STATUS) {
2377 status = CSR_READ_2(sc, XL_STATUS);
2378 if (status & XL_INTRS && status != 0xFFFF) {
2379 CSR_WRITE_2(sc, XL_COMMAND,
2380 XL_CMD_INTR_ACK|(status & XL_INTRS));
2382 if (status & XL_STAT_TX_COMPLETE) {
2387 if (status & XL_STAT_ADFAIL) {
2392 if (status & XL_STAT_STATSOFLOW) {
2393 sc->xl_stats_no_timeout = 1;
2394 xl_stats_update_locked(sc);
2395 sc->xl_stats_no_timeout = 0;
2400 #endif /* DEVICE_POLLING */
2403 * XXX: This is an entry point for callout which needs to take the lock.
2406 xl_stats_update(void *xsc)
2408 struct xl_softc *sc = xsc;
2412 if (xl_watchdog(sc) == EJUSTRETURN)
2415 xl_stats_update_locked(sc);
2419 xl_stats_update_locked(struct xl_softc *sc)
2421 struct ifnet *ifp = sc->xl_ifp;
2422 struct xl_stats xl_stats;
2425 struct mii_data *mii = NULL;
2429 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2431 if (sc->xl_miibus != NULL)
2432 mii = device_get_softc(sc->xl_miibus);
2434 p = (u_int8_t *)&xl_stats;
2436 /* Read all the stats registers. */
2439 for (i = 0; i < 16; i++)
2440 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2442 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2444 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2445 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision;
2448 * Boomerang and cyclone chips have an extra stats counter
2449 * in window 4 (BadSSD). We have to read this too in order
2450 * to clear out all the stats registers and avoid a statsoflow
2454 CSR_READ_1(sc, XL_W4_BADSSD);
2456 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2461 if (!sc->xl_stats_no_timeout)
2462 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
2466 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2467 * pointers to the fragment pointers.
2470 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2474 struct ifnet *ifp = sc->xl_ifp;
2479 * Start packing the mbufs in this chain into
2480 * the fragment pointers. Stop when we run out
2481 * of fragments or hit the end of the mbuf chain.
2483 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2484 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2486 if (error && error != EFBIG) {
2488 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2493 * Handle special case: we used up all 63 fragments,
2494 * but we have more mbufs left in the chain. Copy the
2495 * data into an mbuf cluster. Note that we don't
2496 * bother clearing the values in the other fragment
2497 * pointers/counters; it wouldn't gain us anything,
2498 * and would waste cycles.
2503 m_new = m_defrag(m_head, M_DONTWAIT);
2504 if (m_new == NULL) {
2511 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2512 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2515 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2520 if (sc->xl_type == XL_TYPE_905B) {
2521 status = XL_TXSTAT_RND_DEFEAT;
2523 #ifndef XL905B_TXCSUM_BROKEN
2524 if (m_head->m_pkthdr.csum_flags) {
2525 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2526 status |= XL_TXSTAT_IPCKSUM;
2527 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2528 status |= XL_TXSTAT_TCPCKSUM;
2529 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2530 status |= XL_TXSTAT_UDPCKSUM;
2533 c->xl_ptr->xl_status = htole32(status);
2536 c->xl_mbuf = m_head;
2537 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2542 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2543 * to the mbuf data regions directly in the transmit lists. We also save a
2544 * copy of the pointers since the transmit list fragment pointers are
2545 * physical addresses.
2549 xl_start(struct ifnet *ifp)
2551 struct xl_softc *sc = ifp->if_softc;
2555 if (sc->xl_type == XL_TYPE_905B)
2556 xl_start_90xB_locked(ifp);
2558 xl_start_locked(ifp);
2564 xl_start_locked(struct ifnet *ifp)
2566 struct xl_softc *sc = ifp->if_softc;
2567 struct mbuf *m_head = NULL;
2568 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2569 struct xl_chain *prev_tx;
2576 * Check for an available queue slot. If there are none,
2579 if (sc->xl_cdata.xl_tx_free == NULL) {
2582 if (sc->xl_cdata.xl_tx_free == NULL) {
2583 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2588 start_tx = sc->xl_cdata.xl_tx_free;
2590 while (sc->xl_cdata.xl_tx_free != NULL) {
2591 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2595 /* Pick a descriptor off the free list. */
2597 cur_tx = sc->xl_cdata.xl_tx_free;
2599 /* Pack the data into the descriptor. */
2600 error = xl_encap(sc, cur_tx, m_head);
2606 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2607 cur_tx->xl_next = NULL;
2609 /* Chain it together. */
2611 prev->xl_next = cur_tx;
2612 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2617 * If there's a BPF listener, bounce a copy of this frame
2620 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2624 * If there are no packets queued, bail.
2630 * Place the request for the upload interrupt
2631 * in the last descriptor in the chain. This way, if
2632 * we're chaining several packets at once, we'll only
2633 * get an interupt once for the whole chain rather than
2634 * once for each packet.
2636 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2638 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2639 BUS_DMASYNC_PREWRITE);
2642 * Queue the packets. If the TX channel is clear, update
2643 * the downlist pointer register.
2645 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2648 if (sc->xl_cdata.xl_tx_head != NULL) {
2649 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2650 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2651 htole32(start_tx->xl_phys);
2652 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2653 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2654 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2655 sc->xl_cdata.xl_tx_tail = cur_tx;
2657 sc->xl_cdata.xl_tx_head = start_tx;
2658 sc->xl_cdata.xl_tx_tail = cur_tx;
2660 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2661 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2663 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2668 * Set a timeout in case the chip goes out to lunch.
2670 sc->xl_wdog_timer = 5;
2673 * XXX Under certain conditions, usually on slower machines
2674 * where interrupts may be dropped, it's possible for the
2675 * adapter to chew up all the buffers in the receive ring
2676 * and stall, without us being able to do anything about it.
2677 * To guard against this, we need to make a pass over the
2678 * RX queue to make sure there aren't any packets pending.
2679 * Doing it here means we can flush the receive ring at the
2680 * same time the chip is DMAing the transmit descriptors we
2683 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2684 * nature of their chips in all their marketing literature;
2685 * we may as well take advantage of it. :)
2687 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2691 xl_start_90xB_locked(struct ifnet *ifp)
2693 struct xl_softc *sc = ifp->if_softc;
2694 struct mbuf *m_head = NULL;
2695 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2696 struct xl_chain *prev_tx;
2701 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
2704 idx = sc->xl_cdata.xl_tx_prod;
2705 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2707 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2709 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2710 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2714 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2719 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2721 /* Pack the data into the descriptor. */
2722 error = xl_encap(sc, cur_tx, m_head);
2728 /* Chain it together. */
2730 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2734 * If there's a BPF listener, bounce a copy of this frame
2737 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2739 XL_INC(idx, XL_TX_LIST_CNT);
2740 sc->xl_cdata.xl_tx_cnt++;
2744 * If there are no packets queued, bail.
2750 * Place the request for the upload interrupt
2751 * in the last descriptor in the chain. This way, if
2752 * we're chaining several packets at once, we'll only
2753 * get an interupt once for the whole chain rather than
2754 * once for each packet.
2756 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2758 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2759 BUS_DMASYNC_PREWRITE);
2761 /* Start transmission */
2762 sc->xl_cdata.xl_tx_prod = idx;
2763 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2766 * Set a timeout in case the chip goes out to lunch.
2768 sc->xl_wdog_timer = 5;
2774 struct xl_softc *sc = xsc;
2782 xl_init_locked(struct xl_softc *sc)
2784 struct ifnet *ifp = sc->xl_ifp;
2786 u_int16_t rxfilt = 0;
2787 struct mii_data *mii = NULL;
2792 * Cancel pending I/O and free all RX/TX buffers.
2796 if (sc->xl_miibus == NULL) {
2797 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2800 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2804 if (sc->xl_miibus != NULL)
2805 mii = device_get_softc(sc->xl_miibus);
2807 /* Init our MAC address */
2809 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2810 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2811 IF_LLADDR(sc->xl_ifp)[i]);
2814 /* Clear the station mask. */
2815 for (i = 0; i < 3; i++)
2816 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2818 /* Reset TX and RX. */
2819 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2821 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2824 /* Init circular RX list. */
2825 error = xl_list_rx_init(sc);
2827 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2833 /* Init TX descriptors. */
2834 if (sc->xl_type == XL_TYPE_905B)
2835 error = xl_list_tx_init_90xB(sc);
2837 error = xl_list_tx_init(sc);
2839 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2846 * Set the TX freethresh value.
2847 * Note that this has no effect on 3c905B "cyclone"
2848 * cards but is required for 3c900/3c905 "boomerang"
2849 * cards in order to enable the download engine.
2851 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2853 /* Set the TX start threshold for best performance. */
2854 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2857 * If this is a 3c905B, also set the tx reclaim threshold.
2858 * This helps cut down on the number of tx reclaim errors
2859 * that could happen on a busy network. The chip multiplies
2860 * the register value by 16 to obtain the actual threshold
2861 * in bytes, so we divide by 16 when setting the value here.
2862 * The existing threshold value can be examined by reading
2863 * the register at offset 9 in window 5.
2865 if (sc->xl_type == XL_TYPE_905B) {
2866 CSR_WRITE_2(sc, XL_COMMAND,
2867 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2870 /* Set RX filter bits. */
2872 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2874 /* Set the individual bit to receive frames for this host only. */
2875 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2877 /* If we want promiscuous mode, set the allframes bit. */
2878 if (ifp->if_flags & IFF_PROMISC) {
2879 rxfilt |= XL_RXFILTER_ALLFRAMES;
2880 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2882 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2883 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2887 * Set capture broadcast bit to capture broadcast frames.
2889 if (ifp->if_flags & IFF_BROADCAST) {
2890 rxfilt |= XL_RXFILTER_BROADCAST;
2891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2893 rxfilt &= ~XL_RXFILTER_BROADCAST;
2894 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2898 * Program the multicast filter, if necessary.
2900 if (sc->xl_type == XL_TYPE_905B)
2901 xl_setmulti_hash(sc);
2906 * Load the address of the RX list. We have to
2907 * stall the upload engine before we can manipulate
2908 * the uplist pointer register, then unstall it when
2909 * we're finished. We also have to wait for the
2910 * stall command to complete before proceeding.
2911 * Note that we have to do this after any RX resets
2912 * have completed since the uplist register is cleared
2915 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2917 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2918 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2921 if (sc->xl_type == XL_TYPE_905B) {
2922 /* Set polling interval */
2923 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2924 /* Load the address of the TX list */
2925 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2927 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2928 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2929 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2934 * If the coax transceiver is on, make sure to enable
2935 * the DC-DC converter.
2938 if (sc->xl_xcvr == XL_XCVR_COAX)
2939 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2941 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2944 * increase packet size to allow reception of 802.1q or ISL packets.
2945 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2946 * control register. For 3c90xB/C chips, use the RX packet size
2950 if (sc->xl_type == XL_TYPE_905B)
2951 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2954 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2955 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2956 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2959 /* Clear out the stats counters. */
2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2961 sc->xl_stats_no_timeout = 1;
2962 xl_stats_update_locked(sc);
2963 sc->xl_stats_no_timeout = 0;
2965 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2966 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2969 * Enable interrupts.
2971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2972 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2973 #ifdef DEVICE_POLLING
2974 /* Disable interrupts if we are polling. */
2975 if (ifp->if_capenable & IFCAP_POLLING)
2976 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2979 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2980 if (sc->xl_flags & XL_FLAG_FUNCREG)
2981 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2983 /* Set the RX early threshold */
2984 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2985 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2987 /* Enable receiver and transmitter. */
2988 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2990 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2993 /* XXX Downcall to miibus. */
2997 /* Select window 7 for normal operations. */
3000 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3001 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3003 sc->xl_wdog_timer = 0;
3004 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
3008 * Set media options.
3011 xl_ifmedia_upd(struct ifnet *ifp)
3013 struct xl_softc *sc = ifp->if_softc;
3014 struct ifmedia *ifm = NULL;
3015 struct mii_data *mii = NULL;
3019 if (sc->xl_miibus != NULL)
3020 mii = device_get_softc(sc->xl_miibus);
3024 ifm = &mii->mii_media;
3026 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3031 xl_setmode(sc, ifm->ifm_media);
3038 if (sc->xl_media & XL_MEDIAOPT_MII ||
3039 sc->xl_media & XL_MEDIAOPT_BTX ||
3040 sc->xl_media & XL_MEDIAOPT_BT4) {
3043 xl_setmode(sc, ifm->ifm_media);
3052 * Report current media status.
3055 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3057 struct xl_softc *sc = ifp->if_softc;
3059 u_int16_t status = 0;
3060 struct mii_data *mii = NULL;
3064 if (sc->xl_miibus != NULL)
3065 mii = device_get_softc(sc->xl_miibus);
3068 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3071 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3072 icfg >>= XL_ICFG_CONNECTOR_BITS;
3074 ifmr->ifm_active = IFM_ETHER;
3075 ifmr->ifm_status = IFM_AVALID;
3077 if ((status & XL_MEDIASTAT_CARRIER) == 0)
3078 ifmr->ifm_status |= IFM_ACTIVE;
3082 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3083 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3084 ifmr->ifm_active |= IFM_FDX;
3086 ifmr->ifm_active |= IFM_HDX;
3089 if (sc->xl_type == XL_TYPE_905B &&
3090 sc->xl_media == XL_MEDIAOPT_10FL) {
3091 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3092 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3093 ifmr->ifm_active |= IFM_FDX;
3095 ifmr->ifm_active |= IFM_HDX;
3097 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3100 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3103 * XXX MII and BTX/AUTO should be separate cases.
3106 case XL_XCVR_100BTX:
3111 ifmr->ifm_active = mii->mii_media_active;
3112 ifmr->ifm_status = mii->mii_media_status;
3115 case XL_XCVR_100BFX:
3116 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3119 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3127 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3129 struct xl_softc *sc = ifp->if_softc;
3130 struct ifreq *ifr = (struct ifreq *) data;
3132 struct mii_data *mii = NULL;
3140 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3141 if (ifp->if_flags & IFF_UP) {
3142 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3143 ifp->if_flags & IFF_PROMISC &&
3144 !(sc->xl_if_flags & IFF_PROMISC)) {
3145 rxfilt |= XL_RXFILTER_ALLFRAMES;
3146 CSR_WRITE_2(sc, XL_COMMAND,
3147 XL_CMD_RX_SET_FILT|rxfilt);
3149 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3150 !(ifp->if_flags & IFF_PROMISC) &&
3151 sc->xl_if_flags & IFF_PROMISC) {
3152 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3153 CSR_WRITE_2(sc, XL_COMMAND,
3154 XL_CMD_RX_SET_FILT|rxfilt);
3157 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3161 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3164 sc->xl_if_flags = ifp->if_flags;
3170 /* XXX Downcall from if_addmulti() possibly with locks held. */
3172 if (sc->xl_type == XL_TYPE_905B)
3173 xl_setmulti_hash(sc);
3181 if (sc->xl_miibus != NULL)
3182 mii = device_get_softc(sc->xl_miibus);
3184 error = ifmedia_ioctl(ifp, ifr,
3185 &sc->ifmedia, command);
3187 error = ifmedia_ioctl(ifp, ifr,
3188 &mii->mii_media, command);
3191 #ifdef DEVICE_POLLING
3192 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3193 !(ifp->if_capenable & IFCAP_POLLING)) {
3194 error = ether_poll_register(xl_poll, ifp);
3198 /* Disable interrupts */
3199 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3200 ifp->if_capenable |= IFCAP_POLLING;
3205 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3206 ifp->if_capenable & IFCAP_POLLING) {
3207 error = ether_poll_deregister(ifp);
3208 /* Enable interrupts. */
3210 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
3211 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
3212 if (sc->xl_flags & XL_FLAG_FUNCREG)
3213 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle,
3215 ifp->if_capenable &= ~IFCAP_POLLING;
3219 #endif /* DEVICE_POLLING */
3221 ifp->if_capenable = ifr->ifr_reqcap;
3222 if (ifp->if_capenable & IFCAP_TXCSUM)
3223 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3225 ifp->if_hwassist = 0;
3229 error = ether_ioctl(ifp, command, data);
3237 xl_watchdog(struct xl_softc *sc)
3239 struct ifnet *ifp = sc->xl_ifp;
3240 u_int16_t status = 0;
3244 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3249 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3250 device_printf(sc->xl_dev, "watchdog timeout\n");
3252 if (status & XL_MEDIASTAT_CARRIER)
3253 device_printf(sc->xl_dev,
3254 "no carrier - transceiver cable problem?\n");
3262 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3263 if (sc->xl_type == XL_TYPE_905B)
3264 xl_start_90xB_locked(ifp);
3266 xl_start_locked(ifp);
3269 return (EJUSTRETURN);
3273 * Stop the adapter and free any mbufs allocated to the
3277 xl_stop(struct xl_softc *sc)
3280 struct ifnet *ifp = sc->xl_ifp;
3284 sc->xl_wdog_timer = 0;
3286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3288 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3289 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3291 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3292 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3296 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3298 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3302 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3303 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3304 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3305 if (sc->xl_flags & XL_FLAG_FUNCREG)
3306 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3308 /* Stop the stats updater. */
3309 callout_stop(&sc->xl_stat_callout);
3312 * Free data in the RX lists.
3314 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3315 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3316 bus_dmamap_unload(sc->xl_mtag,
3317 sc->xl_cdata.xl_rx_chain[i].xl_map);
3318 bus_dmamap_destroy(sc->xl_mtag,
3319 sc->xl_cdata.xl_rx_chain[i].xl_map);
3320 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3321 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3324 if (sc->xl_ldata.xl_rx_list != NULL)
3325 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3327 * Free the TX list buffers.
3329 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3330 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3331 bus_dmamap_unload(sc->xl_mtag,
3332 sc->xl_cdata.xl_tx_chain[i].xl_map);
3333 bus_dmamap_destroy(sc->xl_mtag,
3334 sc->xl_cdata.xl_tx_chain[i].xl_map);
3335 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3336 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3339 if (sc->xl_ldata.xl_tx_list != NULL)
3340 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3342 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3346 * Stop all chip I/O so that the kernel's probe routines don't
3347 * get confused by errant DMAs when rebooting.
3350 xl_shutdown(device_t dev)
3352 struct xl_softc *sc;
3354 sc = device_get_softc(dev);
3363 xl_suspend(device_t dev)
3365 struct xl_softc *sc;
3367 sc = device_get_softc(dev);
3377 xl_resume(device_t dev)
3379 struct xl_softc *sc;
3382 sc = device_get_softc(dev);
3388 if (ifp->if_flags & IFF_UP)