2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
100 * This driver is in the /sys/pci directory because it only supports
104 #include <sys/param.h>
105 #include <sys/systm.h>
106 #include <sys/sockio.h>
107 #include <sys/endian.h>
108 #include <sys/mbuf.h>
109 #include <sys/kernel.h>
110 #include <sys/module.h>
111 #include <sys/socket.h>
112 #include <sys/taskqueue.h>
115 #include <net/if_arp.h>
116 #include <net/ethernet.h>
117 #include <net/if_dl.h>
118 #include <net/if_media.h>
119 #include <net/if_types.h>
123 #include <machine/bus.h>
124 #include <machine/resource.h>
126 #include <sys/rman.h>
128 #include <dev/mii/mii.h>
129 #include <dev/mii/miivar.h>
131 #include <dev/pci/pcireg.h>
132 #include <dev/pci/pcivar.h>
134 MODULE_DEPEND(xl, pci, 1, 1, 1);
135 MODULE_DEPEND(xl, ether, 1, 1, 1);
136 MODULE_DEPEND(xl, miibus, 1, 1, 1);
138 /* "device miibus" required. See GENERIC if you get errors here. */
139 #include "miibus_if.h"
141 #include <pci/if_xlreg.h>
144 * TX Checksumming is disabled by default for two reasons:
145 * - TX Checksumming will occasionally produce corrupt packets
146 * - TX Checksumming seems to reduce performance
148 * Only 905B/C cards were reported to have this problem, it is possible
149 * that later chips _may_ be immune.
151 #define XL905B_TXCSUM_BROKEN 1
153 #ifdef XL905B_TXCSUM_BROKEN
154 #define XL905B_CSUM_FEATURES 0
156 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
160 * Various supported device vendors/types and their names.
162 static struct xl_type xl_devs[] = {
163 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
164 "3Com 3c900-TPO Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
166 "3Com 3c900-COMBO Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
168 "3Com 3c905-TX Fast Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
170 "3Com 3c905-T4 Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
172 "3Com 3c900B-TPO Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
174 "3Com 3c900B-COMBO Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
176 "3Com 3c900B-TPC Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
178 "3Com 3c900B-FL Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
180 "3Com 3c905B-TX Fast Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
182 "3Com 3c905B-T4 Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
184 "3Com 3c905B-FX/SC Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
186 "3Com 3c905B-COMBO Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
188 "3Com 3c905C-TX Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
190 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
192 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
194 "3Com 3c980 Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
196 "3Com 3c980C Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
198 "3Com 3cSOHO100-TX OfficeConnect" },
199 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
200 "3Com 3c450-TX HomeConnect" },
201 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
202 "3Com 3c555 Fast Etherlink XL" },
203 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
204 "3Com 3c556 Fast Etherlink XL" },
205 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
206 "3Com 3c556B Fast Etherlink XL" },
207 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
208 "3Com 3c575TX Fast Etherlink XL" },
209 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
210 "3Com 3c575B Fast Etherlink XL" },
211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
212 "3Com 3c575C Fast Etherlink XL" },
213 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
214 "3Com 3c656 Fast Etherlink XL" },
215 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
216 "3Com 3c656B Fast Etherlink XL" },
217 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
218 "3Com 3c656C Fast Etherlink XL" },
222 static int xl_probe(device_t);
223 static int xl_attach(device_t);
224 static int xl_detach(device_t);
226 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
227 static void xl_stats_update(void *);
228 static void xl_stats_update_locked(struct xl_softc *);
229 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf *);
230 static void xl_rxeof(struct xl_softc *);
231 static void xl_rxeof_task(void *, int);
232 static int xl_rx_resync(struct xl_softc *);
233 static void xl_txeof(struct xl_softc *);
234 static void xl_txeof_90xB(struct xl_softc *);
235 static void xl_txeoc(struct xl_softc *);
236 static void xl_intr(void *);
237 static void xl_start(struct ifnet *);
238 static void xl_start_locked(struct ifnet *);
239 static void xl_start_90xB_locked(struct ifnet *);
240 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
241 static void xl_init(void *);
242 static void xl_init_locked(struct xl_softc *);
243 static void xl_stop(struct xl_softc *);
244 static void xl_watchdog(struct ifnet *);
245 static void xl_shutdown(device_t);
246 static int xl_suspend(device_t);
247 static int xl_resume(device_t);
249 #ifdef DEVICE_POLLING
250 static void xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
251 static void xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
252 #endif /* DEVICE_POLLING */
254 static int xl_ifmedia_upd(struct ifnet *);
255 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
257 static int xl_eeprom_wait(struct xl_softc *);
258 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
259 static void xl_mii_sync(struct xl_softc *);
260 static void xl_mii_send(struct xl_softc *, u_int32_t, int);
261 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *);
262 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *);
264 static void xl_setcfg(struct xl_softc *);
265 static void xl_setmode(struct xl_softc *, int);
266 static void xl_setmulti(struct xl_softc *);
267 static void xl_setmulti_hash(struct xl_softc *);
268 static void xl_reset(struct xl_softc *);
269 static int xl_list_rx_init(struct xl_softc *);
270 static int xl_list_tx_init(struct xl_softc *);
271 static int xl_list_tx_init_90xB(struct xl_softc *);
272 static void xl_wait(struct xl_softc *);
273 static void xl_mediacheck(struct xl_softc *);
274 static void xl_choose_media(struct xl_softc *sc, int *media);
275 static void xl_choose_xcvr(struct xl_softc *, int);
276 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
277 static void xl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
278 static void xl_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
280 static void xl_testpacket(struct xl_softc *);
283 static int xl_miibus_readreg(device_t, int, int);
284 static int xl_miibus_writereg(device_t, int, int, int);
285 static void xl_miibus_statchg(device_t);
286 static void xl_miibus_mediainit(device_t);
288 static device_method_t xl_methods[] = {
289 /* Device interface */
290 DEVMETHOD(device_probe, xl_probe),
291 DEVMETHOD(device_attach, xl_attach),
292 DEVMETHOD(device_detach, xl_detach),
293 DEVMETHOD(device_shutdown, xl_shutdown),
294 DEVMETHOD(device_suspend, xl_suspend),
295 DEVMETHOD(device_resume, xl_resume),
298 DEVMETHOD(bus_print_child, bus_generic_print_child),
299 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
302 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
303 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
304 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
305 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
310 static driver_t xl_driver = {
313 sizeof(struct xl_softc)
316 static devclass_t xl_devclass;
318 DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0);
319 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0);
320 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
323 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
328 *paddr = segs->ds_addr;
332 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
333 bus_size_t mapsize, int error)
340 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
342 *paddr = segs->ds_addr;
346 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
347 bus_size_t mapsize, int error)
355 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
359 for (i = 0; i < nseg; i++) {
360 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
361 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
362 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
363 total_len += segs[i].ds_len;
365 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
367 l->xl_status = htole32(total_len);
372 * Murphy's law says that it's possible the chip can wedge and
373 * the 'command in progress' bit may never clear. Hence, we wait
374 * only a finite amount of time to avoid getting caught in an
375 * infinite loop. Normally this delay routine would be a macro,
376 * but it isn't called during normal operation so we can afford
377 * to make it a function.
380 xl_wait(struct xl_softc *sc)
384 for (i = 0; i < XL_TIMEOUT; i++) {
385 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
390 if_printf(sc->xl_ifp, "command never completed!\n");
394 * MII access routines are provided for adapters with external
395 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
396 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
397 * Note: if you don't perform the MDIO operations just right,
398 * it's possible to end up with code that works correctly with
399 * some chips/CPUs/processor speeds/bus speeds/etc but not
403 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
404 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
407 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
408 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
411 * Sync the PHYs by setting data bit and strobing the clock 32 times.
414 xl_mii_sync(struct xl_softc *sc)
419 MII_SET(XL_MII_DIR|XL_MII_DATA);
421 for (i = 0; i < 32; i++) {
423 MII_SET(XL_MII_DATA);
424 MII_SET(XL_MII_DATA);
426 MII_SET(XL_MII_DATA);
427 MII_SET(XL_MII_DATA);
432 * Clock a series of bits through the MII.
435 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
442 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
444 MII_SET(XL_MII_DATA);
446 MII_CLR(XL_MII_DATA);
454 * Read an PHY register through the MII.
457 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
461 /*XL_LOCK_ASSERT(sc);*/
463 /* Set up frame for RX. */
464 frame->mii_stdelim = XL_MII_STARTDELIM;
465 frame->mii_opcode = XL_MII_READOP;
466 frame->mii_turnaround = 0;
469 /* Select register window 4. */
472 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
473 /* Turn on data xmit. */
478 /* Send command/address info. */
479 xl_mii_send(sc, frame->mii_stdelim, 2);
480 xl_mii_send(sc, frame->mii_opcode, 2);
481 xl_mii_send(sc, frame->mii_phyaddr, 5);
482 xl_mii_send(sc, frame->mii_regaddr, 5);
485 MII_CLR((XL_MII_CLK|XL_MII_DATA));
493 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
497 * Now try reading data bits. If the ack failed, we still
498 * need to clock through 16 cycles to keep the PHY(s) in sync.
501 for (i = 0; i < 16; i++) {
508 for (i = 0x8000; i; i >>= 1) {
511 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
512 frame->mii_data |= i;
521 return (ack ? 1 : 0);
525 * Write to a PHY register through the MII.
528 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
531 /*XL_LOCK_ASSERT(sc);*/
533 /* Set up frame for TX. */
534 frame->mii_stdelim = XL_MII_STARTDELIM;
535 frame->mii_opcode = XL_MII_WRITEOP;
536 frame->mii_turnaround = XL_MII_TURNAROUND;
538 /* Select the window 4. */
541 /* Turn on data output. */
546 xl_mii_send(sc, frame->mii_stdelim, 2);
547 xl_mii_send(sc, frame->mii_opcode, 2);
548 xl_mii_send(sc, frame->mii_phyaddr, 5);
549 xl_mii_send(sc, frame->mii_regaddr, 5);
550 xl_mii_send(sc, frame->mii_turnaround, 2);
551 xl_mii_send(sc, frame->mii_data, 16);
564 xl_miibus_readreg(device_t dev, int phy, int reg)
567 struct xl_mii_frame frame;
569 sc = device_get_softc(dev);
572 * Pretend that PHYs are only available at MII address 24.
573 * This is to guard against problems with certain 3Com ASIC
574 * revisions that incorrectly map the internal transceiver
575 * control registers at all MII addresses. This can cause
576 * the miibus code to attach the same PHY several times over.
578 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
581 bzero((char *)&frame, sizeof(frame));
582 frame.mii_phyaddr = phy;
583 frame.mii_regaddr = reg;
585 xl_mii_readreg(sc, &frame);
587 return (frame.mii_data);
591 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
594 struct xl_mii_frame frame;
596 sc = device_get_softc(dev);
598 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
601 bzero((char *)&frame, sizeof(frame));
602 frame.mii_phyaddr = phy;
603 frame.mii_regaddr = reg;
604 frame.mii_data = data;
606 xl_mii_writereg(sc, &frame);
612 xl_miibus_statchg(device_t dev)
615 struct mii_data *mii;
617 sc = device_get_softc(dev);
618 mii = device_get_softc(sc->xl_miibus);
620 /*XL_LOCK_ASSERT(sc);*/
624 /* Set ASIC's duplex mode to match the PHY. */
626 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
627 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
629 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
630 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
634 * Special support for the 3c905B-COMBO. This card has 10/100 support
635 * plus BNC and AUI ports. This means we will have both an miibus attached
636 * plus some non-MII media settings. In order to allow this, we have to
637 * add the extra media to the miibus's ifmedia struct, but we can't do
638 * that during xl_attach() because the miibus hasn't been attached yet.
639 * So instead, we wait until the miibus probe/attach is done, at which
640 * point we will get a callback telling is that it's safe to add our
644 xl_miibus_mediainit(device_t dev)
647 struct mii_data *mii;
650 sc = device_get_softc(dev);
651 mii = device_get_softc(sc->xl_miibus);
652 ifm = &mii->mii_media;
654 /*XL_LOCK_ASSERT(sc);*/
656 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
658 * Check for a 10baseFL board in disguise.
660 if (sc->xl_type == XL_TYPE_905B &&
661 sc->xl_media == XL_MEDIAOPT_10FL) {
663 if_printf(sc->xl_ifp,
665 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
666 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
668 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
670 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
673 if_printf(sc->xl_ifp, "found AUI\n");
674 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
678 if (sc->xl_media & XL_MEDIAOPT_BNC) {
680 if_printf(sc->xl_ifp, "found BNC\n");
681 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
686 * The EEPROM is slow: give it time to come ready after issuing
690 xl_eeprom_wait(struct xl_softc *sc)
694 for (i = 0; i < 100; i++) {
695 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
702 if_printf(sc->xl_ifp, "eeprom failed to come ready\n");
710 * Read a sequence of words from the EEPROM. Note that ethernet address
711 * data is stored in the EEPROM in network byte order.
714 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
717 u_int16_t word = 0, *ptr;
721 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
722 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
724 * XXX: WARNING! DANGER!
725 * It's easy to accidentally overwrite the rom content!
726 * Note: the 3c575 uses 8bit EEPROM offsets.
730 if (xl_eeprom_wait(sc))
733 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
736 for (i = 0; i < cnt; i++) {
737 if (sc->xl_flags & XL_FLAG_8BITROM)
738 CSR_WRITE_2(sc, XL_W0_EE_CMD,
739 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
741 CSR_WRITE_2(sc, XL_W0_EE_CMD,
742 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
743 err = xl_eeprom_wait(sc);
746 word = CSR_READ_2(sc, XL_W0_EE_DATA);
747 ptr = (u_int16_t *)(dest + (i * 2));
754 return (err ? 1 : 0);
758 * NICs older than the 3c905B have only one multicast option, which
759 * is to enable reception of all multicast frames.
762 xl_setmulti(struct xl_softc *sc)
764 struct ifnet *ifp = sc->xl_ifp;
765 struct ifmultiaddr *ifma;
772 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
774 if (ifp->if_flags & IFF_ALLMULTI) {
775 rxfilt |= XL_RXFILTER_ALLMULTI;
776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
780 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
784 rxfilt |= XL_RXFILTER_ALLMULTI;
786 rxfilt &= ~XL_RXFILTER_ALLMULTI;
788 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
792 * 3c905B adapters have a hash filter that we can program.
795 xl_setmulti_hash(struct xl_softc *sc)
797 struct ifnet *ifp = sc->xl_ifp;
799 struct ifmultiaddr *ifma;
806 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
808 if (ifp->if_flags & IFF_ALLMULTI) {
809 rxfilt |= XL_RXFILTER_ALLMULTI;
810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
813 rxfilt &= ~XL_RXFILTER_ALLMULTI;
815 /* first, zot all the existing hash bits */
816 for (i = 0; i < XL_HASHFILT_SIZE; i++)
817 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
819 /* now program new ones */
820 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
821 if (ifma->ifma_addr->sa_family != AF_LINK)
824 * Note: the 3c905B currently only supports a 64-bit hash
825 * table, which means we really only need 6 bits, but the
826 * manual indicates that future chip revisions will have a
827 * 256-bit hash table, hence the routine is set up to
828 * calculate 8 bits of position info in case we need it some
830 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have
831 * a 256 bit hash table. This means we have to use all 8 bits
832 * regardless. On older cards, the upper 2 bits will be
835 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
836 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
837 CSR_WRITE_2(sc, XL_COMMAND,
838 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
843 rxfilt |= XL_RXFILTER_MULTIHASH;
845 rxfilt &= ~XL_RXFILTER_MULTIHASH;
847 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
852 xl_testpacket(struct xl_softc *sc)
855 struct ifnet *ifp = sc->xl_ifp;
857 MGETHDR(m, M_DONTWAIT, MT_DATA);
862 bcopy(&IFP2ENADDR(sc->xl_ifp),
863 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
864 bcopy(&IFP2ENADDR(sc->xl_ifp),
865 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
866 mtod(m, struct ether_header *)->ether_type = htons(3);
867 mtod(m, unsigned char *)[14] = 0;
868 mtod(m, unsigned char *)[15] = 0;
869 mtod(m, unsigned char *)[16] = 0xE3;
870 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
871 IFQ_ENQUEUE(&ifp->if_snd, m);
877 xl_setcfg(struct xl_softc *sc)
881 /*XL_LOCK_ASSERT(sc);*/
884 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
885 icfg &= ~XL_ICFG_CONNECTOR_MASK;
886 if (sc->xl_media & XL_MEDIAOPT_MII ||
887 sc->xl_media & XL_MEDIAOPT_BT4)
888 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
889 if (sc->xl_media & XL_MEDIAOPT_BTX)
890 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
892 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
893 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
897 xl_setmode(struct xl_softc *sc, int media)
901 char *pmsg = "", *dmsg = "";
903 /*XL_LOCK_ASSERT(sc);*/
906 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
908 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
910 if (sc->xl_media & XL_MEDIAOPT_BT) {
911 if (IFM_SUBTYPE(media) == IFM_10_T) {
912 pmsg = "10baseT transceiver";
913 sc->xl_xcvr = XL_XCVR_10BT;
914 icfg &= ~XL_ICFG_CONNECTOR_MASK;
915 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
916 mediastat |= XL_MEDIASTAT_LINKBEAT |
917 XL_MEDIASTAT_JABGUARD;
918 mediastat &= ~XL_MEDIASTAT_SQEENB;
922 if (sc->xl_media & XL_MEDIAOPT_BFX) {
923 if (IFM_SUBTYPE(media) == IFM_100_FX) {
924 pmsg = "100baseFX port";
925 sc->xl_xcvr = XL_XCVR_100BFX;
926 icfg &= ~XL_ICFG_CONNECTOR_MASK;
927 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
928 mediastat |= XL_MEDIASTAT_LINKBEAT;
929 mediastat &= ~XL_MEDIASTAT_SQEENB;
933 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
934 if (IFM_SUBTYPE(media) == IFM_10_5) {
936 sc->xl_xcvr = XL_XCVR_AUI;
937 icfg &= ~XL_ICFG_CONNECTOR_MASK;
938 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
939 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
940 XL_MEDIASTAT_JABGUARD);
941 mediastat |= ~XL_MEDIASTAT_SQEENB;
943 if (IFM_SUBTYPE(media) == IFM_10_FL) {
944 pmsg = "10baseFL transceiver";
945 sc->xl_xcvr = XL_XCVR_AUI;
946 icfg &= ~XL_ICFG_CONNECTOR_MASK;
947 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
948 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
949 XL_MEDIASTAT_JABGUARD);
950 mediastat |= ~XL_MEDIASTAT_SQEENB;
954 if (sc->xl_media & XL_MEDIAOPT_BNC) {
955 if (IFM_SUBTYPE(media) == IFM_10_2) {
957 sc->xl_xcvr = XL_XCVR_COAX;
958 icfg &= ~XL_ICFG_CONNECTOR_MASK;
959 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
960 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
961 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
965 if ((media & IFM_GMASK) == IFM_FDX ||
966 IFM_SUBTYPE(media) == IFM_100_FX) {
969 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
973 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
974 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
977 if (IFM_SUBTYPE(media) == IFM_10_2)
978 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
980 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
982 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
984 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
989 if_printf(sc->xl_ifp, "selecting %s, %s duplex\n", pmsg, dmsg);
993 xl_reset(struct xl_softc *sc)
1000 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1001 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1002 XL_RESETOPT_DISADVFD:0));
1005 * If we're using memory mapped register mode, pause briefly
1006 * after issuing the reset command before trying to access any
1007 * other registers. With my 3c575C cardbus card, failing to do
1008 * this results in the system locking up while trying to poll
1009 * the command busy bit in the status register.
1011 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1014 for (i = 0; i < XL_TIMEOUT; i++) {
1016 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1020 if (i == XL_TIMEOUT)
1021 if_printf(sc->xl_ifp, "reset didn't complete\n");
1023 /* Reset TX and RX. */
1024 /* Note: the RX reset takes an absurd amount of time
1025 * on newer versions of the Tornado chips such as those
1026 * on the 3c905CX and newer 3c908C cards. We wait an
1027 * extra amount of time so that xl_wait() doesn't complain
1028 * and annoy the users.
1030 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1033 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1036 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1037 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1039 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
1040 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
1041 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
1042 XL_RESETOPT_INVERT_LED : 0) |
1043 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
1044 XL_RESETOPT_INVERT_MII : 0));
1047 /* Wait a little while for the chip to get its brains in order. */
1052 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1053 * IDs against our list and return a device name if we find a match.
1056 xl_probe(device_t dev)
1062 while (t->xl_name != NULL) {
1063 if ((pci_get_vendor(dev) == t->xl_vid) &&
1064 (pci_get_device(dev) == t->xl_did)) {
1065 device_set_desc(dev, t->xl_name);
1066 return (BUS_PROBE_DEFAULT);
1075 * This routine is a kludge to work around possible hardware faults
1076 * or manufacturing defects that can cause the media options register
1077 * (or reset options register, as it's called for the first generation
1078 * 3c90x adapters) to return an incorrect result. I have encountered
1079 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1080 * which doesn't have any of the 'mediaopt' bits set. This screws up
1081 * the attach routine pretty badly because it doesn't know what media
1082 * to look for. If we find ourselves in this predicament, this routine
1083 * will try to guess the media options values and warn the user of a
1084 * possible manufacturing defect with his adapter/system/whatever.
1087 xl_mediacheck(struct xl_softc *sc)
1093 * If some of the media options bits are set, assume they are
1094 * correct. If not, try to figure it out down below.
1095 * XXX I should check for 10baseFL, but I don't have an adapter
1098 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1100 * Check the XCVR value. If it's not in the normal range
1101 * of values, we need to fake it up here.
1103 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1106 if_printf(sc->xl_ifp,
1107 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
1108 if_printf(sc->xl_ifp,
1109 "choosing new default based on card type\n");
1112 if (sc->xl_type == XL_TYPE_905B &&
1113 sc->xl_media & XL_MEDIAOPT_10FL)
1115 if_printf(sc->xl_ifp,
1116 "WARNING: no media options bits set in the media options register!!\n");
1117 if_printf(sc->xl_ifp,
1118 "this could be a manufacturing defect in your adapter or system\n");
1119 if_printf(sc->xl_ifp,
1120 "attempting to guess media type; you should probably consult your vendor\n");
1123 xl_choose_xcvr(sc, 1);
1127 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1132 * Read the device ID from the EEPROM.
1133 * This is what's loaded into the PCI device ID register, so it has
1134 * to be correct otherwise we wouldn't have gotten this far.
1136 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1139 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1140 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1141 sc->xl_media = XL_MEDIAOPT_BT;
1142 sc->xl_xcvr = XL_XCVR_10BT;
1144 if_printf(sc->xl_ifp,
1145 "guessing 10BaseT transceiver\n");
1147 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1148 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1149 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1150 sc->xl_xcvr = XL_XCVR_10BT;
1152 if_printf(sc->xl_ifp,
1153 "guessing COMBO (AUI/BNC/TP)\n");
1155 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1156 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1157 sc->xl_xcvr = XL_XCVR_10BT;
1159 if_printf(sc->xl_ifp, "guessing TPC (BNC/TP)\n");
1161 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1162 sc->xl_media = XL_MEDIAOPT_10FL;
1163 sc->xl_xcvr = XL_XCVR_AUI;
1165 if_printf(sc->xl_ifp, "guessing 10baseFL\n");
1167 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1168 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1169 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1170 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1171 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1172 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1173 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1174 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1175 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1176 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1177 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1178 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1179 sc->xl_media = XL_MEDIAOPT_MII;
1180 sc->xl_xcvr = XL_XCVR_MII;
1182 if_printf(sc->xl_ifp, "guessing MII\n");
1184 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1185 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1186 sc->xl_media = XL_MEDIAOPT_BT4;
1187 sc->xl_xcvr = XL_XCVR_MII;
1189 if_printf(sc->xl_ifp,
1190 "guessing 100baseT4/MII\n");
1192 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1193 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1194 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1195 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1196 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1197 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1198 sc->xl_media = XL_MEDIAOPT_BTX;
1199 sc->xl_xcvr = XL_XCVR_AUTO;
1201 if_printf(sc->xl_ifp,
1202 "guessing 10/100 internal\n");
1204 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1205 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1206 sc->xl_xcvr = XL_XCVR_AUTO;
1208 if_printf(sc->xl_ifp,
1209 "guessing 10/100 plus BNC/AUI\n");
1212 if_printf(sc->xl_ifp,
1213 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1214 sc->xl_media = XL_MEDIAOPT_BT;
1220 * Attach the interface. Allocate softc structures, do ifmedia
1221 * setup and ethernet/BPF attach.
1224 xl_attach(device_t dev)
1226 u_char eaddr[ETHER_ADDR_LEN];
1228 struct xl_softc *sc;
1231 int unit, error = 0, rid, res;
1234 sc = device_get_softc(dev);
1235 unit = device_get_unit(dev);
1237 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1239 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1241 did = pci_get_device(dev);
1244 if (did == TC_DEVICEID_HURRICANE_555)
1245 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1246 if (did == TC_DEVICEID_HURRICANE_556 ||
1247 did == TC_DEVICEID_HURRICANE_556B)
1248 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1249 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1250 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1251 if (did == TC_DEVICEID_HURRICANE_555 ||
1252 did == TC_DEVICEID_HURRICANE_556)
1253 sc->xl_flags |= XL_FLAG_8BITROM;
1254 if (did == TC_DEVICEID_HURRICANE_556B)
1255 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1257 if (did == TC_DEVICEID_HURRICANE_575A ||
1258 did == TC_DEVICEID_HURRICANE_575B ||
1259 did == TC_DEVICEID_HURRICANE_575C ||
1260 did == TC_DEVICEID_HURRICANE_656B ||
1261 did == TC_DEVICEID_TORNADO_656C)
1262 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1263 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM;
1264 if (did == TC_DEVICEID_HURRICANE_656)
1265 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1266 if (did == TC_DEVICEID_HURRICANE_575B)
1267 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1268 if (did == TC_DEVICEID_HURRICANE_575C)
1269 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1270 if (did == TC_DEVICEID_TORNADO_656C)
1271 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1272 if (did == TC_DEVICEID_HURRICANE_656 ||
1273 did == TC_DEVICEID_HURRICANE_656B)
1274 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1275 XL_FLAG_INVERT_LED_PWR;
1276 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1277 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1278 sc->xl_flags |= XL_FLAG_PHYOK;
1281 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1282 case TC_DEVICEID_HURRICANE_575A:
1283 case TC_DEVICEID_HURRICANE_575B:
1284 case TC_DEVICEID_HURRICANE_575C:
1285 sc->xl_flags |= XL_FLAG_NO_MMIO;
1292 * Map control/status registers.
1294 pci_enable_busmaster(dev);
1296 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1298 res = SYS_RES_MEMORY;
1300 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1303 if (sc->xl_res != NULL) {
1304 sc->xl_flags |= XL_FLAG_USE_MMIO;
1306 device_printf(dev, "using memory mapped I/O\n");
1309 res = SYS_RES_IOPORT;
1310 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1311 if (sc->xl_res == NULL) {
1312 device_printf(dev, "couldn't map ports/memory\n");
1317 device_printf(dev, "using port I/O\n");
1320 sc->xl_btag = rman_get_bustag(sc->xl_res);
1321 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1323 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1324 rid = XL_PCI_FUNCMEM;
1325 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1328 if (sc->xl_fres == NULL) {
1329 device_printf(dev, "couldn't map ports/memory\n");
1334 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1335 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1338 /* Allocate interrupt */
1340 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1341 RF_SHAREABLE | RF_ACTIVE);
1342 if (sc->xl_irq == NULL) {
1343 device_printf(dev, "couldn't map interrupt\n");
1348 /* Initialize interface name. */
1349 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1351 device_printf(dev, "can not if_alloc()\n");
1356 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1360 /* Reset the adapter. */
1364 * Get station address from the EEPROM.
1366 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1367 device_printf(dev, "failed to read station address\n");
1376 callout_handle_init(&sc->xl_stat_ch);
1377 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1380 * Now allocate a tag for the DMA descriptor lists and a chunk
1381 * of DMA-able memory based on the tag. Also obtain the DMA
1382 * addresses of the RX and TX ring, which we'll need later.
1383 * All of our lists are allocated as a contiguous block
1386 error = bus_dma_tag_create(NULL, 8, 0,
1387 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1388 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1389 &sc->xl_ldata.xl_rx_tag);
1391 device_printf(dev, "failed to allocate rx dma tag\n");
1395 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1396 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1397 &sc->xl_ldata.xl_rx_dmamap);
1399 device_printf(dev, "no memory for rx list buffers!\n");
1400 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1401 sc->xl_ldata.xl_rx_tag = NULL;
1405 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1406 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1407 XL_RX_LIST_SZ, xl_dma_map_addr,
1408 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1410 device_printf(dev, "cannot get dma address of the rx ring!\n");
1411 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1412 sc->xl_ldata.xl_rx_dmamap);
1413 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1414 sc->xl_ldata.xl_rx_tag = NULL;
1418 error = bus_dma_tag_create(NULL, 8, 0,
1419 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1420 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1421 &sc->xl_ldata.xl_tx_tag);
1423 device_printf(dev, "failed to allocate tx dma tag\n");
1427 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1428 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1429 &sc->xl_ldata.xl_tx_dmamap);
1431 device_printf(dev, "no memory for list buffers!\n");
1432 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1433 sc->xl_ldata.xl_tx_tag = NULL;
1437 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1438 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1439 XL_TX_LIST_SZ, xl_dma_map_addr,
1440 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1442 device_printf(dev, "cannot get dma address of the tx ring!\n");
1443 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1444 sc->xl_ldata.xl_tx_dmamap);
1445 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1446 sc->xl_ldata.xl_tx_tag = NULL;
1451 * Allocate a DMA tag for the mapping of mbufs.
1453 error = bus_dma_tag_create(NULL, 1, 0,
1454 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1455 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1456 NULL, &sc->xl_mtag);
1458 device_printf(dev, "failed to allocate mbuf dma tag\n");
1462 /* We need a spare DMA map for the RX ring. */
1463 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1470 * Figure out the card type. 3c905B adapters have the
1471 * 'supportsNoTxLength' bit set in the capabilities
1472 * word in the EEPROM.
1473 * Note: my 3c575C cardbus card lies. It returns a value
1474 * of 0x1578 for its capabilities word, which is somewhat
1475 * nonsensical. Another way to distinguish a 3c90x chip
1476 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1477 * bit. This will only be set for 3c90x boomerage chips.
1479 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1480 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1481 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1482 sc->xl_type = XL_TYPE_905B;
1484 sc->xl_type = XL_TYPE_90X;
1486 ifp->if_mtu = ETHERMTU;
1487 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1488 ifp->if_ioctl = xl_ioctl;
1489 ifp->if_capabilities = IFCAP_VLAN_MTU;
1490 if (sc->xl_type == XL_TYPE_905B) {
1491 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1492 #ifdef XL905B_TXCSUM_BROKEN
1493 ifp->if_capabilities |= IFCAP_RXCSUM;
1495 ifp->if_capabilities |= IFCAP_HWCSUM;
1498 #ifdef DEVICE_POLLING
1499 ifp->if_capabilities |= IFCAP_POLLING;
1500 #endif /* DEVICE_POLLING */
1501 ifp->if_start = xl_start;
1502 ifp->if_watchdog = xl_watchdog;
1503 ifp->if_init = xl_init;
1504 ifp->if_baudrate = 10000000;
1505 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1506 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1507 IFQ_SET_READY(&ifp->if_snd);
1508 ifp->if_capenable = ifp->if_capabilities;
1511 * Now we have to see what sort of media we have.
1512 * This includes probing for an MII interace and a
1516 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1518 device_printf(dev, "media options word: %x\n", sc->xl_media);
1520 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1521 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1522 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1523 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1527 /* XXX Downcalls to ifmedia, miibus about to happen. */
1530 if (sc->xl_media & XL_MEDIAOPT_MII ||
1531 sc->xl_media & XL_MEDIAOPT_BTX ||
1532 sc->xl_media & XL_MEDIAOPT_BT4) {
1534 device_printf(dev, "found MII/AUTO\n");
1536 if (mii_phy_probe(dev, &sc->xl_miibus,
1537 xl_ifmedia_upd, xl_ifmedia_sts)) {
1538 device_printf(dev, "no PHY found!\n");
1546 * Sanity check. If the user has selected "auto" and this isn't
1547 * a 10/100 card of some kind, we need to force the transceiver
1548 * type to something sane.
1550 if (sc->xl_xcvr == XL_XCVR_AUTO) {
1551 /* XXX Direct hardware access needs lock coverage. */
1553 xl_choose_xcvr(sc, bootverbose);
1560 if (sc->xl_media & XL_MEDIAOPT_BT) {
1562 device_printf(dev, "found 10baseT\n");
1563 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1564 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1565 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1566 ifmedia_add(&sc->ifmedia,
1567 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1570 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1572 * Check for a 10baseFL board in disguise.
1574 if (sc->xl_type == XL_TYPE_905B &&
1575 sc->xl_media == XL_MEDIAOPT_10FL) {
1577 device_printf(dev, "found 10baseFL\n");
1578 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1579 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1581 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1582 ifmedia_add(&sc->ifmedia,
1583 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1586 device_printf(dev, "found AUI\n");
1587 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1591 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1593 device_printf(dev, "found BNC\n");
1594 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1597 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1599 device_printf(dev, "found 100baseFX\n");
1600 ifp->if_baudrate = 100000000;
1601 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1604 /* XXX: Unlocked, leaf will take lock. */
1605 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1606 xl_choose_media(sc, &media);
1608 if (sc->xl_miibus == NULL)
1609 ifmedia_set(&sc->ifmedia, media);
1612 /* XXX: Unlocked hardware access, narrow race. */
1613 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1615 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1619 * Call MI attach routine.
1621 ether_ifattach(ifp, eaddr);
1623 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1624 xl_intr, sc, &sc->xl_intrhand);
1626 device_printf(dev, "couldn't set up irq\n");
1627 ether_ifdetach(ifp);
1640 * Choose a default media.
1641 * XXX This is a leaf function only called by xl_attach() and
1642 * acquires/releases the non-recursible driver mutex.
1645 xl_choose_media(struct xl_softc *sc, int *media)
1650 switch (sc->xl_xcvr) {
1652 *media = IFM_ETHER|IFM_10_T;
1653 xl_setmode(sc, *media);
1656 if (sc->xl_type == XL_TYPE_905B &&
1657 sc->xl_media == XL_MEDIAOPT_10FL) {
1658 *media = IFM_ETHER|IFM_10_FL;
1659 xl_setmode(sc, *media);
1661 *media = IFM_ETHER|IFM_10_5;
1662 xl_setmode(sc, *media);
1666 *media = IFM_ETHER|IFM_10_2;
1667 xl_setmode(sc, *media);
1670 case XL_XCVR_100BTX:
1672 /* Chosen by miibus */
1674 case XL_XCVR_100BFX:
1675 *media = IFM_ETHER|IFM_100_FX;
1678 if_printf(sc->xl_ifp, "unknown XCVR type: %d\n",
1681 * This will probably be wrong, but it prevents
1682 * the ifmedia code from panicking.
1684 *media = IFM_ETHER|IFM_10_T;
1692 * Shutdown hardware and free up resources. This can be called any
1693 * time after the mutex has been initialized. It is called in both
1694 * the error case in attach and the normal detach case so it needs
1695 * to be careful about only freeing resources that have actually been
1699 xl_detach(device_t dev)
1701 struct xl_softc *sc;
1705 sc = device_get_softc(dev);
1708 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1711 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1713 res = SYS_RES_MEMORY;
1716 res = SYS_RES_IOPORT;
1719 /* These should only be active if attach succeeded */
1720 if (device_is_attached(dev)) {
1723 ether_ifdetach(ifp);
1727 device_delete_child(dev, sc->xl_miibus);
1728 bus_generic_detach(dev);
1729 ifmedia_removeall(&sc->ifmedia);
1731 if (sc->xl_intrhand)
1732 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1734 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1735 if (sc->xl_fres != NULL)
1736 bus_release_resource(dev, SYS_RES_MEMORY,
1737 XL_PCI_FUNCMEM, sc->xl_fres);
1739 bus_release_resource(dev, res, rid, sc->xl_res);
1742 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1743 bus_dma_tag_destroy(sc->xl_mtag);
1745 if (sc->xl_ldata.xl_rx_tag) {
1746 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1747 sc->xl_ldata.xl_rx_dmamap);
1748 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1749 sc->xl_ldata.xl_rx_dmamap);
1750 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1752 if (sc->xl_ldata.xl_tx_tag) {
1753 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1754 sc->xl_ldata.xl_tx_dmamap);
1755 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1756 sc->xl_ldata.xl_tx_dmamap);
1757 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1761 mtx_destroy(&sc->xl_mtx);
1767 * Initialize the transmit descriptors.
1770 xl_list_tx_init(struct xl_softc *sc)
1772 struct xl_chain_data *cd;
1773 struct xl_list_data *ld;
1780 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1781 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1782 error = bus_dmamap_create(sc->xl_mtag, 0,
1783 &cd->xl_tx_chain[i].xl_map);
1786 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1787 i * sizeof(struct xl_list);
1788 if (i == (XL_TX_LIST_CNT - 1))
1789 cd->xl_tx_chain[i].xl_next = NULL;
1791 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1794 cd->xl_tx_free = &cd->xl_tx_chain[0];
1795 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1797 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1802 * Initialize the transmit descriptors.
1805 xl_list_tx_init_90xB(struct xl_softc *sc)
1807 struct xl_chain_data *cd;
1808 struct xl_list_data *ld;
1815 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1816 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1817 error = bus_dmamap_create(sc->xl_mtag, 0,
1818 &cd->xl_tx_chain[i].xl_map);
1821 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1822 i * sizeof(struct xl_list);
1823 if (i == (XL_TX_LIST_CNT - 1))
1824 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1826 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1828 cd->xl_tx_chain[i].xl_prev =
1829 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1831 cd->xl_tx_chain[i].xl_prev =
1832 &cd->xl_tx_chain[i - 1];
1835 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1836 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1842 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1847 * Initialize the RX descriptors and allocate mbufs for them. Note that
1848 * we arrange the descriptors in a closed ring, so that the last descriptor
1849 * points back to the first.
1852 xl_list_rx_init(struct xl_softc *sc)
1854 struct xl_chain_data *cd;
1855 struct xl_list_data *ld;
1864 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1865 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1866 error = bus_dmamap_create(sc->xl_mtag, 0,
1867 &cd->xl_rx_chain[i].xl_map);
1870 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1873 if (i == (XL_RX_LIST_CNT - 1))
1877 nextptr = ld->xl_rx_dmaaddr +
1878 next * sizeof(struct xl_list_onefrag);
1879 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1880 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1883 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1884 cd->xl_rx_head = &cd->xl_rx_chain[0];
1890 * Initialize an RX descriptor and attach an MBUF cluster.
1891 * If we fail to do so, we need to leave the old mbuf and
1892 * the old DMA map untouched so that it can be reused.
1895 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1897 struct mbuf *m_new = NULL;
1904 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1908 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1910 /* Force longword alignment for packet payload. */
1911 m_adj(m_new, ETHER_ALIGN);
1913 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1914 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1917 if_printf(sc->xl_ifp, "can't map mbuf (error %d)\n",
1922 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1924 c->xl_map = sc->xl_tmpmap;
1925 sc->xl_tmpmap = map;
1927 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1928 c->xl_ptr->xl_status = 0;
1929 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
1930 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1935 xl_rx_resync(struct xl_softc *sc)
1937 struct xl_chain_onefrag *pos;
1942 pos = sc->xl_cdata.xl_rx_head;
1944 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1945 if (pos->xl_ptr->xl_status)
1950 if (i == XL_RX_LIST_CNT)
1953 sc->xl_cdata.xl_rx_head = pos;
1959 * A frame has been uploaded: pass the resulting mbuf chain up to
1960 * the higher level protocols.
1963 xl_rxeof(struct xl_softc *sc)
1966 struct ifnet *ifp = sc->xl_ifp;
1967 struct xl_chain_onefrag *cur_rx;
1973 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1974 BUS_DMASYNC_POSTREAD);
1975 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1976 #ifdef DEVICE_POLLING
1977 if (ifp->if_flags & IFF_POLLING) {
1978 if (sc->rxcycles <= 0)
1982 #endif /* DEVICE_POLLING */
1983 cur_rx = sc->xl_cdata.xl_rx_head;
1984 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1985 total_len = rxstat & XL_RXSTAT_LENMASK;
1988 * Since we have told the chip to allow large frames,
1989 * we need to trap giant frame errors in software. We allow
1990 * a little more than the normal frame size to account for
1991 * frames with VLAN tags.
1993 if (total_len > XL_MAX_FRAMELEN)
1994 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1997 * If an error occurs, update stats, clear the
1998 * status word and leave the mbuf cluster in place:
1999 * it should simply get re-used next time this descriptor
2000 * comes up in the ring.
2002 if (rxstat & XL_RXSTAT_UP_ERROR) {
2004 cur_rx->xl_ptr->xl_status = 0;
2005 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2006 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2011 * If the error bit was not set, the upload complete
2012 * bit should be set which means we have a valid packet.
2013 * If not, something truly strange has happened.
2015 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2017 "bad receive status -- packet dropped\n");
2019 cur_rx->xl_ptr->xl_status = 0;
2020 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2021 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2025 /* No errors; receive the packet. */
2026 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2027 BUS_DMASYNC_POSTREAD);
2028 m = cur_rx->xl_mbuf;
2031 * Try to conjure up a new mbuf cluster. If that
2032 * fails, it means we have an out of memory condition and
2033 * should leave the buffer in place and continue. This will
2034 * result in a lost packet, but there's little else we
2035 * can do in this situation.
2037 if (xl_newbuf(sc, cur_rx)) {
2039 cur_rx->xl_ptr->xl_status = 0;
2040 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2041 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2044 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2045 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2048 m->m_pkthdr.rcvif = ifp;
2049 m->m_pkthdr.len = m->m_len = total_len;
2051 if (ifp->if_capenable & IFCAP_RXCSUM) {
2052 /* Do IP checksum checking. */
2053 if (rxstat & XL_RXSTAT_IPCKOK)
2054 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2055 if (!(rxstat & XL_RXSTAT_IPCKERR))
2056 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2057 if ((rxstat & XL_RXSTAT_TCPCOK &&
2058 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2059 (rxstat & XL_RXSTAT_UDPCKOK &&
2060 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2061 m->m_pkthdr.csum_flags |=
2062 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2063 m->m_pkthdr.csum_data = 0xffff;
2068 (*ifp->if_input)(ifp, m);
2073 * Handle the 'end of channel' condition. When the upload
2074 * engine hits the end of the RX ring, it will stall. This
2075 * is our cue to flush the RX ring, reload the uplist pointer
2076 * register and unstall the engine.
2077 * XXX This is actually a little goofy. With the ThunderLAN
2078 * chip, you get an interrupt when the receiver hits the end
2079 * of the receive ring, which tells you exactly when you
2080 * you need to reload the ring pointer. Here we have to
2081 * fake it. I'm mad at myself for not being clever enough
2082 * to avoid the use of a goto here.
2084 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2085 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2086 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2088 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2089 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2090 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2096 * Taskqueue wrapper for xl_rxeof().
2099 xl_rxeof_task(void *arg, int pending)
2101 struct xl_softc *sc = (struct xl_softc *)arg;
2109 * A frame was downloaded to the chip. It's safe for us to clean up
2113 xl_txeof(struct xl_softc *sc)
2115 struct xl_chain *cur_tx;
2116 struct ifnet *ifp = sc->xl_ifp;
2120 /* Clear the timeout timer. */
2124 * Go through our tx list and free mbufs for those
2125 * frames that have been uploaded. Note: the 3c905B
2126 * sets a special bit in the status word to let us
2127 * know that a frame has been downloaded, but the
2128 * original 3c900/3c905 adapters don't do that.
2129 * Consequently, we have to use a different test if
2130 * xl_type != XL_TYPE_905B.
2132 while (sc->xl_cdata.xl_tx_head != NULL) {
2133 cur_tx = sc->xl_cdata.xl_tx_head;
2135 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2138 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2139 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2140 BUS_DMASYNC_POSTWRITE);
2141 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2142 m_freem(cur_tx->xl_mbuf);
2143 cur_tx->xl_mbuf = NULL;
2146 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2147 sc->xl_cdata.xl_tx_free = cur_tx;
2150 if (sc->xl_cdata.xl_tx_head == NULL) {
2151 ifp->if_flags &= ~IFF_OACTIVE;
2152 sc->xl_cdata.xl_tx_tail = NULL;
2154 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2155 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2156 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2157 sc->xl_cdata.xl_tx_head->xl_phys);
2158 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2164 xl_txeof_90xB(struct xl_softc *sc)
2166 struct xl_chain *cur_tx = NULL;
2167 struct ifnet *ifp = sc->xl_ifp;
2172 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2173 BUS_DMASYNC_POSTREAD);
2174 idx = sc->xl_cdata.xl_tx_cons;
2175 while (idx != sc->xl_cdata.xl_tx_prod) {
2177 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2179 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2180 XL_TXSTAT_DL_COMPLETE))
2183 if (cur_tx->xl_mbuf != NULL) {
2184 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2185 BUS_DMASYNC_POSTWRITE);
2186 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2187 m_freem(cur_tx->xl_mbuf);
2188 cur_tx->xl_mbuf = NULL;
2193 sc->xl_cdata.xl_tx_cnt--;
2194 XL_INC(idx, XL_TX_LIST_CNT);
2198 sc->xl_cdata.xl_tx_cons = idx;
2201 ifp->if_flags &= ~IFF_OACTIVE;
2205 * TX 'end of channel' interrupt handler. Actually, we should
2206 * only get a 'TX complete' interrupt if there's a transmit error,
2207 * so this is really TX error handler.
2210 xl_txeoc(struct xl_softc *sc)
2216 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2217 if (txstat & XL_TXSTATUS_UNDERRUN ||
2218 txstat & XL_TXSTATUS_JABBER ||
2219 txstat & XL_TXSTATUS_RECLAIM) {
2220 if_printf(sc->xl_ifp,
2221 "transmission error: %x\n", txstat);
2222 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2224 if (sc->xl_type == XL_TYPE_905B) {
2225 if (sc->xl_cdata.xl_tx_cnt) {
2229 i = sc->xl_cdata.xl_tx_cons;
2230 c = &sc->xl_cdata.xl_tx_chain[i];
2231 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2233 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2236 if (sc->xl_cdata.xl_tx_head != NULL)
2237 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2238 sc->xl_cdata.xl_tx_head->xl_phys);
2241 * Remember to set this for the
2242 * first generation 3c90X chips.
2244 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2245 if (txstat & XL_TXSTATUS_UNDERRUN &&
2246 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2247 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2248 if_printf(sc->xl_ifp,
2249 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2251 CSR_WRITE_2(sc, XL_COMMAND,
2252 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2253 if (sc->xl_type == XL_TYPE_905B) {
2254 CSR_WRITE_2(sc, XL_COMMAND,
2255 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2257 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2258 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2260 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2261 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2264 * Write an arbitrary byte to the TX_STATUS register
2265 * to clear this interrupt/error and advance to the next.
2267 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2274 struct xl_softc *sc = arg;
2275 struct ifnet *ifp = sc->xl_ifp;
2280 #ifdef DEVICE_POLLING
2281 if (ifp->if_flags & IFF_POLLING) {
2286 if ((ifp->if_capenable & IFCAP_POLLING) &&
2287 ether_poll_register(xl_poll, ifp)) {
2288 /* Disable interrupts. */
2289 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2290 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2291 if (sc->xl_flags & XL_FLAG_FUNCREG)
2292 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle,
2294 xl_poll_locked(ifp, 0, 1);
2298 #endif /* DEVICE_POLLING */
2300 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS &&
2302 CSR_WRITE_2(sc, XL_COMMAND,
2303 XL_CMD_INTR_ACK|(status & XL_INTRS));
2305 if (status & XL_STAT_UP_COMPLETE) {
2308 curpkts = ifp->if_ipackets;
2310 if (curpkts == ifp->if_ipackets) {
2311 while (xl_rx_resync(sc))
2316 if (status & XL_STAT_DOWN_COMPLETE) {
2317 if (sc->xl_type == XL_TYPE_905B)
2323 if (status & XL_STAT_TX_COMPLETE) {
2328 if (status & XL_STAT_ADFAIL) {
2333 if (status & XL_STAT_STATSOFLOW) {
2334 sc->xl_stats_no_timeout = 1;
2335 xl_stats_update_locked(sc);
2336 sc->xl_stats_no_timeout = 0;
2340 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2341 if (sc->xl_type == XL_TYPE_905B)
2342 xl_start_90xB_locked(ifp);
2344 xl_start_locked(ifp);
2350 #ifdef DEVICE_POLLING
2352 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2354 struct xl_softc *sc = ifp->if_softc;
2357 xl_poll_locked(ifp, cmd, count);
2362 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2364 struct xl_softc *sc = ifp->if_softc;
2368 if (!(ifp->if_capenable & IFCAP_POLLING)) {
2369 ether_poll_deregister(ifp);
2370 cmd = POLL_DEREGISTER;
2373 if (cmd == POLL_DEREGISTER) {
2374 /* Final call; enable interrupts. */
2375 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2376 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2377 if (sc->xl_flags & XL_FLAG_FUNCREG)
2378 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle,
2383 sc->rxcycles = count;
2385 if (sc->xl_type == XL_TYPE_905B)
2390 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2391 if (sc->xl_type == XL_TYPE_905B)
2392 xl_start_90xB_locked(ifp);
2394 xl_start_locked(ifp);
2397 if (cmd == POLL_AND_CHECK_STATUS) {
2400 status = CSR_READ_2(sc, XL_STATUS);
2401 if (status & XL_INTRS && status != 0xFFFF) {
2402 CSR_WRITE_2(sc, XL_COMMAND,
2403 XL_CMD_INTR_ACK|(status & XL_INTRS));
2405 if (status & XL_STAT_TX_COMPLETE) {
2410 if (status & XL_STAT_ADFAIL) {
2415 if (status & XL_STAT_STATSOFLOW) {
2416 sc->xl_stats_no_timeout = 1;
2417 xl_stats_update_locked(sc);
2418 sc->xl_stats_no_timeout = 0;
2423 #endif /* DEVICE_POLLING */
2426 * XXX: This is an entry point for callout which needs to take the lock.
2429 xl_stats_update(void *xsc)
2431 struct xl_softc *sc = xsc;
2434 xl_stats_update_locked(sc);
2439 xl_stats_update_locked(struct xl_softc *sc)
2441 struct ifnet *ifp = sc->xl_ifp;
2442 struct xl_stats xl_stats;
2445 struct mii_data *mii = NULL;
2449 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2451 if (sc->xl_miibus != NULL)
2452 mii = device_get_softc(sc->xl_miibus);
2454 p = (u_int8_t *)&xl_stats;
2456 /* Read all the stats registers. */
2459 for (i = 0; i < 16; i++)
2460 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2462 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2464 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2465 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision;
2468 * Boomerang and cyclone chips have an extra stats counter
2469 * in window 4 (BadSSD). We have to read this too in order
2470 * to clear out all the stats registers and avoid a statsoflow
2474 CSR_READ_1(sc, XL_W4_BADSSD);
2476 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2481 if (!sc->xl_stats_no_timeout)
2482 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2486 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2487 * pointers to the fragment pointers.
2490 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2494 struct ifnet *ifp = sc->xl_ifp;
2499 * Start packing the mbufs in this chain into
2500 * the fragment pointers. Stop when we run out
2501 * of fragments or hit the end of the mbuf chain.
2503 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2504 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2506 if (error && error != EFBIG) {
2508 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2513 * Handle special case: we used up all 63 fragments,
2514 * but we have more mbufs left in the chain. Copy the
2515 * data into an mbuf cluster. Note that we don't
2516 * bother clearing the values in the other fragment
2517 * pointers/counters; it wouldn't gain us anything,
2518 * and would waste cycles.
2523 m_new = m_defrag(m_head, M_DONTWAIT);
2524 if (m_new == NULL) {
2531 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2532 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2535 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2540 if (sc->xl_type == XL_TYPE_905B) {
2541 status = XL_TXSTAT_RND_DEFEAT;
2543 #ifndef XL905B_TXCSUM_BROKEN
2544 if (m_head->m_pkthdr.csum_flags) {
2545 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2546 status |= XL_TXSTAT_IPCKSUM;
2547 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2548 status |= XL_TXSTAT_TCPCKSUM;
2549 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2550 status |= XL_TXSTAT_UDPCKSUM;
2553 c->xl_ptr->xl_status = htole32(status);
2556 c->xl_mbuf = m_head;
2557 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2562 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2563 * to the mbuf data regions directly in the transmit lists. We also save a
2564 * copy of the pointers since the transmit list fragment pointers are
2565 * physical addresses.
2569 xl_start(struct ifnet *ifp)
2571 struct xl_softc *sc = ifp->if_softc;
2575 if (sc->xl_type == XL_TYPE_905B)
2576 xl_start_90xB_locked(ifp);
2578 xl_start_locked(ifp);
2584 xl_start_locked(struct ifnet *ifp)
2586 struct xl_softc *sc = ifp->if_softc;
2587 struct mbuf *m_head = NULL;
2588 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2589 struct xl_chain *prev_tx;
2596 * Check for an available queue slot. If there are none,
2599 if (sc->xl_cdata.xl_tx_free == NULL) {
2602 if (sc->xl_cdata.xl_tx_free == NULL) {
2603 ifp->if_flags |= IFF_OACTIVE;
2608 start_tx = sc->xl_cdata.xl_tx_free;
2610 while (sc->xl_cdata.xl_tx_free != NULL) {
2611 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2615 /* Pick a descriptor off the free list. */
2617 cur_tx = sc->xl_cdata.xl_tx_free;
2619 /* Pack the data into the descriptor. */
2620 error = xl_encap(sc, cur_tx, m_head);
2626 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2627 cur_tx->xl_next = NULL;
2629 /* Chain it together. */
2631 prev->xl_next = cur_tx;
2632 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2637 * If there's a BPF listener, bounce a copy of this frame
2640 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2644 * If there are no packets queued, bail.
2650 * Place the request for the upload interrupt
2651 * in the last descriptor in the chain. This way, if
2652 * we're chaining several packets at once, we'll only
2653 * get an interupt once for the whole chain rather than
2654 * once for each packet.
2656 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2658 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2659 BUS_DMASYNC_PREWRITE);
2662 * Queue the packets. If the TX channel is clear, update
2663 * the downlist pointer register.
2665 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2668 if (sc->xl_cdata.xl_tx_head != NULL) {
2669 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2670 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2671 htole32(start_tx->xl_phys);
2672 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2673 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2674 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2675 sc->xl_cdata.xl_tx_tail = cur_tx;
2677 sc->xl_cdata.xl_tx_head = start_tx;
2678 sc->xl_cdata.xl_tx_tail = cur_tx;
2680 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2681 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2683 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2688 * Set a timeout in case the chip goes out to lunch.
2693 * XXX Under certain conditions, usually on slower machines
2694 * where interrupts may be dropped, it's possible for the
2695 * adapter to chew up all the buffers in the receive ring
2696 * and stall, without us being able to do anything about it.
2697 * To guard against this, we need to make a pass over the
2698 * RX queue to make sure there aren't any packets pending.
2699 * Doing it here means we can flush the receive ring at the
2700 * same time the chip is DMAing the transmit descriptors we
2703 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2704 * nature of their chips in all their marketing literature;
2705 * we may as well take advantage of it. :)
2707 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2711 xl_start_90xB_locked(struct ifnet *ifp)
2713 struct xl_softc *sc = ifp->if_softc;
2714 struct mbuf *m_head = NULL;
2715 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2716 struct xl_chain *prev_tx;
2721 if (ifp->if_flags & IFF_OACTIVE)
2724 idx = sc->xl_cdata.xl_tx_prod;
2725 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2727 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2729 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2730 ifp->if_flags |= IFF_OACTIVE;
2734 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2739 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2741 /* Pack the data into the descriptor. */
2742 error = xl_encap(sc, cur_tx, m_head);
2748 /* Chain it together. */
2750 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2754 * If there's a BPF listener, bounce a copy of this frame
2757 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2759 XL_INC(idx, XL_TX_LIST_CNT);
2760 sc->xl_cdata.xl_tx_cnt++;
2764 * If there are no packets queued, bail.
2770 * Place the request for the upload interrupt
2771 * in the last descriptor in the chain. This way, if
2772 * we're chaining several packets at once, we'll only
2773 * get an interupt once for the whole chain rather than
2774 * once for each packet.
2776 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2778 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2779 BUS_DMASYNC_PREWRITE);
2781 /* Start transmission */
2782 sc->xl_cdata.xl_tx_prod = idx;
2783 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2786 * Set a timeout in case the chip goes out to lunch.
2794 struct xl_softc *sc = xsc;
2802 xl_init_locked(struct xl_softc *sc)
2804 struct ifnet *ifp = sc->xl_ifp;
2806 u_int16_t rxfilt = 0;
2807 struct mii_data *mii = NULL;
2812 * Cancel pending I/O and free all RX/TX buffers.
2816 if (sc->xl_miibus == NULL) {
2817 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2824 if (sc->xl_miibus != NULL)
2825 mii = device_get_softc(sc->xl_miibus);
2827 /* Init our MAC address */
2829 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2830 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2831 IFP2ENADDR(sc->xl_ifp)[i]);
2834 /* Clear the station mask. */
2835 for (i = 0; i < 3; i++)
2836 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2838 /* Reset TX and RX. */
2839 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2841 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2844 /* Init circular RX list. */
2845 error = xl_list_rx_init(sc);
2847 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2853 /* Init TX descriptors. */
2854 if (sc->xl_type == XL_TYPE_905B)
2855 error = xl_list_tx_init_90xB(sc);
2857 error = xl_list_tx_init(sc);
2859 if_printf(ifp, "initialization of the tx ring failed (%d)\n",
2866 * Set the TX freethresh value.
2867 * Note that this has no effect on 3c905B "cyclone"
2868 * cards but is required for 3c900/3c905 "boomerang"
2869 * cards in order to enable the download engine.
2871 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2873 /* Set the TX start threshold for best performance. */
2874 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2878 * If this is a 3c905B, also set the tx reclaim threshold.
2879 * This helps cut down on the number of tx reclaim errors
2880 * that could happen on a busy network. The chip multiplies
2881 * the register value by 16 to obtain the actual threshold
2882 * in bytes, so we divide by 16 when setting the value here.
2883 * The existing threshold value can be examined by reading
2884 * the register at offset 9 in window 5.
2886 if (sc->xl_type == XL_TYPE_905B) {
2887 CSR_WRITE_2(sc, XL_COMMAND,
2888 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2891 /* Set RX filter bits. */
2893 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2895 /* Set the individual bit to receive frames for this host only. */
2896 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2898 /* If we want promiscuous mode, set the allframes bit. */
2899 if (ifp->if_flags & IFF_PROMISC) {
2900 rxfilt |= XL_RXFILTER_ALLFRAMES;
2901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2903 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2908 * Set capture broadcast bit to capture broadcast frames.
2910 if (ifp->if_flags & IFF_BROADCAST) {
2911 rxfilt |= XL_RXFILTER_BROADCAST;
2912 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2914 rxfilt &= ~XL_RXFILTER_BROADCAST;
2915 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2919 * Program the multicast filter, if necessary.
2921 if (sc->xl_type == XL_TYPE_905B)
2922 xl_setmulti_hash(sc);
2927 * Load the address of the RX list. We have to
2928 * stall the upload engine before we can manipulate
2929 * the uplist pointer register, then unstall it when
2930 * we're finished. We also have to wait for the
2931 * stall command to complete before proceeding.
2932 * Note that we have to do this after any RX resets
2933 * have completed since the uplist register is cleared
2936 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2938 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2939 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2942 if (sc->xl_type == XL_TYPE_905B) {
2943 /* Set polling interval */
2944 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2945 /* Load the address of the TX list */
2946 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2948 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2949 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2950 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2955 * If the coax transceiver is on, make sure to enable
2956 * the DC-DC converter.
2959 if (sc->xl_xcvr == XL_XCVR_COAX)
2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2962 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2965 * increase packet size to allow reception of 802.1q or ISL packets.
2966 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2967 * control register. For 3c90xB/C chips, use the RX packet size
2971 if (sc->xl_type == XL_TYPE_905B)
2972 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2975 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2976 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2977 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2980 /* Clear out the stats counters. */
2981 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2982 sc->xl_stats_no_timeout = 1;
2983 xl_stats_update_locked(sc);
2984 sc->xl_stats_no_timeout = 0;
2986 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2987 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2990 * Enable interrupts.
2992 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2993 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2994 #ifdef DEVICE_POLLING
2995 /* Disable interrupts if we are polling. */
2996 if (ifp->if_flags & IFF_POLLING)
2997 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2999 #endif /* DEVICE_POLLING */
3000 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
3001 if (sc->xl_flags & XL_FLAG_FUNCREG)
3002 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3004 /* Set the RX early threshold */
3005 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
3006 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
3008 /* Enable receiver and transmitter. */
3009 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
3011 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3014 /* XXX Downcall to miibus. */
3018 /* Select window 7 for normal operations. */
3021 ifp->if_flags |= IFF_RUNNING;
3022 ifp->if_flags &= ~IFF_OACTIVE;
3024 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
3028 * Set media options.
3031 xl_ifmedia_upd(struct ifnet *ifp)
3033 struct xl_softc *sc = ifp->if_softc;
3034 struct ifmedia *ifm = NULL;
3035 struct mii_data *mii = NULL;
3037 /*XL_LOCK_ASSERT(sc);*/
3039 if (sc->xl_miibus != NULL)
3040 mii = device_get_softc(sc->xl_miibus);
3044 ifm = &mii->mii_media;
3046 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3051 xl_setmode(sc, ifm->ifm_media);
3058 if (sc->xl_media & XL_MEDIAOPT_MII ||
3059 sc->xl_media & XL_MEDIAOPT_BTX ||
3060 sc->xl_media & XL_MEDIAOPT_BT4) {
3061 xl_init(sc); /* XXX */
3063 xl_setmode(sc, ifm->ifm_media);
3070 * Report current media status.
3073 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3075 struct xl_softc *sc = ifp->if_softc;
3077 u_int16_t status = 0;
3078 struct mii_data *mii = NULL;
3080 /*XL_LOCK_ASSERT(sc);*/
3082 if (sc->xl_miibus != NULL)
3083 mii = device_get_softc(sc->xl_miibus);
3086 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3089 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3090 icfg >>= XL_ICFG_CONNECTOR_BITS;
3092 ifmr->ifm_active = IFM_ETHER;
3093 ifmr->ifm_status = IFM_AVALID;
3095 if ((status & XL_MEDIASTAT_CARRIER) == 0)
3096 ifmr->ifm_status |= IFM_ACTIVE;
3100 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3101 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3102 ifmr->ifm_active |= IFM_FDX;
3104 ifmr->ifm_active |= IFM_HDX;
3107 if (sc->xl_type == XL_TYPE_905B &&
3108 sc->xl_media == XL_MEDIAOPT_10FL) {
3109 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3110 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3111 ifmr->ifm_active |= IFM_FDX;
3113 ifmr->ifm_active |= IFM_HDX;
3115 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3118 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3121 * XXX MII and BTX/AUTO should be separate cases.
3124 case XL_XCVR_100BTX:
3129 ifmr->ifm_active = mii->mii_media_active;
3130 ifmr->ifm_status = mii->mii_media_status;
3133 case XL_XCVR_100BFX:
3134 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3137 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3143 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3145 struct xl_softc *sc = ifp->if_softc;
3146 struct ifreq *ifr = (struct ifreq *) data;
3148 struct mii_data *mii = NULL;
3156 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3157 if (ifp->if_flags & IFF_UP) {
3158 if (ifp->if_flags & IFF_RUNNING &&
3159 ifp->if_flags & IFF_PROMISC &&
3160 !(sc->xl_if_flags & IFF_PROMISC)) {
3161 rxfilt |= XL_RXFILTER_ALLFRAMES;
3162 CSR_WRITE_2(sc, XL_COMMAND,
3163 XL_CMD_RX_SET_FILT|rxfilt);
3165 } else if (ifp->if_flags & IFF_RUNNING &&
3166 !(ifp->if_flags & IFF_PROMISC) &&
3167 sc->xl_if_flags & IFF_PROMISC) {
3168 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3169 CSR_WRITE_2(sc, XL_COMMAND,
3170 XL_CMD_RX_SET_FILT|rxfilt);
3173 if ((ifp->if_flags & IFF_RUNNING) == 0)
3177 if (ifp->if_flags & IFF_RUNNING)
3180 sc->xl_if_flags = ifp->if_flags;
3186 /* XXX Downcall from if_addmulti() possibly with locks held. */
3188 if (sc->xl_type == XL_TYPE_905B)
3189 xl_setmulti_hash(sc);
3197 /* XXX Downcall from ifmedia possibly with locks held. */
3199 if (sc->xl_miibus != NULL)
3200 mii = device_get_softc(sc->xl_miibus);
3202 error = ifmedia_ioctl(ifp, ifr,
3203 &sc->ifmedia, command);
3205 error = ifmedia_ioctl(ifp, ifr,
3206 &mii->mii_media, command);
3211 ifp->if_capenable = ifr->ifr_reqcap;
3212 if (ifp->if_capenable & IFCAP_TXCSUM)
3213 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3215 ifp->if_hwassist = 0;
3219 error = ether_ioctl(ifp, command, data);
3227 * XXX: Invoked from ifnet slow timer. Lock coverage needed.
3230 xl_watchdog(struct ifnet *ifp)
3232 struct xl_softc *sc = ifp->if_softc;
3233 u_int16_t status = 0;
3239 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3240 if_printf(ifp, "watchdog timeout\n");
3242 if (status & XL_MEDIASTAT_CARRIER)
3243 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3251 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3252 if (sc->xl_type == XL_TYPE_905B)
3253 xl_start_90xB_locked(ifp);
3255 xl_start_locked(ifp);
3262 * Stop the adapter and free any mbufs allocated to the
3266 xl_stop(struct xl_softc *sc)
3269 struct ifnet *ifp = sc->xl_ifp;
3274 #ifdef DEVICE_POLLING
3275 ether_poll_deregister(ifp);
3276 #endif /* DEVICE_POLLING */
3278 taskqueue_drain(taskqueue_swi, &sc->xl_task);
3280 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3281 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3282 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3283 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3285 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3290 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3292 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3296 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3297 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3298 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3299 if (sc->xl_flags & XL_FLAG_FUNCREG)
3300 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3302 /* Stop the stats updater. */
3303 untimeout(xl_stats_update, sc, sc->xl_stat_ch);
3306 * Free data in the RX lists.
3308 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3309 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3310 bus_dmamap_unload(sc->xl_mtag,
3311 sc->xl_cdata.xl_rx_chain[i].xl_map);
3312 bus_dmamap_destroy(sc->xl_mtag,
3313 sc->xl_cdata.xl_rx_chain[i].xl_map);
3314 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3315 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3318 if (sc->xl_ldata.xl_rx_list != NULL)
3319 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3321 * Free the TX list buffers.
3323 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3324 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3325 bus_dmamap_unload(sc->xl_mtag,
3326 sc->xl_cdata.xl_tx_chain[i].xl_map);
3327 bus_dmamap_destroy(sc->xl_mtag,
3328 sc->xl_cdata.xl_tx_chain[i].xl_map);
3329 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3330 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3333 if (sc->xl_ldata.xl_tx_list != NULL)
3334 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3336 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3340 * Stop all chip I/O so that the kernel's probe routines don't
3341 * get confused by errant DMAs when rebooting.
3344 xl_shutdown(device_t dev)
3346 struct xl_softc *sc;
3348 sc = device_get_softc(dev);
3357 xl_suspend(device_t dev)
3359 struct xl_softc *sc;
3361 sc = device_get_softc(dev);
3371 xl_resume(device_t dev)
3373 struct xl_softc *sc;
3376 sc = device_get_softc(dev);
3382 if (ifp->if_flags & IFF_UP)