2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
100 * This driver is in the /sys/pci directory because it only supports
104 #ifdef HAVE_KERNEL_OPTION_HEADERS
105 #include "opt_device_polling.h"
108 #include <sys/param.h>
109 #include <sys/systm.h>
110 #include <sys/sockio.h>
111 #include <sys/endian.h>
112 #include <sys/mbuf.h>
113 #include <sys/kernel.h>
114 #include <sys/module.h>
115 #include <sys/socket.h>
116 #include <sys/taskqueue.h>
119 #include <net/if_arp.h>
120 #include <net/ethernet.h>
121 #include <net/if_dl.h>
122 #include <net/if_media.h>
123 #include <net/if_types.h>
127 #include <machine/bus.h>
128 #include <machine/resource.h>
130 #include <sys/rman.h>
132 #include <dev/mii/mii.h>
133 #include <dev/mii/miivar.h>
135 #include <dev/pci/pcireg.h>
136 #include <dev/pci/pcivar.h>
138 MODULE_DEPEND(xl, pci, 1, 1, 1);
139 MODULE_DEPEND(xl, ether, 1, 1, 1);
140 MODULE_DEPEND(xl, miibus, 1, 1, 1);
142 /* "device miibus" required. See GENERIC if you get errors here. */
143 #include "miibus_if.h"
145 #include <pci/if_xlreg.h>
148 * TX Checksumming is disabled by default for two reasons:
149 * - TX Checksumming will occasionally produce corrupt packets
150 * - TX Checksumming seems to reduce performance
152 * Only 905B/C cards were reported to have this problem, it is possible
153 * that later chips _may_ be immune.
155 #define XL905B_TXCSUM_BROKEN 1
157 #ifdef XL905B_TXCSUM_BROKEN
158 #define XL905B_CSUM_FEATURES 0
160 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
164 * Various supported device vendors/types and their names.
166 static struct xl_type xl_devs[] = {
167 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
168 "3Com 3c900-TPO Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
170 "3Com 3c900-COMBO Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
172 "3Com 3c905-TX Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
174 "3Com 3c905-T4 Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
176 "3Com 3c900B-TPO Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
178 "3Com 3c900B-COMBO Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
180 "3Com 3c900B-TPC Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
182 "3Com 3c900B-FL Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
184 "3Com 3c905B-TX Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
186 "3Com 3c905B-T4 Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
188 "3Com 3c905B-FX/SC Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
190 "3Com 3c905B-COMBO Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
192 "3Com 3c905C-TX Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
194 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
196 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
198 "3Com 3c980 Fast Etherlink XL" },
199 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
200 "3Com 3c980C Fast Etherlink XL" },
201 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
202 "3Com 3cSOHO100-TX OfficeConnect" },
203 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
204 "3Com 3c450-TX HomeConnect" },
205 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
206 "3Com 3c555 Fast Etherlink XL" },
207 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
208 "3Com 3c556 Fast Etherlink XL" },
209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
210 "3Com 3c556B Fast Etherlink XL" },
211 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
212 "3Com 3c575TX Fast Etherlink XL" },
213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
214 "3Com 3c575B Fast Etherlink XL" },
215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
216 "3Com 3c575C Fast Etherlink XL" },
217 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
218 "3Com 3c656 Fast Etherlink XL" },
219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
220 "3Com 3c656B Fast Etherlink XL" },
221 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
222 "3Com 3c656C Fast Etherlink XL" },
226 static int xl_probe(device_t);
227 static int xl_attach(device_t);
228 static int xl_detach(device_t);
230 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
231 static void xl_stats_update(void *);
232 static void xl_stats_update_locked(struct xl_softc *);
233 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf *);
234 static void xl_rxeof(struct xl_softc *);
235 static void xl_rxeof_task(void *, int);
236 static int xl_rx_resync(struct xl_softc *);
237 static void xl_txeof(struct xl_softc *);
238 static void xl_txeof_90xB(struct xl_softc *);
239 static void xl_txeoc(struct xl_softc *);
240 static void xl_intr(void *);
241 static void xl_start(struct ifnet *);
242 static void xl_start_locked(struct ifnet *);
243 static void xl_start_90xB_locked(struct ifnet *);
244 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
245 static void xl_init(void *);
246 static void xl_init_locked(struct xl_softc *);
247 static void xl_stop(struct xl_softc *);
248 static void xl_watchdog(struct ifnet *);
249 static void xl_shutdown(device_t);
250 static int xl_suspend(device_t);
251 static int xl_resume(device_t);
253 #ifdef DEVICE_POLLING
254 static void xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
255 static void xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
258 static int xl_ifmedia_upd(struct ifnet *);
259 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
261 static int xl_eeprom_wait(struct xl_softc *);
262 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
263 static void xl_mii_sync(struct xl_softc *);
264 static void xl_mii_send(struct xl_softc *, u_int32_t, int);
265 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *);
266 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *);
268 static void xl_setcfg(struct xl_softc *);
269 static void xl_setmode(struct xl_softc *, int);
270 static void xl_setmulti(struct xl_softc *);
271 static void xl_setmulti_hash(struct xl_softc *);
272 static void xl_reset(struct xl_softc *);
273 static int xl_list_rx_init(struct xl_softc *);
274 static int xl_list_tx_init(struct xl_softc *);
275 static int xl_list_tx_init_90xB(struct xl_softc *);
276 static void xl_wait(struct xl_softc *);
277 static void xl_mediacheck(struct xl_softc *);
278 static void xl_choose_media(struct xl_softc *sc, int *media);
279 static void xl_choose_xcvr(struct xl_softc *, int);
280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
281 static void xl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
282 static void xl_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
284 static void xl_testpacket(struct xl_softc *);
287 static int xl_miibus_readreg(device_t, int, int);
288 static int xl_miibus_writereg(device_t, int, int, int);
289 static void xl_miibus_statchg(device_t);
290 static void xl_miibus_mediainit(device_t);
292 static device_method_t xl_methods[] = {
293 /* Device interface */
294 DEVMETHOD(device_probe, xl_probe),
295 DEVMETHOD(device_attach, xl_attach),
296 DEVMETHOD(device_detach, xl_detach),
297 DEVMETHOD(device_shutdown, xl_shutdown),
298 DEVMETHOD(device_suspend, xl_suspend),
299 DEVMETHOD(device_resume, xl_resume),
302 DEVMETHOD(bus_print_child, bus_generic_print_child),
303 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
306 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
307 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
308 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
309 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
314 static driver_t xl_driver = {
317 sizeof(struct xl_softc)
320 static devclass_t xl_devclass;
322 DRIVER_MODULE(xl, cardbus, xl_driver, xl_devclass, 0, 0);
323 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0);
324 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
327 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
332 *paddr = segs->ds_addr;
336 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
337 bus_size_t mapsize, int error)
344 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
346 *paddr = segs->ds_addr;
350 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
351 bus_size_t mapsize, int error)
359 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
363 for (i = 0; i < nseg; i++) {
364 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
365 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
366 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
367 total_len += segs[i].ds_len;
369 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
371 l->xl_status = htole32(total_len);
376 * Murphy's law says that it's possible the chip can wedge and
377 * the 'command in progress' bit may never clear. Hence, we wait
378 * only a finite amount of time to avoid getting caught in an
379 * infinite loop. Normally this delay routine would be a macro,
380 * but it isn't called during normal operation so we can afford
381 * to make it a function.
384 xl_wait(struct xl_softc *sc)
388 for (i = 0; i < XL_TIMEOUT; i++) {
389 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
394 if_printf(sc->xl_ifp, "command never completed!\n");
398 * MII access routines are provided for adapters with external
399 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
400 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
401 * Note: if you don't perform the MDIO operations just right,
402 * it's possible to end up with code that works correctly with
403 * some chips/CPUs/processor speeds/bus speeds/etc but not
407 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
408 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
412 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
415 * Sync the PHYs by setting data bit and strobing the clock 32 times.
418 xl_mii_sync(struct xl_softc *sc)
423 MII_SET(XL_MII_DIR|XL_MII_DATA);
425 for (i = 0; i < 32; i++) {
427 MII_SET(XL_MII_DATA);
428 MII_SET(XL_MII_DATA);
430 MII_SET(XL_MII_DATA);
431 MII_SET(XL_MII_DATA);
436 * Clock a series of bits through the MII.
439 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
446 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
448 MII_SET(XL_MII_DATA);
450 MII_CLR(XL_MII_DATA);
458 * Read an PHY register through the MII.
461 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
465 /* Set up frame for RX. */
466 frame->mii_stdelim = XL_MII_STARTDELIM;
467 frame->mii_opcode = XL_MII_READOP;
468 frame->mii_turnaround = 0;
471 /* Select register window 4. */
474 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
475 /* Turn on data xmit. */
480 /* Send command/address info. */
481 xl_mii_send(sc, frame->mii_stdelim, 2);
482 xl_mii_send(sc, frame->mii_opcode, 2);
483 xl_mii_send(sc, frame->mii_phyaddr, 5);
484 xl_mii_send(sc, frame->mii_regaddr, 5);
487 MII_CLR((XL_MII_CLK|XL_MII_DATA));
495 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
499 * Now try reading data bits. If the ack failed, we still
500 * need to clock through 16 cycles to keep the PHY(s) in sync.
503 for (i = 0; i < 16; i++) {
510 for (i = 0x8000; i; i >>= 1) {
513 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
514 frame->mii_data |= i;
523 return (ack ? 1 : 0);
527 * Write to a PHY register through the MII.
530 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
533 /* Set up frame for TX. */
534 frame->mii_stdelim = XL_MII_STARTDELIM;
535 frame->mii_opcode = XL_MII_WRITEOP;
536 frame->mii_turnaround = XL_MII_TURNAROUND;
538 /* Select the window 4. */
541 /* Turn on data output. */
546 xl_mii_send(sc, frame->mii_stdelim, 2);
547 xl_mii_send(sc, frame->mii_opcode, 2);
548 xl_mii_send(sc, frame->mii_phyaddr, 5);
549 xl_mii_send(sc, frame->mii_regaddr, 5);
550 xl_mii_send(sc, frame->mii_turnaround, 2);
551 xl_mii_send(sc, frame->mii_data, 16);
564 xl_miibus_readreg(device_t dev, int phy, int reg)
567 struct xl_mii_frame frame;
569 sc = device_get_softc(dev);
572 * Pretend that PHYs are only available at MII address 24.
573 * This is to guard against problems with certain 3Com ASIC
574 * revisions that incorrectly map the internal transceiver
575 * control registers at all MII addresses. This can cause
576 * the miibus code to attach the same PHY several times over.
578 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
581 bzero((char *)&frame, sizeof(frame));
582 frame.mii_phyaddr = phy;
583 frame.mii_regaddr = reg;
585 xl_mii_readreg(sc, &frame);
587 return (frame.mii_data);
591 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
594 struct xl_mii_frame frame;
596 sc = device_get_softc(dev);
598 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
601 bzero((char *)&frame, sizeof(frame));
602 frame.mii_phyaddr = phy;
603 frame.mii_regaddr = reg;
604 frame.mii_data = data;
606 xl_mii_writereg(sc, &frame);
612 xl_miibus_statchg(device_t dev)
615 struct mii_data *mii;
617 sc = device_get_softc(dev);
618 mii = device_get_softc(sc->xl_miibus);
622 /* Set ASIC's duplex mode to match the PHY. */
624 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
625 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
627 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
628 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
632 * Special support for the 3c905B-COMBO. This card has 10/100 support
633 * plus BNC and AUI ports. This means we will have both an miibus attached
634 * plus some non-MII media settings. In order to allow this, we have to
635 * add the extra media to the miibus's ifmedia struct, but we can't do
636 * that during xl_attach() because the miibus hasn't been attached yet.
637 * So instead, we wait until the miibus probe/attach is done, at which
638 * point we will get a callback telling is that it's safe to add our
642 xl_miibus_mediainit(device_t dev)
645 struct mii_data *mii;
648 sc = device_get_softc(dev);
649 mii = device_get_softc(sc->xl_miibus);
650 ifm = &mii->mii_media;
652 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
654 * Check for a 10baseFL board in disguise.
656 if (sc->xl_type == XL_TYPE_905B &&
657 sc->xl_media == XL_MEDIAOPT_10FL) {
659 if_printf(sc->xl_ifp,
661 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
662 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
664 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
666 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
669 if_printf(sc->xl_ifp, "found AUI\n");
670 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
674 if (sc->xl_media & XL_MEDIAOPT_BNC) {
676 if_printf(sc->xl_ifp, "found BNC\n");
677 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
682 * The EEPROM is slow: give it time to come ready after issuing
686 xl_eeprom_wait(struct xl_softc *sc)
690 for (i = 0; i < 100; i++) {
691 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
698 if_printf(sc->xl_ifp, "eeprom failed to come ready\n");
706 * Read a sequence of words from the EEPROM. Note that ethernet address
707 * data is stored in the EEPROM in network byte order.
710 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
713 u_int16_t word = 0, *ptr;
715 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
716 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
718 * XXX: WARNING! DANGER!
719 * It's easy to accidentally overwrite the rom content!
720 * Note: the 3c575 uses 8bit EEPROM offsets.
724 if (xl_eeprom_wait(sc))
727 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
730 for (i = 0; i < cnt; i++) {
731 if (sc->xl_flags & XL_FLAG_8BITROM)
732 CSR_WRITE_2(sc, XL_W0_EE_CMD,
733 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
735 CSR_WRITE_2(sc, XL_W0_EE_CMD,
736 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
737 err = xl_eeprom_wait(sc);
740 word = CSR_READ_2(sc, XL_W0_EE_DATA);
741 ptr = (u_int16_t *)(dest + (i * 2));
748 return (err ? 1 : 0);
752 * NICs older than the 3c905B have only one multicast option, which
753 * is to enable reception of all multicast frames.
756 xl_setmulti(struct xl_softc *sc)
758 struct ifnet *ifp = sc->xl_ifp;
759 struct ifmultiaddr *ifma;
766 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
768 if (ifp->if_flags & IFF_ALLMULTI) {
769 rxfilt |= XL_RXFILTER_ALLMULTI;
770 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
775 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
780 rxfilt |= XL_RXFILTER_ALLMULTI;
782 rxfilt &= ~XL_RXFILTER_ALLMULTI;
784 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
788 * 3c905B adapters have a hash filter that we can program.
791 xl_setmulti_hash(struct xl_softc *sc)
793 struct ifnet *ifp = sc->xl_ifp;
795 struct ifmultiaddr *ifma;
802 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
804 if (ifp->if_flags & IFF_ALLMULTI) {
805 rxfilt |= XL_RXFILTER_ALLMULTI;
806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
809 rxfilt &= ~XL_RXFILTER_ALLMULTI;
811 /* first, zot all the existing hash bits */
812 for (i = 0; i < XL_HASHFILT_SIZE; i++)
813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
815 /* now program new ones */
817 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
818 if (ifma->ifma_addr->sa_family != AF_LINK)
821 * Note: the 3c905B currently only supports a 64-bit hash
822 * table, which means we really only need 6 bits, but the
823 * manual indicates that future chip revisions will have a
824 * 256-bit hash table, hence the routine is set up to
825 * calculate 8 bits of position info in case we need it some
827 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have
828 * a 256 bit hash table. This means we have to use all 8 bits
829 * regardless. On older cards, the upper 2 bits will be
832 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
833 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
834 CSR_WRITE_2(sc, XL_COMMAND,
835 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
841 rxfilt |= XL_RXFILTER_MULTIHASH;
843 rxfilt &= ~XL_RXFILTER_MULTIHASH;
845 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
850 xl_testpacket(struct xl_softc *sc)
853 struct ifnet *ifp = sc->xl_ifp;
855 MGETHDR(m, M_DONTWAIT, MT_DATA);
860 bcopy(IF_LLADDR(sc->xl_ifp),
861 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
862 bcopy(IF_LLADDR(sc->xl_ifp),
863 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
864 mtod(m, struct ether_header *)->ether_type = htons(3);
865 mtod(m, unsigned char *)[14] = 0;
866 mtod(m, unsigned char *)[15] = 0;
867 mtod(m, unsigned char *)[16] = 0xE3;
868 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
869 IFQ_ENQUEUE(&ifp->if_snd, m);
875 xl_setcfg(struct xl_softc *sc)
879 /*XL_LOCK_ASSERT(sc);*/
882 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
883 icfg &= ~XL_ICFG_CONNECTOR_MASK;
884 if (sc->xl_media & XL_MEDIAOPT_MII ||
885 sc->xl_media & XL_MEDIAOPT_BT4)
886 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
887 if (sc->xl_media & XL_MEDIAOPT_BTX)
888 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
890 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
895 xl_setmode(struct xl_softc *sc, int media)
899 char *pmsg = "", *dmsg = "";
904 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
906 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
908 if (sc->xl_media & XL_MEDIAOPT_BT) {
909 if (IFM_SUBTYPE(media) == IFM_10_T) {
910 pmsg = "10baseT transceiver";
911 sc->xl_xcvr = XL_XCVR_10BT;
912 icfg &= ~XL_ICFG_CONNECTOR_MASK;
913 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
914 mediastat |= XL_MEDIASTAT_LINKBEAT |
915 XL_MEDIASTAT_JABGUARD;
916 mediastat &= ~XL_MEDIASTAT_SQEENB;
920 if (sc->xl_media & XL_MEDIAOPT_BFX) {
921 if (IFM_SUBTYPE(media) == IFM_100_FX) {
922 pmsg = "100baseFX port";
923 sc->xl_xcvr = XL_XCVR_100BFX;
924 icfg &= ~XL_ICFG_CONNECTOR_MASK;
925 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
926 mediastat |= XL_MEDIASTAT_LINKBEAT;
927 mediastat &= ~XL_MEDIASTAT_SQEENB;
931 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
932 if (IFM_SUBTYPE(media) == IFM_10_5) {
934 sc->xl_xcvr = XL_XCVR_AUI;
935 icfg &= ~XL_ICFG_CONNECTOR_MASK;
936 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
937 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
938 XL_MEDIASTAT_JABGUARD);
939 mediastat |= ~XL_MEDIASTAT_SQEENB;
941 if (IFM_SUBTYPE(media) == IFM_10_FL) {
942 pmsg = "10baseFL transceiver";
943 sc->xl_xcvr = XL_XCVR_AUI;
944 icfg &= ~XL_ICFG_CONNECTOR_MASK;
945 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
946 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
947 XL_MEDIASTAT_JABGUARD);
948 mediastat |= ~XL_MEDIASTAT_SQEENB;
952 if (sc->xl_media & XL_MEDIAOPT_BNC) {
953 if (IFM_SUBTYPE(media) == IFM_10_2) {
955 sc->xl_xcvr = XL_XCVR_COAX;
956 icfg &= ~XL_ICFG_CONNECTOR_MASK;
957 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
958 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
959 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
963 if ((media & IFM_GMASK) == IFM_FDX ||
964 IFM_SUBTYPE(media) == IFM_100_FX) {
967 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
971 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
972 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
975 if (IFM_SUBTYPE(media) == IFM_10_2)
976 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
978 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
980 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
982 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
987 if_printf(sc->xl_ifp, "selecting %s, %s duplex\n", pmsg, dmsg);
991 xl_reset(struct xl_softc *sc)
998 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
999 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1000 XL_RESETOPT_DISADVFD:0));
1003 * If we're using memory mapped register mode, pause briefly
1004 * after issuing the reset command before trying to access any
1005 * other registers. With my 3c575C cardbus card, failing to do
1006 * this results in the system locking up while trying to poll
1007 * the command busy bit in the status register.
1009 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1012 for (i = 0; i < XL_TIMEOUT; i++) {
1014 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1018 if (i == XL_TIMEOUT)
1019 if_printf(sc->xl_ifp, "reset didn't complete\n");
1021 /* Reset TX and RX. */
1022 /* Note: the RX reset takes an absurd amount of time
1023 * on newer versions of the Tornado chips such as those
1024 * on the 3c905CX and newer 3c908C cards. We wait an
1025 * extra amount of time so that xl_wait() doesn't complain
1026 * and annoy the users.
1028 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1031 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1034 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1035 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1037 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
1038 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
1039 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
1040 XL_RESETOPT_INVERT_LED : 0) |
1041 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
1042 XL_RESETOPT_INVERT_MII : 0));
1045 /* Wait a little while for the chip to get its brains in order. */
1050 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1051 * IDs against our list and return a device name if we find a match.
1054 xl_probe(device_t dev)
1060 while (t->xl_name != NULL) {
1061 if ((pci_get_vendor(dev) == t->xl_vid) &&
1062 (pci_get_device(dev) == t->xl_did)) {
1063 device_set_desc(dev, t->xl_name);
1064 return (BUS_PROBE_DEFAULT);
1073 * This routine is a kludge to work around possible hardware faults
1074 * or manufacturing defects that can cause the media options register
1075 * (or reset options register, as it's called for the first generation
1076 * 3c90x adapters) to return an incorrect result. I have encountered
1077 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1078 * which doesn't have any of the 'mediaopt' bits set. This screws up
1079 * the attach routine pretty badly because it doesn't know what media
1080 * to look for. If we find ourselves in this predicament, this routine
1081 * will try to guess the media options values and warn the user of a
1082 * possible manufacturing defect with his adapter/system/whatever.
1085 xl_mediacheck(struct xl_softc *sc)
1089 * If some of the media options bits are set, assume they are
1090 * correct. If not, try to figure it out down below.
1091 * XXX I should check for 10baseFL, but I don't have an adapter
1094 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1096 * Check the XCVR value. If it's not in the normal range
1097 * of values, we need to fake it up here.
1099 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1102 if_printf(sc->xl_ifp,
1103 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
1104 if_printf(sc->xl_ifp,
1105 "choosing new default based on card type\n");
1108 if (sc->xl_type == XL_TYPE_905B &&
1109 sc->xl_media & XL_MEDIAOPT_10FL)
1111 if_printf(sc->xl_ifp,
1112 "WARNING: no media options bits set in the media options register!!\n");
1113 if_printf(sc->xl_ifp,
1114 "this could be a manufacturing defect in your adapter or system\n");
1115 if_printf(sc->xl_ifp,
1116 "attempting to guess media type; you should probably consult your vendor\n");
1119 xl_choose_xcvr(sc, 1);
1123 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1128 * Read the device ID from the EEPROM.
1129 * This is what's loaded into the PCI device ID register, so it has
1130 * to be correct otherwise we wouldn't have gotten this far.
1132 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1135 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1136 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1137 sc->xl_media = XL_MEDIAOPT_BT;
1138 sc->xl_xcvr = XL_XCVR_10BT;
1140 if_printf(sc->xl_ifp,
1141 "guessing 10BaseT transceiver\n");
1143 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1144 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1145 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1146 sc->xl_xcvr = XL_XCVR_10BT;
1148 if_printf(sc->xl_ifp,
1149 "guessing COMBO (AUI/BNC/TP)\n");
1151 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1152 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1153 sc->xl_xcvr = XL_XCVR_10BT;
1155 if_printf(sc->xl_ifp, "guessing TPC (BNC/TP)\n");
1157 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1158 sc->xl_media = XL_MEDIAOPT_10FL;
1159 sc->xl_xcvr = XL_XCVR_AUI;
1161 if_printf(sc->xl_ifp, "guessing 10baseFL\n");
1163 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1164 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1165 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1166 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1167 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1168 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1169 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1170 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1171 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1172 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1173 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1174 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1175 sc->xl_media = XL_MEDIAOPT_MII;
1176 sc->xl_xcvr = XL_XCVR_MII;
1178 if_printf(sc->xl_ifp, "guessing MII\n");
1180 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1181 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1182 sc->xl_media = XL_MEDIAOPT_BT4;
1183 sc->xl_xcvr = XL_XCVR_MII;
1185 if_printf(sc->xl_ifp,
1186 "guessing 100baseT4/MII\n");
1188 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1189 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1190 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1191 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1192 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1193 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1194 sc->xl_media = XL_MEDIAOPT_BTX;
1195 sc->xl_xcvr = XL_XCVR_AUTO;
1197 if_printf(sc->xl_ifp,
1198 "guessing 10/100 internal\n");
1200 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1201 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1202 sc->xl_xcvr = XL_XCVR_AUTO;
1204 if_printf(sc->xl_ifp,
1205 "guessing 10/100 plus BNC/AUI\n");
1208 if_printf(sc->xl_ifp,
1209 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1210 sc->xl_media = XL_MEDIAOPT_BT;
1216 * Attach the interface. Allocate softc structures, do ifmedia
1217 * setup and ethernet/BPF attach.
1220 xl_attach(device_t dev)
1222 u_char eaddr[ETHER_ADDR_LEN];
1224 struct xl_softc *sc;
1227 int unit, error = 0, rid, res;
1230 sc = device_get_softc(dev);
1231 unit = device_get_unit(dev);
1233 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1235 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1237 did = pci_get_device(dev);
1240 if (did == TC_DEVICEID_HURRICANE_555)
1241 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1242 if (did == TC_DEVICEID_HURRICANE_556 ||
1243 did == TC_DEVICEID_HURRICANE_556B)
1244 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1245 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1246 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1247 if (did == TC_DEVICEID_HURRICANE_555 ||
1248 did == TC_DEVICEID_HURRICANE_556)
1249 sc->xl_flags |= XL_FLAG_8BITROM;
1250 if (did == TC_DEVICEID_HURRICANE_556B)
1251 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1253 if (did == TC_DEVICEID_HURRICANE_575B ||
1254 did == TC_DEVICEID_HURRICANE_575C ||
1255 did == TC_DEVICEID_HURRICANE_656B ||
1256 did == TC_DEVICEID_TORNADO_656C)
1257 sc->xl_flags |= XL_FLAG_FUNCREG;
1258 if (did == TC_DEVICEID_HURRICANE_575A ||
1259 did == TC_DEVICEID_HURRICANE_575B ||
1260 did == TC_DEVICEID_HURRICANE_575C ||
1261 did == TC_DEVICEID_HURRICANE_656B ||
1262 did == TC_DEVICEID_TORNADO_656C)
1263 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1265 if (did == TC_DEVICEID_HURRICANE_656)
1266 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1267 if (did == TC_DEVICEID_HURRICANE_575B)
1268 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1269 if (did == TC_DEVICEID_HURRICANE_575C)
1270 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1271 if (did == TC_DEVICEID_TORNADO_656C)
1272 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1273 if (did == TC_DEVICEID_HURRICANE_656 ||
1274 did == TC_DEVICEID_HURRICANE_656B)
1275 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1276 XL_FLAG_INVERT_LED_PWR;
1277 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1278 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1279 sc->xl_flags |= XL_FLAG_PHYOK;
1282 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1283 case TC_DEVICEID_HURRICANE_575A:
1284 case TC_DEVICEID_HURRICANE_575B:
1285 case TC_DEVICEID_HURRICANE_575C:
1286 sc->xl_flags |= XL_FLAG_NO_MMIO;
1293 * Map control/status registers.
1295 pci_enable_busmaster(dev);
1297 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1299 res = SYS_RES_MEMORY;
1301 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1304 if (sc->xl_res != NULL) {
1305 sc->xl_flags |= XL_FLAG_USE_MMIO;
1307 device_printf(dev, "using memory mapped I/O\n");
1310 res = SYS_RES_IOPORT;
1311 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1312 if (sc->xl_res == NULL) {
1313 device_printf(dev, "couldn't map ports/memory\n");
1318 device_printf(dev, "using port I/O\n");
1321 sc->xl_btag = rman_get_bustag(sc->xl_res);
1322 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1324 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1325 rid = XL_PCI_FUNCMEM;
1326 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1329 if (sc->xl_fres == NULL) {
1330 device_printf(dev, "couldn't map funcreg memory\n");
1335 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1336 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1339 /* Allocate interrupt */
1341 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1342 RF_SHAREABLE | RF_ACTIVE);
1343 if (sc->xl_irq == NULL) {
1344 device_printf(dev, "couldn't map interrupt\n");
1349 /* Initialize interface name. */
1350 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1352 device_printf(dev, "can not if_alloc()\n");
1357 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1359 /* Reset the adapter. */
1365 * Get station address from the EEPROM.
1367 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1368 device_printf(dev, "failed to read station address\n");
1374 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0);
1375 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1378 * Now allocate a tag for the DMA descriptor lists and a chunk
1379 * of DMA-able memory based on the tag. Also obtain the DMA
1380 * addresses of the RX and TX ring, which we'll need later.
1381 * All of our lists are allocated as a contiguous block
1384 error = bus_dma_tag_create(NULL, 8, 0,
1385 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1386 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1387 &sc->xl_ldata.xl_rx_tag);
1389 device_printf(dev, "failed to allocate rx dma tag\n");
1393 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1394 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1395 &sc->xl_ldata.xl_rx_dmamap);
1397 device_printf(dev, "no memory for rx list buffers!\n");
1398 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1399 sc->xl_ldata.xl_rx_tag = NULL;
1403 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1404 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1405 XL_RX_LIST_SZ, xl_dma_map_addr,
1406 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1408 device_printf(dev, "cannot get dma address of the rx ring!\n");
1409 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1410 sc->xl_ldata.xl_rx_dmamap);
1411 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1412 sc->xl_ldata.xl_rx_tag = NULL;
1416 error = bus_dma_tag_create(NULL, 8, 0,
1417 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1418 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1419 &sc->xl_ldata.xl_tx_tag);
1421 device_printf(dev, "failed to allocate tx dma tag\n");
1425 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1426 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1427 &sc->xl_ldata.xl_tx_dmamap);
1429 device_printf(dev, "no memory for list buffers!\n");
1430 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1431 sc->xl_ldata.xl_tx_tag = NULL;
1435 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1436 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1437 XL_TX_LIST_SZ, xl_dma_map_addr,
1438 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1440 device_printf(dev, "cannot get dma address of the tx ring!\n");
1441 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1442 sc->xl_ldata.xl_tx_dmamap);
1443 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1444 sc->xl_ldata.xl_tx_tag = NULL;
1449 * Allocate a DMA tag for the mapping of mbufs.
1451 error = bus_dma_tag_create(NULL, 1, 0,
1452 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1453 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1454 NULL, &sc->xl_mtag);
1456 device_printf(dev, "failed to allocate mbuf dma tag\n");
1460 /* We need a spare DMA map for the RX ring. */
1461 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1466 * Figure out the card type. 3c905B adapters have the
1467 * 'supportsNoTxLength' bit set in the capabilities
1468 * word in the EEPROM.
1469 * Note: my 3c575C cardbus card lies. It returns a value
1470 * of 0x1578 for its capabilities word, which is somewhat
1471 * nonsensical. Another way to distinguish a 3c90x chip
1472 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1473 * bit. This will only be set for 3c90x boomerage chips.
1475 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1476 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1477 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1478 sc->xl_type = XL_TYPE_905B;
1480 sc->xl_type = XL_TYPE_90X;
1482 ifp->if_mtu = ETHERMTU;
1483 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1484 ifp->if_ioctl = xl_ioctl;
1485 ifp->if_capabilities = IFCAP_VLAN_MTU;
1486 if (sc->xl_type == XL_TYPE_905B) {
1487 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1488 #ifdef XL905B_TXCSUM_BROKEN
1489 ifp->if_capabilities |= IFCAP_RXCSUM;
1491 ifp->if_capabilities |= IFCAP_HWCSUM;
1494 ifp->if_capenable = ifp->if_capabilities;
1495 #ifdef DEVICE_POLLING
1496 ifp->if_capabilities |= IFCAP_POLLING;
1498 ifp->if_start = xl_start;
1499 ifp->if_watchdog = xl_watchdog;
1500 ifp->if_init = xl_init;
1501 ifp->if_baudrate = 10000000;
1502 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1503 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1504 IFQ_SET_READY(&ifp->if_snd);
1507 * Now we have to see what sort of media we have.
1508 * This includes probing for an MII interace and a
1512 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1514 device_printf(dev, "media options word: %x\n", sc->xl_media);
1516 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1517 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1518 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1519 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1523 if (sc->xl_media & XL_MEDIAOPT_MII ||
1524 sc->xl_media & XL_MEDIAOPT_BTX ||
1525 sc->xl_media & XL_MEDIAOPT_BT4) {
1527 device_printf(dev, "found MII/AUTO\n");
1529 if (mii_phy_probe(dev, &sc->xl_miibus,
1530 xl_ifmedia_upd, xl_ifmedia_sts)) {
1531 device_printf(dev, "no PHY found!\n");
1539 * Sanity check. If the user has selected "auto" and this isn't
1540 * a 10/100 card of some kind, we need to force the transceiver
1541 * type to something sane.
1543 if (sc->xl_xcvr == XL_XCVR_AUTO)
1544 xl_choose_xcvr(sc, bootverbose);
1549 if (sc->xl_media & XL_MEDIAOPT_BT) {
1551 device_printf(dev, "found 10baseT\n");
1552 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1553 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1554 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1555 ifmedia_add(&sc->ifmedia,
1556 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1559 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1561 * Check for a 10baseFL board in disguise.
1563 if (sc->xl_type == XL_TYPE_905B &&
1564 sc->xl_media == XL_MEDIAOPT_10FL) {
1566 device_printf(dev, "found 10baseFL\n");
1567 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1568 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1570 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1571 ifmedia_add(&sc->ifmedia,
1572 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1575 device_printf(dev, "found AUI\n");
1576 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1580 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1582 device_printf(dev, "found BNC\n");
1583 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1586 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1588 device_printf(dev, "found 100baseFX\n");
1589 ifp->if_baudrate = 100000000;
1590 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1593 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1594 xl_choose_media(sc, &media);
1596 if (sc->xl_miibus == NULL)
1597 ifmedia_set(&sc->ifmedia, media);
1600 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1602 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1606 * Call MI attach routine.
1608 ether_ifattach(ifp, eaddr);
1610 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1611 xl_intr, sc, &sc->xl_intrhand);
1613 device_printf(dev, "couldn't set up irq\n");
1614 ether_ifdetach(ifp);
1626 * Choose a default media.
1627 * XXX This is a leaf function only called by xl_attach() and
1628 * acquires/releases the non-recursible driver mutex to
1629 * satisfy lock assertions.
1632 xl_choose_media(struct xl_softc *sc, int *media)
1637 switch (sc->xl_xcvr) {
1639 *media = IFM_ETHER|IFM_10_T;
1640 xl_setmode(sc, *media);
1643 if (sc->xl_type == XL_TYPE_905B &&
1644 sc->xl_media == XL_MEDIAOPT_10FL) {
1645 *media = IFM_ETHER|IFM_10_FL;
1646 xl_setmode(sc, *media);
1648 *media = IFM_ETHER|IFM_10_5;
1649 xl_setmode(sc, *media);
1653 *media = IFM_ETHER|IFM_10_2;
1654 xl_setmode(sc, *media);
1657 case XL_XCVR_100BTX:
1659 /* Chosen by miibus */
1661 case XL_XCVR_100BFX:
1662 *media = IFM_ETHER|IFM_100_FX;
1665 if_printf(sc->xl_ifp, "unknown XCVR type: %d\n",
1668 * This will probably be wrong, but it prevents
1669 * the ifmedia code from panicking.
1671 *media = IFM_ETHER|IFM_10_T;
1679 * Shutdown hardware and free up resources. This can be called any
1680 * time after the mutex has been initialized. It is called in both
1681 * the error case in attach and the normal detach case so it needs
1682 * to be careful about only freeing resources that have actually been
1686 xl_detach(device_t dev)
1688 struct xl_softc *sc;
1692 sc = device_get_softc(dev);
1695 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1697 #ifdef DEVICE_POLLING
1698 if (ifp->if_capenable & IFCAP_POLLING)
1699 ether_poll_deregister(ifp);
1702 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1704 res = SYS_RES_MEMORY;
1707 res = SYS_RES_IOPORT;
1710 /* These should only be active if attach succeeded */
1711 if (device_is_attached(dev)) {
1716 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1717 callout_drain(&sc->xl_stat_callout);
1718 ether_ifdetach(ifp);
1721 device_delete_child(dev, sc->xl_miibus);
1722 bus_generic_detach(dev);
1723 ifmedia_removeall(&sc->ifmedia);
1725 if (sc->xl_intrhand)
1726 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1728 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1729 if (sc->xl_fres != NULL)
1730 bus_release_resource(dev, SYS_RES_MEMORY,
1731 XL_PCI_FUNCMEM, sc->xl_fres);
1733 bus_release_resource(dev, res, rid, sc->xl_res);
1739 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1740 bus_dma_tag_destroy(sc->xl_mtag);
1742 if (sc->xl_ldata.xl_rx_tag) {
1743 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1744 sc->xl_ldata.xl_rx_dmamap);
1745 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1746 sc->xl_ldata.xl_rx_dmamap);
1747 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1749 if (sc->xl_ldata.xl_tx_tag) {
1750 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1751 sc->xl_ldata.xl_tx_dmamap);
1752 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1753 sc->xl_ldata.xl_tx_dmamap);
1754 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1757 mtx_destroy(&sc->xl_mtx);
1763 * Initialize the transmit descriptors.
1766 xl_list_tx_init(struct xl_softc *sc)
1768 struct xl_chain_data *cd;
1769 struct xl_list_data *ld;
1776 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1777 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1778 error = bus_dmamap_create(sc->xl_mtag, 0,
1779 &cd->xl_tx_chain[i].xl_map);
1782 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1783 i * sizeof(struct xl_list);
1784 if (i == (XL_TX_LIST_CNT - 1))
1785 cd->xl_tx_chain[i].xl_next = NULL;
1787 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1790 cd->xl_tx_free = &cd->xl_tx_chain[0];
1791 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1793 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1798 * Initialize the transmit descriptors.
1801 xl_list_tx_init_90xB(struct xl_softc *sc)
1803 struct xl_chain_data *cd;
1804 struct xl_list_data *ld;
1811 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1812 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1813 error = bus_dmamap_create(sc->xl_mtag, 0,
1814 &cd->xl_tx_chain[i].xl_map);
1817 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1818 i * sizeof(struct xl_list);
1819 if (i == (XL_TX_LIST_CNT - 1))
1820 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1822 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1824 cd->xl_tx_chain[i].xl_prev =
1825 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1827 cd->xl_tx_chain[i].xl_prev =
1828 &cd->xl_tx_chain[i - 1];
1831 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1832 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1838 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1843 * Initialize the RX descriptors and allocate mbufs for them. Note that
1844 * we arrange the descriptors in a closed ring, so that the last descriptor
1845 * points back to the first.
1848 xl_list_rx_init(struct xl_softc *sc)
1850 struct xl_chain_data *cd;
1851 struct xl_list_data *ld;
1860 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1861 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1862 error = bus_dmamap_create(sc->xl_mtag, 0,
1863 &cd->xl_rx_chain[i].xl_map);
1866 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1869 if (i == (XL_RX_LIST_CNT - 1))
1873 nextptr = ld->xl_rx_dmaaddr +
1874 next * sizeof(struct xl_list_onefrag);
1875 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1876 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1879 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1880 cd->xl_rx_head = &cd->xl_rx_chain[0];
1886 * Initialize an RX descriptor and attach an MBUF cluster.
1887 * If we fail to do so, we need to leave the old mbuf and
1888 * the old DMA map untouched so that it can be reused.
1891 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1893 struct mbuf *m_new = NULL;
1900 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1904 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1906 /* Force longword alignment for packet payload. */
1907 m_adj(m_new, ETHER_ALIGN);
1909 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1910 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1913 if_printf(sc->xl_ifp, "can't map mbuf (error %d)\n",
1918 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1920 c->xl_map = sc->xl_tmpmap;
1921 sc->xl_tmpmap = map;
1923 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1924 c->xl_ptr->xl_status = 0;
1925 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
1926 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1931 xl_rx_resync(struct xl_softc *sc)
1933 struct xl_chain_onefrag *pos;
1938 pos = sc->xl_cdata.xl_rx_head;
1940 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1941 if (pos->xl_ptr->xl_status)
1946 if (i == XL_RX_LIST_CNT)
1949 sc->xl_cdata.xl_rx_head = pos;
1955 * A frame has been uploaded: pass the resulting mbuf chain up to
1956 * the higher level protocols.
1959 xl_rxeof(struct xl_softc *sc)
1962 struct ifnet *ifp = sc->xl_ifp;
1963 struct xl_chain_onefrag *cur_rx;
1969 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1970 BUS_DMASYNC_POSTREAD);
1971 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1972 #ifdef DEVICE_POLLING
1973 if (ifp->if_capenable & IFCAP_POLLING) {
1974 if (sc->rxcycles <= 0)
1979 cur_rx = sc->xl_cdata.xl_rx_head;
1980 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1981 total_len = rxstat & XL_RXSTAT_LENMASK;
1984 * Since we have told the chip to allow large frames,
1985 * we need to trap giant frame errors in software. We allow
1986 * a little more than the normal frame size to account for
1987 * frames with VLAN tags.
1989 if (total_len > XL_MAX_FRAMELEN)
1990 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1993 * If an error occurs, update stats, clear the
1994 * status word and leave the mbuf cluster in place:
1995 * it should simply get re-used next time this descriptor
1996 * comes up in the ring.
1998 if (rxstat & XL_RXSTAT_UP_ERROR) {
2000 cur_rx->xl_ptr->xl_status = 0;
2001 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2002 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2007 * If the error bit was not set, the upload complete
2008 * bit should be set which means we have a valid packet.
2009 * If not, something truly strange has happened.
2011 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2013 "bad receive status -- packet dropped\n");
2015 cur_rx->xl_ptr->xl_status = 0;
2016 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2017 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2021 /* No errors; receive the packet. */
2022 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2023 BUS_DMASYNC_POSTREAD);
2024 m = cur_rx->xl_mbuf;
2027 * Try to conjure up a new mbuf cluster. If that
2028 * fails, it means we have an out of memory condition and
2029 * should leave the buffer in place and continue. This will
2030 * result in a lost packet, but there's little else we
2031 * can do in this situation.
2033 if (xl_newbuf(sc, cur_rx)) {
2035 cur_rx->xl_ptr->xl_status = 0;
2036 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2037 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2040 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2041 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2044 m->m_pkthdr.rcvif = ifp;
2045 m->m_pkthdr.len = m->m_len = total_len;
2047 if (ifp->if_capenable & IFCAP_RXCSUM) {
2048 /* Do IP checksum checking. */
2049 if (rxstat & XL_RXSTAT_IPCKOK)
2050 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2051 if (!(rxstat & XL_RXSTAT_IPCKERR))
2052 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2053 if ((rxstat & XL_RXSTAT_TCPCOK &&
2054 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2055 (rxstat & XL_RXSTAT_UDPCKOK &&
2056 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2057 m->m_pkthdr.csum_flags |=
2058 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2059 m->m_pkthdr.csum_data = 0xffff;
2064 (*ifp->if_input)(ifp, m);
2068 * If we are running from the taskqueue, the interface
2069 * might have been stopped while we were passing the last
2070 * packet up the network stack.
2072 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
2077 * Handle the 'end of channel' condition. When the upload
2078 * engine hits the end of the RX ring, it will stall. This
2079 * is our cue to flush the RX ring, reload the uplist pointer
2080 * register and unstall the engine.
2081 * XXX This is actually a little goofy. With the ThunderLAN
2082 * chip, you get an interrupt when the receiver hits the end
2083 * of the receive ring, which tells you exactly when you
2084 * you need to reload the ring pointer. Here we have to
2085 * fake it. I'm mad at myself for not being clever enough
2086 * to avoid the use of a goto here.
2088 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2089 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2090 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2092 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2093 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2094 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2100 * Taskqueue wrapper for xl_rxeof().
2103 xl_rxeof_task(void *arg, int pending)
2105 struct xl_softc *sc = (struct xl_softc *)arg;
2109 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
2116 * A frame was downloaded to the chip. It's safe for us to clean up
2120 xl_txeof(struct xl_softc *sc)
2122 struct xl_chain *cur_tx;
2123 struct ifnet *ifp = sc->xl_ifp;
2127 /* Clear the timeout timer. */
2131 * Go through our tx list and free mbufs for those
2132 * frames that have been uploaded. Note: the 3c905B
2133 * sets a special bit in the status word to let us
2134 * know that a frame has been downloaded, but the
2135 * original 3c900/3c905 adapters don't do that.
2136 * Consequently, we have to use a different test if
2137 * xl_type != XL_TYPE_905B.
2139 while (sc->xl_cdata.xl_tx_head != NULL) {
2140 cur_tx = sc->xl_cdata.xl_tx_head;
2142 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2145 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2146 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2147 BUS_DMASYNC_POSTWRITE);
2148 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2149 m_freem(cur_tx->xl_mbuf);
2150 cur_tx->xl_mbuf = NULL;
2153 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2154 sc->xl_cdata.xl_tx_free = cur_tx;
2157 if (sc->xl_cdata.xl_tx_head == NULL) {
2158 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2159 sc->xl_cdata.xl_tx_tail = NULL;
2161 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2162 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2163 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2164 sc->xl_cdata.xl_tx_head->xl_phys);
2165 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2171 xl_txeof_90xB(struct xl_softc *sc)
2173 struct xl_chain *cur_tx = NULL;
2174 struct ifnet *ifp = sc->xl_ifp;
2179 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2180 BUS_DMASYNC_POSTREAD);
2181 idx = sc->xl_cdata.xl_tx_cons;
2182 while (idx != sc->xl_cdata.xl_tx_prod) {
2184 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2186 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2187 XL_TXSTAT_DL_COMPLETE))
2190 if (cur_tx->xl_mbuf != NULL) {
2191 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2192 BUS_DMASYNC_POSTWRITE);
2193 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2194 m_freem(cur_tx->xl_mbuf);
2195 cur_tx->xl_mbuf = NULL;
2200 sc->xl_cdata.xl_tx_cnt--;
2201 XL_INC(idx, XL_TX_LIST_CNT);
2205 sc->xl_cdata.xl_tx_cons = idx;
2208 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2212 * TX 'end of channel' interrupt handler. Actually, we should
2213 * only get a 'TX complete' interrupt if there's a transmit error,
2214 * so this is really TX error handler.
2217 xl_txeoc(struct xl_softc *sc)
2223 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2224 if (txstat & XL_TXSTATUS_UNDERRUN ||
2225 txstat & XL_TXSTATUS_JABBER ||
2226 txstat & XL_TXSTATUS_RECLAIM) {
2227 if_printf(sc->xl_ifp,
2228 "transmission error: %x\n", txstat);
2229 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2231 if (sc->xl_type == XL_TYPE_905B) {
2232 if (sc->xl_cdata.xl_tx_cnt) {
2236 i = sc->xl_cdata.xl_tx_cons;
2237 c = &sc->xl_cdata.xl_tx_chain[i];
2238 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2240 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2243 if (sc->xl_cdata.xl_tx_head != NULL)
2244 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2245 sc->xl_cdata.xl_tx_head->xl_phys);
2248 * Remember to set this for the
2249 * first generation 3c90X chips.
2251 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2252 if (txstat & XL_TXSTATUS_UNDERRUN &&
2253 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2254 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2255 if_printf(sc->xl_ifp,
2256 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2258 CSR_WRITE_2(sc, XL_COMMAND,
2259 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2260 if (sc->xl_type == XL_TYPE_905B) {
2261 CSR_WRITE_2(sc, XL_COMMAND,
2262 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2264 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2265 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2267 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2268 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2271 * Write an arbitrary byte to the TX_STATUS register
2272 * to clear this interrupt/error and advance to the next.
2274 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2281 struct xl_softc *sc = arg;
2282 struct ifnet *ifp = sc->xl_ifp;
2287 #ifdef DEVICE_POLLING
2288 if (ifp->if_capenable & IFCAP_POLLING) {
2294 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS &&
2296 CSR_WRITE_2(sc, XL_COMMAND,
2297 XL_CMD_INTR_ACK|(status & XL_INTRS));
2299 if (status & XL_STAT_UP_COMPLETE) {
2302 curpkts = ifp->if_ipackets;
2304 if (curpkts == ifp->if_ipackets) {
2305 while (xl_rx_resync(sc))
2310 if (status & XL_STAT_DOWN_COMPLETE) {
2311 if (sc->xl_type == XL_TYPE_905B)
2317 if (status & XL_STAT_TX_COMPLETE) {
2322 if (status & XL_STAT_ADFAIL) {
2327 if (status & XL_STAT_STATSOFLOW) {
2328 sc->xl_stats_no_timeout = 1;
2329 xl_stats_update_locked(sc);
2330 sc->xl_stats_no_timeout = 0;
2334 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2335 if (sc->xl_type == XL_TYPE_905B)
2336 xl_start_90xB_locked(ifp);
2338 xl_start_locked(ifp);
2344 #ifdef DEVICE_POLLING
2346 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2348 struct xl_softc *sc = ifp->if_softc;
2351 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2352 xl_poll_locked(ifp, cmd, count);
2357 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2359 struct xl_softc *sc = ifp->if_softc;
2363 sc->rxcycles = count;
2365 if (sc->xl_type == XL_TYPE_905B)
2370 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2371 if (sc->xl_type == XL_TYPE_905B)
2372 xl_start_90xB_locked(ifp);
2374 xl_start_locked(ifp);
2377 if (cmd == POLL_AND_CHECK_STATUS) {
2380 status = CSR_READ_2(sc, XL_STATUS);
2381 if (status & XL_INTRS && status != 0xFFFF) {
2382 CSR_WRITE_2(sc, XL_COMMAND,
2383 XL_CMD_INTR_ACK|(status & XL_INTRS));
2385 if (status & XL_STAT_TX_COMPLETE) {
2390 if (status & XL_STAT_ADFAIL) {
2395 if (status & XL_STAT_STATSOFLOW) {
2396 sc->xl_stats_no_timeout = 1;
2397 xl_stats_update_locked(sc);
2398 sc->xl_stats_no_timeout = 0;
2403 #endif /* DEVICE_POLLING */
2406 * XXX: This is an entry point for callout which needs to take the lock.
2409 xl_stats_update(void *xsc)
2411 struct xl_softc *sc = xsc;
2414 xl_stats_update_locked(sc);
2418 xl_stats_update_locked(struct xl_softc *sc)
2420 struct ifnet *ifp = sc->xl_ifp;
2421 struct xl_stats xl_stats;
2424 struct mii_data *mii = NULL;
2428 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2430 if (sc->xl_miibus != NULL)
2431 mii = device_get_softc(sc->xl_miibus);
2433 p = (u_int8_t *)&xl_stats;
2435 /* Read all the stats registers. */
2438 for (i = 0; i < 16; i++)
2439 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2441 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2443 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2444 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision;
2447 * Boomerang and cyclone chips have an extra stats counter
2448 * in window 4 (BadSSD). We have to read this too in order
2449 * to clear out all the stats registers and avoid a statsoflow
2453 CSR_READ_1(sc, XL_W4_BADSSD);
2455 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2460 if (!sc->xl_stats_no_timeout)
2461 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
2465 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2466 * pointers to the fragment pointers.
2469 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2473 struct ifnet *ifp = sc->xl_ifp;
2478 * Start packing the mbufs in this chain into
2479 * the fragment pointers. Stop when we run out
2480 * of fragments or hit the end of the mbuf chain.
2482 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2483 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2485 if (error && error != EFBIG) {
2487 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2492 * Handle special case: we used up all 63 fragments,
2493 * but we have more mbufs left in the chain. Copy the
2494 * data into an mbuf cluster. Note that we don't
2495 * bother clearing the values in the other fragment
2496 * pointers/counters; it wouldn't gain us anything,
2497 * and would waste cycles.
2502 m_new = m_defrag(m_head, M_DONTWAIT);
2503 if (m_new == NULL) {
2510 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2511 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2514 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2519 if (sc->xl_type == XL_TYPE_905B) {
2520 status = XL_TXSTAT_RND_DEFEAT;
2522 #ifndef XL905B_TXCSUM_BROKEN
2523 if (m_head->m_pkthdr.csum_flags) {
2524 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2525 status |= XL_TXSTAT_IPCKSUM;
2526 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2527 status |= XL_TXSTAT_TCPCKSUM;
2528 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2529 status |= XL_TXSTAT_UDPCKSUM;
2532 c->xl_ptr->xl_status = htole32(status);
2535 c->xl_mbuf = m_head;
2536 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2541 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2542 * to the mbuf data regions directly in the transmit lists. We also save a
2543 * copy of the pointers since the transmit list fragment pointers are
2544 * physical addresses.
2548 xl_start(struct ifnet *ifp)
2550 struct xl_softc *sc = ifp->if_softc;
2554 if (sc->xl_type == XL_TYPE_905B)
2555 xl_start_90xB_locked(ifp);
2557 xl_start_locked(ifp);
2563 xl_start_locked(struct ifnet *ifp)
2565 struct xl_softc *sc = ifp->if_softc;
2566 struct mbuf *m_head = NULL;
2567 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2568 struct xl_chain *prev_tx;
2575 * Check for an available queue slot. If there are none,
2578 if (sc->xl_cdata.xl_tx_free == NULL) {
2581 if (sc->xl_cdata.xl_tx_free == NULL) {
2582 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2587 start_tx = sc->xl_cdata.xl_tx_free;
2589 while (sc->xl_cdata.xl_tx_free != NULL) {
2590 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2594 /* Pick a descriptor off the free list. */
2596 cur_tx = sc->xl_cdata.xl_tx_free;
2598 /* Pack the data into the descriptor. */
2599 error = xl_encap(sc, cur_tx, m_head);
2605 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2606 cur_tx->xl_next = NULL;
2608 /* Chain it together. */
2610 prev->xl_next = cur_tx;
2611 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2616 * If there's a BPF listener, bounce a copy of this frame
2619 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2623 * If there are no packets queued, bail.
2629 * Place the request for the upload interrupt
2630 * in the last descriptor in the chain. This way, if
2631 * we're chaining several packets at once, we'll only
2632 * get an interupt once for the whole chain rather than
2633 * once for each packet.
2635 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2637 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2638 BUS_DMASYNC_PREWRITE);
2641 * Queue the packets. If the TX channel is clear, update
2642 * the downlist pointer register.
2644 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2647 if (sc->xl_cdata.xl_tx_head != NULL) {
2648 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2649 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2650 htole32(start_tx->xl_phys);
2651 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2652 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2653 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2654 sc->xl_cdata.xl_tx_tail = cur_tx;
2656 sc->xl_cdata.xl_tx_head = start_tx;
2657 sc->xl_cdata.xl_tx_tail = cur_tx;
2659 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2660 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2662 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2667 * Set a timeout in case the chip goes out to lunch.
2672 * XXX Under certain conditions, usually on slower machines
2673 * where interrupts may be dropped, it's possible for the
2674 * adapter to chew up all the buffers in the receive ring
2675 * and stall, without us being able to do anything about it.
2676 * To guard against this, we need to make a pass over the
2677 * RX queue to make sure there aren't any packets pending.
2678 * Doing it here means we can flush the receive ring at the
2679 * same time the chip is DMAing the transmit descriptors we
2682 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2683 * nature of their chips in all their marketing literature;
2684 * we may as well take advantage of it. :)
2686 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2690 xl_start_90xB_locked(struct ifnet *ifp)
2692 struct xl_softc *sc = ifp->if_softc;
2693 struct mbuf *m_head = NULL;
2694 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2695 struct xl_chain *prev_tx;
2700 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
2703 idx = sc->xl_cdata.xl_tx_prod;
2704 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2706 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2708 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2709 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2713 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2718 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2720 /* Pack the data into the descriptor. */
2721 error = xl_encap(sc, cur_tx, m_head);
2727 /* Chain it together. */
2729 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2733 * If there's a BPF listener, bounce a copy of this frame
2736 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2738 XL_INC(idx, XL_TX_LIST_CNT);
2739 sc->xl_cdata.xl_tx_cnt++;
2743 * If there are no packets queued, bail.
2749 * Place the request for the upload interrupt
2750 * in the last descriptor in the chain. This way, if
2751 * we're chaining several packets at once, we'll only
2752 * get an interupt once for the whole chain rather than
2753 * once for each packet.
2755 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2757 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2758 BUS_DMASYNC_PREWRITE);
2760 /* Start transmission */
2761 sc->xl_cdata.xl_tx_prod = idx;
2762 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2765 * Set a timeout in case the chip goes out to lunch.
2773 struct xl_softc *sc = xsc;
2781 xl_init_locked(struct xl_softc *sc)
2783 struct ifnet *ifp = sc->xl_ifp;
2785 u_int16_t rxfilt = 0;
2786 struct mii_data *mii = NULL;
2791 * Cancel pending I/O and free all RX/TX buffers.
2795 if (sc->xl_miibus == NULL) {
2796 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2799 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2803 if (sc->xl_miibus != NULL)
2804 mii = device_get_softc(sc->xl_miibus);
2806 /* Init our MAC address */
2808 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2809 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2810 IF_LLADDR(sc->xl_ifp)[i]);
2813 /* Clear the station mask. */
2814 for (i = 0; i < 3; i++)
2815 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2817 /* Reset TX and RX. */
2818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2823 /* Init circular RX list. */
2824 error = xl_list_rx_init(sc);
2826 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2832 /* Init TX descriptors. */
2833 if (sc->xl_type == XL_TYPE_905B)
2834 error = xl_list_tx_init_90xB(sc);
2836 error = xl_list_tx_init(sc);
2838 if_printf(ifp, "initialization of the tx ring failed (%d)\n",
2845 * Set the TX freethresh value.
2846 * Note that this has no effect on 3c905B "cyclone"
2847 * cards but is required for 3c900/3c905 "boomerang"
2848 * cards in order to enable the download engine.
2850 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2852 /* Set the TX start threshold for best performance. */
2853 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2854 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2857 * If this is a 3c905B, also set the tx reclaim threshold.
2858 * This helps cut down on the number of tx reclaim errors
2859 * that could happen on a busy network. The chip multiplies
2860 * the register value by 16 to obtain the actual threshold
2861 * in bytes, so we divide by 16 when setting the value here.
2862 * The existing threshold value can be examined by reading
2863 * the register at offset 9 in window 5.
2865 if (sc->xl_type == XL_TYPE_905B) {
2866 CSR_WRITE_2(sc, XL_COMMAND,
2867 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2870 /* Set RX filter bits. */
2872 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2874 /* Set the individual bit to receive frames for this host only. */
2875 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2877 /* If we want promiscuous mode, set the allframes bit. */
2878 if (ifp->if_flags & IFF_PROMISC) {
2879 rxfilt |= XL_RXFILTER_ALLFRAMES;
2880 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2882 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2883 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2887 * Set capture broadcast bit to capture broadcast frames.
2889 if (ifp->if_flags & IFF_BROADCAST) {
2890 rxfilt |= XL_RXFILTER_BROADCAST;
2891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2893 rxfilt &= ~XL_RXFILTER_BROADCAST;
2894 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2898 * Program the multicast filter, if necessary.
2900 if (sc->xl_type == XL_TYPE_905B)
2901 xl_setmulti_hash(sc);
2906 * Load the address of the RX list. We have to
2907 * stall the upload engine before we can manipulate
2908 * the uplist pointer register, then unstall it when
2909 * we're finished. We also have to wait for the
2910 * stall command to complete before proceeding.
2911 * Note that we have to do this after any RX resets
2912 * have completed since the uplist register is cleared
2915 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2917 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2918 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2921 if (sc->xl_type == XL_TYPE_905B) {
2922 /* Set polling interval */
2923 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2924 /* Load the address of the TX list */
2925 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2927 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2928 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2929 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2934 * If the coax transceiver is on, make sure to enable
2935 * the DC-DC converter.
2938 if (sc->xl_xcvr == XL_XCVR_COAX)
2939 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2941 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2944 * increase packet size to allow reception of 802.1q or ISL packets.
2945 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2946 * control register. For 3c90xB/C chips, use the RX packet size
2950 if (sc->xl_type == XL_TYPE_905B)
2951 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2954 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2955 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2956 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2959 /* Clear out the stats counters. */
2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2961 sc->xl_stats_no_timeout = 1;
2962 xl_stats_update_locked(sc);
2963 sc->xl_stats_no_timeout = 0;
2965 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2966 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2969 * Enable interrupts.
2971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2972 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2973 #ifdef DEVICE_POLLING
2974 /* Disable interrupts if we are polling. */
2975 if (ifp->if_capenable & IFCAP_POLLING)
2976 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2979 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2980 if (sc->xl_flags & XL_FLAG_FUNCREG)
2981 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2983 /* Set the RX early threshold */
2984 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2985 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2987 /* Enable receiver and transmitter. */
2988 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2990 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2993 /* XXX Downcall to miibus. */
2997 /* Select window 7 for normal operations. */
3000 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3001 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3003 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
3007 * Set media options.
3010 xl_ifmedia_upd(struct ifnet *ifp)
3012 struct xl_softc *sc = ifp->if_softc;
3013 struct ifmedia *ifm = NULL;
3014 struct mii_data *mii = NULL;
3018 if (sc->xl_miibus != NULL)
3019 mii = device_get_softc(sc->xl_miibus);
3023 ifm = &mii->mii_media;
3025 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3030 xl_setmode(sc, ifm->ifm_media);
3037 if (sc->xl_media & XL_MEDIAOPT_MII ||
3038 sc->xl_media & XL_MEDIAOPT_BTX ||
3039 sc->xl_media & XL_MEDIAOPT_BT4) {
3042 xl_setmode(sc, ifm->ifm_media);
3051 * Report current media status.
3054 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3056 struct xl_softc *sc = ifp->if_softc;
3058 u_int16_t status = 0;
3059 struct mii_data *mii = NULL;
3063 if (sc->xl_miibus != NULL)
3064 mii = device_get_softc(sc->xl_miibus);
3067 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3070 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3071 icfg >>= XL_ICFG_CONNECTOR_BITS;
3073 ifmr->ifm_active = IFM_ETHER;
3074 ifmr->ifm_status = IFM_AVALID;
3076 if ((status & XL_MEDIASTAT_CARRIER) == 0)
3077 ifmr->ifm_status |= IFM_ACTIVE;
3081 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3082 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3083 ifmr->ifm_active |= IFM_FDX;
3085 ifmr->ifm_active |= IFM_HDX;
3088 if (sc->xl_type == XL_TYPE_905B &&
3089 sc->xl_media == XL_MEDIAOPT_10FL) {
3090 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3091 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3092 ifmr->ifm_active |= IFM_FDX;
3094 ifmr->ifm_active |= IFM_HDX;
3096 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3099 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3102 * XXX MII and BTX/AUTO should be separate cases.
3105 case XL_XCVR_100BTX:
3110 ifmr->ifm_active = mii->mii_media_active;
3111 ifmr->ifm_status = mii->mii_media_status;
3114 case XL_XCVR_100BFX:
3115 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3118 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3126 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3128 struct xl_softc *sc = ifp->if_softc;
3129 struct ifreq *ifr = (struct ifreq *) data;
3131 struct mii_data *mii = NULL;
3139 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3140 if (ifp->if_flags & IFF_UP) {
3141 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3142 ifp->if_flags & IFF_PROMISC &&
3143 !(sc->xl_if_flags & IFF_PROMISC)) {
3144 rxfilt |= XL_RXFILTER_ALLFRAMES;
3145 CSR_WRITE_2(sc, XL_COMMAND,
3146 XL_CMD_RX_SET_FILT|rxfilt);
3148 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3149 !(ifp->if_flags & IFF_PROMISC) &&
3150 sc->xl_if_flags & IFF_PROMISC) {
3151 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3152 CSR_WRITE_2(sc, XL_COMMAND,
3153 XL_CMD_RX_SET_FILT|rxfilt);
3156 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3160 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3163 sc->xl_if_flags = ifp->if_flags;
3169 /* XXX Downcall from if_addmulti() possibly with locks held. */
3171 if (sc->xl_type == XL_TYPE_905B)
3172 xl_setmulti_hash(sc);
3180 if (sc->xl_miibus != NULL)
3181 mii = device_get_softc(sc->xl_miibus);
3183 error = ifmedia_ioctl(ifp, ifr,
3184 &sc->ifmedia, command);
3186 error = ifmedia_ioctl(ifp, ifr,
3187 &mii->mii_media, command);
3190 #ifdef DEVICE_POLLING
3191 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3192 !(ifp->if_capenable & IFCAP_POLLING)) {
3193 error = ether_poll_register(xl_poll, ifp);
3197 /* Disable interrupts */
3198 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3199 ifp->if_capenable |= IFCAP_POLLING;
3204 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3205 ifp->if_capenable & IFCAP_POLLING) {
3206 error = ether_poll_deregister(ifp);
3207 /* Enable interrupts. */
3209 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
3210 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
3211 if (sc->xl_flags & XL_FLAG_FUNCREG)
3212 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle,
3214 ifp->if_capenable &= ~IFCAP_POLLING;
3218 #endif /* DEVICE_POLLING */
3220 ifp->if_capenable = ifr->ifr_reqcap;
3221 if (ifp->if_capenable & IFCAP_TXCSUM)
3222 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3224 ifp->if_hwassist = 0;
3228 error = ether_ioctl(ifp, command, data);
3236 * XXX: Invoked from ifnet slow timer. Lock coverage needed.
3239 xl_watchdog(struct ifnet *ifp)
3241 struct xl_softc *sc = ifp->if_softc;
3242 u_int16_t status = 0;
3248 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3249 if_printf(ifp, "watchdog timeout\n");
3251 if (status & XL_MEDIASTAT_CARRIER)
3252 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3260 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3261 if (sc->xl_type == XL_TYPE_905B)
3262 xl_start_90xB_locked(ifp);
3264 xl_start_locked(ifp);
3271 * Stop the adapter and free any mbufs allocated to the
3275 xl_stop(struct xl_softc *sc)
3278 struct ifnet *ifp = sc->xl_ifp;
3284 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3285 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3287 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3289 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3290 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3294 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3296 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3300 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3301 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3302 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3303 if (sc->xl_flags & XL_FLAG_FUNCREG)
3304 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3306 /* Stop the stats updater. */
3307 callout_stop(&sc->xl_stat_callout);
3310 * Free data in the RX lists.
3312 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3313 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3314 bus_dmamap_unload(sc->xl_mtag,
3315 sc->xl_cdata.xl_rx_chain[i].xl_map);
3316 bus_dmamap_destroy(sc->xl_mtag,
3317 sc->xl_cdata.xl_rx_chain[i].xl_map);
3318 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3319 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3322 if (sc->xl_ldata.xl_rx_list != NULL)
3323 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3325 * Free the TX list buffers.
3327 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3328 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3329 bus_dmamap_unload(sc->xl_mtag,
3330 sc->xl_cdata.xl_tx_chain[i].xl_map);
3331 bus_dmamap_destroy(sc->xl_mtag,
3332 sc->xl_cdata.xl_tx_chain[i].xl_map);
3333 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3334 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3337 if (sc->xl_ldata.xl_tx_list != NULL)
3338 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3340 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3344 * Stop all chip I/O so that the kernel's probe routines don't
3345 * get confused by errant DMAs when rebooting.
3348 xl_shutdown(device_t dev)
3350 struct xl_softc *sc;
3352 sc = device_get_softc(dev);
3361 xl_suspend(device_t dev)
3363 struct xl_softc *sc;
3365 sc = device_get_softc(dev);
3375 xl_resume(device_t dev)
3377 struct xl_softc *sc;
3380 sc = device_get_softc(dev);
3386 if (ifp->if_flags & IFF_UP)